KR102450078B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, comprising: a substrate including a display area and a non-display area surrounding the display area; an oxide semiconductor thin film transistor disposed on the substrate in the display area; and at least one side of the display area in the non-display area a plurality of power supply wirings, a plurality of first power wirings extending from the power supply wirings to the display area, and a plurality of first power wirings extending in a different direction from the plurality of first power wirings in the display area and made of the same material as the active layer of the oxide semiconductor thin film transistor of the second power supply wiring. Accordingly, by arranging the plurality of power supply wirings to cross the display area, a uniform power supply voltage can be supplied to all of the plurality of pixels, thereby improving the luminance uniformity.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having improved luminance uniformity by securing high potential voltage uniformity.

Currently, various display devices are being developed and marketed. For example, a liquid crystal display device (LCD), a field emission display device (FED), an electrophoretic display device (EPD), an electro-wetting display device (electro-wetting display device) There are display devices such as a display device (EWD), an organic light emitting display device (OLED), and a quantum dot display device (QD).

The display device includes a display area in which a plurality of pixels are disposed to display an image, and a non-display area in which an image is not displayed, which surrounds the display area. In this case, a plurality of pixels may be defined in the display area. Also, wirings and circuits for transmitting various signals to the plurality of pixels are disposed in the non-display area.

In a display device, a high potential voltage is supplied to a plurality of pixels through a power supply line extending from a power supply line disposed in the non-display area to the display area. In this case, as the display device has a high resolution, there is a problem in that the space occupied by the power wiring decreases. In addition, since the length of the power wiring increases as the size of the display device increases, the resistance of the power wiring increases and a voltage drop of a high potential voltage occurs.

The inventors of the present invention have recognized a problem in that a voltage drop of a high potential voltage occurs as the size of a display device increases. The high potential voltage is supplied to each pixel through a power supply line extending from a power supply line disposed in the non-display area to the display area. Although the power wiring is made of a metal material, the space occupied by the power wiring decreases as the display device becomes high-resolution, and the length of the power wiring increases as the size of the display device increases, so that the resistance of the power wiring increases. will do Accordingly, the inventors of the present invention have recognized that a voltage drop with respect to a high potential voltage supplied through a power supply line may occur, resulting in luminance non-uniformity and RC delay for each position of the display device.

Accordingly, the inventors of the present invention have developed a display device having a new structure in order to solve the problems of supplying a power voltage according to the enlargement of the display device and the high resolution of the display device as described above.

Specifically, an object of the present invention is to provide a display device that minimizes a voltage drop of a power supply voltage by including an additional power supply line made of the same material as an active layer of an oxide semiconductor thin film transistor.

Another object of the present invention is to provide a display device having improved luminance uniformity by connecting additional power wiring in a mesh shape with the existing power wiring in parallel.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment includes a substrate including a display area and a non-display area surrounding the display area, an oxide semiconductor thin film transistor disposed on the substrate in the display area, and a non-display area. In the display area, a power supply wiring disposed on at least one side of the display area, a plurality of first power wirings extending from the power supply wiring, and a plurality of first power wirings extending in a different direction from the plurality of first power wirings in the display area, the oxide semiconductor thin film transistor and a plurality of second power wirings made of the same material as the active layer. Accordingly, it is possible to suppress a power supply voltage drop due to an increase in the resolution of the display device.

In order to solve the above problems, a display device according to another embodiment of the present invention includes a substrate having a defined display area, an oxide semiconductor thin film transistor disposed in the display area, a plurality of first power lines disposed in the display area, and The plurality of first power sources are made of the same material as the active layer of the oxide semiconductor thin film transistor and are made of the same material as the active layer of the oxide semiconductor thin film transistor to suppress a power supply voltage drop due to an increase in the size and resolution of the display area and to provide luminance uniformity at intersections with the plurality of first power lines. and a plurality of second power wirings electrically connected to the wirings. Accordingly, the luminance uniformity may be improved by connecting the existing power wiring and the additional power wiring in parallel.

The details of other embodiments are included in the detailed description and drawings.

The present invention suppresses a power supply voltage drop due to an enlargement of a display device and an increase in resolution of the display device by adding a power supply wiring made of the same material as the active layer of the oxide semiconductor thin film transistor in the display area to intersect with the existing power supply wiring. can do.

According to the present invention, a uniform power voltage can be supplied to all of the plurality of pixels by connecting the additional power wiring in the form of a mesh in parallel with the existing power wiring, so that the luminance uniformity can be improved.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view of a display device according to an exemplary embodiment.
2 is a cross-sectional view of a display device according to an exemplary embodiment.
FIG. 3 is an enlarged view of region X of FIG. 1 .
4 is a cross-sectional view of the display device taken along line IV-IV' of FIG. 3 .
5 is a cross-sectional view of a display device according to another exemplary embodiment.
6 is a cross-sectional view of a display device according to another exemplary embodiment.
FIG. 7 is an enlarged view of the Y region of FIG. 6 .
8 is a cross-sectional view of a display device taken along line VIII-VIII' of FIG. 6 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

When an element or layer is referred to as another element or layer (on), it includes all cases in which another layer or other element is interposed immediately on or in the middle of another element.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and as those skilled in the art will fully understand, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other. It may be possible to implement together in a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment. In FIG. 1 , only the substrate 110 , the pad area PA, the power supply wiring 120 , the power wirings VDDL1 and VDDL2 , and the connection wiring CL among various components of the display device 100 for convenience of explanation are shown in FIG. 1 . shown.

The substrate 110 is a substrate 110 for supporting and protecting various components of the display device 100 . The substrate 110 may be made of glass or a plastic material having flexibility. When the substrate 110 is made of a plastic material, it may be made of, for example, polyimide (PI). However, it is not limited thereto.

A display area AA and a non-display area NA surrounding the display area AA may be defined in the substrate 110 .

The display area AA is an area in which an image is displayed in the display device 100 , and a display element and various driving elements for driving the display element may be disposed in the display area AA. For example, the display unit may be a display unit including an organic light emitting device 140 including an anode 141 , an organic light emitting layer 142 , and a cathode 143 . However, the present invention is not limited thereto, and the display unit may be a liquid crystal display unit. In addition, various driving devices such as thin film transistors, capacitors, and wires for driving the display unit may be disposed in the display area AA. A more detailed description of the display area AA will be described later with reference to FIG. 2 .

A plurality of pixels are disposed in the display area AA. The plurality of pixels is a minimum unit emitting light and may include a red pixel, a green pixel, and a blue pixel. Also, the plurality of pixels may further include a white pixel. Each of the plurality of pixels in the display area AA may be connected to a gate line and a data line.

The non-display area NA is adjacent to the display area AA and surrounds the display area AA. The non-display area NA is an area where an image is not displayed, and wirings and circuits may be formed therein.

The non-display area NA includes a pad area PA in which a plurality of pads are formed. The pad area PA is an area in which a plurality of pads and an external module, for example, a chip on film (COF) are bonded. The plurality of pads may be disposed at an end of the power supply wiring 120 , and an area including the plurality of pads may be defined as a pad area PA. The COF may include a base film made of an insulating material and a driving IC formed on the base film. The COF may supply a power voltage and a data voltage to the plurality of pixels in the display area AA through the pad.

Referring to FIG. 1 , the plurality of power supply wirings 120 are located in the non-display area NA and are wirings for supplying a high potential voltage to the pixel. As shown in FIG. 1 , the plurality of power supply wirings 120 are connected to the plurality of power supply wirings VDDL1 and VDDL2 . For example, the power supply wiring 120 may be disposed on at least one side of the display area AA to supply a power voltage to each pixel of the display area AA.

1 , the plurality of power supply wirings 120 includes a first power supply wiring 121 and a second power supply wiring 122 . The first power supply wiring 121 is disposed on one side of the display area AA where the pad area PA is defined, and the second power supply wiring 122 is disposed on the other side opposite to the one side. That is, the second power supply wiring 122 is disposed on the other side of the display area AA opposite to the first power supply wiring 121 . For example, the plurality of power supply wirings 120 may extend in the same direction as the extending direction of the gate wirings disposed in the display area AA.

In addition, the plurality of first power supply wirings 121 and the plurality of second power supply wirings 122 are connected through the connection wiring CL. The connection wiring CL is in the non-display area NA, and connects the first power supply wiring 121 and the second power supply wiring 122 in order to transfer the power voltage to the second power supply wiring 122 . it is wiring The connection wiring may have a width smaller than that of the first power supply 121 and the second power supply wiring 122 , but is not limited thereto.

Referring to FIG. 1 , the plurality of power supply wirings 120 are connected to the plurality of power supply wirings VDDL1 and VDDL2 .

The plurality of power lines VDDL1 and VDDL2 are disposed in the display area AA and supply power voltages to the plurality of pixels. The plurality of power wirings VDDL1 and VDDL2 include a first power wiring VDDL1 extending from the plurality of power supply wirings 120 to the display area AA and a second power supply wiring extending in a different direction from the first power wiring VDDL1 . A power supply wiring (VDDL2) is included. Here, the second power line VDDL2 may be connected to the connection line CL and the non-display area NA.

Hereinafter, the display device 100 will be described with reference to FIG. 2 for a more detailed description.

2 is a cross-sectional view of a display device according to an exemplary embodiment. 2 schematically illustrates one pixel defined in the display area AA of the display device 100 .

Referring to FIG. 2 , a display device 100 according to an exemplary embodiment includes a substrate 110 , a buffer layer 111 , a first gate insulating layer 112 , a first interlayer insulating layer 113 , and a passivation layer. 114 , an overcoat layer 115 , a bank 116 , an organic light emitting diode 140 , and a thin film transistor 130 disposed on the substrate 110 .

Referring to FIG. 2 , a buffer layer 111 is disposed on a substrate 110 . The buffer layer 111 serves to improve adhesion between the layers formed on the buffer layer 111 and the substrate 110 , and to block alkali components leaking from the substrate 110 . The buffer layer 111 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx). However, the buffer layer 111 is not an essential component, and may be omitted based on the type and material of the substrate 110 , the structure and type of the thin film transistor 130 , and the like.

The oxide semiconductor thin film transistor 130 is disposed on the buffer layer 111 to drive the organic light emitting diode 140 in the display area AA. The oxide semiconductor thin film transistor 130 includes an active layer 131 made of an oxide semiconductor, a gate electrode 132 , a source electrode 133 , and a drain electrode 134 . Although FIG. 2 illustrates a thin film transistor having a coplanar structure, the type and structure of the thin film transistor are not limited thereto.

As shown in FIG. 2 , an oxide semiconductor thin film transistor 130 using an oxide semiconductor material as the active layer 131 is used. Since the oxide semiconductor material has a larger bandgap than the silicon material, electrons do not cross the bandgap in the off state, and thus the off-current is low. In addition, since the off-current is low, the size of the storage capacitor may be reduced, so that the oxide semiconductor thin film transistor 130 is suitable for a high-resolution display device.

The active layer 131 of the oxide semiconductor thin film transistor 130 is disposed on the buffer layer 111 in the display area AA. The active layer 131 is a region in which a channel is formed when the thin film transistor is driven. The active layer 131 is formed of an oxide semiconductor, and oxide-based materials used as the active layer 131 include zinc oxide (ZnO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), and indium gallium zinc oxide. (IGZO) or indium tin zinc oxide (ITZO) may be used, but is not limited thereto.

The active layer 131 includes a channel region 131C overlapping the gate electrode 132 and conductive regions 131S and 131D positioned on both sides of the channel region 131C. The channel region 131C of the active layer 131 is a region in which a channel is formed when the oxide semiconductor thin film transistor 130 is turned on, and overlaps the gate electrode 132 . The conductive regions 131S and 131D of the active layer 131 are the remaining regions of the active layer 131 excluding the channel region 131C, and are regions in which the oxide semiconductor constituting the channel region 131C is conductive. Accordingly, the conductive regions 131S and 131D of the active layer 131 may be formed of a conductive oxide semiconductor. The conductive regions 131S and 131D may include a source region 131S that is in contact with the source electrode 133 and a drain region 131D that is in contact with the drain electrode 134 .

The second power line VDDL2 is disposed on the same layer as the active layer 131 in the display area AA. The second power wiring VDDL2 may be formed of the same material as the active layer 131 , and in particular, may be formed of the same material as the conductive regions 131S and 131D of the active layer 131 . Accordingly, the second power wiring VDDL2 and the conductive regions 131S and 131D of the active layer 131 may be simultaneously formed by the same process. For example, the second power wiring VDDL2 and the conductive regions 131S and 131D of the active layer 131 may be formed by dry etching the oxide semiconductor material. A more detailed description of the second power line VDDL2 will be described later with reference to FIGS. 3 and 4 .

A first gate insulating layer 112 is disposed on the active layer 131 . The first gate insulating layer 112 insulates the active layer 131 from the gate electrode 132 . The first gate insulating layer 112 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). In FIG. 2 , the first gate insulating layer 112 is patterned to have the same width as the gate electrode 132 , but the present invention is not limited thereto.

A gate electrode 132 is disposed on the first gate insulating layer 112 . The gate electrode 132 is disposed on the first gate insulating layer 112 to overlap the channel region 131C of the active layer 131 . The gate electrode 132 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be any one of copper (Cu), an alloy of two or more, or multiple layers thereof.

A first interlayer insulating layer 113 is disposed on the gate electrode 132 , a portion of the buffer layer 111 , and the active layer 131 . The first interlayer insulating layer 113 insulates the gate electrode 132 , the source electrode 133 , and the drain electrode 134 . The first interlayer insulating layer 113 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). In the first interlayer insulating layer 113 , a contact hole is formed for the source electrode 133 and the drain electrode 134 to contact each of the source region 131S and the drain region 131D of the active layer 131 .

A source electrode 133 and a drain electrode 134 are disposed on the first interlayer insulating layer 113 . The source electrode 133 and the drain electrode 134 are electrically connected to the source region 131S and the drain region 131D of the active layer 131 through the contact hole of the first interlayer insulating layer 113 . The source electrode 133 and the drain electrode 134 may include various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be made of any one of neodymium (Nd) and copper (Cu), an alloy of two or more, or a multilayer thereof.

The first power wiring VDDL1 is disposed on the same layer as the source electrode 133 and the drain electrode 134 in the display area AA. The first power wiring VDDL1 may be formed of the same material as the source electrode 133 and the drain electrode 134 . Accordingly, the first power wiring VDDL1, the source electrode 133, and the drain electrode 134 may be simultaneously formed in the same process. A more detailed description of the first power line VDDL1 will be described later with reference to FIGS. 3 and 4 .

2 shows only the driving thin film transistor among various thin film transistors that may be included in the display device 100 for convenience of explanation, but other thin film transistors such as a switching thin film transistor may also be included in the display device 100 . In addition, although the oxide semiconductor thin film transistor 130 has been described as having a coplanar structure in this specification, it may be implemented in other structures such as a staggered structure.

A passivation layer 114 for protecting the oxide semiconductor thin film transistor 130 and an overcoating layer 115 for planarizing an upper portion of the oxide semiconductor thin film transistor 130 are formed on the oxide semiconductor thin film transistor 130 . As shown in FIG. 2 , a contact hole for exposing the source electrode 133 of the thin film transistor is formed in the passivation layer 114 and the overcoat layer 115 . The passivation layer 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). In addition, the overcoat layer 115 may include an acrylic resin, an epoxy resin, a phenol resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene-based resin, a polyphenylene sulfide-based resin, benzocyclobutene, and a photoresist. It may consist of one of the resists. However, the passivation layer 114 may be omitted in some embodiments.

The organic light emitting device 140 is disposed on the overcoat layer 115 . The organic light emitting device 140 includes an anode 141 electrically connected to the source electrode 133 , an organic light emitting layer 142 disposed on the anode 141 , and a cathode 143 disposed on the organic light emitting layer 142 . do.

The anode 141 is disposed on the overcoat layer 115 and is connected to the source electrode 133 through a contact hole between the overcoat layer 115 and the passivation layer 114 . The anode 141 may be made of a conductive material having a high work function in order to supply holes to the organic emission layer 142 . The anode 141 may be formed of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). can

When the display device 100 is the top emission type display device 100 , the anode 141 includes a reflective layer for reflecting the light emitted from the organic emission layer 142 toward the cathode 143 and the organic emission layer 142 . A transparent conductive layer for supplying holes may be included. However, it may be defined that the anode 141 includes only a transparent conductive layer and the reflective layer is a separate component from the anode 141 .

In FIG. 2 , the anode 141 is shown to be electrically connected to the source electrode 133 of the oxide semiconductor thin film transistor 130 through a contact hole, but the anode 141 is determined by the type of the thin film transistor and the design method of the driving circuit. ) may be configured to be electrically connected to the drain electrode 134 of the oxide semiconductor thin film transistor 130 through a contact hole.

The organic emission layer 142 is a layer for emitting light of a specific color and may include one of a red emission layer, a green emission layer, a blue emission layer, and a white emission layer. In addition, the organic emission layer 142 may further include various layers such as a hole transport layer, a hole injection layer, an electron injection layer, an electron transport layer, and the like. Although the organic emission layer 142 is illustrated as being patterned in FIG. 2 , the organic emission layer 142 may be formed as a single layer over the entire display area AA.

The cathode 143 is disposed on the organic emission layer 142 . The cathode 143 supplies electrons to the organic emission layer 142 . The cathode 143 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (Zinc Oxide, ZnO), and tin. It may be made of a transparent conductive oxide (Tin Oxide, TO)-based oxide or a ytterbium (Yb) alloy. Alternatively, the cathode 143 may be made of a metal material.

Referring to FIG. 2 , a bank 116 is disposed on the anode 141 and the overcoat layer 115 . The bank 116 may cover a portion of the anode 141 of the organic light emitting device 140 to define a light emitting region. The bank 116 may be formed of an organic material. For example, the bank 116 may be made of polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

Hereinafter, for a more detailed description of the plurality of power lines VDDL1 and VDDL2 disposed in the display area AA of the display device 100 , it will be described with reference to FIGS. 3 and 4 together.

FIG. 3 is an enlarged view of region X of FIG. 1 . 4 is a cross-sectional view of the display device taken along line IV-IV' of FIG. 3 . For convenience of explanation, only the first power wiring VDDL1 and the second power wiring VDDL2 disposed in the X region are shown in FIG. 3 , and in FIG. 4 , the substrate 110 , the buffer layer 111 , and the second power wiring ( VDDL2), only the first interlayer insulating layer 113 and the first power wiring VDDL1 are illustrated.

3 and 4 , a plurality of power lines VDDL1 and VDDL2 are disposed on the substrate 110 in the display area AA. Specifically, the second power wiring VDDL2 is disposed on the buffer layer 111 , the first interlayer insulating layer 113 is disposed on the second power wiring VDDL2 , and the first interlayer insulating layer 113 is disposed on the first interlayer insulating layer 113 . A first power line VDDL1 is disposed on the . In this case, the first power line VDDL1 and the second power line VDDL2 are electrically connected through a contact hole included in the first interlayer insulating layer 113 . As shown in FIG. 3 , the first power line VDDL1 and the second power line VDDL2 are connected to each other at the crossing point. That is, the first power line VDDL1 and the second power line VDDL2 may be disposed to cross each other to form a mesh shape, but is not limited thereto.

The plurality of first power wirings VDDL1 may be disposed in a direction extending from the power supply wiring 120 to the display area AA, that is, in a column direction. The first power wiring VDDL1 may be formed of the same material as the source electrode 133 and the drain electrode 134 of the oxide semiconductor thin film transistor 130 .

The plurality of second power wirings VDDL2 extend in different directions from the plurality of first power wirings VDDL1 . For example, the plurality of second power lines VDDL2 may be disposed in a row direction that is perpendicular to the plurality of first power lines VDDL1 . The plurality of second power wirings VDDL2 may be formed of the same material as the active layer 131 of the oxide semiconductor thin film transistor 130 . Specifically, the plurality of second power wirings VDDL2 may be formed of the same material as the conductive regions 131S and 131D in which the active layer 131 made of an oxide semiconductor is conductive.

In general, the high potential voltage is supplied to each pixel through a power supply wiring extending from a power supply wiring disposed in the non-display area to the display area. Although the power wiring is made of a metal material, the space occupied by the power wiring decreases as the display device becomes high-resolution, and the length of the power wiring increases as the size of the display device increases. Accordingly, the resistance of the power wiring increases, and a voltage drop with respect to the high potential voltage supplied through the power wiring may occur. In addition, luminance non-uniformity and RC delay may occur for each position of the display device due to such a voltage drop phenomenon.

Accordingly, in the display device 100 according to an embodiment of the present invention, the first power wiring VDDL1 is made of the same material as the active layer 131 and extends in a different direction from the first power wiring VDDL1. By connecting to the second power line (VDDL2), the voltage drop of the power voltage can be minimized. That is, the second power wiring VDDL2 made of the same material as the conductive regions 131S and 131D of the active layer 131 is added to the first power wiring VDDL1 so that the power supply voltage in the display area AA is increased. The problem of non-uniformity for each position can be solved, and the problem of non-uniform luminance for each position can also be solved.

Also, the second power wiring VDDL2 may be formed simultaneously with the conductive regions 131S and 131D of the active layer 131 by the same process. Accordingly, in the process of manufacturing the display device 100 according to the exemplary embodiment, a separate process and mask for forming the second power wiring VDDL2 are not added. Accordingly, even if the second power wiring VDDL2 is additionally formed, manufacturing cost and process time do not increase.

5 is a cross-sectional view of a display device according to another exemplary embodiment. The display device 500 illustrated in FIG. 5 is substantially the same as the display device 100 illustrated in FIGS. 1 to 4 except that the LTPS thin film transistor 550 is added, and thus a redundant description thereof will be omitted.

Referring to FIG. 5 , a display device 500 according to another embodiment of the present invention has a second gate insulating layer 517 and a second interlayer insulating layer compared to the display device 100 according to an embodiment of the present invention. 518 and an LTPS thin film transistor 550 .

Referring to FIG. 5 , the LTPS thin film transistor 550 is disposed on the buffer layer 111 . The LTPS thin film transistor 550 is a thin film transistor using a polycrystalline silicon material as the active layer 551 . Polycrystalline silicon material has high mobility (100 cm 2 /Vs or more), low energy consumption, and excellent reliability.

The LTPS thin film transistor 550 includes an active layer 551 made of polysilicon, a gate electrode 552 , a source electrode 553 , and a drain electrode. The LTPS thin film transistor 550 is a thin film transistor having a top gate structure in which a gate electrode 552 is disposed on the active layer 551 . Although not shown in FIG. 5 , the drain electrode may be connected to any one electrode or wire constituting the display device 500 according to another embodiment of the present invention.

The LTPS thin film transistor 550 may share one of a source electrode 133 and a drain electrode (not shown) with the oxide semiconductor thin film transistor 130 . In FIG. 5 , the LTPS thin film transistor 550 is illustrated as sharing the oxide semiconductor thin film transistor 130 and the source electrodes 133 and 533 , but the present invention is not limited thereto, and the LTPS thin film transistor 550 and the oxide semiconductor thin film transistor 130 are not limited thereto. ) may share the drain electrode 134 .

An active layer 551 of the LTPS thin film transistor 550 is disposed on the substrate 110 . The active layer 551 includes polycrystalline silicon. Accordingly, polycrystalline silicon is formed by depositing an amorphous silicon material on the substrate 110 and performing a dehydrogenation process and a crystallization process, and the active layer 551 of the LTPS thin film transistor 550 is formed by patterning the polycrystalline silicon. is formed However, the present invention is not limited thereto, and the active layer 551 may be formed through another process.

A second gate insulating layer 517 is disposed on the active layer 551 of the LTPS thin film transistor 550 . The second gate insulating layer 517 is a layer for insulating the active layer 551 and the gate electrode 552 and may be made of an insulating material. For example, the second gate insulating layer 517 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx).

A gate electrode 552 of the LTPS thin film transistor 550 is disposed on the second gate insulating layer 517 . In this case, the gate electrode 552 is disposed on the second gate insulating layer 517 to overlap the active layer 551 . The gate electrode 552 of the LTPS thin film transistor 550 includes a conductive material, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). , and copper (Cu), or an alloy of two or more, or a multilayer thereof.

A second interlayer insulating layer 518 is disposed on the gate electrode 552 of the LTPS thin film transistor 550 . The second interlayer insulating layer 518 may be formed of an insulating material. For example, the second interlayer insulating layer 518 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx).

The oxide semiconductor thin film transistor 130 is disposed on the second interlayer insulating layer 518 . That is, the active layer 131 of the oxide semiconductor thin film transistor is disposed on the second interlayer insulating layer 518 .

In the display device 500 according to another embodiment of the present invention, the oxide semiconductor thin film transistor 130 and the LTPS thin film transistor 550 are simultaneously used. Accordingly, in the display device 500 according to another embodiment of the present invention, advantageous characteristics of the oxide semiconductor thin film transistor 130 and advantageous characteristics of the LTPS thin film transistor 550 can be implemented in one panel.

6 is a cross-sectional view of a display device according to another exemplary embodiment. FIG. 7 is an enlarged view of the Y region of FIG. 6 . 8 is a cross-sectional view of a display device taken along line VIII-VIII' of FIG. 7 . The display device 600 shown in FIGS. 6 to 8 is substantially the same as the display device 100 shown in FIGS. 1 to 4 , except that a third power supply line VDDL3 is added. is omitted.

Referring to FIG. 6 , a plurality of power lines VDDL1 , VDDL2 , and VDDL3 may be disposed in the display area AA. The plurality of power supply lines VDDL1 , VDDL2 , and VDDL3 are wirings for supplying power supply voltages to the plurality of pixels.

6 to 8 , the third power line VDDL3 is a line extending in the same direction as the first power line VDDL1 . Also, the third power line VDDL3 is disposed to overlap the first power line VDDL1 and may contact the first power line VDDL1 a plurality of times through a plurality of contact holes. For convenience of explanation, in FIG. 7 , the width of the third power line VDDL3 is greater than the width of the first power line VDDL1 , but the present invention is not limited thereto, and the width of the third power line VDDL3 is equal to the first It may be the same as the width of the power wiring VDDL1.

The third power line VDDL3 is disposed on the same layer as the second power line VDDL2 to cross the second power line VDDL2 . For example, the third power line VDDL3 may cross the second power line VDDL2 in a vertical direction to form a mesh shape.

The third power line VDDL3 may be made of the same material as the second power line VDDL2 and may be integrally formed with the second power line VDDL2 . That is, the third power line VDDL3 may be made of the same conductive oxide semiconductor material as the second power line VDDL2 . Also, the third power line VDDL3 and the second power line VDDL2 may be simultaneously formed by the same process.

In the display device 600 according to another embodiment of the present invention, the second power line VDDL2 and the third power line VDDL3 formed on the same layer are connected in parallel with the first power line VDDL1 to provide power The total resistance of the wirings VDDL1, VDDL2, and VDDL3 can be minimized. That is, the second power wiring VDDL1 and the first power supply extending in a different direction from the generally used first power wiring VDDL1 and the first power wiring VDDL2 and connected at the intersection with the first power wiring VDDL1 . A drop in the power voltage in the power lines VDDL1, VDDL2, and VDDL3 using the third power line VDDL3 overlapping the line VDDL1 and electrically connected to the first power line VDDL1 through a plurality of contact holes phenomenon can be reduced. Accordingly, a uniform power voltage can be supplied to all of the plurality of pixels, so that the luminance uniformity can be improved.

An exemplary embodiment of the present invention can be described as follows.

A display device according to an exemplary embodiment includes a substrate including a display area and a non-display area surrounding the display area, an oxide semiconductor thin film transistor disposed on the substrate in the display area, and at least one side of the display area in the non-display area. the disposed power supply wiring, a plurality of first power wirings extending from the power supply wiring to the display area, and a plurality of first power wirings extending in a different direction from the plurality of first power wirings in the display area, and made of the same material as the active layer of the oxide semiconductor thin film transistor It may include a plurality of second power supply wiring formed.

According to another feature of the present invention, the active layer of the oxide semiconductor thin film transistor includes a channel region overlapping the gate electrode and a conductive region positioned on both sides of the channel region, and the plurality of second power wirings are identical to the conductive region. It can be made of material.

According to another feature of the present invention, the display further includes an LTPS thin film transistor disposed on a substrate in the display area, wherein the oxide semiconductor thin film transistor and the LTPS thin film transistor may share one of a source electrode and a drain electrode.

According to another feature of the present invention, the gate electrode of the LTPS thin film transistor is disposed on the active layer of the LPTS thin film transistor, the active layer of the oxide semiconductor thin film transistor is disposed on the gate electrode of the LTPS thin film transistor, and the oxide semiconductor thin film transistor A gate electrode of the oxide semiconductor thin film transistor may be disposed on the active layer of

According to another feature of the present invention, the plurality of first power wirings and the plurality of second power wirings may be connected to each other at crossing points.

According to another feature of the present invention, a plurality of third power wirings disposed to overlap the plurality of first power supply wirings and made of the same material as the plurality of second power supply wirings may be further included.

According to another feature of the present invention, the plurality of second power wirings and the plurality of third power wirings may be disposed to cross each other on the same layer to form a mesh shape.

According to another feature of the present invention, each of the plurality of third power wirings may contact the overlapping first power wirings among the plurality of first power wirings a plurality of times.

According to another feature of the present invention, the power supply wiring includes a first power supply wiring disposed on one side of the display area in which the pad area is defined, a second power supply wiring disposed on the other side opposite to the one side, and A connection line disposed in the non-display area to connect the first power supply line and the second power supply line may be further included.

According to another feature of the present invention, the plurality of second power wirings may be connected to the connection wiring in the non-display area.

A display device according to another exemplary embodiment of the present invention provides a substrate having a defined display area, an oxide semiconductor thin film transistor disposed in the display area, a plurality of first power lines disposed in the display area, and an increase in size and resolution of the display area. In order to suppress the power supply voltage drop and provide luminance uniformity, a plurality of third power lines made of the same material as the active layer of the oxide semiconductor thin film transistor and electrically connected to the plurality of first power lines at intersections with the plurality of first power lines 2 may include power wiring.

According to another feature of the present invention, it further includes an LTPS thin film transistor disposed on a substrate in the display area, wherein the LTPS thin film transistor and the oxide semiconductor thin film transistor may share one of a source electrode and a drain electrode.

According to still another feature of the present invention, the display device further includes a power supply wiring disposed in a non-display area of the substrate surrounding the display area, wherein the power supply wiring is disposed on one side and the other side of the display area to reduce a power voltage drop, respectively. the first power supply wiring and the second power supply wiring, and a connection wiring connecting the first power supply wiring and the second power supply wiring and having a width smaller than that of the first power supply wiring and the second power supply wiring. have.

According to another feature of the present invention, the plurality of second power wirings may be made of the same material as a portion of the active layer of the oxide semiconductor thin film transistor in contact with the source electrode and the drain electrode of the oxide semiconductor thin film transistor.

According to another feature of the present invention, a plurality of third power wirings overlapping the plurality of first power wirings, forming an integral with the plurality of second power wirings, and forming a mesh shape may further include.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 500, 600: display device
110: substrate
111: buffer layer
112: first gate insulating layer
113: first interlayer insulating layer
114: passivation layer
115: over coating layer
116: bank
120: a plurality of power supply wiring
121: first power supply wiring
122: second power supply wiring
130: oxide semiconductor thin film transistor
131: active layer
131S: source area
131D: drain region
131C: Channel area
132: gate electrode
133: source electrode
134: drain electrode
140: organic light emitting device
141: anode
142: organic light emitting layer
143: cathode
517: second gate insulating layer
518: second interlayer insulating layer
550: LTPS thin film transistor
551: active layer
552: gate electrode
553: source electrode
AA: display area
NA: non-display area
PA: pad area
CL: connecting wiring
VDDL1: first power wiring
VDDL2: second power wiring
VDDL3: Third power wiring

Claims (15)

a substrate including a display area and a non-display area surrounding the display area;
an active layer including a channel region made of an oxide semiconductor on a substrate of the display region and a conductive region in which the oxide semiconductor is dry etched on both sides of the channel region;
a plurality of second power wirings formed of the same material as the conductive region on the same layer as the active layer;
a gate electrode disposed on the active layer with a first gate insulating layer interposed therebetween;
a source electrode and a drain electrode disposed on the active layer and electrically connected to the conductive region;
a power supply line disposed on at least one side of the display area in the non-display area; and
and a plurality of first power wirings disposed on the same layer as the source electrode and the drain electrode and extending from the power supply wiring to the display area. According to claim 1,
and the active layer, the gate electrode, the source electrode, and the drain electrode constitute an oxide semiconductor thin film transistor. 3. The method of claim 2,
Further comprising an LTPS thin film transistor disposed on the substrate of the display area,
The LTPS thin film transistor shares one of a source electrode and a drain electrode of the oxide semiconductor thin film transistor. 4. The method of claim 3,
A gate electrode of the LTPS thin film transistor is disposed on the active layer of the LTPS thin film transistor,
and an active layer of the oxide semiconductor thin film transistor is disposed on a gate electrode of the LTPS thin film transistor. According to claim 1,
The plurality of first power wirings and the plurality of second power wirings cross each other and are connected to each other at the crossing points. According to claim 1,
The display device of claim 1 , further comprising: a plurality of third power wirings disposed to overlap the plurality of first power supply wirings and made of the same material as the plurality of second power supply wirings. 7. The method of claim 6,
The plurality of second power wirings and the plurality of third power wirings are disposed to cross each other on the same layer to form a mesh shape. 8. The method of claim 7,
Each of the plurality of third power wirings is in contact with the overlapping first power wiring among the plurality of first power wirings a plurality of times. According to claim 1,
The power supply wiring is
a first power supply line disposed at one side of the display area in which a pad area is defined;
a second power supply wiring disposed on the other side opposite to the one side; and
and a connection line disposed in the non-display area to connect the first power supply line and the second power supply line. 10. The method of claim 9,
and the plurality of second power lines are connected to the connection line in the non-display area. delete delete 10. The method of claim 9,
and the connection wiring has a width smaller than a width of the first power supply wiring and the second power supply wiring.
delete delete

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