KR20180074164A - Organic light emitting display device - Google Patents

Abstract

An organic light emitting display device includes a substrate having a display area including a plurality of sub-pixels each having an anode, an organic emitting layer, and a cathode; a first data line disposed on the substrate and applying a first data voltage to a first sub-pixel emitting light of a first color and to a second sub-pixel emitting light of a second color different from the first color; and a first line disposed between the first data line and an anode overlapping the first data line among the anodes of the plurality of sub-pixels. Accordingly, parasitic capacitance occurring between the first data line and the anode overlapping with the first data line is reduced, and color change in the sub-pixels is suppressed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display, and more particularly, to an organic light emitting diode (OLED) display capable of reducing an interference phenomenon that may occur between a wiring and an organic light emitting diode.

The organic light emitting display device is a self-emission type display device, unlike a liquid crystal display device, a separate light source is not required, and thus it can be manufactured in a light and thin shape. Further, the organic light emitting display device is advantageous not only in terms of power consumption in accordance with low voltage driving but also in response speed, viewing angle, and contrast ratio, and is being studied as a next generation display.

The organic light emitting display includes a plurality of sub-pixels connected to a plurality of wirings. Each of the plurality of sub-pixels includes a thin film transistor, a capacitor, and an organic light emitting element, and the thin film transistor and the capacitor may be connected to the wirings to transfer a driving current to the organic light emitting element based on the electrical signals of the wirings.

In recent years, as a demand for an organic light emitting display device of high resolution has been increased, studies have been made to densely arrange wirings, thin film transistors, capacitors, and organic light emitting devices. As the arrangement of the wirings, the thin film transistor, the capacitor, and the organic light emitting element becomes more dense, a region where the wirings and the organic light emitting element are overlapped can be generated.

As a result of the overlap between the wirings and the organic light emitting device, an interference phenomenon may occur in the organic light emitting device due to a signal applied to the wiring. For example, a parasitic capacitance may be formed between the anode and the data line of an organic light emitting diode included in a specific sub-pixel. Such a parasitic capacitance causes crosstalk between the anode and the data line, and may cause an interference phenomenon with respect to a voltage applied to the anode. Accordingly, a current amount of the driving current of the organic light emitting device is changed and ripples are generated, which may cause a problem that the brightness of the organic light emitting device changes.

 [Related Technical Literature]

1. Organic light emitting display (Patent Application No. 10-2012-0145657).

The inventors of the present invention have studied various sub-pixel structures of an organic light emitting display. Specifically, the inventor of the present invention has been able to design various arrangements of a plurality of sub-pixels, that is, position and size in consideration of lifetime characteristics, luminance characteristics, material characteristics, and the like for each of a plurality of sub-pixels.

There is a structure in which a data voltage is applied to a sub-pixel in which one data line among the plurality of sub-pixels arranged in various designs emits different colors. For example, two sub-pixels of a red sub-pixel, a green sub-pixel and a blue sub-pixel are alternately connected to one data line and the other of the red sub-pixel, the green sub- One sub-pixel is connected. When a general image is displayed in such a sub-pixel structure, in a general image, the screen continuously changes in each frame, so that an AC voltage may be applied to the data line and interference may occur between the data line and the anode. However, in a general image, the screen changes almost every frame and the data voltage fluctuates, so that the time of occurrence of interference is also very short. Therefore, the inventor of the present invention has recognized that, when a general image is displayed, a human can not recognize the interference phenomenon that may occur between the data wire and the anode.

In the sub-pixel structure as described above, the inventors of the present invention have found that when a monochromatic image of one color is displayed on the entire screen of the organic light emitting display device or a specific portion of the screen for a long time, And that it can be seen. For example, it is assumed that a red sub-pixel and a blue sub-pixel are alternately connected to one data line and a green sub-pixel is connected to another data line. In this case, if red is displayed on the entire screen, the green sub-pixel and the blue sub-pixel must be turned off and only the red sub-pixel must be turned on. However, as the red sub-pixel and the blue sub-pixel are connected to the same data line, an AC voltage swinging between a high voltage and a low voltage is applied to the data line to which the red sub-pixel and the blue sub-pixel are connected. As a result, an AC voltage is applied to the data line for applying the data voltage to the sub-pixels emitting different colors for a long time, so that an interference phenomenon may occur between the data line and the anode overlapping the data line. Accordingly, the amount of current of the driving current of the organic light emitting device may be changed, causing a problem that the brightness of the organic light emitting device changes or an undesired color is recognized by the user.

Accordingly, the inventor of the present invention invented an organic light emitting display device having a new structure for solving the above-mentioned problems.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an organic light emitting display device capable of reducing a parasitic capacitance that may occur between a data line and an anode as one data line supplies a data voltage to sub- And a display device.

Another problem to be solved by the present invention is to reduce crosstalk that can be generated in a sub-pixel overlapping a data line connected to sub-pixels emitting different colors, thereby minimizing the color change in the sub-pixel And an organic light emitting display device.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an organic light emitting display including a substrate having a display region including a plurality of sub-pixels each including an anode, an organic light emitting layer, and a cathode, A first data line for applying a first data voltage to a first sub-pixel that emits a first color of a plurality of sub-pixels and a second sub-pixel that emits a second color that is different from the first color, And a first wiring disposed between the anode and the first data wiring overlapping with the first data wiring among the anodes of the anode. Thus, the parasitic capacitance that can occur between the anode and the first data line overlapping the first data line can be reduced, and the color change in the sub-pixel can be reduced.

According to another aspect of the present invention, there is provided an organic light emitting display including a first data line for supplying a data voltage to sub-pixels emitting different colors, When displaying a plurality of first anodes and monochromes arranged so as to overlap with wirings, the interference between the first data line and the first anode is reduced to reduce the fluctuation of the luminance in the sub-pixels having the plurality of first anodes And a first wiring disposed between the first data line and the first anode. Therefore, when the organic light emitting display device displays a single color, interference occurs in sub-pixels superimposed on the first data line by the first data line supplying the data voltage to the sub-pixels emitting different colors Can be suppressed.

The details of other embodiments are included in the detailed description and drawings.

The present invention can minimize the interference phenomenon with respect to the data line for transmitting the AC voltage and the anode of the specific sub pixel when the monochromatic color is displayed in the organic light emitting display device by forming the wiring between the data line and the anode of the specific sub pixel .

In addition, the present invention can reduce the parasitic capacitance that may occur between the data line and the anode by configuring the wiring between the data line and the anode of the specific sub-pixel, thereby reducing the fluctuation of the luminance in the sub-pixel where the anode is arranged.

Further, according to the present invention, a wiring is formed between a data wiring and an anode of a specific sub-pixel to solve crosstalk between the data wiring connected to the sub-pixels emitting different colors and the anode overlapping the data wiring, The color change can be minimized and the pixel stability can be provided.

Further, the present invention can reduce the interference phenomenon between the data line and the anode by the first wiring, by constituting the connection wiring connecting the first wiring and the second wiring.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a schematic plan view of an OLED display according to an embodiment of the present invention.
Figure 2a is a schematic enlarged view of the X region of Figure 1;
FIG. 2B is a cross-sectional view taken along line IIb-IIb 'of FIG. 2A.
2C is a cross-sectional view taken along line IIc-IIc 'of FIG. 2A.
3A is a schematic plan view of an OLED display according to another embodiment of the present invention.
FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.
3C is a cross-sectional view taken along line IIIc-IIIc 'of FIG. 3A.
4A is a schematic plan view of an OLED display according to another embodiment of the present invention.
4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A.
5 to 7 are schematic plan views of an organic light emitting diode display according to various embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It will be understood that when an element or layer is referred to as being on another element or layer, it encompasses the case where it is directly on or intervening another element or intervening another element or element.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of an OLED display according to an embodiment of the present invention. Referring to FIG. 1, the OLED display 100 may include a substrate 110, a gate driver 120, a data driver 130, and wires 140 and 150.

The substrate 110 supports various components of the OLED display 100. The substrate 110 may be formed of a transparent insulating material, for example, an insulating material such as glass, plastic, or the like.

A display area DA and a non-display area NA may be defined on the substrate 110. [ The display area DA may include a plurality of sub-pixels, which are units for realizing a single color, in an area where an image is actually displayed in the OLED display 100. The plurality of sub-pixels may include, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The red sub-pixel, the green sub-pixel, and the blue sub-pixel form one group, thereby achieving a desired color. Each of the plurality of sub-pixels includes an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode. A more detailed description of the sub-pixel including the organic light emitting element will be described later with reference to FIGS. 2A to 2C.

The non-display area NA can be defined as an area in which no image is displayed and an area surrounding the display area DA. In the non-display area NA, various components for driving the plurality of sub-pixels arranged in the display area DA can be arranged. For example, as shown in FIG. 1, the gate driver 120, the data driver 130, the wirings 140 and 150, and the like may be disposed in the non-display area NA of the substrate 110.

The gate driver 120 outputs a scan signal and a light emission control signal under the control of the timing controller to select a sub pixel to be charged with a data voltage through a wiring 150 such as a scan line and a light emission control signal line, . The gate driver 120 shifts the scan signal and the emission control signal using a shift register and sequentially supplies the scan signal and the emission control signals to the wire 150. [ The shift register of the gate driver 120 may be formed directly on the substrate 110 as shown in FIG. 1 using a gate-driver In Panel (GIP) method, but is not limited thereto.

The data driver 130 may convert the digital data of the input image received from the timing controller for each frame of the image displayed on the organic light emitting diode display device 100 into a data voltage and then supply the data voltage to the wiring 140. The timing controller may be integrated with the data driver 130 according to the product model of the OLED display. The data driver 130 may output a data voltage using a digital to analog converter (DAC) or the like that converts the digital data into a gamma compensation voltage. At this time, the wiring 140 extending from the data driver 130 and transmitting a signal to the plurality of sub-pixels of the display area DA includes an initialization voltage wiring, a light emission control signal wiring, a high potential power wiring, a low potential power wiring, .

Hereinafter, FIGS. 2A to 2C will be referred to for a more detailed description of a plurality of sub-pixels defined in the substrate 110 of the OLED display 100 according to an exemplary embodiment of the present invention.

Figure 2a is a schematic enlarged view of the X region of Figure 1; FIG. 2B is a cross-sectional view taken along line IIb-IIb 'of FIG. 2A. 2C is a cross-sectional view taken along line IIc-IIc 'of FIG. 2A. 2A to 2C, the OLED display 100 includes a first data line DL1, a second data line DL2, a first power line VDD1, a second power line VDD2, 1 wire L1, a second wire L2, a thin film transistor 160, and an organic light emitting diode 170. [ 2A, for convenience of explanation, the anode 171 of the organic light emitting element 170 and the first data line DL1, the second data line DL2, the first power line VDD1 Only the second power supply line VDD2, the first wiring L1 and the second wiring L2 are shown, and the other components are not shown. In FIG. 2B, the sectional structures of the first sub-pixel SP1 and the second sub-pixel SP2 are substantially identical to each other, so the cross-sectional structures of the first sub-pixel SP1 and the second sub-pixel SP2 will be described together.

Referring to FIG. 2A, the substrate 110 may include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix form on the substrate 110. [ For example, as shown in FIG. 2A, a plurality of sub-pixels SP1, SP2, and SP3 having a rectangular shape may be disposed in a matrix, but the present invention is not limited to the shape of the sub-pixels.

The plurality of sub-pixels SP1, SP2 and SP3 may include a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 are sub-pixels emitting different colors. In other words, the first sub-pixel SP1 emits a first color, the second sub-pixel SP2 emits a second color different from the first color, the third sub-pixel SP3 emits a first color, And may be configured to emit a third color different from the two colors. For example, each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 includes a red sub pixel emitting red light, a green sub pixel emitting green light, And may be one of blue sub-pixels emitting light. Hereinafter, it is described that the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a blue sub-pixel, and the third sub-pixel SP3 is a green sub-pixel, But it is not limited thereto as long as it emits different colors.

The first sub-pixel SP1 and the second sub-pixel SP2 of the plurality of sub-pixels SP1, SP2 and SP3 may be arranged in the same column. Specifically, as shown in FIG. 2A, the first sub-pixel SP1 and the second sub-pixel SP2 may be alternately arranged in the same column. The third sub-pixel SP3 of the plurality of sub-pixels SP1, SP2 and SP3 may be arranged in a column different from the first sub-pixel SP1 and the second sub-pixel SP2. For example, as shown in FIG. 2A, the column adjacent to the column in which the first sub-pixel SP1 and the second sub-pixel SP2 are alternately arranged may be composed of only the third sub-pixel SP3. As described above, as the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 are arranged, the first sub-pixel SP1 and the second sub- The sub-pixel SP2 and the third sub-pixel SP3 arranged in the other column can be repeatedly arranged on the substrate 110. [

In FIG. 2A, all of the plurality of sub-pixels SP1, SP2, and SP3 have a rectangular shape and all have the same size, but the present invention is not limited thereto. In other words, the shape of the plurality of sub-pixels SP1, SP2, SP3 may be changed to a shape other than a rectangular shape in consideration of the efficiency of arrangement of the plurality of sub-pixels SP1, SP2, SP3, Pixels SP1, SP2, and SP3 may have different shapes. Likewise, the sizes of the plurality of sub-pixels SP1, SP2, and SP3 may be variously set in consideration of lifetime characteristics, brightness characteristics, and the like of each of the plurality of sub-pixels SP1, SP2, and SP3. For example, in some embodiments, the size of the second sub-pixel SP2 is set to be larger than the size of the first sub-pixel SP1 or the size of the third sub-pixel SP3 in consideration of lifetime characteristics, Can be configured.

Referring to FIG. 2A, a first data line DL1, a second data line DL2, a first power line VDD1, and a second power line VDD2 may be disposed on a substrate 110.

The first data line DL1 and the second data line DL2 may be spaced apart from each other on the substrate 110 and may extend parallel to each other, for example. The first data line DL1 and the second data line DL2 may provide data voltages to the sub-pixels connected to the first data line DL1 and the second data line DL2, respectively. Specifically, the first data line DL1 provides a data voltage to the first sub-pixel SP1 and the second sub-pixel SP2 connected to the first data line DL1, and the second data line DL2 provides a data voltage to the first sub- And the data voltage can be supplied to the third sub-pixel SP3. The first data line DL1 and the second data line DL2 must be provided with different data voltages and are not connected to each other.

The first power supply line VDD1 and the second power supply line VDD2 may extend apart from each other on the substrate 110 and may extend, for example, in parallel with each other. The first power supply line VDD1 and the second power supply line VDD2 may be spaced apart from the first data line DL1 and the second data line DL2 on the substrate 110 and extend parallel to each other. The first power supply line VDD1 and the second power supply line VDD2 may transmit high-potential voltages to the sub-pixels connected to the first power supply line VDD1 and the second power supply line VDD2. Specifically, the first power supply line VDD1 supplies a high potential voltage to the first sub-pixel SP1 and the second sub-pixel SP2 connected to the first power supply line VDD1, and the second power supply line VDD2 supplies the high- Pixel SP3 to the third sub-pixel SP3. At this time, the high potential voltage transmitted by the first power supply line VDD1 and the high potential voltage transmitted by the second power supply line VDD2 may be a constant voltage. The same constant voltage may be provided to the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 via the first power supply line VDD1 and the second power supply line VDD2 have. In some embodiments, the first power supply line VDD1 and the second power supply line VDD2 may be electrically connected to each other in the non-display area NA of the substrate 110. [

The organic light emitting element 170 is disposed on the first data line DL1, the second data line DL2, the first power supply line VDD1 and the second power supply line VDD2. The organic light emitting device 170 may be disposed in each of the plurality of sub-pixels SP1, SP2, and SP3. 2A, only the anode 171 among the components of the organic light emitting device 170 is shown for convenience of description, and the organic light emitting device 170 will be described later in detail with reference to FIGS. 2B and 2C.

Referring to FIG. 2A, the anode 171 may be disposed in each of the plurality of sub-pixels SP1, SP2, and SP3. In FIG. 2A, the anode 171 has a rectangular shape, and all of the plurality of sub-pixels SP1, SP2, and SP3 have the same size. 2A, the anode 171 of the first sub-pixel SP1 connected to the first data line DL1 and the anode 171 of the second sub-pixel SP2 are connected to the second data line DL2 And the anode 171 of the three sub-pixels SP3 are arranged in a staggered manner. However, the size, shape, and arrangement of the anode 171 can be variously set in consideration of the arrangement efficiency, the luminance characteristic, the life characteristic, and the like of the organic light emitting device 170.

The anode 171 may be arranged so as to overlap with various wirings such as the first data line DL1, the second data line DL2, the first power source line VDD1 and the second power source line VDD2. 2A, the anode 171 of the first sub-pixel SP1 and the anode 171 of the second sub-pixel SP2 overlap the first data line DL1 and the anode 171 of the second sub- 171 are overlapped with the second data line DL2.

As described above, since the first sub-pixel SP1 and the second sub-pixel SP2 emitting different colors receive the data voltage from the first data line DL1, the first data line DL1 ) And the first data line DL1 and the overlapping anode 171 may be a problem. In the organic light emitting diode display 100 according to an embodiment of the present invention, the anode 171 of the anode 171 of the plurality of sub-pixels SP1, SP2, and SP3 is overlapped with the first data line DL1, , And a first wiring (L1) is disposed between the first data lines DL1. Hereinafter, referring to FIGS. 2B and 2C together for a more detailed description of the cross-sectional structure of the OLED display 100, FIG.

Referring to FIG. 2B, a buffer layer 111 is formed on a substrate 110. The buffer layer 111 may be a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx). The buffer layer 111 improves adhesion between the layers formed on the buffer layer 111 and the substrate 110 and may block water or oxygen penetrating through the substrate 110. However, the buffer layer 111 is not an essential component, and may be omitted based on the type and material of the substrate 110, structure and type of the thin film transistor 160, and the like.

A thin film transistor 160 for driving the organic light emitting element 170 is formed on the buffer layer 111. Specifically, an active layer 161 on which a channel of the thin film transistor 160 is formed is disposed on the buffer layer 111, and a gate electrode 162 is disposed on the active layer 161. A gate insulating layer 112 for insulating the active layer 161 from the gate electrode 162 is disposed between the active layer 161 and the gate electrode 162. The gate insulating layer 112 may be patterned to have the same width as the gate electrode 162, but is not limited thereto.

An interlayer insulating layer 113 is disposed on the gate electrode 162 and a source electrode 163 and a drain electrode 164 are disposed on the interlayer insulating layer 113 to form a gate insulating layer 112 and an interlayer insulating layer 113 ) Through the contact hole of the active layer 161. The active layer 161 may be formed of an oxide semiconductor such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), or ITZO (Indium Tin Zinc Oxide) For example, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

The gate electrode 162, the source electrode 163 and the drain electrode 164 may be formed of various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au) , Nickel (Ni), neodymium (Nd), and copper (Cu), two or more alloys thereof, or multilayers thereof.

The gate insulating layer 112 and the interlayer insulating layer 113 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx) . 2A, only the driving thin film transistor 160 is illustrated as a thin film transistor 160 for driving the organic light emitting element 170. However, the switching thin film transistor 160, the capacitor, Emitting element 170 may be disposed between the light-emitting element 170 and the light-

In the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 and the first power line VDD1 are disposed on the interlayer insulating layer 113. [ The first data line DL1 is a wire for supplying a data voltage to the first sub-pixel SP1 and the second sub-pixel SP2, and the first power line VDD1 is a line for supplying data voltages to the first sub- And supplies the high potential voltage to the two sub-pixels SP2.

The first data line DL1 and the first power line VDD1 may be formed of a conductive metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ni), neodymium (Nd), and copper (Cu), or two or more alloys, or multiple layers thereof. The first data line DL1 and the first power line VDD1 may be formed of the same material at the same time as the source electrode 163 and the drain electrode 164 on the interlayer insulating layer 113. [

A first planarization layer 114 is disposed on the thin film transistor 160, the first data line DL1, and the first power line VDD1. The first planarization layer 114 protects the thin film transistor 160 and smoothes the step on the substrate 110 by the thin film transistor 160, the first data line DL1 and the first power line VDD1 And an insulating layer for planarizing an upper portion of the substrate 110. [ The first planarization layer 114 may be formed of a material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, But is not limited thereto.

The second planarization layer 115 is disposed on the first planarization layer 114. The second planarizing layer 115 is an insulating layer for planarizing the first planarizing layer 114. The second planarization layer 115 may be formed of a material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, But is not limited thereto. The second planarization layer 115 may be formed of the same material as the first planarization layer 114.

In the OLED display 100 according to an exemplary embodiment of the present invention, the first planarization layer 114 and the second planarization layer 115 are used as planarization layers for planarizing the TFTs. Thus, an additional space in which the various wirings used in the OLED display 100 can be disposed can be provided. That is, as compared with the case where one planarization layer is used, the space between the first planarization layer 114 and the second planarization layer 115, that is, the additional planarization layer 114, Space can be provided. Therefore, in the organic light emitting diode display 100 according to the embodiment of the present invention, the degree of design freedom for wiring arrangement and the like can be increased.

The organic light emitting device 170 and the bank 116 are disposed on the second planarization layer 115. The organic light emitting device 170 includes an anode 171, an organic light emitting layer 172 on the anode 171, and a cathode 173 on the organic light emitting layer 172. Specifically, an anode 171 is disposed on the second planarization layer 115, and a bank 116 capable of defining the light emitting region of the organic light emitting element 170 is disposed over both sides of the anode 171 . The organic light emitting layer 172 is disposed on the anode 171 not covered with the bank 116 and the cathode 173 is disposed on the organic light emitting layer 172 and the bank 116. [ The organic light emitting layer 172 may be configured to emit light having a color that emits light at the corresponding sub-pixel. For example, as described above, when the first sub-pixel SP1 is a red sub-pixel and the second sub-pixel SP2 is a blue sub-pixel, the organic light emitting layer 172 of the first sub- And the organic light emitting layer 172 of the second sub-pixel SP2 may be configured to emit blue light. The fine metal mask (Fine Metal A spacer may be formed on the bank 116 to prevent damage to the organic light emitting device 170 that may be generated by the mask (FMM) directly contacting the bank 116 or the anode 171. [

Although only the organic emission layer 172 is illustrated as being disposed on the anode 171 in FIG. 2B, it is also possible to use an organic layer other than the organic emission layer 172, for example, at least one hole injection layer, Layer, a hole blocking layer and an electron transporting layer may additionally be disposed. The hole injecting layer, the hole transporting layer, the electron blocking layer, the electron injecting layer, the hole blocking layer or the electron transporting layer may be formed in the form of a single layer in common to all the sub-pixels.

A connection electrode CE for electrically connecting the thin film transistor 160 and the anode 171 is disposed on the first planarization layer 114. The two planarization layers 114 and 115 are disposed between the thin film transistor 160 and the organic light emitting device 170 so that the anode 171 and the thin film transistor 160 are electrically connected through a single contact hole forming process It can be difficult. In the OLED display 100 according to an exemplary embodiment of the present invention, a connection electrode CE electrically connected to the TFT 160 is disposed on the first planarization layer 114, The anode 171 disposed on the first planarization layer 115 may be connected to the connection electrode CE through the contact hole of the second planarization layer 115. [ The connecting electrode CE is formed of a conductive metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium Copper (Cu), or two or more alloys, or a multilayer thereof.

2B, the anode 171 is electrically connected to the source electrode 163 of the thin film transistor 160 through the connection electrode CE. However, depending on the type of the thin film transistor 160, The anode 171 may be configured to be electrically connected to the drain electrode 164 of the thin film transistor 160 through the connection electrode CE.

As shown in FIG. 2B, the anode 171 of the first sub-pixel SP1 and the second sub-pixel SP2 overlaps the first data line DL1. Therefore, when the OLED display 100 displays a single color, particularly when the color represented by either the first sub-pixel SP1 or the second sub-pixel SP2 is displayed, the first data line DL1, Pixel SP1 and the second sub-pixel SP2, and a voltage for turning off the other one of the first sub-pixel SP1 and the second sub-pixel SP2. Therefore, the data voltage applied through the first data line DL1 may have the form of an AC voltage. In this case, parasitic capacitance is generated between the first data line DL1 and the anode 171 of the first sub-pixel SP1 and the second sub-pixel SP2 as a data voltage having the form of an AC voltage is applied, A phenomenon may occur. Therefore, the sub-pixels to be turned on among the first sub-pixel SP1 and the second sub-pixel SP2 are changed or the sub-pixels to be turned off are driven to display an undesired color, Can occur.

Accordingly, in the OLED display 100 according to an embodiment of the present invention, a data voltage is applied to sub-pixels emitting different colors, that is, a first sub-pixel SP1 and a second sub-pixel SP2 The first wiring L1 is disposed between the first data line DL1 and the anode 171 of the first sub-pixel SP1 and the second sub-pixel SP2 overlapping the first data line DL1 . More specifically, the first wiring line L1 is connected only to the first data line DL1 and the first data line DL1 of the first power source line VDD1 between the first planarization layer 114 and the second planarization layer 115 As shown in FIG. The first wiring L1 may be formed of a conductive metal such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium And copper (Cu), or two or more alloys, or a multilayer thereof. In addition, the first wiring L1 may be formed of the same material as the connection electrode CE.

A constant voltage may be applied to the first wiring L1. As described above, the first data line DL1, the first sub-pixel SP1, and the second sub-pixel SP2, which may occur as the data voltage applied to the first data voltage has the form of an AC voltage, In order to reduce parasitic capacitance between the anode 171, a constant voltage may be applied to the first wiring L1. Here, the positive voltage applied to the first wiring L1 may be the same voltage as the high potential voltage applied through the first power supply line VDD1. Thus, the first wiring L1 can be electrically connected to the first power supply line VDD1 in the non-display area NA outside the display area DA.

2C, a thin film transistor 160, a first planarization layer 114, a connection electrode CE and an organic light emitting element 170 are arranged on a substrate 110 in a third sub-pixel SP3 do. Except that the color of the light emitted by the organic light emitting layer 172 of the organic light emitting element 170 of the third sub pixel SP3 is different from that of the first sub pixel SP1 and the second sub pixel SP2, The thin film transistor 160, the first planarization layer 114, the connection electrode CE and the organic light emitting diode 170 shown in FIG. 2B may include the thin film transistor 160, the first planarization layer 114, The electrode CE and the organic light emitting element 170, and thus redundant description will be omitted.

In the third sub-pixel SP3, the second data line DL2 and the second power line VDD2 are disposed on the interlayer insulating layer 113. [ The second planarization layer 115 may be disposed to cover the first data line DL1 and the first power line VDD1 as well as the second data line DL2 and the second power line VDD2. The second data line DL2 is a wiring for supplying a data voltage to the third sub pixel SP3 and the second power line VDD2 is a wiring for supplying a high potential voltage to the third sub pixel SP3 . The high-potential voltage supplied through the second power supply line VDD2 may be a constant voltage, and may be a constant voltage having a fixed value. The constant voltage supplied through the second power supply line VDD2 may be the same voltage as the constant voltage supplied through the first power supply line VDD1. Therefore, the first power supply line VDD1 and the second power supply line VDD2 can be electrically connected in the non-display area NA.

The second data line DL2 and the second power line VDD2 may be formed of a conductive metal such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ni), neodymium (Nd), and copper (Cu), or two or more alloys, or multiple layers thereof. The second data line DL2 and the second power line VDD2 may be formed of the same material at the same time as the source electrode 163 and the drain electrode 164 on the interlayer insulating layer 113. [

As shown in Fig. 2C, the anode 171 of the third sub-pixel SP3 overlaps with the second data line DL2. The second data line DL2 supplies the data voltage only to the third sub pixel SP3 so that the second data line DL2 and the third sub pixel SP3 are turned on when the OLED display 100 displays a single color, The parasitic capacitance does not occur between the anode 171 of the third data line DL2 and the anode 171 of the third sub-pixel SP3. Specifically, in the case where the organic light emitting diode display 100 displays the color represented by the first sub-pixel SP1 or the second sub-pixel SP2 and the color represented by the third sub-pixel SP3, The second data line DL2 supplies a data voltage in the form of a DC rather than an AC voltage. Therefore, a separate wiring for preventing the parasitic capacitance that may occur between the data line supplied to the second data line DL2 and the anode 171 of the third sub-pixel SP3 is not necessarily required.

In the OLED display 100 according to an embodiment of the present invention, the second power line VDD2 overlaps the second power line VDD2 for applying a high potential to the third sub-pixel SP3, And the second wiring L2 electrically connected to the second wiring line L2 is used. Specifically, the second wiring L2 is disposed between the first planarization layer 114 and the second planarization layer 115 so as to overlap the second power supply line VDD2. The second wiring line L2 may be formed of a conductive metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium And copper (Cu), or two or more alloys, or a multilayer thereof. The second wiring L2 may be formed of the same material as the connection electrode CE and the first wiring L1.

The second wiring L2 is electrically connected to the second power supply line VDD2 through the contact hole of the first planarization layer 114. [ 2A, the second wiring L2 is electrically connected to the second power line VDD2 and the second power line VDD2 in such a manner as to be in contact with the second power line VDD2 through a plurality of contact holes in the display area DA And can be electrically connected. The plurality of contact holes may be formed in all the third sub-pixels SP3, or may be formed in every third sub-pixel SP3

The second wiring L2 and the second power wiring VDD2 are electrically connected to each other through the plurality of contact holes in the display area DA and the second power line VDD2, (DA). Therefore, the voltage drop phenomenon that may occur in the second power supply line VDD2 can be reduced as compared with the case where the second power supply line VDD2 is used alone. That is, as the second wiring L2 and the second power wiring VDD2 are connected in parallel in the display area DA through the plurality of contact holes, the resistance of the wiring carrying the high- Can be reduced as compared with the case of transmitting the above voltage. Therefore, the voltage drop phenomenon of the high potential voltage transmitted through the second wiring line L2 and the second power supply line VDD2 is reduced, so that the power consumption of the organic light emitting diode display 100 can be improved, The luminance uniformity in the central region and the outer region in the apparatus 100 can be improved.

In the OLED display 100 according to an exemplary embodiment of the present invention, the first planarization layer 114 and the second planarization layer 115 may be used to provide a space in which additional wiring may be disposed. In the organic light emitting diode display 100 according to an exemplary embodiment of the present invention, the organic light emitting diode display 100 may include a plurality of sub-pixels SP1, SP2, and SP3 in consideration of a connection relationship between the data lines DL1 and DL2 and a plurality of sub- Additional wirings for preventing the performance degradation of the sub-pixels SP1, SP2, and SP3 may be selectively applied to the plurality of sub-pixels SP1, SP2, and SP3.

Specifically, a first data line DL1 for supplying a data voltage to the first sub-pixel SP1 and a second sub-pixel SP2 emitting light of different colors, a first data line DL2 for supplying a data voltage to the first sub- And the first wiring L1 may be disposed between the anode 171 of the second transistor SP2. Therefore, the phenomenon of interference between the first data line DL1 and the anode 171 of the first sub-pixel SP1 and the second sub-pixel SP2 can be suppressed. Since the second data line DL2 supplies the data voltage only to the third sub-pixel SP3, the second data line DL2 in the third sub-pixel SP3 and the second data line DL2 in the anode of the third sub- The second wiring L2 for reducing the resistance of the second power supply line VDD2 for supplying the high potential voltage to the third sub-pixel SP3 may be arranged without arranging the additional wiring between the first power supply line 171 and the third subpixel SP3. That is, in the organic light emitting diode display 100 according to an embodiment of the present invention, the problem of color change and luminance variation that may occur when one data line supplies data voltages to sub-pixels emitting different colors is solved In the first sub-pixel SP1 and the second sub-pixel SP2, the first wiring L1 is arranged so as to overlap the first data line DL1. When a data voltage is supplied to a sub-pixel in which one data line emits light of the same color, in order to reduce the voltage drop phenomenon in the second power supply line VDD2 for supplying a high-potential voltage to the sub-pixel, In the three sub-pixels SP3, the second wiring L2 is connected in parallel with the second power wiring VDD2 through the contact hole. Therefore, in the OLED display 100 according to an embodiment of the present invention, the arrangement and connection of additional wirings disposed on the first planarization layer 114 can be controlled by changing the voltage of the voltage supplied by the data lines DL1 and DL2 Type, the data lines DL1 and DL2, and the anode 171, the various performance of the OLED display 100 may be improved.

In the OLED display 100 according to an exemplary embodiment of the present invention, the first wiring line L1 and the second wiring line L2, which are disposed on the first planarization layer 114, And the first wiring L1 may be connected to the first power supply line in the non-display area NA while the second power supply line VDD2 is connected to the display area DA. Therefore, a contact hole of the first planarization layer 114 for connecting the first wiring L1 with another wiring in the display area DA is not required. The first planarization layer 114 should have a planarization function for planarizing the upper portion of the thin film transistor 160. However, if the number of contact holes formed in the first planarization layer 114 increases, the first planarization layer 114 may not provide a sufficient planarization function by a plurality of contact holes. Also, since there is a process margin in the process of forming the contact holes in the first planarization layer 114, it may be difficult to form an excessively large number of contact holes in the first planarization layer 114 . In the organic light emitting diode display 100 according to an exemplary embodiment of the present invention, the first wiring line L1 and the second wiring line L2 of the first planarization layer 114, Since the first wiring L1 is connected to the second power supply wiring VDD2 in the display area DA and the first wiring L1 is not connected to the other wiring in the display area DA, the planarization function of the first planarization layer 114 is ensured And the process for forming the contact hole in the first planarization layer 114 can be easily performed.

3A is a schematic plan view of an OLED display according to another embodiment of the present invention. FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A. 3C is a cross-sectional view taken along line IIIc-IIIc 'of FIG. 3A. The organic light emitting display device 200 shown in FIGS. 3A to 3C is different from the organic light emitting display device 100 shown in FIGS. 2A to 2C in that the anode 171 and the first wiring L1 and the second wirings L2 are different from each other and the other components are substantially the same, and redundant description will be omitted. 3B and 3C, the cross-sectional structures of the first sub-pixel SP1 and the second sub-pixel SP2 are substantially the same, so that the cross-sectional structures of the first sub-pixel SP1 and the second sub- Explain.

3A, the anode 271 of the organic light emitting diode 270 is connected to the first data line DL1, the second data line DL2, the first power line VDD1, the second power line VDD2, May be arranged to overlap with at least one of the various wirings. 3A, the anode 271 of the first sub-pixel SP1 and the anode 271 of the second sub-pixel SP2 overlap the second data line DL2 and the anode 271 of the second sub- 271 are overlapped with the first data line DL1.

As described above, since the first sub-pixel SP1 and the second sub-pixel SP2 emitting different colors receive the data voltage from the first data line DL1, the first data line DL1 ) And the first data line DL1 and the overlapping anode 271 may be a problem. In the OLED display 200 according to another embodiment of the present invention, the anode 271 and the anode 271 overlap with the first data line DL1 of the anode 271 of the plurality of sub-pixels SP1, SP2, , And a first wiring (L1) is disposed between the first data lines DL1. 3B and 3C will be referred to for a more detailed description of the cross-sectional structure of the OLED display 200. FIG.

3B and 3C, in the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 and the first power line VDD1 are arranged on the interlayer insulating layer 113 do. The first data line DL1 is a wire for supplying a data voltage to the first sub-pixel SP1 and the second sub-pixel SP2, and the first power line VDD1 is a line for supplying data voltages to the first sub- And supplies the high potential voltage to the two sub-pixels SP2. The high-potential voltage supplied through the first power supply line VDD1 may be a constant voltage and may be a constant voltage having a fixed value.

Referring to FIGS. 3B and 3C, the second data line DL2 and the second power line VDD2 are disposed on the interlayer insulating layer 113 in the third sub-pixel SP3. The second data line DL2 is a wiring for supplying a data voltage to the third sub pixel SP3 and the second power line VDD2 is a wiring for supplying a high potential voltage to the third sub pixel SP3 . The high-potential voltage supplied through the second power supply line VDD2 may be a constant voltage and may be a constant voltage having a fixed value. The constant voltage supplied through the second power supply line VDD2 may be the same voltage as the constant voltage supplied through the first power supply line VDD1. Therefore, the first power supply line VDD1 and the second power supply line VDD2 can be electrically connected to each other in the non-display area NA.

Referring to FIG. 3C, the anode 271 of the third sub-pixel SP3 overlaps the first data line DL1. When the organic light emitting diode display 200 displays a single color as described above, particularly when the color represented by any one of the first sub-pixel SP1 and the second sub-pixel SP2 is displayed, The wiring DL1 alternately supplies the voltage for turning on one of the first sub-pixel SP1 and the second sub-pixel SP2 and the voltage for turning off the other. Therefore, the data voltage applied through the first data line DL1 may have the form of an AC voltage. In this case, parasitic capacitance is generated between the first data line DL1 and the anode 271 of the third sub-pixel SP3 due to the application of the data voltage having the form of an AC voltage, so that an interference phenomenon may occur. Therefore, the third sub-pixel SP3 to be turned off is operated to display an undesired color, and a color change or a luminance variation may occur.

Accordingly, in the OLED display 200 according to another embodiment of the present invention, a data voltage is applied to the sub-pixels emitting different colors, that is, the first sub-pixel SP1 and the second sub-pixel SP2 The first wiring L1 is disposed between the first data line DL1 and the anode 271 of the third sub pixel SP3 overlapping the first data line DL1.

A constant voltage may be applied to the first wiring L1. As described above, the parasitic capacitance between the first data line DL1 and the anode 271 of the third sub-pixel SP3, which can occur as the data voltage applied to the first data voltage has the form of an AC voltage, A constant voltage may be applied to the first wiring L1. Here, the constant voltage applied to the first wiring L1 may be the same voltage as the high-potential voltage applied through the second power supply line VDD2. Thus, the first wiring L1 can be electrically connected to the first power supply line VDD1 in the non-display area NA outside the display area DA.

The first wiring L1 may be electrically connected to the second power supply line VDD2 through a plurality of contact holes of the first planarization layer 114 in the display area DA. 3A and 3C, the first wiring L1 may include a plurality of protruding portions PR protruding to overlap with the second power source wiring VDD2. The plurality of protrusions PR can be in contact with the second power supply line VDD2 through the contact holes of the first planarization layer 114 on the second power supply line VDD2. A plurality of contact holes may be formed in all the third sub-pixels SP3, or may be formed in every third sub-pixel SP3. The plurality of protruding portions PR may be formed simultaneously with the same material as the first wiring L1.

The first wiring L1 and the second power line VDD2 are electrically connected to each other through the plurality of contact holes in the display area DA and the second power line VDD2, (DA). Therefore, the voltage drop of the high-potential voltage transmitted through the first wiring L1 and the second power supply line VDD2 can be reduced to improve the power consumption of the OLED display 200, The luminance uniformity in the central region and the outer region in the apparatus 200 can be improved.

Referring to FIG. 3B, the anode 271 of the first sub-pixel SP1 overlaps the second data line DL2. Since the second data line DL2 supplies the data voltage only to the third sub-pixel SP3, when the OLED display 200 displays a single color, the second data line DL2 and the first sub- And the anode 271 of the second sub-pixel SP1 and the second sub-pixel SP2 without generating parasitic capacitance between the second data line DL2 and the anode 271 of the second sub-pixel SP2, The interference phenomenon does not occur. Specifically, when the organic light emitting diode display 200 displays the color represented by the first sub-pixel SP1 or the second sub-pixel SP2 and the color represented by the third sub-pixel SP3, The second data line DL2 supplies a data voltage in the form of a DC rather than an AC voltage. Therefore, a separate wiring for preventing the parasitic capacitance that may occur between the data line supplied to the second data line DL2 and the anode 271 of the first sub-pixel SP1 and the second sub-pixel SP2 It is not absolutely necessary.

In the OLED display 200 according to another embodiment of the present invention, the second wiring line L2 disposed in the first planarization layer 114 is connected to the first power line VDD1 or the second data line DL2. The first data line VDD1 or the second data line DL2 may overlap the first power line VDD1 or the second data line DL2. However, the first sub-pixel SP1 and the second sub-pixel SP2 overlapping the third sub-pixel SP3 and the second data line DL2, to which the data voltage is applied through the second data line DL2, And are sub-pixels emitting different colors. 3B, in order to minimize an interference phenomenon between the second data line DL2 and the anode 271 of the first sub-pixel SP1 and the second sub-pixel SP2, the second wiring L2 May be disposed between the second data line DL2 and the anode 271 of the first sub-pixel SP1 and the second sub-pixel SP2. However, the arrangement position of the second wiring L2 is not limited thereto.

A constant voltage may be applied to the second wiring L2. That is, in order to minimize the interference phenomenon between the second data line DL2 and the anode 271 of the first sub-pixel SP1 and the second sub-pixel SP2, a positive voltage may be applied to the first wiring L1 have. Here, the constant voltage applied to the second wiring line L2 may be the same voltage as the high-potential voltage applied through the first power source line VDD1. Thus, the second wiring line L2 can be electrically connected to the first power source line VDD1 in the non-display area NA outside the display area DA.

In some embodiments, the second wiring L2 may be electrically connected through the plurality of contact holes in the display area DA and the first power supply line VDD1. The second wiring L2 is electrically connected to the first power supply line VDD1 through the plurality of contact holes of the first planarization layer 114 when the second wiring L2 is arranged so as to overlap with the first power supply wiring VDD1, In a direct manner. Next, as shown in FIG. 3B, when the second wiring L2 is arranged so as to overlap with the second data wiring DL2, the second wiring L2 protrudes so as to overlap with the first power wiring VDD1 And may include a plurality of protrusions. That is, the second wiring L2 is electrically connected to the first power line (VDD1) through a plurality of projections contacting the first power line VDD1 through the plurality of contact holes of the first planarization layer 114 on the first power line VDD1 VDD1).

4A is a schematic plan view of an OLED display according to another embodiment of the present invention. 4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A. The organic light emitting display 300 shown in FIGS. 4A and 4B is different from the organic light emitting display 200 shown in FIGS. 2A to 2C in that the first wiring L1 and the first power wiring VDD1 are different from each other And the other components are substantially the same, so redundant description is omitted. In addition, the sectional structure in the third sub-pixel SP3 in FIG. 4A, that is, the sectional structure in accordance with IIc-IIc 'is substantially the same as the sectional structure in the third sub-pixel SP3 shown in FIG. Duplicate descriptions are omitted. In FIG. 4B, the sectional structures of the first sub-pixel SP1 and the second sub-pixel SP2 are substantially identical to each other, so the cross-sectional structures of the first sub-pixel SP1 and the second sub-pixel SP2 will be described together.

4A and 4B, the anode 371 of the organic light emitting diode 370 of the first sub-pixel SP1 and the second sub-pixel SP2 overlaps the first data line DL1. Accordingly, in the OLED display 300 according to another embodiment of the present invention, the data voltages are applied to the sub-pixels emitting different colors, that is, the first and second sub-pixels SP1 and SP2. The first wiring L1 is disposed between the first data line DL1 for overlapping the first data line DL1 and the anode 371 of the first sub-pixel SP1 and the second sub-pixel SP2 overlapping the first data line DL1 do. Therefore, the color change or the luminance variation in the organic light emitting diode display 300 according to another embodiment of the present invention can be minimized.

Further, a constant voltage may be applied to the first wiring L1. Between the first data line DL1 and the anode 371 of the first sub-pixel SP1 and the second sub-pixel SP2, which may occur as the data voltage applied to the first data voltage has the form of an AC voltage, A constant voltage may be applied to the first wiring L1 to reduce the parasitic capacitance of the first wiring L1. Here, the positive voltage applied to the first wiring L1 may be the same voltage as the high potential voltage applied through the first power supply line VDD1. Thus, the first wiring L1 can be electrically connected to the first power supply line VDD1 in the non-display area NA outside the display area DA. The first wiring L1 may be electrically connected to the first power supply line VDD1 through a plurality of contact holes of the first planarization layer 114 in the display area DA. 4A and 4B, the first wiring L1 may include a plurality of protruding portions PR protruding to overlap with the first power source wiring VDD1. The plurality of protrusions PR can be in contact with the first power supply line VDD1 through the contact holes of the first planarization layer 114 on the first power supply line VDD1. A plurality of contact holes may be formed in all the first sub-pixel SP1 and the second sub-pixel SP2 or may be formed at specific periods of the first sub-pixel SP1 and the second sub-pixel SP2 . The plurality of protruding portions PR may be formed simultaneously with the same material as the first wiring L1.

The first wiring L1 and the first power wiring VDD1 are electrically connected to each other through the plurality of contact holes in the display region DA and the first power supply line VDD1, (DA). Therefore, the voltage drop phenomenon of the high potential voltage transmitted through the first wiring line L1 and the first power source line VDD1 is reduced, so that the power consumption of the organic light emitting display device 300 can be improved, The luminance uniformity in the central region and the peripheral region in the apparatus 300 can be improved.

5 to 7 are schematic plan views of an organic light emitting diode display according to various embodiments of the present invention. The organic light emitting diode display 400 shown in FIG. 5 has a connection wiring CL as compared with the organic light emitting display 100 shown in FIGS. 2A to 2C, and the other components are substantially the same, Is omitted. The organic light emitting diode display 500 shown in FIG. 6 is different from the OLED display 200 shown in FIGS. 3A to 3C in that the connection wiring CL is added, and the other components are substantially the same, Is omitted. The organic light emitting diode display 600 shown in FIG. 7 is different from the OLED display 300 shown in FIGS. 4A and 4B in that a connection wiring line CL is added, and other components are substantially identical, Is omitted.

5 to 7, the connection wiring CL electrically connects the first wiring L1 and the second wiring L2. The connection wiring CL is disposed so as to intersect on the same plane as the first wiring L1 and the second wiring L2. That is, the connection wiring line CL can be formed simultaneously with the same material as the first wiring line L1 and the second wiring line L2. Thus, the connection wiring CL, the first wiring L1 and the second wiring L2 can be integrally formed on the first planarization layer 114 and have the same potential.

5 to 7, the connection wiring CL constitutes a grid wiring GL together with the first wiring L1 and the second wiring L2. The lattice wiring GL is a wiring having a lattice shape and composed of a connection wiring CL extending in the transverse direction and a first wiring L1 and a second wiring L2 extending in the longitudinal direction in Figs.

The voltage drop phenomenon in the second power supply line VDD2 can be reduced as the connection wiring CL, the first wiring L1 and the second wiring L2 are connected to each other to form the grid wiring GL. Specifically, since the connection wirings CL are additionally disposed and the first wirings L1, the second wirings L2 and the connection wirings CL provide the same potential in the display area DA in a lattice form, The resistance of the wiring for transferring the high potential voltage to the sub-pixel SP3 can be reduced as compared with the case where the grid wiring GL is not used. Therefore, the voltage drop phenomenon of the high potential voltage transmitted through the second power supply line VDD2 can be reduced. Since the second power supply line VDD2 and the first power supply line VDD1 can be electrically connected in the non-display area NA, the voltage drop phenomenon of the high potential voltage transmitted through the first power supply line VDD1 also Can be reduced. In particular, in the OLED display 600 shown in FIG. 7, since the lattice wiring GL can be electrically connected to the first power supply line VDD1 through the plurality of contact holes in the display area DA, The voltage drop phenomenon of the high potential voltage transmitted through the power supply line VDD1 and the second power supply line VDD2 can also be reduced. Accordingly, the power consumption of the organic light emitting display devices 400, 500 and 600 can be improved more effectively and the luminance uniformity in the central area and the peripheral area can be more effectively improved in the organic light emitting display devices 400, .

The first wirings L1 are connected to the second wirings L2 through the connection wirings CL more effectively so that the first wirings L1 are connected to the first data lines DL1 and the first wirings L1, 371 can be reduced. As described above, in order to reduce the interference phenomenon between the first data line DL1 and the anode 171, 271 and 371, the first data line DL1 and the anode 171, 271, A constant voltage is applied to the first wiring L1. 5 to 7, the first interconnection line L1 forms the interconnection line CL and the second interconnection line L2 and the interconnection line GL, and the interconnection line GL includes the plurality of interconnection lines CL, The second power supply line VDD2 and the first power supply line VDD1 are electrically connected to each other in the display area DA through the holes so that a more stable constant voltage can be provided to the first wiring L1. Therefore, the interference phenomenon caused by the parasitic capacitance occurring between the first data line DL1 and the anodes 171, 271, and 371 can be more effectively reduced.

An exemplary embodiment of the present invention can be described as follows.

An OLED display according to an embodiment of the present invention includes a substrate having a display region including a plurality of sub-pixels each having an anode, an organic light-emitting layer, and a cathode, a substrate disposed on the substrate, A first data line for applying a first data voltage to a first sub-pixel emitting a color and a second sub-pixel emitting a second color different from the first color and a first data line overlapping the first data line among the anodes of the plurality of sub- And a first wiring disposed between the anode and the first data wiring.

According to another aspect of the present invention, a constant voltage may be applied to the first wiring.

According to another aspect of the present invention, the first sub-pixel and the second sub-pixel may be alternately arranged in the same column.

According to another aspect of the present invention, an OLED display further includes a first power line for applying a high potential voltage to the first sub-pixel and the second sub-pixel, the first line includes a first data line, It can be overlapped with the first data line among the power lines.

According to another aspect of the present invention, an OLED display includes a first data line and a second data line, each of which applies a second data voltage to a third sub-pixel that emits a third color different from the first color and the second color, A second power line and a second data line for applying a high potential voltage to the third sub-pixel, and a second line disposed on the first power line or the second power line.

According to another aspect of the present invention, the anode of the first sub-pixel and the anode of the second sub-pixel overlap with the first data line, the anode of the third sub-pixel overlaps with the second data line, And the second wiring is in contact with the second power supply wiring through the plurality of contact holes of the planarization layer disposed on the second power supply wiring.

According to another aspect of the present invention, the first wiring may include a plurality of protrusions, which are respectively in contact with the first power supply wiring through the contact holes of the planarization layer disposed on the first power supply wiring.

According to still another aspect of the present invention, the anode of the first sub-pixel and the anode of the second sub-pixel overlap with the second data line, the anode of the third sub-pixel overlaps with the first data line, And a plurality of protrusions which are respectively in contact with the second power supply wiring through contact holes of the planarization layer disposed on the second power supply wiring and the second wiring can be electrically connected to the first power supply wiring outside the display area.

According to another aspect of the present invention, the second wiring may be electrically connected to the first power source wiring through the plurality of contact holes in the display region.

According to another aspect of the present invention, an OLED display includes a first planarization layer covering a first data line, a second data line, a first power line, and a second power line, and a second planarization layer on the first planarization layer, Wherein the first wiring and the second wiring are disposed between the first planarization layer and the second planarization layer and the anode of the plurality of subpixels may be disposed on the second planarization layer.

According to another aspect of the present invention, each of the first sub-pixel and the second sub-pixel may be one of a red sub-pixel and a blue sub-pixel, and the third sub-pixel may be a green sub-pixel.

According to another aspect of the present invention, an organic light emitting diode display device further includes a connection wiring which crosses the first wiring and the second wiring on the same plane, and electrically connects the first wiring and the second wiring, , The second wiring and the connection wiring are in a lattice shape and can have the same potential.

The organic light emitting display according to another embodiment of the present invention includes a first data line for supplying a data voltage to sub-pixels emitting different colors, a plurality of data lines arranged to overlap with the first data line on the first data line, In order to reduce the interference between the first data line and the first anode and to reduce the fluctuation of the luminance in the sub-pixels having the plurality of first anodes in displaying the one anode and the single color, And a first wiring disposed between the first wiring and the second wiring.

According to another aspect of the present invention, a voltage for reducing the parasitic capacitance between the first data line and the first anode may be supplied to the first wiring.

According to another aspect of the present invention, an OLED display device includes a second data line that is different from sub-pixels that emit different colors and supplies a data voltage to sub-pixels that emit the same color, A first power supply line for supplying a high potential voltage to sub-pixels emitting different colors, a second power supply line for supplying a high potential voltage to the sub-pixels emitting the same color, And a second wiring disposed on the same layer as the second power supply wiring and the first wiring to be supplied.

According to still another aspect of the present invention, the first wiring is provided between the first power supply wiring or the second power supply wiring and the first power supply wiring and the second power supply wiring so as to reduce the wiring resistance of the first power supply wiring or the second power supply wiring, And may be electrically connected through a plurality of contact holes of the planarization layer disposed on the planarization layer.

According to another aspect of the present invention, there is provided an organic light emitting diode display comprising a first wiring and a second wiring formed integrally with each other to form a lattice shape, and further comprising a connection wiring for reducing wiring resistance in the first wiring and the second wiring .

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

110: substrate
111: buffer layer
112: gate insulating layer
113: interlayer insulating layer
114: first planarization layer
115: second planarization layer
116: Bank
170, 270, 370: organic light emitting element
171, 271, 371: anode
172: organic light emitting layer
173: Cathode
120: Gate driver
130: Data driver
140, 150: Wiring
160: thin film transistor
161: active layer
162: gate electrode
163: source electrode
164: drain electrode
100, 200, 300, 400, 500, 600: organic light emitting display
DA: Display area
NA: non-display area
GL: Grating wiring
L1: first wiring
L2: second wiring
CL: Connection wiring
DL1: first data line
DL2: second data line
VDD1: first power supply wiring
VDD2: Second power supply wiring
SP1: first sub-pixel
SP2: second sub-pixel
SP3: Third sub-pixel
CE: connecting electrode
PR:

Claims (17)

A substrate provided with a display region including a plurality of sub-pixels each having an anode, an organic light-emitting layer, and a cathode;
A first sub-pixel disposed on the substrate and adapted to apply a first data voltage to a first sub-pixel emitting a first color of the plurality of sub-pixels and a second sub-pixel emitting a second color different from the first color, Data wiring; And
And an anode overlapping the first data line among anodes of the plurality of sub-pixels, and a first wiring disposed between the first data line and the anode. The method according to claim 1,
And a positive voltage is applied to the first wiring. The method according to claim 1,
And the first sub-pixel and the second sub-pixel are alternately arranged in the same column. The method according to claim 1,
And a first power wiring line for applying a high potential voltage to the first sub-pixel and the second sub-pixel,
Wherein the first wiring overlaps the first data wiring among the first data wiring and the first power supply wiring. 5. The method of claim 4,
A second data line for applying a second data voltage to a third sub-pixel which emits a third color different from the first color and the second color among the plurality of sub-pixels;
A second power supply line for applying a high potential voltage to the third sub-pixel; And
And a second wiring disposed on the second data line, the first power line, or the second power line. 6. The method of claim 5,
The anode of the first sub-pixel and the anode of the second sub-pixel overlap the first data line,
The anode of the third sub-pixel overlaps with the second data line,
The first wiring is electrically connected to the first power supply wiring outside the display region,
And the second wiring is in contact with the second power supply wiring via a plurality of contact holes of the planarization layer disposed on the second power supply wiring. The method according to claim 6,
Wherein the first wiring includes a plurality of protrusions which are in contact with the first power supply wiring through contact holes of the planarization layer disposed on the first power supply wiring. 6. The method of claim 5,
The anode of the first sub-pixel and the anode of the second sub-pixel overlap the second data line,
The anode of the third sub-pixel overlaps with the first data line,
Wherein the first wiring includes a plurality of protrusions which are respectively in contact with the second power supply wiring through contact holes of the planarization layer disposed on the second power supply wiring,
And the second wiring is electrically connected to the first power supply wiring outside the display region. 9. The method of claim 8,
And the second wiring is electrically connected through the plurality of contact holes in the display region with the first power supply wiring. 6. The method of claim 5,
A first planarization layer covering the first data line, the second data line, the first power line, and the second power line; And
And a second planarization layer on the first planarization layer,
The first wiring and the second wiring are disposed between the first planarization layer and the second planarization layer,
And the anode of the plurality of sub-pixels is disposed on the second planarization layer. 6. The method of claim 5,
Wherein each of the first sub-pixel and the second sub-pixel is one of a red sub-pixel and a blue sub-pixel,
And the third sub-pixel is a green sub-pixel. 12. The method according to any one of claims 5 to 11,
Further comprising a connection wiring which crosses on the same plane as the first wiring and the second wiring and electrically connects the first wiring and the second wiring,
Wherein the first wiring, the second wiring, and the connection wiring have a lattice shape and have the same potential. A first data line supplying a data voltage to sub-pixels emitting different colors;
A plurality of first anodes arranged to overlap with the first data lines on the first data line; And
The first data line and the first anode are reduced to reduce the fluctuation of the luminance in the sub-pixels having the plurality of first anodes, And a first wiring disposed between the first anode and the first anode. 14. The method of claim 13,
Wherein a voltage for reducing a parasitic capacitance between the first data line and the first anode is supplied to the first wiring. 14. The method of claim 13,
A second data line which is different from the sub-pixels emitting different colors and supplies a data voltage to sub-pixels emitting the same color;
A plurality of second anodes arranged to overlap the second data lines on the second data lines;
A first power supply line for supplying a high potential voltage to the sub-pixels emitting the different colors;
A second power supply line for supplying a high potential voltage to the sub-pixels emitting the same color; And
And a second wiring disposed on the same layer as the first wiring. 16. The method of claim 15,
The first wiring is arranged on the first power supply wiring or the second power supply wiring and the first power supply wiring and the second power supply wiring so as to reduce the wiring resistance of the first power supply wiring or the second power supply wiring And the plurality of contact holes of the planarization layer are electrically connected to each other. 17. The method of claim 16,
And a connection wiring which is formed integrally with the first wiring and the second wiring to form a lattice shape and to reduce wiring resistance in the first wiring and the second wiring.

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