KR102061764B1 - Electrostatic discharge circuit and display device having thereof - Google Patents

Abstract

The present invention discloses an electrostatic discharge circuit and a display device having the same. The disclosed electrostatic discharge circuit includes a first lower gate electrode, a first channel layer, a first source electrode, a first drain, and a first upper gate electrode overlapping the first lower gate electrode and the first channel layer. A first thin film transistor; A second thin film transistor including a second lower gate electrode, a second channel layer, the first source electrode, a second drain electrode, and a second upper gate electrode overlapping the second lower gate electrode and the second channel layer; And a third thin film transistor including a third lower gate electrode, a third channel layer, a second source electrode, the first drain electrode, and a third upper gate electrode overlapping the third lower gate electrode and the third channel layer. The first to third upper gate electrodes may be electrically connected to each other.
The electrostatic discharge circuit of the present invention and the display device having the same have the effect of reducing the leakage current generated in the electrostatic discharge circuit when the non-driving thin film transistor of the electrostatic discharge circuit formed on the display display device has a dual gate structure.

Description

Electrostatic discharge circuit and a display device having the same {ELECTROSTATIC DISCHARGE CIRCUIT AND DISPLAY DEVICE HAVING THEREOF}

The present invention relates to an electrostatic discharge circuit and a display device having the same capable of reducing leakage current and reducing the design area of the electrostatic discharge circuit.

Liquid crystal display, one of the flat panel display elements, is an element that changes the optical anisotropy by applying an electric field to a liquid crystal that combines the liquidity and the optical properties of the crystal, and has a low power consumption and a large volume as compared to a conventional cathode ray tube. It is small and is widely used because it can be enlarged and fixed.

Such a liquid crystal display device has a variety of modes depending on the nature of the liquid crystal and the structure of the pattern.

That is, TN mode (Twisted Nematic Mode) for arranging the liquid crystal directors to be twisted by 90 ° and then applying voltage to control the liquid crystal directors, and dividing one pixel into several domains to realize the wide viewing angle by changing the main viewing angle direction of each domain. Multi-Domain Mode, OCB Mode (Optically Compensated Birefringence Mode), which compensates the phase change of light according to the direction of light by attaching a compensation film to the outer peripheral surface of the substrate, and two electrodes on one substrate. In-plane switching mode in which the directors of the liquid crystal are twisted in the parallel plane of the alignment layer, and VA mode in which the long axis of the liquid crystal molecules is vertically aligned with the alignment layer plane by using the negative type liquid crystal and the vertical alignment layer. Vertical Alignment).

In particular, pixel areas are defined in the LCD panel by arranging a plurality of gate lines and a plurality of data lines. A thin film transistor (TFT) is disposed in an intersection region of the gate line and the data line, and according to the operation of the thin film transistor, a data signal supplied from the data line is supplied to the pixel electrode disposed in the pixel region to supply an electric field. Form.

In addition, each of the gate lines and the data lines of the liquid crystal display device has an electrostatic discharge circuit such as an equivalent circuit of FIG. Is placed.

In a display device such as a liquid crystal display, thin film transistors having an amorphous silicon layer (a-Si) as a channel layer have been used as an electrostatic discharge circuit element in a pixel region or a pad region of a liquid crystal display panel. Thin film transistors having an oxide semiconductor layer (a-IGZO) as a channel layer having excellent time current characteristics have been applied.

1 is a graph illustrating leakage current characteristics in a driving voltage of an electrostatic discharge circuit composed of conventional amorphous silicon thin film transistors and an oxide semiconductor thin film transistor, and FIG. 2 illustrates a conventional amorphous silicon thin film transistors. The electrostatic discharge circuit composed of the electrostatic discharge circuit and the oxide semiconductor thin film transistors is a graph showing the leakage current characteristics in the off voltage, Figure 3 is a graph of the electrostatic discharge circuit according to the width and length of the channel layer of the oxide semiconductor thin film transistor A graph comparing leakage current.

A1 to A3 are electrostatic discharge circuits applying oxide semiconductor thin film transistors, and B is an electrostatic discharge circuit applying amorphous silicon thin film transistors.

In addition, the channel width (W) and length (L) of the oxide semiconductor thin film transistor of A1 are 4/25 μm, A2 is 4/40 μm, A3 is 4/75 μm, and B is the channel width of the amorphous silicon thin film transistor ( W) and the length L are 10/20 micrometers.

 1 to 3, as shown in FIG. 1, the electrostatic discharge circuit A1 including the oxide semiconductor thin film transistors having a driving voltage supplied to the data line and the gate line in a range of 6V to 20V includes the amorphous silicon thin film transistors. It can be seen that the current characteristics are higher than the antistatic circuit (B).

This is because the electron mobility of the oxide semiconductor layer is higher than that of amorphous silicon (FIG. 2). On the contrary, in the off voltage (non-driving voltage: approximately 6V or less) region, the leakage current includes the oxide semiconductor layer. Larger ones can be seen in the electrostatic discharge circuit.

As shown in Fig. 3, when using the thin film transistor of A1 (4/25 mu m) having a channel width and length similar to that of the electrostatic discharge circuit B using the amorphous silicon thin film transistor, the leakage current is 4 times larger. can see.

As such, when the leakage current increases, power consumption increases, so it is necessary to reduce the leakage current. Based on the graph of FIG. 3, when the oxide semiconductor thin film transistor is used, the leakage current is reduced to a level similar to that of the amorphous silicon thin film transistor. In order to reduce, a problem arises in that the channel layer length L of the oxide semiconductor must be extended to 75 µm, such as A3 (4/75 µm).

In addition, when the length L of the channel layer of the oxide semiconductor is long, it is difficult to implement a high resolution display device due to the limitation of the design area.

The present invention provides a electrostatic discharge circuit and a display device having the same by reducing the leakage current generated in the electrostatic discharge circuit when the non-driven thin film transistor of the electrostatic discharge circuit formed on the display display device in a dual gate structure. There is this.

The present invention also provides an electrostatic discharge in which a thin film transistor of an electrostatic discharge circuit formed in a display display device is formed in a dual gate structure, and a leakage current of the electrostatic discharge circuit is prevented by applying a voltage opposite to the gate driving voltage to the upper gate electrode. Another object is to provide a circuit and a display device having the same.

The electrostatic discharge circuit of the present invention for solving the above problems of the prior art, the first lower gate electrode, the first channel layer, the first source electrode, the first drain and the first lower gate electrode and the first channel layer. A first thin film transistor including a first upper gate electrode overlapping the first thin film transistor; A second thin film transistor including a second lower gate electrode, a second channel layer, the first source electrode, a second drain electrode, and a second upper gate electrode overlapping the second lower gate electrode and the second channel layer; And a third thin film transistor including a third lower gate electrode, a third channel layer, a second source electrode, the first drain electrode, and a third upper gate electrode overlapping the third lower gate electrode and the third channel layer. The first to third upper gate electrodes may be electrically connected to each other.

In addition, a display device including an electrostatic discharge circuit according to the present invention includes a liquid crystal display panel including a plurality of gate lines and data lines and a pixel region defined by them; A gate driver and a data driver supplying a display signal to the liquid crystal display panel; A backlight unit supplying a light source to the liquid crystal display panel; A signal controller supplying a display signal and a control signal to the gate driver, the data driver, and the backlight unit; And at least one electrostatic discharge circuit connected to each of the plurality of gate lines and data lines, wherein one end of the electrostatic discharge circuit is connected to each of the plurality of gate lines and data lines. And, the other end is characterized in that connected to the common line.

The electrostatic discharge circuit of the present invention and the display device having the same have the effect of reducing the leakage current generated in the electrostatic discharge circuit when the non-driving thin film transistor of the electrostatic discharge circuit formed on the display display device in a dual gate structure.

In addition, the present invention has the effect of forming the thin film transistor of the electrostatic discharge circuit formed in the display display device in a dual gate structure, and applying a voltage opposite to the gate driving voltage to the upper gate electrode to prevent leakage current of the electrostatic discharge circuit. have.

1 is a graph illustrating leakage current characteristics within a driving voltage of a conventional static discharge circuit composed of amorphous silicon thin film transistors and an electrostatic discharge circuit composed of oxide semiconductor thin film transistors.
2 is a graph illustrating leakage current characteristics in an off voltage of a conventional static discharge circuit composed of amorphous silicon thin film transistors and an electrostatic discharge circuit composed of oxide semiconductor thin film transistors.
3 is a graph comparing leakage current of an electrostatic discharge circuit according to a width and a length of a channel layer of an oxide semiconductor thin film transistor.
4 is a block diagram showing the structure of a liquid crystal display of the present invention.
FIG. 5 is an equivalent circuit diagram of the electrostatic discharge circuit of FIG. 4.
6 is a view showing the structure of an electrostatic discharge circuit according to the present invention.
FIG. 7 is a cross-sectional view taken along line II ′ of FIG. 6.
8 is a graph showing the threshold voltage characteristics of the oxide semiconductor thin film transistor used in the electrostatic discharge circuit of the present invention.
9 is a graph showing the current characteristics of the electrostatic discharge circuit of the present invention.
FIG. 10 is an enlarged view of region X of FIG. 9.
11 is a graph showing discharge characteristics of the electrostatic discharge circuit.
12 is a graph showing current characteristics according to channel layer length of a dual gate structure thin film transistor formed in an electrostatic discharge circuit of the present invention.
FIG. 13 is a graph showing discharge characteristics of channel layers of dual gate structure thin film transistors formed in the electrostatic discharge circuit of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

In addition, although a liquid crystal display device will be described here, the same applies to a flat panel display device such as an organic light emitting display device.

4 is a block diagram showing the structure of a liquid crystal display of the present invention.

Referring to FIG. 4, the liquid crystal display according to the present invention includes a liquid crystal display panel 30, a gate driver 40, a data driver 50, and a gray voltage generator 80 connected to the data driver 50. The backlight unit includes a DC-DC converter 91, a light source unit 92 connected to the DC-DC converter 91, and a signal controller 60 for controlling the backlight unit.

In the equivalent circuit, the liquid crystal display panel 30 is connected to a plurality of gate lines and data lines G1 -Gn and D1 -Dm, and a plurality of pixels P arranged in a substantially matrix form. Include them. In addition, although not shown in the drawings, the liquid crystal display panel 30 includes a lower and upper substrate facing each other and a liquid crystal layer interposed between the two. The lower substrate is a substrate including a pixel electrode and a thin film transistor, and the upper substrate is a substrate including a color filter layer.

The gate lines G1 -Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 -Dm extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q (TFT) connected to a gate line (G1-Gn) and a data line (D1-Dm), a liquid crystal capacitor (CLC), and a storage capacitor (CST) connected thereto. It includes. The storage capacitor functions to maintain a data signal applied to the pixel region for a predetermined time.

The switching element Q of each pixel is connected to a control terminal connected to the gate lines G1 -Gn, an input terminal connected to the data lines D1 -Dm, and a liquid crystal capacitor CLC and a storage capacitor CST. It is a three-terminal device with an output terminal connected.

The backlight unit for supplying a light source to the liquid crystal display panel 30 includes a DC-DC converter 91 and a light source 92, and the DC-DC converter 91 is a direct current voltage from the signal controller 60. And a control signal to drive a plurality of LEDs or lamps mounted on the light source unit 92. In the present invention, the DC-DC converter 91 is mounted on an internal printed circuit board on which the signal controller 60, the gate driver 40, the data driver 50, and the like are mounted, and the light source 92 is ripple. It is mounted on an external printed circuit board with a removal capacitor.

In addition, in the present invention, an electrostatic discharge circuit ESD is disposed in each of the gate lines G1, ... Gn and the data lines D1, .. Dn. In the electrostatic discharge circuit ESD formed in each of the gate lines and the data lines, two or more electrostatic discharge circuits ESD may be connected in series.

Although only the structure in which the electrostatic discharge circuit ESD is connected in series is shown, the electrostatic discharge circuits ESD may be connected in parallel with the gate lines or the data lines, respectively.

When the electrostatic discharge circuits ESD are connected in series, one terminal is connected to one edge of the gate line or data line, and the other terminal is a common line Vcom or ground GND formed in the liquid crystal display panel 30. ) Can be connected. However, the other terminal of the electrostatic discharge circuit ESD may be connected to a signal line capable of supplying a reference voltage from the data driver 50 or the gate driver 40.

In addition, when at least two electrostatic discharge circuits (ESD) are connected to the gate line or the data line, they may be connected in parallel. In this case, it may be connected to a power supply voltage VDD or a gate low voltage VGL supply line.

In addition, the switching elements formed in the pixel region of the present invention and the thin film transistors formed in the electrostatic discharge circuit have an oxide semiconductor (a-IGZO) as a channel layer. In addition, the oxide semiconductor thin film transistor formed in the electrostatic discharge circuit may have a dual gate structure in which a lower gate electrode is formed below the channel layer and an upper gate electrode is formed above the channel layer.

In addition, the upper gate electrodes of the oxide semiconductor thin film transistor of the electrostatic discharge circuit of the present invention are electrically connected to each other and receive a voltage opposite to the lower gate electrode from the gate driver 40 or the data driver 50. Thus, the threshold voltage Vth of the oxide thin film transistor formed in the electrostatic discharge circuit is shifted by ΔV to reduce the leakage current of the electrostatic discharge circuit ESD.

FIG. 5 is an equivalent circuit diagram of the electrostatic discharge circuit of FIG. 4, FIG. 6 is a diagram illustrating the structure of the electrostatic discharge circuit according to the present invention, and FIG. 7 is a cross-sectional view taken along line II ′ of FIG. 6.

5 to 7, the electrostatic discharge circuit ESD may include a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.

The source electrode of the first thin film transistor T1 is connected to the gate electrode of the second thin film transistor T2, and the gate electrode is electrically connected to the drain electrode of the second thin film transistor T2 and the source electrode of the third thin film transistor T2. The drain electrode is electrically connected to the gate electrode and the drain electrode of the third thin film transistor T3.

The source electrode of the second thin film transistor T2 is connected to the source electrode of the first thin film transistor T1 and the gate electrode of the second thin film transistor T2.

In addition, the gate electrode of the third thin film transistor T3 is connected to the drain electrode of the first thin film transistor T1 and the drain electrode of the third thin film transistor T3.

Although each of the thin film transistors T1, T2, and T3 is named as a gate electrode, a source electrode, and a drain electrode, referring to FIG. 6, the source electrode and the second thin film transistor (T1) of the first thin film transistor T1 ( The source electrode of T2) is formed integrally with one electrode. In addition, the drain electrode of the first thin film transistor T1 is integrally formed with the drain electrode of the third thin film transistor T3. Thus, these electrodes are represented by one first source electrode 117 and first drain electrode 118, but serve as source or drain electrodes for two thin film transistors.

In the electrostatic discharge circuit ESD having the above structure, one terminal is connected to the gate line or the data line, and the other terminal is connected to the common line Vcom of the liquid crystal display device.

Referring to FIG. 6, the first thin film transistor T1 of the electrostatic discharge circuit ESD includes the first lower gate electrode 101, the first channel layer 114, the first source electrode 117, and the first drain electrode. 118, and the second thin film transistor T2 includes a second lower gate electrode 201, a second channel layer 214, a first source electrode 117, and a second drain electrode 217. .

In addition, the third thin film transistor T3 includes a third lower gate electrode 301, a third channel layer 314, a second source electrode 218, and a first drain electrode 118. The second drain electrode 217 and the second source electrode 218 are integrally formed and electrically connected.

The first source electrode 117 serves as a source electrode of the first thin film transistor T1 and the second thin film transistor T2 in the equivalent circuit of FIG. 5, and the first drain electrode 118 is equivalent to that of FIG. 5. The circuit serves as a drain electrode of the first thin film transistor T1 and the third thin film transistor T3.

In addition, the first source electrode 117 and the second lower gate electrode 201 are electrically connected to each other through a first contact hole C1, and the first lower gate electrode 101 is connected to a second contact hole ( It is electrically connected to the second source electrode 218 and the second drain electrode 217 through C2).

In addition, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 of the electrostatic discharge circuit ESD of the present invention may have first, second, and third upper gate electrodes 150, respectively. 250 and 350 are formed. That is, the first, second, and third thin film transistors T1, T2, and T3 are each formed in a dual gate structure having a lower gate electrode and an upper gate electrode.

The first, second, and third upper gate electrodes 150, 250, and 350 are electrically connected to each other by the first, second, and third connectors 211, 212, and 213, respectively. In addition, the first, second, and third upper gate electrodes 150, 250, and 350 that are electrically connected to each other are electrically connected to the control signal line 220 by a fourth connector 214. Although not shown in the drawings, RA, which is not described, refers to a region from which an etch stopper layer is removed.

Referring to FIG. 7, the third thin film transistor T3 of the electrostatic discharge circuit ESD of the present invention forms a metal film on the substrate 100 and then performs a mask process to form the third lower gate electrode 301. The gate insulating layer 302 is formed on the substrate 100 on which the third lower gate electrode 301 is formed. The gate insulating film 302 may be formed of an SiNx based insulating film or an SiO ₂ based insulating film.

When the third lower gate electrode 301 is formed, the first lower gate electrode 101 and the second lower gate electrode 201 of the first and second thin film transistors T1 and T2 shown in FIG. 6 are simultaneously connected. Is formed. That is, FIG. 7 is a cross-sectional view of the third thin film transistor T3, but the same configuration names of the first and second thin film transistors T1 and T2 are formed together.

The third lower gate electrode 301 is made of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), and chromium (Cr). ), Low resistance opaque conductive materials such as molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and the like may be used. In addition, a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) and an opaque conductive material may be formed in a multilayered structure.

As described above, when the third lower gate electrode 301 and the gate insulating layer 302 are formed on the substrate 100, an oxide semiconductor layer is formed on the entire surface of the substrate 100, and then patterned to form the third lower gate. A third channel layer 314 is formed on the gate insulating layer 302 so as to overlap the electrode 301.

The oxide semiconductor layer may be formed of an amorphous oxide including at least one of indium (In), zinc (Zn), gallium (Ga), or hafnium (Hf). For example, when the Ga-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of In 2 O 3, Ga 2 O 3, and ZnO may be used, or a single target of Ga—In—Zn oxide may be used. In addition, when the hf-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of HfO 2, In 2 O 3, and ZnO may be used, or a single target of Hf—In—Zn oxide may be used.

As described above, when the third channel layer 314 is formed on the substrate 100, an insulating layer is formed on the entire surface of the substrate 100, and then a etch stopper pattern 305 is formed by performing a mask process. The etch stopper pattern 305 is formed in the center of the third channel layer 314, and is also formed in a region spaced a predetermined distance from the third channel layer 314. That is, as shown in FIG. 6, the etch stopper pattern 305 is parallel to the third channel layer 314, the first drain electrode 118, and the second source electrode 218 through a predetermined patterning process. Accordingly, the region RA where the gate insulating layer 302 is exposed is formed.

This structure is similarly formed in the first and second thin film transistors T1 and T2.

As described above, when the etch stopper pattern 305 is formed on the substrate 100, a source / drain metal film is formed on the entire surface of the substrate 100, and then the second source electrode 218 and the second source electrode 218 are formed using a mask process. One drain electrode 118 is formed. In particular, referring to FIG. 6, the first drain electrode 118 is electrically contacted with the third lower gate electrode 301 through the third contact hole.

The source / drain metal layer may use a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum, or the like. In addition, a transparent conductive material such as indium tin oxide and indium zinc oxide and an opaque conductive material may be formed in a multilayered structure.

As described above, when the second source electrode 218 and the first drain electrode 118 are formed on the substrate 100, the passivation layer 309 is formed on the entire surface of the substrate 100, and then the organic layer is formed for planarization. 310 is formed.

A third upper gate electrode 350 is formed on the organic layer 310 corresponding to the third channel layer 314. When the organic layer 310 is formed, the third upper gate electrode 350 sequentially forms the pixel electrode or the common electrode in the pixel area of the liquid crystal display, and is formed at the same time.

That is, when the pixel electrode or the common electrode is formed on the organic layer 310, the third upper gate electrode 350 may be simultaneously formed. Therefore, the third upper gate electrode 350 may be formed of transparent conductive materials ITO, ITZO, and IZO.

As described above, in the present invention, the structure of the thin film transistor formed in the electrostatic discharge circuit (ESD) has a dual gate structure, and the upper gate electrodes of the thin film transistor are electrically connected to each other.

In addition, the first, second, and third upper gate electrodes 150, 250, and 350 of the electrostatic discharge circuit ESD may include a driving voltage supplied to the first, second, and third lower gate electrodes 101, 201, and 301. The leakage current was reduced by supplying voltages of opposite polarities to shift the threshold voltages Vth of the first to third thin film transistors.

Therefore, when the thin film transistors of the ESD circuit are N-MOS transistors, a negative voltage may be supplied to the upper gate electrode to shift the threshold voltage Vth of the thin film transistor.

The voltage ΔV range shifted from the threshold voltage Vth is 0.1 to 3V, and the voltages supplied to the upper gate electrodes of the thin film transistor may be changed according to the range of the shifted voltage.

In the present invention, the three transistors are built in the electrostatic discharge circuit (ESD). However, even when a single transistor or two or more transistors are applied, the transistors have the same structure as the lower gate electrode and the upper gate electrode.

In particular, even when two or more transistors are applied, the upper gate electrodes are electrically connected.

8 is a graph showing the threshold voltage characteristics of the oxide semiconductor thin film transistor used in the electrostatic discharge circuit of the present invention, FIG. 9 is a graph showing the current characteristics of the electrostatic discharge circuit of the present invention, and FIG. 9 is an enlarged view of region X, and FIG. 11 is a graph showing discharge characteristics of the electrostatic discharge circuit.

8 to 11, in the case of an N-MOS transistor of a thin film transistor formed in an electrostatic discharge circuit (ESD), a negative DC voltage may be applied to the first to third upper gate electrodes of the first to third thin film transistors. Supply the voltage.

As such, when a negative voltage is supplied to the upper gate electrode of the N-MOS thin film transistor, the threshold voltage Vth of the N-MOS thin film transistor is changed by only Vth + ΔV.

As shown in FIG. 8, it can be seen that the position of Vth is shifted to the right based on the voltage of Vgs. Vth of the oxide semiconductor layer thin film transistor A1 was changed to the thin film transistor C of the present invention. A1 and C have the width W and the length L of the same channel layer, but the gate electrode structures of the thin film transistors are different, and the applied voltages are different to have different Vth values.

When the electrostatic discharge circuit (ESD) is configured using the thin film transistors having the changed Vth as described above, as shown in FIGS. 9 to 11, the formed oxide semiconductor thin film transistors have the same channel width and length (W / L: 4/25 μm). It can be seen that the leakage current decreases (A1-C).

In addition, the off-voltage range of the electrostatic discharge circuit is increased from 6.8V to 10V during non-driving, and in the past, a leakage current was generated in the 6.8V region. However, in the present invention, a leakage current is generated in the 10V region, resulting in a 6.8V region. The leakage current at is significantly reduced.

As shown in FIG. 6, each of the oxide semiconductor thin film transistors of the present invention includes first to third upper gate electrodes, and upper gate electrodes have direct current voltages having opposite polarities to those of the lower gate electrodes. This is because the threshold voltage (Vth) of the thin film transistors is forcibly shifted by ΔV by supplying.

 Referring to the discharge characteristics of the ESD circuit of FIG. 11, an electrostatic discharge circuit (ESD) using an oxide semiconductor thin film transistor having a dual gate structure and an electrostatic discharge circuit (ESD) using an oxide semiconductor thin film transistor having a single gate structure are shown. It can be seen that there is almost no change in the discharge characteristics.

That is, the electrostatic discharge circuit (ESD) employing the dual gate structure thin film transistor of the present invention reduces the leakage current, but does not deteriorate the discharge characteristics.

12 is a graph showing current characteristics according to channel layer length of a dual gate structure thin film transistor formed in an electrostatic discharge circuit of the present invention, and FIG. 13 is a channel of a dual gate structure thin film transistor formed in an electrostatic discharge circuit of the present invention. It is a graph showing the discharge characteristics according to the layer length.

C is a thin film having a width (W) and a length (L) of 4/25 μm of a channel layer of an oxide semiconductor and a negative voltage supplied to the upper gate electrode, but shifted by 1 V (ΔV) from the threshold voltage Vth. An electrostatic discharge circuit (ESD) employing a transistor, where C1 is the width (W) and length (L) of the channel layer shifted by 4/20 μm and 1V (ΔV) from Vth, C2 is the width (W) of the channel layer. ) And length L are 4/15 占 퐉 and 1V (ΔV) shifted from Vth, C3 is the width W and length L of the channel layer shifted 4/10 占 퐉 and 1V (ΔV) from Vth. If it is.

As described above, when the Vth is further shifted by ΔV in the dual gate structure thin film transistor of the present invention, it can be seen that the channel layer width W and the length L of the thin film transistor can be reduced to 4/10 μm. (Drive voltage range is within 10V)

As shown in FIG. 13, the discharge characteristics of the electrostatic discharge circuit ESD are also reduced by 50% in discharge time at 4/10 μm, compared with the width W and the length L of the channel layer being 4/25 μm. You can see that.

As described above, in the present invention, an oxide semiconductor thin film transistor having a dual gate structure is used to reduce leakage current at the same channel layer width W and length L. FIG. However, when maintaining a leakage current of an electrostatic discharge circuit using a general oxide semiconductor thin film transistor, in the case of the dual gate structure thin film transistor of the present invention, the length (L) of the channel layer is remarkably reduced.

For example, the leakage current of an electrostatic discharge circuit ESD using an oxide semiconductor thin film transistor having a width W and a length L of 4/25 μm of the channel layer is a width W and a length L of the channel layer. It is similar to the leakage current of an electrostatic discharge circuit (ESD) using a dual gate structure oxide semiconductor thin film transistor having a 4/10 탆.

As described above, according to the present invention, the thin film transistor of the electrostatic discharge circuit formed in the display display device has a dual gate structure, thereby reducing the leakage current generated in the electrostatic discharge circuit during non-drive.

In addition, according to the present invention, the thin film transistor of the electrostatic discharge circuit formed on the display display device has a dual gate structure, and a leakage current of the electrostatic discharge circuit is prevented by applying a voltage opposite to the gate driving voltage to the upper gate electrode. .

30: liquid crystal display panel 40: gate driver
50: data driver 60: signal controller
80: gray voltage generator 91: DC-DC converter
92: light source unit 150: first upper gate electrode
250: second upper gate electrode 350: third upper gate electrode
T1: first thin film transistor T2: second thin film transistor
T3: third thin film transistor

Claims (19)

A first thin film transistor including a first lower gate electrode, a first channel layer, a first source electrode, a first drain electrode, and a first upper gate electrode overlapping the first lower gate electrode and the first channel layer;
A second thin film transistor including a second lower gate electrode, a second channel layer, the first source electrode, a second drain electrode, and a second upper gate electrode overlapping the second lower gate electrode and the second channel layer; And
A third thin film transistor including a third lower gate electrode, a third channel layer, a second source electrode, the first drain electrode, and a third upper gate electrode overlapping the third lower gate electrode and the third channel layer; ,
The first to third upper gate electrodes may be electrically connected to each other to receive a negative voltage, and the first to third lower gate electrodes may receive voltages of opposite polarity to the first to third upper gate electrodes. Electrostatic discharge circuit, characterized in that.
The electrostatic discharge circuit of claim 1, wherein the first to third channel layers are formed of an oxide semiconductor.
The electrostatic discharge circuit of claim 2, wherein the oxide semiconductor is indium gallium zinc oxide (IGZO).
delete The electrostatic discharge circuit of claim 1, wherein the voltage ΔV shifted from the threshold voltage Vth of the first to third thin film transistors is 0.1 to 3V. The electrostatic discharge circuit of claim 1, further comprising a control signal line for supplying voltage to the first to third upper gate electrodes.
The electrostatic discharge circuit of claim 6, wherein the first to third upper gate electrodes and the control signal line are electrically connected to each other by first to fourth connectors. The display device of claim 1, wherein the first upper gate electrode, the first source electrode and the first drain electrode, the second upper gate electrode, the first source electrode and the second drain electrode, and the third upper gate electrode and the first upper gate electrode And a protective film between the second source electrode and the first drain electrode.
The electrostatic discharge circuit of claim 8, further comprising an organic layer between the first to third upper gate electrodes and the passivation layer.
A liquid crystal display panel including a plurality of gate lines and data lines and a pixel region defined by the plurality of gate lines and data lines;
A gate driver and a data driver supplying a display signal to the liquid crystal display panel;
A backlight unit supplying a light source to the liquid crystal display panel;
A signal controller supplying a display signal and a control signal to the gate driver, the data driver, and the backlight unit; And
The liquid crystal display panel includes at least one electrostatic discharge circuit connected to each of the plurality of gate lines and data lines,
One end of the electrostatic discharge circuit is connected to each of the plurality of gate lines and data lines, and the other end is connected to a common line.
The electrostatic discharge circuit includes a thin film transistor including an upper gate electrode and a lower gate electrode,
The upper gate electrode is the other end of the electrostatic discharge circuit and receives a negative voltage from the common line,
And the lower gate electrode is one end of the electrostatic discharge circuit and is connected to each of the plurality of gate lines and the data lines and is supplied with a voltage having a polarity opposite to that of the upper gate electrode. The method of claim 10, wherein the electrostatic discharge circuit,
A first thin film transistor including a first lower gate electrode, a first channel layer, a first source electrode, a first drain, and a first upper gate electrode overlapping the first lower gate electrode and the first channel layer;
A second thin film transistor including a second lower gate electrode, a second channel layer, the first source electrode, a second drain electrode, and a second upper gate electrode overlapping the second lower gate electrode and the second channel layer; And
A third thin film transistor including a third lower gate electrode, a third channel layer, a second source electrode, the first drain electrode, and a third upper gate electrode overlapping the third lower gate electrode and the third channel layer; ,
And the first to third upper gate electrodes are electrically connected to each other.
The display apparatus of claim 11, wherein the first to third channel layers are formed of an oxide semiconductor.
The display apparatus of claim 12, wherein the oxide semiconductor is indium gallium zinc oxide (IGZO).
delete The display apparatus of claim 10, wherein the voltage ΔV shifted from the threshold voltage Vth of the first to third thin film transistors is 0.1 to 3V.
The display apparatus of claim 10, further comprising a control signal line for supplying a voltage to the first to third upper gate electrodes.
The display apparatus of claim 16, wherein the first to third upper gate electrodes and the control signal line are electrically connected to each other by first to fourth connectors. 12. The display device of claim 11, wherein the first upper gate electrode, the first source electrode and the first drain electrode, the second upper gate electrode, the first source electrode and the second drain electrode, and the third upper gate electrode and the first upper gate electrode And a passivation layer between the second source electrode and the first drain electrode.
The display device of claim 18, further comprising an organic layer between the first to third upper gate electrodes and the passivation layer.

Images