KR100555309B1 - Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a display device and a method of manufacturing the same, which can ensure reliability while simplifying a process by using a lift-off process.

A method of manufacturing a thin film transistor substrate of the present invention includes forming a signal line of a first conductive layer on a substrate; Forming a first insulating layer covering the first conductive layer; Forming a signal line of a second conductive layer on the first insulating layer; Forming a second insulating layer over the second conductive layer; Forming a contact hole penetrating through the first and second insulating layers to expose adjacent portions of the first and second conductive layers together; Forming a contact electrode of a third conductive layer connecting the first and second conductive layers exposed in the contact hole.

Description

Thin film transistor substrate for display device and method for manufacturing same {Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same}             

1 is a plan view partially showing a conventional thin film transistor substrate.

FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 2.

4 is an equivalent circuit diagram of an antistatic element.

4A and 4B are plan and cross-sectional views showing an antistatic element and a shorting bar region of a thin film transistor substrate.

6 is a plan view illustrating an antistatic device and a shorting bar region of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the antistatic portion and the shorting bar region illustrated in FIG. 6 taken along lines IV-IV ′ and V-V ′. FIG.

8A and 8B are a plan view and a cross-sectional view for explaining a first mask process among the method for manufacturing the thin film transistor substrate shown in FIG. 6.

9A and 9B are a plan view and a sectional view for explaining a second mask process in the method for manufacturing the thin film transistor substrate shown in FIG. 6.

10A to 10D are cross-sectional views for describing the second mask process in detail.

11A and 11B are a plan view and a cross-sectional view for illustrating a third mask process among the method for manufacturing the thin film transistor substrate shown in FIG. 6.

12A and 12D are cross-sectional views for describing the third mask process in detail.

FIG. 13 is a plan view illustrating an antistatic device and a shorting bar region of a thin film transistor substrate according to a second exemplary embodiment of the present invention. FIG.

FIG. 14 is a cross-sectional view of the antistatic part and the shorting bar area shown in FIG. 13 taken along the line VI-VI ′ and VIII-VIII. FIG.

15A and 15B are a plan view and a sectional view for explaining a first mask process in the method for manufacturing the thin film transistor substrate shown in FIG. 14.

16A and 16B are a plan view and a sectional view for explaining a second mask process in the method of manufacturing the thin film transistor substrate shown in FIG. 14.

17A to 17B are plan views and cross-sectional views for describing in detail a third mask process in the method of manufacturing the thin film transistor substrate illustrated in FIG. 14.

18A and 18B are a plan view and a cross-sectional view for explaining a fourth mask process among the method for manufacturing the thin film transistor substrate shown in FIG. 14.

19A and 19D are cross-sectional views for describing the fourth mask process in detail.

 <Description of Symbols for Main Parts of Drawings>

2: gate line 4: data line

6, 100, 110, 120, 200, 210, 220, 300, 310, 320: thin film transistor

8, 102, 112, 122, 202, 212, 222, 302, 312, 322: gate electrode

10, 104, 114, 124, 204, 214, 224, 304, 314, 324: source electrode

12, 106, 116, 126, 206, 216, 226, 306, 316, 326: drain electrode

14, 130, 230, 308, 318, 328: active layer

16, 24, 30, 38, 140, 142, 144, 146, 148, 150, 154, 194, 198, 240, 294, 340, 394: contact hole

18: pixel electrode 20: storage capacitor

22: upper storage electrode 26: gate pad portion

28: gate pad lower electrode 32: gate pad upper electrode

34, 155, 255, 355: data pad portion

152, 252, 352: data pad lower electrode

40, 156, 256, 356: data pad upper electrode

42, 160, 260, 360: substrate 44, 162, 262, 362: gate insulating film

48, 164, 264, 364: ohmic contact layer 50, 166, 266, 366: protective film

152, 270, 280, 370: photoresist pattern

132, 134, 136, 198, 232, 234, 236, 298, 332, 334, 336, 398: contact electrode

191, 291, 391: Aude Shorting Bar 191A, 291A, 391A: Aude Shorting Bar Horizontal

191B, 291B, 391B: Aude Shorting Bar Vertical Section

192, 292: Evening bar 192A, 292A: Evening bar horizontal part

192B, 292B: Even shorting bar vertical section

230A: amorphous silicon layer 164A: n ⁺ amorphous silicon layer

272: source / drain gold layer 282, 372: transparent conductive layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate applied to a display element and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same, which can simplify the process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor substrate and a color filter substrate facing each other, a liquid crystal injected between the two substrates, and a spacer for maintaining a cell gap between the two substrates.

The thin film transistor substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed in a liquid crystal cell unit and connected to the thin film transistor, and the like applied thereon. Composed of aligned alignment films. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter substrate may include color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It is composed.

The liquid crystal panel is completed by separately manufacturing the thin film transistor substrate and the color filter substrate, and then injecting and encapsulating the liquid crystal.

In the liquid crystal panel, the thin film transistor substrate includes a semiconductor process and also requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a thin film transistor substrate.

FIG. 1 is a plan view of a thin film transistor substrate employing a four mask process, for example. FIG. 2 is a cross-sectional view of the thin film transistor substrate of FIG. 1 taken along the line II ′.

The thin film transistor substrate shown in FIGS. 1 and 2 has a gate line 2 and a data line 4 formed to intersect on a lower substrate 42 with a gate insulating film 44 therebetween, and a thin film transistor formed at each intersection thereof. (6) and the pixel electrode 18 formed in the cell area provided in the cross structure. The thin film transistor substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line 4. Is provided with a data pad section 34 connected thereto.

The thin film transistor 6 causes the pixel signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the scan signal supplied to the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 16. 12 and an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12.

The active layer 14 including the channel portion between the source electrode 10 and the drain electrode 12 while overlapping the source electrode 10 and the drain electrode 12 is the data line 4 and the data pad lower electrode 36. It is also formed to overlap with the storage electrode 22. The ohmic contact layer 48 for ohmic contact with the data line 4, the source electrode 10 and the drain electrode 12, the data pad lower electrode 36, and the storage electrode 22 is further formed on the active layer 14. Is formed.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel signal. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes a storage upper electrode 22 overlapping the front gate line 2 with the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 interposed therebetween. And the pixel electrode 22 which is overlapped with the storage upper electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel signal charged in the pixel electrode 18 to remain stable until the next pixel signal is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 has the gate lower electrode 28 through the gate lower electrode 28 extending from the gate line 2 and the third contact hole 30 penetrating the gate insulating film 44 and the passivation layer 50. ) And a gate pad upper electrode 32 connected thereto.

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad part 34 is connected to the data pad 36 through the data lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. It consists of an electrode 40.

A method of manufacturing a thin film transistor substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28 are formed on the lower substrate 42 using the first mask process.

In detail, the gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form gate metal patterns including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 3B, a gate insulating layer 44 is coated on the lower substrate 42 on which the gate metal patterns are formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 48 on the gate insulating layer 44 using a second mask process; Source / drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 36, and the storage electrode 22 are sequentially formed.

In detail, the gate insulating layer 44, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate metal patterns are formed by a deposition method such as PECVD or sputtering. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 44. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Subsequently, a photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 22 are formed. Source / drain metal patterns including are formed.

Then, the ohmic contact layer 48 and the active layer 14 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

In addition, after the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process, the source / drain metal pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

Referring to FIG. 3C, a passivation layer 50 including first to fourth contact holes 16, 24, 30, and 38 may be formed on a gate insulating layer 44 on which source / drain metal patterns are formed using a third mask process. ) Is formed.

In detail, the passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain metal patterns are formed by a deposition method such as PECVD. Subsequently, the passivation layer 50 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 16, 24, 30, and 38. The first contact hole 16 penetrates the passivation layer 50 to expose the drain electrode 12, and the second contact hole 24 penetrates the passivation layer 50 to expose the storage upper electrode 22. Is formed. The third contact hole 30 is formed to pass through the passivation layer 50 and the gate insulating layer 44 to expose the gate pad lower electrode 28. The fourth contact hole 38 penetrates the passivation layer 50 to expose the data pad upper electrode 36.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 44 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, transparent conductive layer patterns including the pixel electrode 18, the gate pad upper electrode 32, and the data pad upper electrode 40 are formed on the passivation layer 50 using a fourth mask process. .

The transparent conductive film is apply | coated on the protective film 50 by vapor deposition methods, such as sputtering. Subsequently, the transparent conductive layer is etched through the photolithography process and the etching process using the fourth mask, thereby forming the transparent conductive layer pattern including the pixel electrode 18, the gate pad upper electrode 32, and the data pad upper electrode 40. Are formed. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16 and overlaps the front gate line 2 through the second contact hole 24. And electrically connected. The gate pad upper electrode 32 is electrically connected to the gate pad lower electrode 28 through the third contact hole 30. The data pad upper electrode 40 is electrically connected to the data lower electrode 36 through the fourth contact hole 38. Here, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or the like is used as a material of the transparent conductive film.

As described above, the conventional thin film transistor substrate and its manufacturing method can reduce the manufacturing cost by simplifying the process using a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

Accordingly, an object of the present invention is to provide a thin film transistor substrate for a display element and a method of manufacturing the same, which can ensure reliability while simplifying the process by using a lift-off process.

In order to achieve the above object, a thin film transistor substrate for a display element according to an aspect of the present invention includes a signal line of the first conductive layer formed on the substrate; A first insulating layer formed on the first conductive layer; A signal line of a second conductive layer formed on the first insulating layer; A second insulating layer formed on the second conductive layer; A contact hole penetrating the first and second insulating layers to expose adjacent portions of the first and second conductive layers together; And a third conductive layer formed in the contact hole to connect the exposed first and second conductive layers.

Specifically, the thin film transistor substrate of the present invention includes an antistatic element including a plurality of thin film transistors connected to the signal line in a non-display area; Each of the plurality of thin film transistors may include a gate electrode formed of the first conductive layer, a source electrode and a drain electrode formed of the second conductive layer; A semiconductor layer forming a channel between the source electrode and the drain electrode; A contact hole for exposing adjacent portions of the first conductive layer of the thin film transistor and the second conductive layer of the other thin film transistor together; And a contact electrode of a third conductive layer formed in the contact hole to connect the exposed first and second conductive layers.

Each of the plurality of thin film transistors includes: another contact hole exposing adjacent portions of the first conductive layer and the second conductive layer of the thin film transistor together; Another contact electrode of the third conductive layer formed in the other contact hole to connect the exposed first and second conductive layers is further provided.

The present invention may further include first and second shorting bars for inspecting the signal lines in the non-display area; Each of the first and second shorting bars includes a plurality of first and second vertical portions formed of any one of the first and second conductive layers connected to the signal line, respectively; A first horizontal part formed of the same conductive layer as the plurality of first vertical parts and connected in common; A second horizontal portion formed of a conductive layer different from the plurality of second vertical portions to cross the first vertical portion; Another contact hole for simultaneously exposing adjacent portions of the second vertical portion and the horizontal portion; Another contact electrode of the third conductive layer formed in the another contact hole and connecting the exposed second vertical portion and the horizontal portion is provided.

Each of the contact holes may be formed through the gate insulating film on the first conductive layer and the passivation layer on the second conductive layer, and each of the contact electrodes may be formed bordering the passivation layer in the contact hole.

The semiconductor layer extends along the second conductive layer.

Each of the contact holes further exposes a portion of the semiconductor layer under the second conductive layer.

The signal line includes at least one of a gate line and a data line.

In addition, the method of manufacturing a thin film transistor substrate according to the present invention includes forming a signal line of a first conductive layer on the substrate; Forming a first insulating layer covering the first conductive layer; Forming a signal line of a second conductive layer on the first insulating layer; Forming a second insulating layer over the second conductive layer; Forming a contact hole penetrating the first and second insulating layers to expose adjacent portions of the first and second conductive layers together; Forming a contact electrode of a third conductive layer connecting the first and second conductive layers exposed in the contact hole.

Specifically, the manufacturing method of the present invention is a method of manufacturing a thin film transistor substrate for a display element comprising an antistatic element including a plurality of thin film transistors connected to the signal line in a non-display area, wherein a gate insulating film is disposed between the substrates. Forming a thin film transistor including the first and second conductive layers and a semiconductor layer together with the signal lines; Forming a protective film covering the plurality of thin film transistors; Forming a contact hole penetrating through the passivation layer and the gate insulating layer to expose adjacent portions of the first conductive layer of the thin film transistor and the second conductive layer of the other thin film transistor together; And forming a contact electrode of the third conductive layer connecting the exposed first and second conductive layers in the contact hole.

In addition, the present invention includes forming another contact hole for exposing adjacent portions of the first conductive layer and the second conductive layer of the thin film transistor together; And forming another contact electrode of the third layer connecting the exposed first and second conductive layers in the other contact hole.

The method may further include forming a vertical portion of the first and second shorting bars from one of the first and second conductive layers so as to be connected to the signal line in the non-display area, respectively. Forming a horizontal portion of the first shorting bar to be commonly connected to the same conductive layer as the plurality of first vertical portions; Forming a horizontal portion of the second shorting bar crossing the vertical portion of the first shorting bar with a conductive layer different from the plurality of second vertical portions; Forming another contact hole through the passivation layer and the gate insulating layer to expose adjacent portions of the vertical portion and the horizontal portion of the second shorting bar together; And forming another contact electrode of the third conductive layer connecting the vertical portion and the horizontal portion of the exposed second shorting bar in the another contact hole.

The forming of the corresponding contact hole and the corresponding contact electrode may include forming a photoresist pattern on the passivation layer; Etching the passivation layer and the gate insulating layer exposed through the photoresist pattern; Forming the third conductive layer on the substrate having the photoresist pattern; And removing the photoresist pattern from the third conductive layer thereon.

The forming of the plurality of thin film transistors may include forming a gate electrode of the thin film transistor as the first conductive layer; Forming the gate insulating film; Forming the semiconductor layer; And forming a source electrode and a drain electrode of the thin film transistor as the second conductive layer.

The semiconductor layer, the source electrode and the drain electrode are formed using the same mask, and the semiconductor layer is formed along the second conductive layer.

The forming of the signal line may include forming a gate line of the first conductive layer together with the gate electrode; Forming a data line of the second conductive layer together with the source electrode and the drain electrode.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

First, before describing the embodiment of the present invention, the antistatic device and the shorting bar structure of the existing four-mask process to be contrasted with the present invention will be described as an example.

In general, the thin film transistor substrate includes an antistatic device formed in a non-display area to block static electricity flowing into the display area. For example, the antistatic element is configured of a plurality of thin film transistors 100, 110, and 120 connected to a data line or a gate line in a non-display area and having an interconnection relationship as illustrated in FIG. 4. Such an antistatic device has a low impedance in a high voltage region caused by static electricity, so that overcurrent is discharged, thereby preventing the inflow of static electricity, and in a normal driving environment, the antistatic device has a high impedance (for example, several tens of mA) and is supplied through a data line or a gate line. It does not affect the driving signal. Specific configurations of such an antistatic device are as shown in FIGS. 5A and 5B, for example.

5A is a plan view partially illustrating an antistatic element and a shorting bar region of a general thin film transistor substrate, and FIG. 5B is a cutaway view of the thin film transistor substrate illustrated in FIG. 5A along lines II-II 'and III-III'. It is a cross section.

The antistatic device illustrated in FIGS. 5A and 5B includes first to third thin film transistors 100, 110, and 120 connected to a data link 158 connecting a data pad 155 and a data line.

The first thin film transistor 100 includes a first source electrode 104 connected to the data link 158, a first drain electrode 106 facing the first source electrode 104, a first source and A first gate electrode 102 overlapping the drain electrodes 104 and 106, the semiconductor layers 130 and 164, and the gate insulating layer 162 is provided therebetween.

The second thin film transistor 110 includes a second source electrode 114 connected to the first source electrode 104, a second drain electrode 116 facing the second source electrode 114, and a second source electrode 114. Second source and drain electrodes 114 and 116, semiconductor layers 130 and 164, and gate insulating layer 162 may be interposed between the second gate electrodes 112. Here, the second gate electrode 112 is connected to the second source electrode 114 through the first contact electrode 132 formed over the first and second contact holes 140 and 142. In other words, the first contact electrode 132 may pass through the passivation layer 166 to expose a portion of the second source electrode 114, the passivation layer 166, and the gate insulating layer 162. The second gate electrode 112 and the source electrode 114 are connected to each other by being formed over the second contact hole 142 through which the second gate electrode 112 is exposed.

The third thin film transistor 120 includes a third source electrode 124 connected to the first drain electrode 106, a third drain electrode 126 opposed to the third source electrode 134, and a third source electrode 126. Third source and drain electrodes 124 and 126, the semiconductor layers 130 and 164, and the gate insulating layer 162 are interposed between the third gate electrodes 122. Here, the third drain electrode 126 is connected to the second drain electrode 116, and the first gate electrode (134) is formed through the second contact electrode 134 formed over the third and fourth contact holes 144 and 146. 102 is also connected. In other words, the second contact electrode 134 may pass through the passivation layer 166 to expose a portion of the second drain electrode 116, the passivation layer 166, and the gate insulating layer 162. The second drain electrode 116 and the first gate electrode 102 are connected to each other by being formed over the fourth contact hole 146 through which the portion of the first gate electrode 102 is exposed. The third gate electrode 112 is connected to the third source electrode 124 through the third contact electrode 136 formed over the fifth and sixth contact holes 148 and 150. In other words, the third contact electrode 136 may pass through the passivation layer 166 to expose a portion of the third source electrode 124, the passivation layer 166, and the gate insulating layer 162. The third gate electrode 122 and the source electrode 124 are connected to each other by being formed over the sixth contact hole 150 through which the portion of the third gate electrode 122 is exposed.

In the first to third thin film transistors 100, 110, and 120, the gate electrodes 102, 112, and 122 are first conductive layers (gate metal layers) on the substrate 160, and source electrodes 104, 114, and 124. ) And the drain electrodes 106, 116, and 126 are formed of a second conductive layer (source / drain metal layer) on the semiconductor layers 130 and 164, and the contact electrodes 132, 134, and 136 are formed on the passivation layer 166. Is formed of a third conductive layer (transparent conductive layer or Ti)

The data pad 155 is connected to the data lower electrode 152 through the data lower electrode 152 of the second conductive layer formed on the gate insulating layer 162 and the ninth contact hole 154 penetrating through the passivation layer 166. And a data pad upper electrode 156 of the third conductive layer.

The data pad 155 is connected to the odd and even shorting bars 191 and 192 formed in the non-display area for signal inspection after fabrication of the thin film transistor substrate. The odd shorting bar 191 is commonly connected to the plurality of odd data pads 155, and the even shorting bar 192 is commonly connected to the plurality of even data pads 155.

The odd shorting bar 191 includes an odd vertical portion 191B connected to the odd data pad lower electrode 152, and an odd horizontal portion 191A commonly connected to the plurality of odd vertical portions 191B. The odd shorting bar 191 is formed of the same second conductive layer as the data pad lower electrode 152.

The even shorting bar 192 includes an even vertical part 192B connected to the even data pad lower electrode 152, and an even horizontal part 192B commonly connected to the plurality of even vertical parts 192B. Here, the even vertical part 192B is formed of the same second conductive layer as the lower data pad lower electrode 152, and the even horizontal part 191A across the ob vertical part 191B is formed of the first conductive layer. The even horizontal part 192A and the vertical part 192B are connected through the fourth contact electrode 198 of the third conductive layer formed over the seventh and eighth contact holes 194 and 196. In other words, the fourth contact electrode 198 may pass through the passivation layer 166 to expose a portion of the even vertical portion 192B, and the passivation layer 166 and the gate insulating layer 162. It is formed over the eighth contact hole 194 penetrating and exposing a part of the even horizontal part 192A, thereby connecting the even vertical part 192A and the horizontal part 192B.

The semiconductor layer may include an active layer 130 forming a channel in each of the first to third thin film transistors 100, 110, and 120, a source electrode 104, 114, 124, and a drain electrode 106, 116, 126. The ohmic contact layer 164 formed on the active layer 130 except for the channel portion is provided for ohmic contact with the organic material. The active layer 130 and the ohmic contact layer 164 include a data link 158, a data pad lower electrode 152, an odd shorting bar 191, and a vertical portion 192B of the even shorting bar 192. It is formed along the second conductive layer.

The antistatic element and the shorting bar having such a configuration are formed by the four mask process as described above. In detail, the gate electrodes 102, 112, and 122 and the even horizontal bar 192A of the first conductive layer are formed on the substrate 160 by the first mask process. Semiconductor layers 130 and 164 on the gate insulating layer 162 in a second mask process; Source electrodes 104, 114, 116, drain electrodes 106, 116, 126 of the second conductive layer, data link 158, data pad lower electrodes 152, odd shorting bars 191, even vertical portions ( 192B) is formed. In the third mask process, contact holes 140, 142, 144, 146, 148, 150, 154, 194, and 196 penetrating the passivation layer 166 and the gate insulating layer 162 are formed. Contact electrodes 132, 134, 136, and 198 and data pad upper electrode 156 are formed.

The contact holes 140, 144, 148, and 196 exposing the second conductive layer and the contact holes 142, 146, 150, and 194 exposing the first conductive layer are formed independently of each other to form different steps. The risk of disconnection of the contact electrodes 132, 134, 136, and 198 increases.

On the other hand, in the invention (hereinafter, referred to as the invention of the invention), which was previously filed in the applicant's patent application No. 2002-88323, a thin-film transistor substrate has been proposed by forming a three-mask process by applying a lift-off process. The source invention reduces the number of mask processes by forming a hole penetrating the protective film and the gate insulating film, and a process of patterning the third conductive layer in one mask process using a lift-off process. Accordingly, the source invention has a structural feature in which the patterned third conductive layer is formed only in a region in which the photoresist pattern for forming holes is not formed in the protective film and the gate insulating film so as to be bounded by the protective film in the hole. Therefore, in the source invention, as shown in FIGS. 5A and 5B, when two contact holes exposing the first and second conductive layers are formed in the antistatic element and the shorting bar region, the first and second conductive layers are formed as contact electrodes. You will have the disadvantage of not being able to connect.

In order to solve these disadvantages, the thin film transistor substrate according to the embodiment of the present invention is formed by integrating contact holes exposing the first and second conductive layers. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 19D.

6 is a plan view partially showing an antistatic element and a shorting bar region of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 7 is a line IV-IV ′ and V-V ′ of the thin film transistor substrate illustrated in FIG. 6. It is sectional drawing cut along.

6 and 7 may include first to third thin film transistors 200, 210, and 220 connected to signal lines, that is, data links 258 connecting data pads 255 and data lines. Equipped.

The first thin film transistor 200 includes a first source electrode 204 connected to the data link 258, a first drain electrode 206 facing the first source electrode 204, a first source and The first gate electrode 202 overlaps the drain electrodes 204 and 206 with the semiconductor layers 230 and 264 and the gate insulating layer 262 interposed therebetween.

The second thin film transistor 210 includes a second source electrode 214 connected to the first source electrode 204, a second drain electrode 216 opposite to the second source electrode 214, and a second source electrode 214. Second source and drain electrodes 214 and 216, semiconductor layers 230 and 264, and a gate insulating layer 262 are interposed between the second gate electrodes 212. Here, the second gate electrode 212 is connected to the second source electrode 214 through the first contact electrode 232 formed in the first contact hole 240. In other words, the first contact electrode 232 penetrates the passivation layer 266 and the gate insulating layer 262 to simultaneously expose the second gate electrode 212 and a portion of the second source electrode 214 adjacent thereto. It is formed in the first contact hole 240 to connect the second gate electrode 212 and the source electrode 214.

The third thin film transistor 220 may include a third source electrode 224 connected to the first drain electrode 206, a third drain electrode 226 facing the third source electrode 224, and a third source electrode 226. Third source and drain electrodes 224 and 226, semiconductor layers 230 and 264, and gate insulating layer 262 may be interposed between the third gate electrodes 222. The third drain electrode 226 is connected to the second drain electrode 216 and is also connected to the first gate electrode 202 through the second contact electrode 234 formed in the second contact hole 144. In other words, the second contact electrode 234 penetrates the passivation layer 266 and the gate insulating layer 262 to simultaneously expose the second drain electrode 226 and a portion of the first gate electrode 202 adjacent thereto. It is formed in the second contact hole 244 to connect the second drain electrode 226 and the first gate electrode 202. The third gate electrode 212 is connected to the third source electrode 224 through the third contact electrode 236 formed in the third contact hole 148. In other words, the third contact electrode 236 penetrates the passivation layer 166 and the gate insulating layer 262 to simultaneously expose the third source electrode 224 and a portion of the third gate electrode 222 adjacent thereto. It is formed in the three contact hole 248 to connect the third source electrode 224 and the gate electrode 222.

In the first to third thin film transistors 200, 210, and 220, the gate electrodes 202, 212, and 222 are first conductive layers (gate metal layers) on the substrate 260, and source electrodes 204, 214, and 224. ) And the drain electrodes 206, 216, and 226 are formed of a second conductive layer (source / drain metal layer) on the semiconductor layers 230 and 264, and the contact electrodes 232, 234, and 236 are formed on the passivation layer 266. Is formed of a third conductive layer (transparent conductive layer or Ti)

The data pad 255 is connected to the data lower electrode 252 through the data lower electrode 252 of the second conductive layer formed on the gate insulating layer 262 and the fifth contact hole 254 penetrating through the passivation layer 266. And a data pad upper electrode 256 of the third conductive layer.

The data pad 255 is connected to the odd and even shorting bars 291 and 292 formed in the non-display area for signal inspection after fabrication of the thin film transistor substrate. The odd shorting bar 291 is commonly connected to the plurality of odd data pads 255, and the even shorting bar 292 is commonly connected to the plurality of even data pads 255.

The odd shorting bar 291 includes an odd vertical portion 291B connected to the odd data pad lower electrode 252 and an odd horizontal portion 291A commonly connected to the plurality of odd vertical portions 291B. The odd shorting bar 291 is formed of the same second conductive layer as the data pad lower electrode 252.

The even shorting bar 292 includes an even vertical part 292B connected to the even data pad lower electrode 252, and an even horizontal part 292B commonly connected to the plurality of even vertical parts 292B. Here, the even vertical portion 292B is formed of the same second conductive layer as the data pad lower electrode 252, and the even horizontal portion 291A across the ob vertical portion 291B is formed of the first conductive layer. The even horizontal portion 292A and the vertical portion 292B are connected through the fourth contact electrode 298 of the third conductive layer formed in the fourth contact hole 194. In other words, the fourth contact electrode 298 penetrates the passivation layer 266 and the gate insulating layer 262 to simultaneously expose the even vertical portion 292B and a portion of the even horizontal portion 292A adjacent thereto. By forming in the hole 294, the even vertical portion 292A and the horizontal portion 292B are connected.

The semiconductor layer may include an active layer 230 forming a channel in each of the first to third thin film transistors 200, 210, and 220, a source electrode 204, 214, and 224, and a drain electrode 206, 216, and 226. The ohmic contact layer 264 formed on the active layer 230 except for the channel part is provided for ohmic contact with the channel. The active layer 230 and the ohmic contact layer 264 include a data link 258, a data pad lower electrode 252, an odd shorting bar 291, and a vertical portion 292B of the even shorting bar 292. It is formed along the second conductive layer.

As described above, in the thin film transistor substrate according to the present invention, the first to fourth contact holes 240, 244, 248, and 294 are formed to simultaneously expose adjacent first and second conductive layers, thereby contacting the contact holes 240 and 244. And the first and second conductive layers may be connected through the contact electrodes 232, 234, and 236, which are formed in the first through second electrodes 248 and 294, respectively. In this case, the first to fourth contact holes 240, 244, 248, and 294 sequentially expose the second conductive layer, the semiconductor layer, and the first conductive layer to reduce the step, thereby reducing the contact electrodes 232, 234, and 236. The risk of disconnection can be prevented. The contact electrodes 232, 234, and 236, together with the data pad upper electrode 254, are lift-off processes for removing the photoresist pattern used during the patterning of the passivation layer 266 and the gate insulating layer 262. Is formed. Accordingly, the thin film transistor substrate according to the present invention may be formed in a three mask process as follows.

8A and 8B illustrate a plan view and a cross-sectional view for describing a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

In the first mask process, a first conductive pattern including the gate electrodes 202, 212, and 222 and the horizontal portion 292A of the even horizontal bar 292 is formed on the lower substrate 260.

In detail, the gate metal layer is formed on the lower substrate 260 through a deposition method such as a sputtering method. Subsequently, the first conductive layer is patterned by a photolithography process and an etching process using the first mask to thereby include a first conductive layer including the horizontal portions 292A of the gate electrodes 202, 212, 222, and the even horizontal bar 292. A pattern is formed. Here, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) or the like is used as the first conductive layer.

9A and 9B illustrate a plan view and a cross-sectional view for describing a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 10A to 10D illustrate the second mask process in detail. Figures below are shown.

First, the entire gate insulating layer 262 is formed on the lower substrate 260 on which the first conductive pattern is formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 262, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

A semiconductor pattern including an active layer 230 and an ohmic contact layer 264 stacked on the gate insulating layer 262 by a second mask process; Vertical portions of the source electrodes 204, 214, 224, the drain electrodes 206, 216, 226, the data link 258, the data pad lower electrode 252, the odd shorting bar 191, and the even shorting bar 292. A second conductive pattern including 292B is formed.

In detail, as shown in FIG. 10A, an amorphous silicon layer 230A, an n + amorphous silicon layer 264A, and a second conductive layer 272 are sequentially formed on the gate insulating layer 262 through a deposition method such as PECVD or sputtering. . As the second conductive layer 272, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd), or the like is used. Subsequently, the photoresist is entirely coated on the second conductive layer 272, and then a photoresist pattern 270 having a step is formed as shown in FIG. 10A by a photolithography process using a second mask, which is a partial exposure mask. In this case, as the second mask, a partial exposure mask having a diffractive exposure portion (or semi-transmissive portion) at a portion where a channel of the thin film transistor is to be formed is used. Accordingly, the photoresist pattern 270 corresponding to the diffractive exposure portion (or transflective portion) of the second mask has a lower height than the photoresist pattern 270 corresponding to the transmission portion (or blocking portion) of the second mask. . In other words, the photoresist pattern 270 of the channel portion has a lower height than the photoresist pattern 270 of the other source / drain metal pattern portions.

As the second conductive layer 272 is patterned by a wet etching process using the photoresist pattern 270, as shown in FIG. 10B, the source electrodes 204, 214, and 224, and the source electrodes 204, 214, and 224, respectively. And vertical portions 292B of the drain electrodes 206, 216, and 226, the data link 258, the data pad lower electrode 252, the odd shorting bar 191, and the even shorting bar 292. 2 conductive patterns are formed. In addition, the n + amorphous silicon layer 264A and the amorphous silicon layer 230A are simultaneously patterned by a dry etching process using the same photoresist pattern 270, so that the ohmic contact layer 264 and the active layer 230 are illustrated in FIG. 10B. ) Has a structure formed along the second conductive pattern.

Then, an ashing process using an oxygen (O ₂ ) plasma removes the photoresist pattern 270 of the channel portion having a relatively low height as shown in FIG. 10C, and the other source / drain metal pattern portion. The photoresist pattern 270 is lowered in height. In the dry etching process using the remaining photoresist pattern 270, the second conductive layer and the ohmic contact layer 264 are etched at the portion where the channel is to be formed, as shown in FIG. 10C, so that the source electrodes 204, 214, and 224 are etched. ) And the drain electrodes 206, 216, and 226 are separated from each other, and the active layer 230 is exposed. Accordingly, a channel formed of the active layer 230 is formed between the source electrodes 204, 214, and 224 and the drain electrodes 206, 216, and 226, respectively.

Then, all of the photoresist pattern 270 remaining in the second conductive pattern portion by the stripping process is removed as shown in FIG. 10D.

11A and 11B illustrate a plan view and a cross-sectional view for describing a third mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 12A to 12D illustrate the third mask process in detail. Figures below are shown.

In the third mask process, the entire passivation layer 266 and the gate insulating layer 262 are patterned to form contact holes 240, 244, 248, and 294, and the contact electrodes 232, together with the data pad upper electrode 254. Third conductive patterns including 234, 236, and 298 are formed. The third conductive pattern is formed bordering the patterned passivation layer 266.

In detail, as shown in FIG. 12A, the passivation layer 266 is entirely formed on the gate insulating layer 262 on which the second conductive pattern is formed. As the material of the protective film 266, an inorganic insulating material similar to the gate insulating film 262 or an organic insulating material is used. The photoresist pattern 280 is formed on the entire surface of the passivation layer 266 by using a third mask in a photolithography process as shown in FIG. 12A.

Subsequently, the entire passivation layer 266 and the gate insulating layer 262 are patterned by an etching process using the photoresist pattern 280 to form the first to fourth contact holes 240, 244, 248, and 294 as shown in FIG. 12B. ) Is formed together with the fifth contact hole. The first contact hole 240 is the second source electrode 214 and the gate electrode 212, the second contact hole 244 is the third drain electrode 226 and the first gate electrode 202, the third The contact hole 248 may include the third source electrode 224 and the gate electrode 222, and the fourth contact hole 294 may include the horizontal portion 292A and the vertical portion 292B of the even shorting bar 292. The contact hole exposes the data pad lower electrode 152.

Subsequently, as shown in FIG. 12C, the third conductive layer 282 is formed on the entire surface of the thin film transistor substrate on which the photoresist pattern 280 is present by a deposition method such as sputtering or the like. The third conductive layer 282 may be a transparent conductive layer including indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), SnO ₂ , or the like. Titanium (Ti) having corrosion resistance and high strength is used.

The third conductive layer 282 is patterned by removing the photoresist pattern 280 and the third conductive layer 282 thereon in a lift-off process. Accordingly, contact electrodes 232, 234, 236, and 298 are formed in the first to fourth contact holes 240, 244, 248, and 248, respectively, as shown in FIG. 12D, and the data pad upper electrode ( 254 is formed. Accordingly, the first contact electrode 232 connects the second source electrode 214 and the gate electrode 212, and the second contact electrode 234 connects the third drain electrode 226 and the first gate electrode 202. The third contact electrode 236 may include the third source electrode 224 and the gate electrode 222, and the fourth contact electrode 298 may include the horizontal portion 292A and the vertical portion 292B of the even shorting bar 292. The fifth contact hole is connected to the upper and lower electrodes 152 and 154 of the data pad.

FIG. 13 is a plan view partially showing an antistatic element and a shorting bar region of a thin film transistor substrate according to another exemplary embodiment. FIG. 14 is a VI-VI 'line and a VIII-VIII line of the thin film transistor substrate shown in FIG. It is a cross-sectional view cut along the.

The thin film transistor substrate shown in FIGS. 13 and 14 has a structure formed by a four mask process as compared to the thin film transistor substrates shown in FIGS. 6 and 7 except that the semiconductor layer is formed only in the thin film transistor region. With components. Accordingly, detailed description of overlapping components will be omitted.

13 and 14, the first to third thin film transistors 300, 310, and 320 of the antistatic device illustrated in FIGS. 13 and 14 may be formed independently of a corresponding region, that is, in an island type, to form a channel. 318, 328. An ohmic contact layer 264 is further formed at an overlapping portion between the active layers 308, 318, and 328, the source electrodes 304, 314, and 324, and the drain electrodes 306, 316, and 326.

The first contact electrode 332 is formed in the first contact hole 340 to connect the second gate electrode 312 and the source electrode 314. The second contact electrode 334 is formed in the second contact hole 344 to connect the second drain electrode 326 and the first gate electrode 302. The third contact electrode 336 is formed in the third contact hole 348 to connect the third source electrode 324 and the gate electrode 322. The fourth contact electrode 398 is formed in the fourth contact hole 394 to connect the even vertical portion 392A and the horizontal portion 392B. The contact electrodes 332, 334, and 336, together with the data pad upper electrode 354, are lift-off processes of removing the photoresist pattern used during the patterning of the passivation layer 366 and the gate insulating layer 362. Is formed. Accordingly, the thin film transistor substrate according to the present invention may be formed in a four mask process as follows.

15A and 15B illustrate a plan view and a cross-sectional view for describing a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

In the first mask process, a first conductive pattern including the gate electrodes 302, 312, and 322 and the horizontal portion 392A of the even horizontal bar 392 is formed on the lower substrate 360. In other words, the first conductive layer is formed on the lower substrate 360 through a deposition method such as a sputtering method, and the first conductive layer is patterned by a photolithography process and an etching process using the first mask to form a gate electrode ( First conductive patterns including 302, 312, and 322 and the horizontal portion 392A of the even horizontal bar 392 are formed.

16A and 16B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

First, the entire gate insulating layer 362 is formed on the lower substrate 360 on which the first conductive pattern is formed through a deposition method such as PECVD or sputtering. A semiconductor pattern including first to third active layers 308, 318, and 328 and an ohmic contact layer 364 may be formed on the gate insulating layer 362 by a second mask process. In other words, an amorphous silicon layer and an n + amorphous silicon layer are laminated on the gate insulating film 362 through a deposition method such as PECVD and sputtering, and the semiconductor layer is patterned by a photolithography process and an etching process using a second mask. As a result, a semiconductor pattern including the first to third active layers 308, 318, and 328 and the ohmic contact layer 364 is formed in the thin film transistor region.

17A and 17B are plan and cross-sectional views for describing a third mask process in the method of manufacturing a thin film transistor substrate according to the embodiment of the present invention.

A source electrode 304, 314, 324, a drain electrode 306, 316, 326, a data link 358, and a data pad lower electrode 352 on the gate insulating layer 362 having the semiconductor pattern formed by a third mask process. The second conductive pattern including the odd shorting bar 391 and the vertical portion 392B of the even shorting bar 392 is formed. In other words, a second conductive layer is formed on the gate insulating layer 362 through a deposition method such as PECVD or sputtering, and the source electrode is patterned by patterning the second conductive layer by a photolithography process and an etching process using a third mask. 304, 314, 324, drain electrodes 306, 316, 326, data link 358, data pad lower electrode 352, odd shorting bar 391, vertical part of even shorting bar 392 392B A second conductive pattern including) is formed.

In addition, the ohmic contact layer 364 exposed between the source electrodes 304, 314, and 324 and the drain electrodes 306, 316, and 326 is removed by a dry etching process using the second conductive pattern as a mask, thereby forming the active layer 308. , 318, 328).

18A and 18B illustrate a plan view and a cross-sectional view for describing a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 19A to 19D illustrate the third mask process in detail. Figures below are shown.

In the third mask process, the entire passivation layer 366 and the gate insulating layer 362 are patterned to form contact holes 340, 344, 348, and 394. The contact electrodes 332 and the data pad upper electrode 354 are formed. Third conductive patterns including 334, 336, and 398 are formed.

Specifically, as shown in FIG. 19A, the passivation layer 366 is entirely formed on the gate insulating layer 362 having the second conductive pattern formed thereon. The photoresist pattern 370 is formed on the entire surface of the passivation layer 366 by a photolithography process using a third mask as shown in FIG. 19A.

Subsequently, the entire protective layer 366 and the gate insulating layer 362 are patterned by an etching process using the photoresist pattern 370, so that the first to fourth contact holes 340, 344, 348, and 394 as shown in FIG. 19B. ) Is formed together with the fifth contact hole. The first contact hole 340 is the second source electrode 314 and the gate electrode 312, the second contact hole 344 is the third drain electrode 326 and the first gate electrode 302, the third The contact hole 348 may include the third source electrode 324 and the gate electrode 322, and the fourth contact hole 394 may include the horizontal portion 392A and the vertical portion 392B of the even shorting bar 392. The contact hole exposes the data pad lower electrode 352.

Subsequently, as illustrated in FIG. 19C, the third conductive layer 372 is formed on the entire surface of the thin film transistor substrate on which the photoresist pattern 370 exists by a deposition method such as sputtering or the like. The third conductive layer 372 may be a transparent conductive layer including indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), SnO ₂ , or the like. Titanium (Ti) having corrosion resistance and high strength is used.

The third conductive layer 372 is patterned by removing the photoresist pattern 370 and the third conductive layer 372 thereon in a lift-off process. Accordingly, contact electrodes 332, 334, 336, and 398 are formed in the first to fourth contact holes 340, 344, 348, and 348, respectively, as shown in FIG. 19D, and the data pad upper electrode ( 354) is formed.

As described above, the thin film transistor substrate and the manufacturing method thereof according to the present invention are formed by integrating contact holes exposing the first and second conductive layers in order to apply the lift-off process. Accordingly, the first and second conductive layers exposed through the contact electrode formed in the contact hole can be connected, and the step difference is reduced, thereby preventing the risk of disconnection.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A signal line of the first conductive layer formed on the substrate; A first insulating layer formed on the first conductive layer; A signal line of a second conductive layer formed on the first insulating layer; A second insulating layer formed on the second conductive layer; A contact hole penetrating the first insulating layer and the second insulating layer to expose adjacent portions of the first conductive layer and the second conductive layer together; A third conductive layer formed in the contact hole and connecting the exposed first conductive layer and the second conductive layer, The contact hole is formed by etching the passivation layer exposed through the photoresist pattern formed on the passivation layer. An antistatic device including a plurality of thin film transistors connected to the signal lines in the non-display area; Each of the plurality of thin film transistors, A gate electrode formed of the first conductive layer, A source electrode and a drain electrode formed of the second conductive layer; A semiconductor layer forming a channel between the source electrode and the drain electrode; A contact hole for exposing adjacent portions of the first conductive layer of the thin film transistor and the second conductive layer of the other thin film transistor together; A contact electrode of a third conductive layer formed in the contact hole and connecting the exposed first and second conductive layers, Each of the contact holes is formed through the gate insulating film on the first conductive layer and the passivation layer on the second conductive layer, and each of the contact electrodes is formed to form a boundary with the passivation layer in the contact hole. And the semiconductor layer extends along the second conductive layer. The method of claim 2, Each of the plurality of thin film transistors, Another contact hole exposing adjacent portions of the first conductive layer and the second conductive layer of the thin film transistor together; And another contact electrode of a third conductive layer formed in the other contact hole to connect the exposed first and second conductive layers. The method of claim 3, wherein Further including first and second shorting bars for inspecting the signal lines in the non-display area; Each of the first and second shorting bars A plurality of first and second vertical portions formed of any one of the first and second conductive layers connected to the signal line, respectively; A first horizontal part formed of the same conductive layer as the plurality of first vertical parts and connected in common; A second horizontal portion formed of a conductive layer different from the plurality of second vertical portions to cross the first vertical portion; Another contact hole for simultaneously exposing adjacent portions of the second vertical portion and the horizontal portion; And another contact electrode of a third conductive layer formed in the another contact hole and connecting the exposed second vertical portion and the horizontal portion. delete delete The method of claim 2, Each of the contact holes further exposes a portion of the semiconductor layer under the second conductive layer. The method according to any one of claims 2 to 4, The signal line includes at least one of a gate line and a data line. Forming a signal line of the first conductive layer on the substrate; Forming a first insulating layer covering the first conductive layer; Forming a signal line of a second conductive layer on the first insulating layer; Forming a second insulating layer over the second conductive layer; Forming a contact hole penetrating through the first and second insulating layers to expose adjacent portions of the first and second conductive layers together; Forming a contact electrode of a third conductive layer connecting the first and second conductive layers exposed in the contact hole, Forming the corresponding contact hole and the corresponding contact electrode Forming a photoresist pattern on the protective film; Etching the passivation layer and the gate insulating layer exposed through the photoresist pattern; Forming the third conductive layer on the substrate having the photoresist pattern; And removing the photoresist pattern from the third conductive layer thereon. In the manufacturing method of the thin film transistor substrate for display elements provided with the antistatic element containing the several thin film transistor connected with the signal line in the non-display area, Forming a thin film transistor including a first conductive layer and a second conductive layer having a gate insulating film interposed therebetween and a semiconductor layer on the substrate, together with the signal line; Forming a protective film covering the plurality of thin film transistors; Forming a contact hole penetrating through the passivation layer and the gate insulating layer to expose adjacent portions of the first conductive layer of the thin film transistor and the second conductive layer of the other thin film transistor together; Forming a contact electrode of the third conductive layer connecting the exposed first conductive layer and the second conductive layer in the contact hole; Forming another contact hole exposing adjacent portions of the first conductive layer and the second conductive layer of the thin film transistor together; Forming another contact electrode of the third conductive layer connecting the exposed first conductive layer and the second conductive layer in the other contact hole; Forming a vertical portion of the first shorting bar and the second shorting bar as one of the first conductive layer and the second conductive layer so as to be respectively connected to the signal line in the non-display area; Forming a horizontal portion of the first shorting bar to be commonly connected to the same conductive layer as the plurality of first vertical portions; Forming a horizontal portion of the second shorting bar across the vertical portion of the first shorting bar with a conductive layer different from the plurality of second vertical portions; Forming another contact hole through the passivation layer and the gate insulating layer to expose adjacent portions of the vertical portion and the horizontal portion of the second shorting bar together; And forming another contact electrode of the third conductive layer connecting the vertical portion and the horizontal portion of the exposed second shorting bar in the another contact hole, the thin film transistor substrate for a display element. delete delete The method of claim 10, Forming the corresponding contact hole and the corresponding contact electrode Forming a photoresist pattern on the protective film; Etching the passivation layer and the gate insulating layer exposed through the photoresist pattern; Forming the third conductive layer on the substrate having the photoresist pattern; And removing the photoresist pattern from the third conductive layer thereon. The method according to claim 10 or 13, Forming the plurality of thin film transistors Forming a gate electrode of the thin film transistor as the first conductive layer; Forming the gate insulating film; Forming the semiconductor layer; And forming a source electrode and a drain electrode of the thin film transistor as the second conductive layer. The method of claim 14, The semiconductor layer, the source electrode and the drain electrode are formed using the same mask, The semiconductor layer is formed along the second conductive layer. The method of claim 15, And each of the contact holes further exposes a part of the semiconductor layer under the second conductive layer. The method of claim 14, Forming the signal line Forming a gate line of the first conductive layer together with the gate electrode; And forming a data line of the second conductive layer together with the source electrode and the drain electrode.

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