KR100903746B1 - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of minimizing the area of a semiconductor pattern exposed to a backlight by extending a gate light shielding pattern and a method of manufacturing the same.

       According to an embodiment of the present invention, any one of a gate line and a data line intersecting a gate insulating film therebetween, a thin film transistor formed at an intersection of the gate line and data line, a pixel electrode connected to the thin film transistor, and two adjacent gate lines And a gate shading pattern connected to the gate line of the gate line and overlapping the data line, and a gate hole formed in the gate line adjacent to the gate shading pattern to disconnect the gate line and the shading pattern, if necessary. It relates to an array substrate.

The present invention minimizes the semiconductor area exposed to the backlight by connecting the gate shielding pattern to the gate line, and can easily repair the disconnected data line by forming the gate line having the gate hole.

Description

      Thin Film Transistor Array Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}             

      1 is a plan view showing a portion of a thin film transistor array substrate included in a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3A to 3D are cross-sectional views illustrating a step in manufacturing a thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view showing a portion of a thin film transistor array substrate included in a liquid crystal display of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along lines II-II 'and III-III'; FIG.

6A through 6D are cross-sectional views illustrating a manufacturing process of the thin film transistor array substrate illustrated in FIG. 5 in stages.

FIG. 7 is a plan view illustrating a portion of a thin film transistor array substrate for explaining a method of repairing when a data line according to the present invention shown in FIG. 4 is disconnected. FIG.

         <Explanation of symbols for the main parts of the drawings>

2,102: Gate line 3,103: Gate shading film

4,104: data line 8,108: gate electrode

10,110 source electrode 12112 drain electrode

14,114 active layer 18,118 pixel electrode

11,111: Gate Hall

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, and more particularly, to a thin film transistor array substrate and a method of manufacturing the same, which can minimize photo photocurrent of a semiconductor layer due to a backlight and easily repair a data line.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

FIG. 1 is a plan view illustrating a thin film transistor array substrate by a four mask process, for example. FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided.                         

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The thin film transistor 6 keeps the pixel signal supplied to the data line 4 charged in the pixel electrode 18 in response to the gate signal supplied to the gate line 2. Here, the active layer 14 overlapping the source electrode 10 and the drain electrode 12 extends along the data line 4. The data line 4, the source electrode 10, and the drain are disposed on the active layer 14. An ohmic contact layer 48 for ohmic contact with the electrode 12 is further formed.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a contact hole 16 penetrating through the passivation layer 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The gate light blocking pattern 3 is formed in an ISLAND type overlapping the data line 4 with a predetermined distance from the gate line 2 and the previous gate line 2. For example, the distances d1 and d2 of the gate line 2 are separated by about 15 μm above and below the gate light blocking pattern 3. The gate light blocking pattern 3 blocks the active layer 14 and the ohmic contact layer 48 from being exposed to the backlight. Accordingly, the semiconductor layer is activated by the backlight to reduce the photocurrent generated.

A method of manufacturing a thin film transistor substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a gate pattern is formed on the lower substrate 42.

The gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form patterns including the gate blocking pattern 3, the gate line 2, and the gate electrode 8. As the gate metal, chromium (Cr), molybdenum (Mo), an aluminum metal, or the like is used.

The gate insulating layer 44, the active layer 14, the ohmic contact layer 48, and the source / drain patterns are sequentially formed on the lower substrate 42 on which the gate patterns are formed.

After the gate insulating film 44, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate patterns are formed by PECVD or sputtering, a source / drain metal layer The photoresist pattern is formed by a photolithography process using the second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Then, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the source including the data line 4, the source electrode 10, and the drain electrode 12 integrated with the source electrode 10. Drain patterns are formed.

Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 48 and the active layer 14. In this case, the side portions of the source / drain patterns are overetched so that the semiconductor pattern including the ohmic contact layer 48 and the active layer 14 has a wider line width than the source / drain pattern.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12.

Next, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 3C, the passivation layer 50 including the contact hole 16 is formed on the gate insulating layer 44 on which the source / drain patterns are formed.

The passivation layer 50 is entirely formed on the gate insulating layer 44 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 50 is patterned by a photolithography process and an etching process using a third mask to form a contact hole 16. The contact hole 16 penetrates the passivation layer 50 to expose the drain electrode 12.

As the material of the protective film 50, an inorganic insulating material such as the gate insulating film 44 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, transparent electrode patterns are formed on the passivation layer 50.

The transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through the photolithography process and the etching process using the fourth mask to form the pixel electrode 18. The pixel electrode 18 is electrically connected to the drain electrode 12 through the contact hole 16. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, the conventional thin film transistor array substrate using four masks and a method of manufacturing the same may reduce the photocurrent generated when the semiconductor pattern overlapping the data line is exposed to the backlight using the gate blocking pattern. However, since the conventional light shielding pattern is formed in an island type between two gate lines, it is impossible to completely block the semiconductor pattern from the backlight. As a result, a portion of the semiconductor pattern exposed to the backlight is activated by the energy of the backlight to generate a photocurrent. In addition, the photocurrent increases as the driving time of the liquid crystal display becomes longer, thereby distorting the pixel signal supplied to the pixel electrode, resulting in deterioration of image quality such as flicker.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a manufacturing method which can extend the gate shielding pattern to minimize the area of the semiconductor pattern exposed to the backlight and facilitate the repair when the data line is disconnected.

       In order to achieve the above object, the thin film transistor array substrate according to the present invention is connected to the gate line and data line intersecting the gate insulating film, the thin film transistor formed on the gate line and the data line intersection portion, and the thin film transistor A gate light shielding pattern connected to the pixel electrode, one of the two adjacent gate lines and overlapping the data line, and a disconnection between the gate line and the light shielding pattern if necessary in the gate line adjacent to the gate light shielding pattern. It characterized in that it comprises a gate hole formed for.

       In order to achieve the above object, the thin film transistor array substrate according to the present invention includes a gate electrode of the thin film transistor on the substrate, a gate line to which the gate electrode is connected and having a gate hole, and a gate shading pattern connected to the gate line. A first mask process of forming a gate pattern, a second mask process of depositing a gate insulating film on the gate pattern, and forming a source / drain pattern including a semiconductor pattern, a data line, and a source / drain electrode on the insulating film; And a third mask process of depositing a passivation layer on the source / drain pattern, forming a contact hole, and a fourth mask process of forming a pixel electrode pattern on the passivation layer.

       And forming a cut portion that crosses the gate line at both ends of the long axis of the gate hole.

       When the data line is disconnected, the disconnected data line may be repaired using the gate light blocking pattern.

       And disconnecting a portion of the gate line between the gate hole and the gate light blocking pattern to electrically separate the gate line and the gate light blocking pattern.

       Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

       Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 8.

       4 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention.

       FIG. 5 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 4 taken along lines II-II 'and III-III'.

       The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 142 with a gate insulating layer 144 therebetween, and a thin film formed at each intersection thereof. A transistor 106, a pixel electrode 118 formed in a cell region provided in an intersecting structure thereof, and a gate light shielding pattern 103 connected to any one of the two gate lines and overlapping the data line 104.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 connected to the pixel electrode 116. And an active layer 114 overlapping the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. The thin film transistor 106 keeps the pixel signal supplied to the data line 104 charged to the pixel electrode 118 in response to the gate signal supplied to the gate line 102. The active layer 114 overlapping the source electrode 110 and the drain electrode 112 extends along the data line 104. An ohmic contact layer 148 for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114.

The pixel electrode 118 is connected to the drain electrode 112 of the thin film transistor 106 through the contact hole 16 penetrating the passivation layer 150. The pixel electrode 118 generates a potential difference from a common electrode (not shown) formed on an upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate 142 and the upper substrate (not shown) is rotated by dielectric anisotropy, and light incident through the pixel electrode 118 from a light source (not shown) is transferred to the upper substrate. Is transmitted toward the side.

The gate light blocking pattern 103 is connected to one of the gate lines 102 of two gate lines, and overlaps the data line 104 and the gate insulating layer 144 therebetween. For example, the gate light blocking pattern 103 is connected to the upper gate line. The light blocking pattern 144 prevents the semiconductor pattern under the data line 104, that is, the active layer 114 and the ohmic contact layer 148 from being exposed to the backlight. In particular, as the gate light shielding pattern 103 is formed to be connected to the gate line 102, the exposed area of the semiconductor pattern can be reduced. In addition, when the data line 104 is opened, the disconnected data line 104 is repaired using the gate light blocking pattern 103. In detail, when the data line 104 is disconnected, the disconnected data line 104 and the gate light blocking pattern 103 are connected to repair the disconnected data line 104. In this case, a gate hole 111 is formed in the gate line 102 to electrically insulate the gate light blocking pattern 103 in contact with the data line 104 from the gate line.

The gate hole 111 is adjacent to the portion where the gate line and the gate light blocking pattern 103 are in contact with each other, and has a wider line width than the semiconductor pattern. Accordingly, a part of the gate line is opened between the gate hole 111 and the gate shading pattern 103 of the disconnected data line 104 by using a laser to open the gate shading pattern 103 (not shown). Is electrically separated from the gate line 102.

A method of manufacturing a thin film transistor substrate having such a configuration will be described with reference to FIGS. 6A to 6D in detail using a four mask process.

6A is a cross-sectional view illustrating gate patterns formed on a lower substrate 142 by a first mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

The gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask, so that the gate includes a light blocking pattern 103, a gate line 52 having a gate hole 111, and a gate electrode 108. Patterns are formed. Here, the gate hole 111 is formed to be adjacent to the contact portion of the gate light blocking pattern 103 and to have a wider line width than the semiconductor pattern to be formed thereon. As the gate metal, chromium (Cr), molybdenum (Mo), an aluminum metal, or the like is used.

6B is a cross-sectional view of a substrate formed by a second mask process in the method of manufacturing a thin film transistor array substrate.

The gate insulating layer 144, the amorphous silicide layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 144 on which the gate patterns are formed by a deposition method such as PECVD or sputtering. The gate insulating layer 144 is formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) such that the gate patterns are not exposed. As the source / drain metal, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used.

Subsequently, the source / drain metal layer, the n + amorphous silicon layer, the amorphous silicon layer, are patterned by a photolithography process using a second mask and a plurality of ashing and etching processes. As a result, a semiconductor pattern and a source / drain pattern are formed. The semiconductor pattern includes an active layer 114 and an ohmic contact layer 148. The source / drain pattern includes a source electrode 110, a drain electrode 112, and a data line 104.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, the second mask uses a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor so that the photoresist pattern of the channel portion has a lower height than other source / drain patterns.

Subsequently, a source / drain including a data line 104, a source electrode 110, and a drain electrode 112 integrated with the source electrode 110 is formed by patterning the source / drain metal layer by a wet etching process using a photoresist pattern. Patterns are formed.

Then, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 148 and the active layer 114.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 148 of the channel portion are etched by a dry etching process. Accordingly, the active layer 114 of the channel portion is exposed to separate the source electrode 110 and the drain electrode 112.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

Referring to FIG. 6C, the passivation layer 150 including the contact hole 116 is formed on the gate insulating layer 144 on which the source / drain patterns are formed.

The passivation layer 150 is entirely formed on the gate insulating layer 144 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a third mask to form a contact hole 116. The contact hole 116 penetrates the passivation layer 150 to expose the drain electrode 112.

As the material of the passivation layer 150, an inorganic insulating material such as the gate insulating film 144, an acrylic insulating compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

Referring to FIG. 6D, transparent electrode patterns are formed on the passivation layer 150.

The transparent electrode material is deposited on the passivation layer 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through the photolithography process and the etching process using the fourth mask to form the pixel electrode 118. The pixel electrode 118 is electrically connected to the drain electrode 112 through the contact hole 116. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

FIG. 7 is a diagram for describing a repairing method when a data line according to the present invention shown in FIG. 4 is disconnected.

Referring to FIG. 7, when the data line 104 is disconnected and needs to be repaired, the data line 104 and the gate light shielding pattern 103 are electrically shorted by using a laser. A portion of the gate line 104 exposed between the gate hole 111 and the gate light blocking film is opened using a laser so that the gate light blocking pattern shorted with the data line 104 is electrically separated from the gate line 102. do.

      As described above, in the thin film transistor array substrate and the method of manufacturing the same, the area of the semiconductor exposed to the backlight may be minimized by connecting the gate blocking pattern to the gate line. Accordingly, according to the thin film transistor array substrate and the manufacturing method according to the present invention, the light current of the semiconductor layer is minimized due to the backlight energy, thereby preventing the distortion of the pixel signal due to the light current and improving the image display quality.

      In addition, the thin film transistor array substrate and the method of manufacturing the same according to the present invention form a gate hole in a direction crossing the semiconductor layer in a gate line adjacent to the gate shading pattern to easily repair the disconnected data line using the gate shading pattern. The gate line and the gate light blocking pattern can be electrically separated.

      Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

       A gate line and a data line that intersect with the gate insulating layer interposed therebetween,        A thin film transistor formed at an intersection of the gate line and the data line; A semiconductor pattern including an active layer extending along the data line and overlapping the data line while forming a channel portion of the thin film transistor;        A pixel electrode connected to the thin film transistor,        A gate shielding pattern connected to one of the two adjacent gate lines and overlapping the data line and the semiconductor pattern; A gate hole positioned adjacent to a connection portion to which the gate light blocking pattern and the gate line are connected, and formed to disconnect the gate line and the gate light blocking pattern ; And the gate hole is formed in the gate line in a direction crossing the data line and the semiconductor pattern, and has a wider line width than the semiconductor pattern . delete delete delete        A first mask process of forming a gate pattern comprising a gate electrode of a thin film transistor, a gate line connected to the gate electrode and having a gate hole, and a gate blocking pattern connected to the gate line, on a substrate;       A second mask process of depositing a gate insulating film on the gate pattern and forming a source / drain pattern including a semiconductor pattern, a data line and a source / drain electrode on the gate insulating film;        A third mask process of depositing a protective film on the source / drain pattern and forming a contact hole;        A fourth mask process for forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer, The semiconductor pattern includes an active layer and a channel portion extending along the data line and overlapping the data line, wherein the gate hole is formed to disconnect the gate line and the gate light blocking pattern, and the gate light blocking pattern and the gate line. A method of manufacturing a thin film transistor array substrate, characterized in that it is located adjacent to the connecting portion to be connected . delete The method of claim 5 , When the data line of the disconnection of the data line disconnection method of manufacturing a TFT array arrangement, characterized in that further comprising a repair process in which, using the gate light-shielding pattern.        The method of claim 7, wherein Method of manufacturing a TFT array arrangement, characterized in that to break the gate lines between the repair when said gate hole and the gate light-shielding pattern further includes a step of electrically isolating the gate line and the gate light-shielding pattern.

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