KR101116820B1 - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of improving the aperture ratio and a method of manufacturing the same.

A thin film transistor array substrate includes a gate line and a data line formed to cross each other on a substrate, a thin film transistor formed at the cross region, and a pixel electrode connected to the thin film transistor. At least one line-shaped groove is provided in a region where a line is to be formed, and the gate line is partially located in the at least one line-shaped groove.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}             

1 is a plan view illustrating a thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II ′. FIG.

3 is a cross-sectional view showing another conventional thin film transistor array substrate.

4 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line II-II ′ of the thin film transistor array substrate illustrated in FIG. 4.

6A to 6D are views for explaining a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

7A to 7E are diagrams for describing in detail a process of forming the gate pattern of FIG. 6A.

8 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.                 

FIG. 9 is a perspective view illustrating a substrate on which at least one line groove of FIG. 8 is formed.

10 is a plan view illustrating a thin film transistor array substrate according to a third exemplary embodiment of the present invention.

11A to 11C are diagrams for describing a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention.

         <Explanation of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

14, 114: active layer 16, 116: first contact hole

18, 118: pixel electrodes 20, 120: storage capacitor

22, 122: storage electrode 24: second contact hole

26, 126: gate pad portion 28, 128: gate pad

30,130: third contact hole 34, 134: data pad portion

38 and 138: fourth contact hole 102a: first metal pattern

102b: second metal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor array substrate capable of improving an aperture ratio and a method of manufacturing the same.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.                         

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

FIG. 1 is a plan view of a conventional thin film transistor array substrate, for example. FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′.

The thin film transistor array substrate shown in FIGS. 1 and 2 includes a gate line 2 and a data line 4 intersecting each other with a gate insulating film 44 interposed on the lower substrate 42, and a thin film formed at each intersection thereof. The transistor 6 and the pixel electrode 18 formed in the cell area provided in the cross structure are provided. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the front gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line ( And a data pad portion 34 connected to 4).

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 16. And an active layer 14 overlapping the gate electrode 8 and forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and the source electrode 10 and the drain electrode ( 12) further comprises a channel section therebetween. An ohmic contact layer 48 for ohmic contact with the data pad lower electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14. do. The thin film transistor 6 keeps the pixel voltage signal supplied to the data line 4 charged in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes the front gate line 2, the storage electrode 22 overlapping the gate line 2, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 48 therebetween. And a pixel electrode 18 which is overlapped with the storage electrode 22 and the passivation layer 50 interposed therebetween and connected via the second contact hole 24 formed in the passivation layer 50. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad lower electrode 26 is formed through the gate pad lower electrode 28 extending from the gate line 2 and the third contact hole 30 penetrating through the gate insulating layer 44 and the passivation layer 50. And a gate pad upper electrode 32 connected to (28).                         

The data line 4 is connected to a data driver (not shown) through the data pad unit 34. The data pad portion 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth contact hole 38 penetrating through the passivation layer 50. The data pad upper electrode 40 is formed.

In the conventional thin film transistor array substrate having such a configuration, the gate line 2 has a wide line width d1 of about 20 μm or more, thereby reducing the aperture ratio. In this case, when the line width d1 of the gate line is formed narrow, the line resistance increases, so that the signal cannot be applied normally, so that the gate line 2 cannot be formed below 20 μm.

In order to solve this problem, as shown in FIG. 3, a thin film transistor array substrate having a structure having a high height instead of narrowing the line width of the gate line 2 has been proposed. However, when the height of the gate pattern such as the gate line 2 is increased in this manner, thin films such as the gate insulating film 44, the source / drain electrodes 10 and 12, and the semiconductor layer formed on the gate pattern have a high level of difference in the gate pattern. Due to the problem that partly disconnected.

Accordingly, it is an object of the present invention to provide a thin film transistor array substrate capable of improving the aperture ratio and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a thin film transistor array substrate comprising a gate line and a data line formed to cross each other on a substrate, a thin film transistor formed at the cross region, and a pixel electrode connected to the thin film transistor. The substrate may be provided with at least one line groove in a region where the gate line is to be formed, and the gate line may be partially located in the at least one line groove.

The thin film transistor array substrate may further include a gate pattern including a gate electrode connected to the gate line and a gate pad electrode extending from the gate line, wherein the gate pattern is partially positioned in the groove of the line shape. It features.

The gate line comprises a first metal pattern located in the line-shaped groove; And a second metal pattern positioned on the first metal pattern.

The first metal pattern is characterized in that the far-line form.

The thin film transistor array substrate includes a gate line and a data line formed to cross each other on a substrate, a thin film transistor formed at the cross region, and a pixel electrode connected to the thin film transistor. A first metal pattern formed on the substrate; The second metal pattern may be formed to cover the first metal pattern and may have a stepped end thereof with a stepped step.                     

The line width of the gate line is about 8 µm to 12 µm, and the height thereof is about 4500 µs to 5500 µs.

Method of manufacturing a thin film transistor array substrate according to the present invention comprises the steps of forming a groove in the form of at least one line on the substrate; Forming a gate pattern including a gate line including a first metal pattern positioned in the at least one line-shaped groove and a second metal pattern formed on the first metal pattern; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a source electrode and a drain electrode of the thin film transistor and a data line to which the source electrode is connected, on the substrate on which the gate insulating film is formed; Forming a passivation layer having a contact hole exposing the drain electrode on the source / drain pattern; And forming a pixel electrode connected to the drain electrode of the thin film transistor through the contact hole.

The step of forming at least one line-shaped groove on the substrate includes the steps of forming a photoresist pattern in a region other than a region where the line-shaped groove is to be formed on the substrate; And patterning the substrate exposed through the photoresist pattern to form the grooves in the form of lines.

The forming of the first metal pattern may include forming a first metal material on the line-shaped groove and photoresist pattern; Removing the photoresist pattern and simultaneously removing the first metal material on the photoresist pattern.                     

The first metal pattern may be formed in a multi-line shape.

The forming of the gate pattern may include forming a gate electrode connected to the gate line and a gate pad electrode extending from the gate line.

A method of manufacturing a thin film transistor array substrate according to the present invention includes a gate line formed on a substrate to cover a first metal pattern and the first metal pattern, and a second metal pattern having an end thereof at a step thereof. Forming a gate pattern; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a source electrode and a drain electrode of the thin film transistor and a data line to which the source electrode is connected, on the substrate on which the gate insulating film is formed; Forming a passivation layer having a contact hole exposing the drain electrode on the source / drain pattern; And forming a pixel electrode connected to the drain electrode of the thin film transistor through the contact hole.

The forming of the gate pattern may include forming a gate electrode connected to the gate line and a gate pad electrode extending from the gate line.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 11C.                     

4 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 4 taken along a line II-II ′.

4 and 5, the thin film transistor array substrate intersects the gate insulating layer 144 therebetween on the lower substrate 142 provided with the line-shaped groove 170 in the region where the gate line 102 is formed. A gate line 102 and a data line 104 formed, a thin film transistor 106 formed at each intersection thereof, and a pixel electrode 118 formed in a cell region provided in the intersection structure. Gate line 102 is partially located in the groove 170 of the line.

The thin film transistor array substrate includes a storage capacitor 120 formed at an overlapping portion of the pixel electrode 118 and the front gate line 102, a gate pad portion 126 connected to the gate line 102, and a data line ( And a data pad portion 134 connected to 104.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 112 connected to the pixel electrode 116. And an active layer 114 overlapping the gate electrode 108 and forming a channel between the source electrode 110 and the drain electrode 112. The active layer 114 is formed to overlap the data pad lower electrode 136, the storage electrode 122, the data line 104, the source electrode 110, and the drain electrode 112, and the source electrode 110 and the drain electrode ( It further comprises a channel section between 112). An ohmic contact layer 148 for ohmic contact with the data pad lower electrode 136, the storage electrode 122, the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114. do. The thin film transistor 106 keeps the pixel voltage signal supplied to the data line 104 charged to the pixel electrode 118 in response to the gate signal supplied to the gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the thin film transistor 106 through the first contact hole 116 penetrating the passivation layer 150. The pixel electrode 118 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 118 from the light source (not shown) toward the upper substrate.

The storage capacitor 120 includes the front gate line 102, the storage electrode 122 overlapping the gate line 102, the gate insulating layer 144, the active layer 114, and the ohmic contact layer 148 therebetween. The pixel electrode 118 is overlapped with the storage electrode 122 and the passivation layer 150 interposed therebetween, and connected to the pixel electrode 118 via the second contact hole 124 formed in the passivation layer 150. The storage capacitor 120 allows the pixel voltage charged in the pixel electrode 118 to be stably maintained until the next pixel voltage is charged.

The data line 104 is connected to a data driver (not shown) through the data pad unit 134. The data pad unit 134 is connected to the data pad lower electrode 136 through the data pad lower electrode 136 extending from the data line 104 and the fourth contact hole 138 penetrating the passivation layer 150. The data pad upper electrode 140 is formed.                     

The gate line 102 is connected to a gate driver (not shown) through the gate pad part 126. The gate pad lower electrode 128 is formed through the gate pad lower electrode 128 extending from the gate line 102 and the third contact hole 130 penetrating through the gate insulating layer 144 and the passivation layer 150. And a gate pad upper electrode 132 connected to 128.

Here, the gate line 102 is partially positioned in the groove 170 of the line shape formed on the lower substrate 142, so that the line width of the gate line 102 can be formed with a smaller line width d2. .

In more detail, the gate line 102 according to the present invention includes a first metal pattern 102a located in a line-shaped groove 170 provided on the lower substrate 142, and the first metal pattern 102a. It includes a second metal pattern 102a positioned on.

The gate line 102 formed of the first and second metal patterns 102a and 102b has a line width d2 smaller than the line width d1 of the gate line 2 shown in FIG. 1. In this case, a part of the height of the gate line 102 is formed in the line-shaped groove 170 provided on the lower substrate 142, thereby compensating for the increase in the line resistance due to the decrease in the line width d2. That is, by increasing the height of the gate line 102 instead of decreasing the line width d2, the line width of the gate line 102 can be reduced without changing the line resistance, and a portion of the elevated gate line 102 is formed on the lower substrate ( The thin film, such as the gate insulating layer 144, the source / drain electrodes 110 and 112, the semiconductor layer, and the like formed on the gate line 102 may not be disconnected by being positioned in the line-shaped groove 170 provided on the 142. Will not.                     

Accordingly, the area occupied by the gate line 102 formed on the lower substrate 142 is reduced, thereby improving the aperture ratio. Here, when the line width d2 of the gate line 102 is about 8 µm to 12 µm, the height thereof is formed to about 4500 GPa to 5500 GPa.

6A to 6D are views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention, and FIGS. 7A to 7E are views illustrating a method of manufacturing a gate pattern of the present invention.

First, as shown in FIG. 6A, gate patterns are formed on a lower substrate 142 using a photolithography process, an etching process, or the like.

Specifically, the photoresist pattern 158a is formed on the lower substrate 142 by a photolithography process and an etching process. Subsequently, the lower substrate 142 is patterned by an etching process using the photoresist pattern 158a as a mask to form a groove 170 having a line shape as shown in FIG. 7A.

Subsequently, the first gate metal material 127a is deposited on the line 170 and the photoresist pattern 158a using a deposition method such as sputtering or PECVD. Thereafter, the photoresist pattern 158a is removed using a stripping process. At this time, while the photoresist pattern 158a is removed, the first gate metal material 127a positioned on the photoresist pattern 158a is also removed (this method is referred to as "lift off"). And only the first gate metal material 127a formed in the line-shaped groove 170 remains. Accordingly, as shown in FIG. 7C, the first metal pattern 102a is formed in the groove 170 having a line shape.                     

The second gate metal material 127b is deposited on the lower substrate 142 on which the first metal pattern 102a is formed using a deposition method such as sputtering or PECVD. Thereafter, as shown in FIG. 7D, a photoresist pattern 180b is formed by a photolithography process and an etching process. The second gate metal material 127b is patterned using the photoresist pattern 180b as a mask to form a second metal pattern 102b. Thereafter, the photoresist pattern 180b is removed by the strip process, so that the gate electrode 108, the gate line 102, and the gate pad lower electrode 128 formed of the first and second metal patterns, as shown in FIG. 7E. A gate pattern comprising a is formed.

Here, as the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or double layer structure, and when the line width d2 of the gate line 102 is about 8 μm to 12 μm, The height is formed to about 4500Å to 5500Å.

Referring to FIG. 6B, the gate insulating layer 144, the active layer 114, the ohmic contact layer 148, and the source / drain patterns are sequentially formed on the lower substrate 142 on which the gate patterns are formed.

The gate insulating layer 144, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 142 on which the gate patterns are formed by a deposition method such as PECVD or sputtering.

A photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 104, the source electrode 110, the drain electrode 112 integrated with the source electrode 110, and the storage electrode 122 are formed. Source / drain patterns including are formed.

Then, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 148 and the active layer 114.

The photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, and then the source / drain pattern and the ohmic contact layer 148 of the channel portion are etched by a dry etching process. Accordingly, the active layer 114 of the channel portion is exposed to separate the source electrode 110 and the drain electrode 112.

Subsequently, the photoresist pattern remaining on the source / drain pattern portion is removed by a stripping process.

As the material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 6C, a passivation layer 150 including first to fourth contact holes 116, 124, 130, and 138 is formed on the gate insulating layer 144 on which the source / drain patterns are formed.

The passivation layer 150 is entirely formed on the gate insulating layer 144 on which the source / drain patterns are formed by a deposition method such as PECVD. The passivation layer 150 is patterned by a photolithography process and an etching process using a mask to form first to fourth contact holes 116, 124, 130, and 138. The first contact hole 116 is formed to pass through the passivation layer 150 to expose the drain electrode 112, and the second contact hole 124 is formed to pass through the passivation layer 150 to expose the storage electrode 122. do. The third contact hole 130 is formed to pass through the passivation layer 150 and the gate insulating layer 144 to expose the gate pad lower electrode 128. The fourth contact hole 138 is formed to pass through the passivation layer 150 to expose the data pad lower electrode 136.

As the material of the passivation layer 150, an inorganic insulating material such as the gate insulating film 194, an acryl-based organic compound having a low dielectric constant, or an organic insulating material such as BCB or PFCB is used.

Referring to FIG. 6D, transparent electrode patterns are formed on the passivation layer 150.

The transparent electrode material is deposited on the passivation layer 150 by a deposition method such as sputtering. Subsequently, the transparent electrode material is etched through a photolithography process and an etching process using a mask, thereby forming transparent electrode patterns including the pixel electrode 118, the gate pad upper electrode 132, and the data pad upper electrode 140. . The pixel electrode 118 is electrically connected to the drain electrode 112 through the first contact hole 116 and the storage electrode 122 overlapping the front gate line 102 through the second contact hole 124. Electrically connected. The gate pad upper electrode 132 is electrically connected to the gate pad lower electrode 128 through the third contact hole 130. The data pad upper electrode 140 is electrically connected to the data pad lower electrode 136 through the fourth contact hole 138. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, in the thin film transistor array substrate and the method of manufacturing the same according to the first embodiment of the present invention, a part of the gate pattern including the gate line 102 is formed in the line-shaped groove 170 provided on the lower substrate 142. Is formed. Accordingly, the gate pattern of the gate line 102 and the like can be formed with a small line width and a high height as compared with the related art, thereby reducing the area in which the gate line 102 and the like are formed on the lower substrate 142, thereby reducing the aperture ratio. Is improved.

8 is a cross-sectional view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

The thin film transistor array substrate shown in FIG. 8 has a multi-line (at least) line-shaped groove 170 provided on the lower substrate 142 on which the gate pattern is to be formed as compared with the thin film transistor array substrate shown in FIGS. 4 and 5. And having the same components except that the first metal pattern 102a is formed in the groove 170 of the multi-line (at least two or more of the line-shaped grooves) shape. The same components as those in FIGS. 4 and 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Lower substrate 142 of the thin film transistor array substrate shown in FIG. 8 As shown in FIG. 9, at least two grooves 170 having a multi-line shape are formed in a region where each gate pattern is to be formed. The first metal pattern 102a is formed in the groove 170 having a far line shape. Accordingly, the first metal pattern 102a is also formed in a multi-line form. Here, as in the first embodiment of the present invention, the first metal pattern 102a compensates for the increased line resistance of the gate pattern such as the gate line 102, that is, the gate line 102 and the gate electrode ( 108, the line resistance d increases as the line width d of the gate pattern including the gate pad lower electrode 128 decreases. Here, when the line width d2 of the gate line is about 8 µm to 12 µm, the height thereof is formed to about 4500 GPa to 5500 GPa.

In the method of manufacturing a thin film transistor array substrate according to the second exemplary embodiment of the present invention, at least two grooves 170 having a multi-line shape are formed in a region where a gate pattern is to be formed on the lower substrate 142, and the grooves 170 are formed. Is formed by the same method as the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention shown in FIGS. 6A to 7E except that the first metal pattern 102 having a multi-line shape is formed in As a result, the following detailed description will be omitted.

10 is a cross-sectional view illustrating a thin film transistor array substrate according to a third exemplary embodiment of the present invention.

In the thin film transistor array substrate illustrated in FIG. 10, a gate pattern having a two-layer structure is formed without a separate groove 170 formed on the lower substrate 142 as compared to the thin film transistor array substrate illustrated in FIGS. 4 and 5. Since the same components are provided except for the same components, the same components as those of FIGS. 4 and 5 will be denoted by the same reference numerals and detailed description thereof will be omitted.                     

Referring to FIG. 10, the gate pattern including the gate line 102, the gate electrode 108, and the get pad lower electrode 128 may include the first metal pattern 102a formed on the lower substrate 142. A second metal pattern 102b formed to cover the first metal pattern 102a is provided. Here, the line width d2 of the second metal pattern 102b has the same line width as that of the gate patterns of the first and second embodiments of the present invention, and the stepped end A of the stepped shape is formed on the first metal pattern 102a. It is formed to have Accordingly, the other thin film patterns at positions corresponding to the stepped step A of the gate pattern are also formed to have stepped stepped, so that the disconnection problem due to the sudden stepped thin film patterns on the gate pattern does not occur. Will not. In other words, even if the gate pattern has a narrow line width and is formed at a high height, the problem of disconnection of other thin film patterns positioned on the gate pattern is prevented. Here, when the line width d2 of the gate line 102 is about 8 µm to 12 µm, the height thereof is formed to about 4500 GPa to 5500 GPa.

As described above, the thin film transistor array substrate according to the third exemplary embodiment of the present invention is formed such that the gate pattern covers the first metal pattern 102a and the first metal pattern 102a and the end thereof has a stepped step. The branch is formed of the second metal pattern 102b. As a result, a gate pattern such as the gate line 102 having a narrow line width can be formed, thereby improving the aperture ratio.

11A to 11C are diagrams for describing a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention.

First, the first gate metal material is deposited on the lower substrate 142 by sputtering, PECVD, or the like. Then, the first gate metal material is patterned by a photolithography process and an etching process, and thus shown in FIG. 11A. As described above, the first metal pattern 102a is formed.

After the second gate metal layer 127b is deposited on the lower substrate 142 on which the first metal pattern 102a is formed, a photoresist pattern 189a is formed as shown in FIG. 11B by a photolithography process.

By using the photoresist pattern 189a as a mask, the second gate metal material 127b is patterned to form a second metal pattern 102b covering the first metal pattern 102a as shown in FIG. 11C. Here, the second metal pattern 102b has a stepped shape and is formed to cover the first metal pattern 102a.

Thereafter, the thin film transistor array substrate according to the third embodiment is formed by the same method as the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention illustrated in FIGS. 6B to 6C, and thus the detailed description thereof will be omitted. do.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the present invention enable a gate pattern such as a gate line to be formed with a small line width and a high height without increasing the line resistance. As a result, the area in which the gate lines and the like are formed on the lower substrate is reduced, thereby improving the aperture ratio.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A thin film transistor array substrate comprising a gate line and a data line formed to cross each other on a substrate, a thin film transistor formed at the cross region, and a pixel electrode connected to the thin film transistor. The substrate is provided with two or more line grooves in a region where one gate line is to be formed, The one gate line may include a first metal pattern partially positioned in a groove of two or more line shapes and a multi-line shape, and a second metal pattern located on the first metal pattern and in contact with the first metal pattern. Thin film transistor array substrate comprising a. The method of claim 1, The thin film transistor array substrate And a gate pattern including a gate electrode connected to the gate line and a gate pad electrode extending from the gate line. The gate pattern is a thin film transistor array substrate, characterized in that a portion is located in the line-shaped groove. delete delete delete The method of claim 1, The line width of the gate line is about 8㎛ to 12㎛, the height of the thin film transistor array substrate, characterized in that about 4500 ~ 5500GHz. Forming two or more line grooves in a region where one gate line is to be formed on the substrate; A gate pattern including a first metal pattern positioned in the at least two line grooves and having a multi-line first metal pattern and a second metal pattern formed on the first metal pattern to contact the first metal pattern Forming a; Forming a gate insulating film on the gate pattern; Forming a source / drain pattern including a source electrode and a drain electrode of the thin film transistor and a data line to which the source electrode is connected, on the substrate on which the gate insulating film is formed; Forming a passivation layer having a contact hole exposing the drain electrode on the source / drain pattern; And forming a pixel electrode connected to the drain electrode of the thin film transistor through the contact hole. The method of claim 7, wherein Forming two or more lined grooves on the substrate Forming a photoresist pattern on an area of the substrate except for an area in which the line-shaped groove is to be formed; And patterning the substrate exposed through the photoresist pattern to form the grooves in the form of lines. The method of claim 8, Forming the first metal pattern Forming a first metal material on the line-shaped groove and photoresist pattern; Removing the photoresist pattern and simultaneously removing the first metal material on the photoresist pattern. delete The method of claim 7, wherein Forming the gate pattern Forming a gate electrode connected to the gate line and a gate pad electrode extending from the gate line. delete delete

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