KR20150015608A - Electrostatic discharge circuit and display device having thereof - Google Patents

Abstract

The present invention discloses an electrostatic discharge circuit and a display device thereof. The electrostatic discharge circuit includes: a first thin-film transistor which includes: a first lower gate electrode; a first channel layer; a first source electrode; a first drain; and a first upper gate electrode overlapping the first lower gate electrode and the first channel layer; a second transistor including a second lower gate electrode, a second channel layer, and a second upper gate electrode overlapping the second channel layer; and a third thin-film transistor including a third lower gate electrode, a third channel layer, a third lower gate electrode, and a third upper gate electrode overlapping the third channel layer.

Description

TECHNICAL FIELD [0001] The present invention relates to an electrostatic discharge (ESD) circuit,

The present invention relates to an electrostatic discharge circuit capable of reducing a leakage current and reducing a design area of an electrostatic discharge circuit and a display device having the same.

One of the flat panel display devices is a device that changes the optical anisotropy by applying an electric field to the liquid crystal having fluidity of liquid and optical properties of crystals. It has lower power consumption and lower volume than a conventional cathode ray tube It is small and can be enlarged and fixed tax is widely used.

Such a liquid crystal display device has various modes depending on the nature of the liquid crystal and the structure of the pattern.

That is, a TN mode (twisted nematic mode) in which a liquid crystal director is arranged to be twisted by 90 ° and then a voltage is applied to control the liquid crystal director, and a twisted nematic mode in which a pixel is divided into a plurality of domains, An OCB mode (Optically Compensated Birefringence Mode) in which a compensating film is attached to an outer circumferential surface of a substrate to compensate for a phase change of light along a traveling direction of light, (In-Plane Switching Mode) in which a director of the liquid crystal is twisted in a plane parallel to the alignment layer, a VA mode in which the long axis of the liquid crystal molecules is vertically aligned on the plane of the alignment layer using a negative type liquid crystal and a vertical alignment film Vertical Alignment).

In particular, the liquid crystal display panel defines pixel regions by crossing a plurality of gate lines and a plurality of data lines. A thin film transistor (TFT) is disposed in an intersecting region of the gate line and the data line, and a data signal supplied from the data line according to the operation of the thin film transistor is supplied to the pixel electrode arranged in the pixel region, .

In order to prevent short-circuiting, disconnection due to external electrostatic discharge, and damage to elements of the array area where the thin-film transistors are formed, the gate lines and the data lines of the liquid crystal display device are each provided with an electrostatic discharge circuit .

Though thin-film transistors having a channel layer of an amorphous silicon layer (a-Si) are used as pixel regions or electrostatic discharge circuit elements of pad regions of a liquid crystal display panel in a display device such as a liquid crystal display device, Thin film transistors having an oxide semiconductor layer (a-IGZO) excellent in current characteristics as a channel layer have been applied.

FIG. 1 is a graph showing leakage current characteristics of an electrostatic discharge circuit composed of conventional amorphous silicon thin film transistors and an electrostatic discharge circuit composed of oxide semiconductor thin film transistors in a driving voltage. FIG. 2 is a graph showing the leakage current characteristics of conventional amorphous silicon thin film transistors FIG. 3 is a graph showing leakage current characteristics in an OFF voltage of an electrostatic discharge circuit constituted by the electrostatic discharge circuit and the oxide semiconductor thin film transistors. FIG. 3 is a graph showing the leakage current characteristics of the electrostatic discharge circuit according to the width and length of the channel layer of the oxide semiconductor thin film transistor. A graph comparing leakage currents.

A1 to A3 are electrostatic discharge circuits using oxide semiconductor thin film transistors, and B is an electrostatic discharge circuit using amorphous silicon thin film transistors.

The channel width (W) and the length (L) of the oxide semiconductor thin film transistor of A1 are 4/25 占 퐉, A2 is 4/40 占 퐉 and A3 is 4/75 占 퐉, B is the channel width of the amorphous silicon thin film transistor W) and the length (L) are 10/20 占 퐉.

 1 to 3, an electrostatic discharge circuit (A1) having oxide semiconductor thin film transistors in the range of 6V to 20V supplied with a data line and a gate line, as shown in FIG. 1, includes amorphous silicon thin film transistors It can be seen that the current characteristic is higher than that of the antistatic circuit (B).

This is because the electron mobility of the oxide semiconductor layer is higher than that of the amorphous silicon (FIG. 2). On the contrary, in the region where the off voltage (non-driving voltage: about 6 V or less) You can see a bigger thing in the electrostatic discharge circuit.

As shown in Fig. 3, when a thin film transistor A1 (4/25 mu m) having a channel width and a length similar to those of the electrostatic discharge circuit B using the amorphous silicon thin film transistor is used, the leakage current is four times larger can see.

In the case where the oxide semiconductor thin film transistor is used, it is necessary to reduce the leakage current to a level similar to that of the amorphous silicon thin film transistor. There is a problem that the channel layer length L of the oxide semiconductor needs to be extended up to 75 占 퐉 like A3 (4/75 占 퐉).

Further, if the length L of the channel layer of the oxide semiconductor becomes long, it is difficult to realize a high-resolution display device due to the limitation of the design area.

The present invention provides an electrostatic discharge circuit in which a thin film transistor of an electrostatic discharge circuit formed in a display device is formed in a dual gate structure to reduce a leakage current generated in an electrostatic discharge circuit that is not driven simultaneously and a display device having the electrostatic discharge circuit .

The present invention also provides a method of manufacturing a display device in which a thin film transistor of an electrostatic discharge circuit formed in a display device is formed in a dual gate structure and an opposite voltage to a gate driving voltage is applied to an upper gate electrode to prevent a leakage current of the electrostatic discharge circuit Circuit and a display device having the same.

According to an aspect of the present invention, there is provided an electrostatic discharge circuit including a first bottom gate electrode, a first channel layer, a first source electrode, a first drain, A first thin film transistor composed of a first upper gate electrode superimposed on the first thin film transistor; A second thin film transistor composed of a second bottom gate electrode, a second channel layer, a first source electrode, a second drain electrode, and a second top gate electrode overlapping the second bottom gate electrode and the second channel layer; And a third thin film transistor composed of a third lower gate electrode, a third channel layer, a second source electrode, a first drain electrode, and a third upper gate electrode overlapping the third lower gate electrode and the third channel layer And the first to third upper gate electrodes are electrically connected to each other.

Further, a display device including the electrostatic discharge circuit of the present invention includes: a liquid crystal display panel including a plurality of gate lines and data lines and a pixel region defined by the plurality of gate lines; A gate driving unit and a data driving unit for supplying a display signal to the liquid crystal display panel; A backlight unit for supplying a light source to the liquid crystal display panel; A signal controller for supplying a display signal and a control signal to the gate driver, the data driver, and the backlight unit; And at least one electrostatic discharge circuit connected to each of the plurality of gate lines and data lines in the liquid crystal display panel, wherein one end of the electrostatic discharge circuit is connected to each of the plurality of gate lines and the data lines And the other end is connected to a common line.

The electrostatic discharge circuit of the present invention and the display device having the same have the effect of reducing the leakage current generated in the non-conductive electrostatic discharge circuit by forming the thin film transistor of the electrostatic discharge circuit formed in the display device with a dual gate structure.

The present invention is also effective in preventing the leakage current of the electrostatic discharge circuit by forming the thin film transistor of the electrostatic discharge circuit formed in the display device with a dual gate structure and applying a voltage opposite to the gate driving voltage to the upper gate electrode have.

1 is a graph showing leakage current characteristics in a driving voltage of an electrostatic discharge circuit composed of conventional amorphous silicon thin film transistors and an electrostatic discharge circuit composed of oxide semiconductor thin film transistors.
2 is a graph showing leakage current characteristics in an off voltage of an electrostatic discharge circuit composed of conventional amorphous silicon thin film transistors and an electrostatic discharge circuit composed of oxide semiconductor thin film transistors.
3 is a graph comparing the leakage current of the electrostatic discharge circuit with the width and length of the channel layer of the oxide semiconductor thin film transistor.
4 is a block diagram showing the structure of a liquid crystal display device of the present invention.
5 is an equivalent circuit diagram of the electrostatic discharge circuit of FIG.
6 is a diagram showing a structure of an electrostatic discharge circuit according to the present invention.
7 is a cross-sectional view taken along the line I-I 'in Fig.
8 is a graph showing the threshold voltage characteristics of the oxide semiconductor thin film transistor used in the electrostatic discharge circuit of the present invention.
9 is a graph showing current characteristics of the electrostatic discharge circuit of the present invention.
10 is an enlarged view of the X region of FIG.
11 is a graph showing discharge characteristics of the present electrostatic discharge circuit.
12 is a graph showing a current characteristic according to a channel layer length of a dual gate structure thin film transistor formed in the electrostatic discharge circuit of the present invention.
13 is a graph showing a discharge characteristic according to a channel layer length of a dual gate structure thin film transistor formed in the electrostatic discharge circuit of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

Although the liquid crystal display device will be mainly described here, the present invention can be similarly applied to a flat panel display device such as an organic light emitting display device.

4 is a block diagram showing the structure of a liquid crystal display device of the present invention.

4, a liquid crystal display according to the present invention includes a liquid crystal display panel 30, a gate driving unit 40 and a data driving unit 50 connected thereto, a gray scale voltage generating unit 80 connected to the data driving unit 50, A backlight unit including a DC-DC converter 91 and a light source 92 connected to the DC-DC converter 91, and a signal controller 60 for controlling the backlight unit.

The liquid crystal display panel 30 includes a plurality of gate lines and data lines G1-Gn and D1-Dm and a plurality of pixels P connected to the gate lines and the data lines, . Although not shown in the drawings, the liquid crystal display panel 30 includes a liquid crystal layer interposed between the lower and upper substrates facing each other. The lower substrate is a substrate including a pixel electrode and a thin film transistor, and the upper substrate is a substrate including a color filter layer.

The gate lines G1-Gn extend substantially in the row direction and are substantially parallel to each other and the data lines D1-Dm extend in a substantially column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to the gate lines G1-Gn and the data lines D1-Dm and a liquid crystal capacitor CLC and a storage capacitor CST connected thereto. . The storage capacitor maintains a data signal applied to the pixel region for a predetermined period of time.

The switching element Q of each pixel is connected to a control terminal connected to the gate lines G1-Gn, an input terminal connected to the data lines D1-Dm, and an input terminal connected to the liquid crystal capacitor CLC and the storage capacitor CST Terminal device having an output terminal connected thereto.

The backlight unit for supplying the light source to the liquid crystal display panel 30 includes a DC-DC conversion unit 91 and a light source unit 92. The DC-DC conversion unit 91 receives a DC voltage And a plurality of LEDs or lamps mounted on the light source unit 92 are driven. The DC-DC converter 91 according to the present invention is mounted on an internal printed circuit board on which the signal controller 60, the gate driver 40 and the data driver 50 are mounted, And is mounted on an external printed circuit board together with a removal capacitor.

In the present invention, an electrostatic discharge circuit (ESD) is disposed in each of the gate lines G1, ..., Gn and the data lines D1, .., Dn. The electrostatic discharge circuit (ESD) formed in each of the gate lines and the data lines may have two or more electrostatic discharge circuits (ESD) connected in series per each line.

Although only the structure in which the electrostatic discharge circuit (ESD) is connected in series is shown in the drawing, the electrostatic discharge circuits (ESD) may be connected in parallel with the gate lines or the data lines, respectively.

When the electrostatic discharge circuits (ESD) are connected in series, one terminal is connected to one edge of the gate line or the data line and the other terminal is connected to a common line Vcom or ground (GND ). However, the other terminal of the electrostatic discharge circuit (ESD) may be connected to a signal line capable of supplying a reference voltage in the data driver 50 or the gate driver 40, as the case may be.

In addition, if there are at least two electrostatic discharge circuits (ESD) in the gate line or the data line, they may be connected in parallel. In this case, the power supply voltage VDD or the gate low voltage VGL supply line can be connected.

Further, the thin film transistors formed in the switching element and the electrostatic discharge circuit formed in the pixel region of the present invention have an oxide semiconductor (a-IGZO) as a channel layer. The oxide semiconductor thin film transistor formed in the electrostatic discharge circuit may have a dual gate structure in which a bottom gate electrode is formed under the channel layer and an upper gate electrode is formed over the channel layer.

The upper gate electrodes of the oxide semiconductor thin film transistors of the electrostatic discharge circuit of the present invention are electrically connected to each other and receive a voltage opposite to that of the lower gate electrode from the gate driver 40 or the data driver 50. This reduces the leakage current of the electrostatic discharge circuit (ESD) by shifting the threshold voltage (Vth) of the oxide thin film transistor formed in the electrostatic discharge circuit by? V.

Fig. 5 is an equivalent circuit diagram of the electrostatic discharge circuit of Fig. 4, Fig. 6 is a diagram showing the structure of the electrostatic discharge circuit according to the present invention, and Fig. 7 is a sectional view taken along line I-I 'of Fig.

5 to 7, an electrostatic discharge (ESD) circuit according to the present invention may include a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.

The source electrode of the first thin film transistor T1 is connected to the gate electrode of the second thin film transistor T2 and the gate electrode thereof is electrically connected to the drain electrode of the second thin film transistor T2 and the source electrode of the third thin film transistor T2. And the drain electrode is electrically connected to the gate electrode and the drain electrode of the third thin film transistor T3.

The source electrode of the second thin film transistor T2 is connected to the source electrode of the first thin film transistor T1 and the gate electrode of the second thin film transistor T2.

The gate electrode of the third thin film transistor T3 is connected to the drain electrode of the first thin film transistor T1 and the drain electrode of the third thin film transistor T3.

6, the source electrode of the first thin film transistor T1 and the source electrode of the second thin film transistor T1 are connected to the first and second thin film transistors T1, T2 are formed integrally with one electrode. The drain electrode of the first thin film transistor T1 is formed integrally with the drain electrode of the third thin film transistor T3. Accordingly, these electrodes are represented by a first source electrode 117 and a first drain electrode 118, but serve as source or drain electrodes for the two thin film transistors.

In the electrostatic discharge circuit (ESD) having the above structure, one terminal is connected to the gate line or the data line, and the other terminal is connected to the common line (Vcom) of the liquid crystal display device.

6, the first thin film transistor T1 of the electrostatic discharge circuit ESD includes a first lower gate electrode 101, a first channel layer 114, a first source electrode 117, And the second thin film transistor T2 comprises a second lower gate electrode 201, a second channel layer 214, a first source electrode 117 and a second drain electrode 217 .

The third thin film transistor T3 is composed of a third lower gate electrode 301, a third channel layer 314, a second source electrode 218 and a first drain electrode 118. [ The second drain electrode 217 and the second source electrode 218 are integrally formed and electrically connected.

The first source electrode 117 serves as a source electrode of the first thin film transistor T1 and the second thin film transistor T2 in the equivalent circuit of FIG. 5, and the first drain electrode 118 serves as the source electrode of the equivalent And functions as a drain electrode of the first thin film transistor T1 and the third thin film transistor T3 in the circuit.

The first source electrode 117 and the second bottom gate electrode 201 are electrically connected through a first contact hole C1 and the first bottom gate electrode 101 is electrically connected to a second contact hole The second source electrode 218 and the second drain electrode 217 are electrically connected to each other.

The first, second and third upper gate electrodes 150 and 150 are respectively connected to the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 of the electrostatic discharge circuit (ESD) 250, and 350 are formed. That is, the first, second, and third thin film transistors T1, T2, and T3 are formed in a dual gate structure having a bottom gate electrode and a top gate electrode, respectively.

The first, second and third upper gate electrodes 150, 250 and 350 are electrically connected by first, second and third connection portions 211, 212 and 213, respectively. The first, second and third upper gate electrodes 150, 250 and 350 electrically connected to each other are electrically connected to the control signal line 220 by a fourth connection part 214. Although not shown in the drawings, the unexplained RA refers to a region where the etch stopper layer is removed.

7, the third thin film transistor T3 of the electrostatic discharge circuit (ESD) of the present invention forms a metal film on the substrate 100 and then performs a mask process to form a third lower gate electrode 301 And a gate insulating layer 302 is formed on the substrate 100 on which the third bottom gate electrode 301 is formed. The gate insulating layer 302 may be formed of an SiNx-based insulating layer or an SiO ₂ -based insulating layer.

When the third bottom gate electrode 301 is formed, the first bottom gate electrode 101 and the second bottom gate electrode 201 of the first and second thin film transistors T1 and T2 shown in FIG. 6 are simultaneously . That is, Fig. 7 is a sectional view of the third thin film transistor T3, but the same configuration names of the first and second thin film transistors T1 and T2 are formed together.

The third bottom gate electrode 301 may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium Resistance opaque conductive material such as molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) In addition, a multi-layer structure in which a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) and an opaque conductive material are stacked can be formed.

As described above, when the third bottom gate electrode 301 and the gate insulating layer 302 are formed on the substrate 100, an oxide semiconductor layer is formed on the entire surface of the substrate 100, A third channel layer 314 is formed on the gate insulating layer 302 so as to overlap with the electrode 301.

The oxide semiconductor layer may be formed of an amorphous oxide including at least one of indium (In), zinc (Zn), gallium (Ga), and hafnium (Hf). For example, when a Ga-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of In2O3, Ga2O3, and ZnO may be used, or a single target of Ga-In-Zn oxide may be used. When the hf-In-Zn-O oxide semiconductor is formed by a sputtering process, each target formed of HfO 2, In 2 O 3, and ZnO may be used, or a single target of Hf-In-Zn oxide may be used.

As described above, when the third channel layer 314 is formed on the substrate 100, an insulating layer is formed on the entire surface of the substrate 100, and then a mask process is performed to form an etch stopper pattern 305. The etch stopper pattern 305 is formed at the center of the third channel layer 314 and is formed in a region spaced apart from the third channel layer 314 by a predetermined distance. 6, the etch stopper pattern 305 is patterned in a direction parallel to the third channel layer 314, the first drain electrode 118, and the second source electrode 218 through a predetermined patterning process. That is, as shown in FIG. 6, A region RA in which the gate insulating film 302 is exposed is formed.

This structure is also formed in the first and second thin film transistors T1 and T2.

As described above, when the etch stopper pattern 305 is formed on the substrate 100, a source / drain metal film is formed on the entire surface of the substrate 100, and then the second source electrode 218 and the source / 1 drain electrode 118 are formed. In particular, referring to FIG. 6, the first drain electrode 118 is electrically connected to the third lower gate electrode 301 through the third contact hole.

The source / drain metal layer may be a low resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum or tantalum. In addition, a multi-layered structure in which a transparent conductive material such as indium-tin-oxide or indium-zinc-oxide and an opaque conductive material are laminated can be formed.

As described above, when the second source electrode 218 and the first drain electrode 118 are formed on the substrate 100, a protective film 309 is formed on the entire surface of the substrate 100, (310).

A third upper gate electrode 350 is formed on the organic layer 310 corresponding to the third channel layer 314. When the organic layer 310 is formed, the third upper gate electrode 350 sequentially forms a pixel electrode or a common electrode in the pixel region of the liquid crystal display device. At this time, the third upper gate electrode 350 is formed.

That is, when the pixel electrode or the common electrode is formed on the organic layer 310, the third upper gate electrode 350 may be formed at the same time. Accordingly, the third upper gate electrode 350 may be formed of a transparent conductive material (ITO, ITZO, IZO).

As described above, in the present invention, the structure of the thin film transistor formed in the electrostatic discharge circuit (ESD) is formed in a dual gate structure, and the upper gate electrodes of the thin film transistor are electrically connected to each other.

The first, second and third upper gate electrodes 150, 250 and 350 of the electrostatic discharge circuit ESD are connected to the driving voltage supplied to the first, second and third lower gate electrodes 101, 201 and 301, The voltage of the opposite polarity is supplied to shift the threshold voltage (Vth) of the first to third thin film transistors to reduce the leakage current.

Accordingly, when the thin film transistors of the electrostatic discharge circuit (ESD) are N-MOS transistors, the threshold voltage (Vth) of the thin film transistor can be shifted by supplying a negative voltage to the upper gate electrode.

The range of the voltage (? V) shifted from the threshold voltage (Vth) is 0.1 to 3 V, and the voltage supplied to the upper gate electrodes of the thin film transistor can be changed according to the range of the voltage to be shifted.

In the present invention, the case where three transistors are embedded in the electrostatic discharge circuit (ESD) has been described. However, even when a single transistor or two or more transistors are applied, the bottom gate electrode and the top gate electrode structure are likewise employed.

In particular, even when two or more transistors are applied, the upper gate electrodes are electrically connected.

FIG. 8 is a graph showing the threshold voltage characteristics of the oxide semiconductor thin film transistor used in the electrostatic discharge circuit of the present invention. FIG. 9 is a graph showing current characteristics of the electrostatic discharge circuit of the present invention, 9 is an enlarged view of the area X in FIG. 9, and FIG. 11 is a graph showing discharge characteristics of the present electrostatic discharge circuit.

Referring to FIGS. 8 to 11, in the case of the N-MOS transistor of the thin film transistor formed in the electrostatic discharge circuit (ESD), the first to third upper gate electrodes of the first to third thin film transistors Voltage is supplied.

As described above, when a negative voltage is supplied to the upper gate electrode of the N-MOS thin film transistor, the threshold voltage (Vth) of the N-MOS thin film transistor changes by Vth +? V.

As shown in FIG. 8, it can be seen that the position of Vth moves to the right with reference to the Vgs voltage. The oxide semiconductor layer thin film transistor A1 was changed to the thin film transistor C of the present invention in which the Vth of the oxide semiconductor layer thin film transistor A1 was changed. A1 and C have a width W and a length L of the same channel layer. However, the gate electrode structure of the thin film transistor is different and the applied voltage differs to have different Vth values.

When the electrostatic discharge circuit (ESD) is constructed using the thin film transistors having the Vth changed as described above, the oxide semiconductor thin film transistors formed have the same channel width and the same length (W / L: 4/25 mu m) (A1-C). However, the leakage current is reduced.

In addition, although the off-voltage range of the non-conductive electrostatic discharge circuit increased from 6.8 V to 10 V, a leakage current was generated in the 6.8 V region in the past. However, in the present invention, The leakage current in the battery is remarkably reduced.

6, first to third upper gate electrodes are formed in each of the oxide semiconductor thin film transistors of the present invention, and a DC voltage having an opposite polarity to the lower gate electrodes is formed in the upper gate electrodes, And forcibly shifts the threshold voltage (Vth) of the thin-film transistors by the? V voltage.

 11, the electrostatic discharge circuit (ESD) using the oxide semiconductor thin film transistor having the dual gate structure and the electrostatic discharge circuit (ESD) using the oxide semiconductor thin film transistor having the single gate structure, It is seen that there is almost no change in the discharge characteristics of the discharge cell.

That is, the electrostatic discharge circuit (ESD) employing the dual gate structure thin film transistor of the present invention reduces the leakage current, but does not lower the discharge characteristic.

FIG. 12 is a graph showing a current characteristic according to a channel layer length of a dual gate structure thin film transistor formed in the electrostatic discharge circuit of the present invention. FIG. And a discharge characteristic according to the layer length.

C is a film thickness of the thin film which has a width W and a length L of the channel layer of the oxide semiconductor of 4/25 μm and which is supplied with a negative voltage to the upper gate electrode but shifted from the threshold voltage Vth by 1 V C1 is an electrostatic discharge circuit (ESD) employing a transistor, C1 is a width of the channel layer W and length L is 4/20 占 퐉 and Vth is shifted by 1V (? V) ) And the length L are shifted by 4/15 占 퐉 and 1 V (? V) from Vth, the width C3 and the length L of the channel layer are shifted by 4/10 占 퐉 and 1 V (? V) .

As described above, it can be seen that, in the case of shifting the Vth by .DELTA.V in the thin film transistor of the dual gate structure of the present invention, the channel layer width W and the length L of the thin film transistor can be reduced to 4/10 .mu.m (The driving voltage range is within 10V)

As shown in Fig. 13, the discharge characteristics of the electrostatic discharge circuit (ESD) also show that the discharge time is reduced by 50% at 4/10 탆 compared with the width W and length L of the channel layer being 4/25 탆 Can be seen.

As described above, in the present invention, leakage current is reduced in the same channel layer width (W) and length (L) by using an oxide semiconductor thin film transistor having a dual gate structure. However, when the leakage current of the electrostatic discharge circuit using the general oxide semiconductor thin film transistor is maintained, the length L of the channel layer can be remarkably reduced in the case of the dual gate structure of the present invention.

For example, a leakage current of an electrostatic discharge circuit (ESD) using an oxide semiconductor thin film transistor having a channel layer width W and a length L of 4/25 μm is determined by a width W and a length L of a channel layer, Is similar to the leakage current of the electrostatic discharge circuit (ESD) using a dual gate oxide semiconductor thin film transistor having a size of 4/10 m.

As described above, according to the present invention, the thin film transistor of the electrostatic discharge circuit formed in the display device has a dual gate structure, thereby reducing the leakage current generated in the non-driven electrostatic discharge circuit.

In the present invention, the thin film transistor of the electrostatic discharge circuit formed in the display device has a dual gate structure, and the opposite voltage to the gate driving voltage is applied to the upper gate electrode to prevent the leakage current of the electrostatic discharge circuit .

30: liquid crystal display panel 40: gate driver
50: Data driver 60: Signal controller
80: gradation voltage generation unit 91: DC-DC conversion unit
92: light source part 150: first upper gate electrode
250: second upper gate electrode 350: third upper gate electrode
T1: first thin film transistor T2: second thin film transistor
T3: Third thin film transistor

Claims (19)

A first thin film transistor composed of a first bottom gate electrode, a first channel layer, a first source electrode, a first drain electrode, and a first top gate electrode overlapping the first bottom gate electrode and the first channel layer;
A second thin film transistor composed of a second bottom gate electrode, a second channel layer, a first source electrode, a second drain electrode, and a second top gate electrode overlapping the second bottom gate electrode and the second channel layer; And
A third lower gate electrode, a third channel layer, a second source electrode, a third drain electrode, and a third upper gate electrode overlapped with the third lower gate electrode and the third channel layer, ,
Wherein the first to third upper gate electrodes are electrically connected to each other.
The electrostatic discharge circuit according to claim 1, wherein the first to third channel layers are formed of an oxide semiconductor.
The electrostatic discharge circuit according to claim 2, wherein the oxide semiconductor is IGZO (Indium Gallium Zinc Oxide).
The electrostatic discharge circuit according to claim 1, wherein the first to third top gate electrodes are supplied with a voltage having a polarity opposite to that of the first to third bottom gate electrodes.
The electrostatic discharge circuit according to claim 4, wherein the voltage (? V) shifted from the threshold voltage (Vth) of the first to third thin film transistors is 0.1 to 3V. The electrostatic discharge circuit according to claim 1, further comprising a control signal line for supplying a voltage to the first to third upper gate electrodes.
The electrostatic discharge circuit according to claim 6, wherein the first to third top gate electrodes and the control signal line are electrically connected to each other by first to fourth connection portions. 2. The semiconductor device according to claim 1, wherein the first upper gate electrode, the first source electrode and the first drain electrode, the second upper gate electrode, the first source electrode and the second drain electrode, 2 source electrode, and the first drain electrode.
The electrostatic discharge circuit according to claim 8, further comprising an organic film between the first to third upper gate electrodes and the protective film.
A liquid crystal display panel including a plurality of gate lines and data lines and a pixel region defined by the plurality of gate lines and data lines;
A gate driving unit and a data driving unit for supplying a display signal to the liquid crystal display panel;
A backlight unit for supplying a light source to the liquid crystal display panel;
A signal controller for supplying a display signal and a control signal to the gate driver, the data driver, and the backlight unit; And
Wherein the liquid crystal display panel includes at least one electrostatic discharge circuit connected to each of the plurality of gate lines and data lines,
Wherein one end of the electrostatic discharge circuit is connected to each of the plurality of gate lines and the data lines, and the other end is connected to a common line. The electrostatic discharge apparatus according to claim 10,
A first thin film transistor composed of a first bottom gate electrode, a first channel layer, a first source electrode, a first drain, and a first top gate electrode overlapping the first bottom gate electrode and the first channel layer;
A second thin film transistor composed of a second bottom gate electrode, a second channel layer, a first source electrode, a second drain electrode, and a second top gate electrode overlapping the second bottom gate electrode and the second channel layer; And
A third lower gate electrode, a third channel layer, a second source electrode, a third drain electrode, and a third upper gate electrode overlapped with the third lower gate electrode and the third channel layer, ,
And the first to third upper gate electrodes are electrically connected to each other.
The display device of claim 11, wherein the first to third channel layers are formed of an oxide semiconductor.
13. The display device according to claim 12, wherein the oxide semiconductor is IGZO (Indium Gallium Zinc Oxide).
11. The display device of claim 10, wherein the first to third top gate electrodes are supplied with a voltage having a polarity opposite to that of the voltages supplied to the first to third bottom gate electrodes.
The display device according to claim 14, wherein a voltage (? V) shifted from a threshold voltage (Vth) of the first to third thin film transistors is 0.1 to 3V.
The display device of claim 10, further comprising a control signal line for supplying a voltage to the first to third top gate electrodes.
17. The display device of claim 16, wherein the first to third upper gate electrodes and the control signal line are electrically connected to each other by first to fourth connection portions. 11. The semiconductor device according to claim 10, wherein the first upper gate electrode, the first source electrode and the first drain electrode, the second upper gate electrode, the first source electrode and the second drain electrode, 2 source electrode, and the first drain electrode.
The display device of claim 18, further comprising an organic film between the first to third upper gate electrodes and the passivation layer.

Images