KR101412740B1 - Liquid display device and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of manufacturing the same that prevent channel shorting of a thin film transistor by static electricity.

A liquid crystal display of the present invention includes a first thin film transistor for applying a high gray scale data signal inputted from a first data line to a first pixel electrode, a first thin film transistor connected to a first pixel electrode through a first contact hole, A first storage capacitor for storing a high gray scale data signal and a second thin film capacitor for applying a low gray scale data signal inputted from a second data line to a second pixel electrode connected through a second contact hole, And an upper electrode connected to the second pixel electrode through a third contact hole, and includes a second storage capacitor for storing a low gray level data signal.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

1 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

FIG. 2A is a view showing a structure of a pixel of the liquid crystal display device shown in FIG. 1,

FIG. 2B is a sectional view taken along line I-I 'of the first storage capacitor shown in FIG. 2A,

3A to 3E are views for explaining a method of manufacturing a thin film transistor substrate of the liquid crystal display device shown in FIG. 1, and FIGS.

4 is a block diagram illustrating a liquid crystal display device according to another embodiment of the present invention, and Fig.

5 is a diagram showing the pixel structure of the liquid crystal display device shown in FIG.

 Description of the Related Art

110: liquid crystal panel 120: gate driver

130: Data driver 140: Timing controller

150: gamma voltage section 152: high tone gamma voltage section

154: low gray level gamma voltage unit 156: gamma voltage switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that prevent channel shorting of a thin film transistor due to static electricity.

In general, a liquid crystal display device refers to a device that displays an image by driving liquid crystal molecules according to an electric field to adjust the light transmittance. Since the liquid crystal display device transmits light in a direction that is not shielded by the liquid crystal to display an image, the viewing angle is narrower than in a relatively different display device.

Vertical alignment mode is used as a typical wide viewing angle technique of a liquid crystal display device. In the vertical alignment mode, liquid crystal molecules having a negative dielectric anisotropy are vertically aligned and driven perpendicular to the electric field direction to control the light transmittance. Such a vertical alignment mode technique is classified into a multi-domain vertical alignment (MVA) technique, a patterned-ITO vital alignment (PVA) technique, and an S-patterned-ITO vital alignment (S-PVA) technique according to a domain formation method.

MVA (Multi-domain Vertical Alignment) technology is a VA mode using protrusions. The protrusions are formed on the upper and lower plates so that the liquid crystal molecules are pre-tilted symmetrically with respect to the protrusions. And is driven in a pre-tilted direction to form a multi-domain.

The patterned-ITO Vetal Alignment (PVA) technique is a VA mode using a slit pattern. A slit is formed in the common electrode and the pixel electrode of the upper and lower plates, and liquid crystal molecules are formed by using a fringe electric field generated by the slit Domain is formed by being symmetrically driven with respect to the slit.

In the S-PVA (S-Patterned-ITO Vetical Alignment) technique, a pixel is classified into a high gray sub-pixel and a low gray sub-pixel, which represent data by different gamma curves, And independently driven through a gray-scale transistor and a low-gray-scale transistor.

However, in the manufacturing process of a liquid crystal display device using the S-PVA technique, channel short defects due to static electricity, particularly static electricity, short-circuit the channel of the high gray scale transistor, resulting in a problem that the production yield of the liquid crystal display device is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display device in which a drain electrode of a transistor for switching a high gray scale data signal is directly connected to an upper electrode of a storage capacitor to remove a contact hole between the drain electrode and the high gray scale pixel electrode, .

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a first thin film transistor for applying a first data signal voltage input from a first data line to a first pixel electrode; A first storage capacitor connected to the first pixel electrode through a first contact hole and having a terminal electrode directly connected to the first thin film transistor, the first storage capacitor storing the first data signal voltage; A second thin film transistor for applying a second data signal voltage input from a second data line to a second pixel electrode connected through a second contact hole; And a second storage capacitor including a terminal electrode connected to the second pixel electrode through a third contact hole, the second storage capacitor storing the second data signal voltage.

Here, it is preferable that the first data signal voltage and the second data signal voltage are generated by different gradation voltage curves.

The first thin film transistor includes a source electrode connected to the first data line and a drain electrode connected directly to the terminal electrode of the first storage capacitor.

The second thin film transistor includes a source electrode connected to the second data line and a drain electrode connected to the second pixel electrode.

It is preferable that the first storage capacitor has a capacity larger than that of the second storage capacitor.

The first thin film transistor applies the first data signal voltage to the first pixel electrode during a certain period of one horizontal period, and the second thin film transistor applies the second data signal voltage to the first pixel electrode during a certain period of one horizontal period It is preferable to apply the voltage to the second pixel electrode for the remaining period.

According to another aspect of the present invention, there is provided a liquid crystal display comprising: a data driver for applying a first data signal voltage to a first data line and applying a second data signal voltage to a second data line; A gate driver for applying a gate driving signal to the gate line; A first thin film transistor for applying the first data signal voltage to the first pixel electrode in response to the gate driving signal; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to store the first data signal voltage; A second thin film transistor for applying the second data signal voltage to a second pixel electrode connected through a second contact hole in response to the gate driving signal; And a second storage capacitor connected to the second pixel electrode through a third contact hole to store the second data signal voltage.

Here, the liquid crystal display of the present invention further includes a gamma voltage unit for supplying a first gray-scale gamma voltage for generating the first data signal voltage and a second gray-scale gamma voltage for generating the second data signal voltage to the data driver .

The liquid crystal display of the present invention is defined by a plurality of first data lines for transmitting a first data signal voltage, a plurality of second data lines for transmitting a second data signal voltage, and a plurality of gate lines for transmitting a gate driving signal Wherein the pixel includes: a first pixel electrode for displaying the first data signal voltage; A first thin film transistor for applying the first data signal voltage to the first pixel electrode; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, the first storage capacitor storing the first data signal voltage; A second pixel electrode for displaying the second data signal voltage; A second thin film transistor connected to the second pixel electrode through a second contact hole and applying the second data signal voltage to the second pixel electrode; And a second storage capacitor connected to the second pixel electrode through a third contact hole and accumulating the second data signal voltage.

The first storage capacitor includes a first terminal electrode, a second terminal electrode connected to the first thin film transistor and the first pixel electrode, and an insulating film between the first terminal electrode and the second terminal electrode.

The second storage capacitor may include a third terminal electrode connected to the first terminal electrode, a fourth terminal electrode connected to the second pixel electrode, and an insulating film between the third terminal electrode and the fourth terminal electrode.

The second pixel electrode may be formed separately from the first pixel electrode, and may be formed to surround the first pixel electrode.

The liquid crystal display of the present invention includes: a first thin film transistor for applying a first data signal voltage input from a data line to a first pixel electrode in response to a first gate driving signal; A first storage capacitor connected to the first pixel electrode through a first contact hole and having a terminal electrode directly connected to the first thin film transistor, the first storage capacitor storing the first data signal voltage; A second thin film transistor for applying a second data signal voltage input from the data line to a second pixel electrode connected through a second contact hole in response to a second gate driving signal; And a second storage capacitor including a terminal electrode connected to the second pixel electrode through a third contact hole, the second storage capacitor storing the second data signal voltage.

Here, it is preferable that the first gate driving signal and the second gate driving signal are sequentially applied to the first and second thin film transistors for one horizontal period time.

A method of manufacturing a liquid crystal display device according to the present invention includes: forming a gate line having a first gate electrode on a glass substrate and a storage capacitor line including a first terminal electrode; An active layer forming step of forming an active layer over the first gate electrode with a gate insulating film interposed therebetween on a glass substrate on which the gate line and the storage capacitor line are formed; A first data line for transmitting a first data signal voltage, a first source electrode and a first drain electrode of a first transistor connected to the first data line, a second terminal electrode opposed to the first terminal electrode, A source / drain forming step of forming a source / drain pattern including a first drain line connecting the first drain electrode and the second terminal electrode; And forming a first contact hole exposing the second terminal electrode by forming an organic insulating film on the glass substrate on which the source / drain pattern is formed and removing the formed organic thin film.

Here, the gate line forming step may include forming a storage capacitor line including a gate line including a second gate electrode and a third terminal electrode on a glass substrate, and the active layer forming step may include: And forming an active layer on the glass substrate on which the capacitor line is formed with the gate insulating film interposed therebetween so as to overlap the second gate electrode, wherein the source / A second source electrode and a second drain electrode of a second transistor connected to the second data line, a fourth terminal electrode opposed to the third terminal electrode, and a second drain line connected to the second drain electrode Forming a source / drain pattern, wherein the forming of the contact hole partially removes the organic insulating film formed, A second contact hole exposing a second drain line connected to the lane electrode, and a third contact hole exposing the fourth terminal electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: forming a first pixel electrode for displaying a first data signal voltage and a second pixel electrode for displaying a low gray level data signal on a glass substrate having the contact hole formed thereon by transparent conductive patterning And a pixel electrode forming step of forming a pixel electrode.

The pixel electrode forming step may include forming the first pixel electrode by connecting the first pixel electrode to the first contact hole and connecting the second pixel electrode to the second contact hole and the third contact hole .

The forming of the gate line may include forming the storage capacitor line such that the first terminal electrode has a larger area than the third terminal electrode. In the source / drain forming step, the second terminal electrode is electrically connected to the fourth terminal electrode It is preferable to form the source / drain pattern so as to have a larger area.

A method of manufacturing a liquid crystal display device according to the present invention includes: forming a storage capacitor line including a gate line including first and second gate electrodes on a glass substrate and first and second terminal electrodes; An active layer forming step of forming an active layer over the first and second gate electrodes with a gate insulating film interposed therebetween on a glass substrate on which the gate lines and the storage capacitor lines are formed; First and second data lines for respectively transmitting first and second data signal voltages, a first source electrode and a first drain electrode of a first transistor connected to the first data line, A second source electrode and a second drain electrode of the second transistor, third and fourth terminal electrodes opposed to the first and second terminal electrodes, and a drain line connecting the first drain electrode and the third terminal electrode, A source / drain forming step of forming a source / drain pattern including the source / drain pattern; A first contact hole exposing the third terminal electrode, and a second contact hole exposing a drain line connected to the second drain electrode, the method comprising: forming an organic insulating layer on the glass substrate on which the source / drain pattern is formed, And a third contact hole exposing the fourth terminal electrode; And a first pixel electrode connected to the first contact hole and a second data signal line connected to the second contact hole and the third contact hole, And a pixel electrode forming step of forming a second pixel electrode connected to the pixel electrode by transparent conductive patterning.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram showing a liquid crystal display according to an embodiment of the present invention. 1, a liquid crystal display 100 according to an exemplary embodiment of the present invention includes a liquid crystal panel 110, a gate driver 120 for driving gate lines GL1 and GL2 of the liquid crystal panel 110, A data driver 130 for driving the data lines DL1 to DL4 of the liquid crystal panel 110, a timing controller 140 for controlling the gate driver 120 and the data driver 130, And a gamma voltage unit 150 for selectively supplying a voltage and a low-gradation gamma voltage.

The liquid crystal panel 110 includes a plurality of pixels P1 to P4 defined by one gate line GL1 and two data lines DL1 and DL2 and DL3 and DL4. One pixel P1 is connected to the first pixel electrode VH and the second pixel electrode VL, the first pixel electrode VH and the second pixel electrode VL formed in the low gradation region and the high gradation region, A first thin film transistor T1 and a second thin film transistor T2 which are independently connected and a gate line GL1 commonly connected to the first thin film transistor T1 and the second thin film transistor T2, And data lines DL1 and DL2 connected to the transistor T1 and the second thin film transistor T2, respectively. Here, the first pixel electrode (VH) and the second pixel electrode (VL) formed in the low gradation region and the high gradation region respectively represent data according to the gradation voltage generated by different gradation voltage curves (Gamma-curves).

On the other hand, the odd-numbered pixel P1 connected to the odd-numbered gate line GL1 is connected to the first pixel electrode VH and the second thin-film transistor T2 is connected to the second pixel electrode Numbered pixel P2 connected to the odd gate line GL1 is connected to the second pixel electrode VL and the second thin film transistor T3 is connected to the second pixel electrode VL. Is connected to the first pixel electrode (VH).

The odd-numbered pixel P3 connected to the even-numbered gate line GL2 is connected to the second pixel electrode VL through the first thin film transistor T5 and the second thin-film transistor T6 is connected to the first pixel electrode VH The even pixel P4 connected to the even gate line GL2 has a structure in which the first thin film transistor T7 is connected to the first pixel electrode VH and the second thin film transistor T8 is connected to the first pixel electrode VH, And connected to the second pixel electrode VL.

The timing controller 140 generates a gate control signal for controlling the gate driver 120 and a data control signal for controlling the data driver 130 by using a synchronous signal and a clock signal input from the outside, And supplies the data signals to the data driver 130. The timing controller 140 also generates a switching signal for controlling the gamma voltage unit 150. Where the switching signal controls the gamma voltage switch 156 to switch the outputs of the high gray gamma voltage portion 152 and the low gray gamma voltage portion 154 during one horizontal period period.

The gamma voltage unit 150 includes a high gray level gamma voltage unit 152 for generating a plurality of high gray level gamma voltages, a low gray level gamma voltage unit 154 for generating a plurality of low gray level gamma voltages, And a gamma voltage switch 156 for switching the output of the low gray level gamma voltage section 154 and the low gray level gamma voltage section 154. [ The gamma voltage switch 156 switches the high gray level gamma voltage from the high gray level gamma voltage portion 152 during the 1/2 horizontal period period to the low gray level gamma voltage 154 from the low gray level gamma voltage portion 154 during the remaining 1/2 horizontal period, And supplies the data to the data driver 130.

The gate driver 120 applies gate driving signals to the gate lines GL1 and GL2 of the liquid crystal panel 110 in response to a gate control signal from the timing controller 140 to sequentially drive the gate lines GL1 and GL2 .

In response to the data control signal from the timing controller 140, the data driver 130 uses the high gray-scale gamma voltage during the 1/2 horizontal period to convert the data signal from the timing controller 140 into a high gray- And supplies the converted data signal to the data line DL1. The data signal from the timing controller 140 is converted into a low-gradation data signal by using the low-gradation gamma voltage during the remaining half horizontal period, and supplied to the data line DL2 do.

2A and 2B, the structure of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention will be described in more detail. 2A is a plan view showing a structure of a pixel of the liquid crystal display device of FIG. As shown in FIG. The pixel of the liquid crystal display according to an exemplary embodiment of the present invention includes a first pixel electrode 260, a second pixel electrode 262, a first thin film transistor T1, a second thin film transistor T2, a gate line 210 A first data line 220, a second data line 225, a first storage capacitor CST1, and a second storage capacitor CST2.

The first pixel electrode 260 is connected to the drain electrode 254 of the first transistor T 1 and the upper electrode 250 of the first storage capacitor CST 1 through the contact hole 268. The first pixel electrode 260 receives the high gray level data signal from the first data line 220 through the first transistor T1 and expresses the high gray level data signal.

The second pixel electrode 262 may be formed separately from the first pixel electrode 260 to surround the first pixel electrode 260. The second pixel electrode 262 is connected to the drain electrode 259 of the second transistor T2 through the contact hole 264 and is connected to the upper electrode of the second storage capacitor CST2 through the contact hole 266 255). The second pixel electrode 262 receives the low gray level data signal from the second data line 225 through the second transistor T2 to express the low gray level data signal.

The first thin film transistor T1 includes a gate electrode 212 connected to the gate line 210, a source electrode 222 connected to the first data line 220, a drain electrode connected to the drain line 252 254, and an active layer 230 overlapping the gate electrode 212 via an insulating layer. The first thin film transistor Tl is connected to the drain electrode 254 in response to a gate driving signal applied to the gate line 210 by applying a high gray scale data signal supplied from the first data line 220 during a 1/2 horizontal period period To the drain line 252.

The second thin film transistor T2 includes a gate electrode 214 connected to the gate line 210, a source electrode 227 connected to the second data line 225, a drain electrode connected to the drain line 257 259, and an active layer 232 overlapping the gate electrode 214 via an insulating layer. The second thin film transistor T2 responds to a gate driving signal applied to the gate line 210 and applies a high gray scale data signal supplied from the second data line 225 to the drain electrode 259 during the remaining 1/2 horizontal period, Lt; / RTI >

The gate line 210 is connected to the gate electrode 212 of the first thin film transistor T1 and the gate electrode 214 of the second thin film transistor T2. The gate line 210 applies a gate driving signal input from the gate driver to the gate electrode 212 of the first thin film transistor T1 and the gate electrode 214 of the second thin film transistor T2.

The first data line 220 is formed on one side of the pixel and is perpendicular to the gate line 210 and is connected to the source electrode 222 of the first thin film transistor T 1. The first data line 220 applies a high gray level data signal input from the data driver to the source electrode 222 of the first thin film transistor T1 during the 1/2 horizontal period.

The second data line 225 is formed on the other side of the pixel and is perpendicularly intersected with the gate line 210 and connected to the source electrode 227 of the second thin film transistor T2. The second data line 225 applies a low gray level data signal input from the data driver to the source electrode 227 of the second thin film transistor T2 during the remaining half horizontal period.

The first storage capacitor CST1 includes a lower electrode 244 connected to the storage capacitor line 240 and an upper electrode 250 overlapping the lower electrode 244 via an insulating layer. The upper electrode 250 is integrated with the drain electrode 254 of the first thin film transistor Tl through the drain line 252. The lower electrode 244 and the upper electrode 250 of the first storage capacitor CST1 preferably have a larger area than the lower electrode 242 and the upper electrode 255 of the second storage capacitor CST2.

The upper electrode 250 connected to the drain line 252 is connected to the first pixel electrode 260 through the contact hole 268. The high gray scale data signal inputted through the drain line 252 connected to the drain electrode 254 of the first thin film transistor Tl is applied to the first pixel electrode 260 and is simultaneously applied to the first storage capacitor CST1 Can be accumulated.

The second storage capacitor CST2 includes a lower electrode 242 connected to the storage capacitor line 240 and an upper electrode 255 overlapping the lower electrode 242 via an insulating layer. The upper electrode 255 is connected to the second pixel electrode 262 connected to the drain electrode 259 of the second thin film transistor T 2 through the contact hole 266. The low gray level data signal input through the drain line 257 connected to the drain electrode 259 of the second thin film transistor T2 is applied to the second pixel electrode 262 and accumulated in the second storage capacitor CST2 .

The first storage capacitor CST1 will be described in more detail. 2B is a sectional view taken along line I-I 'of the first storage capacitor of FIG. 2A. 2B, the first storage capacitor CST1 includes a lower electrode 244 formed on a glass substrate 202 and an upper electrode 244 formed by overlapping the lower electrode 244 with an insulating layer 204 interposed therebetween 250). The upper electrode 250 is integrated with the drain electrode of the first thin film transistor through the drain line 252 and is connected to the first pixel electrode 260 through the contact hole 268 formed in the protective film 206.

The liquid crystal display according to an exemplary embodiment of the present invention may be used for connecting the drain electrode 254 of the first thin film transistor T1 to the upper electrode 250 and the first pixel electrode 260 of the first storage capacitor CST1 A second contact hole 264 and a second pixel electrode 262 for connecting the drain electrode 259 of the second thin film transistor T 2 and the second pixel electrode 262, And a third contact hole 266 for connection of the upper electrode 255 of the bipolar capacitance CST2.

In the liquid crystal display according to an exemplary embodiment of the present invention, the contact hole for connection between the first pixel electrode 260 and the upper electrode 255 of the first storage capacitor CST1 is removed, The drain electrode 254 of the transistor T1 is directly connected to the upper electrode 255 of the first storage capacitor CST1 so that static electricity flows into the first thin film transistor T1 during the manufacturing process of the liquid crystal display device And the generated static electricity can be accumulated in the first storage capacitor CST1 before being introduced into the first thin film transistor T1. Accordingly, in the manufacturing process of the liquid crystal display device, a problem that a channel of a high gray scale transistor is short-circuited due to a channel short failure due to static electricity, particularly static electricity, can be solved.

The contact hole for connection between the first pixel electrode 260 and the upper electrode 255 of the first storage capacitor CST1 is removed and the drain electrode 254 of the first thin film transistor T1 is directly connected The second storage capacitor CST1 is connected to the upper electrode 255. However, the present invention is not limited to this structure, and a contact hole for connection between the second pixel electrode 262 and the second storage capacitor CST2 may be removed And the drain electrode 257 of the second thin film transistor T2 can be directly connected to the upper electrode 255 of the second storage ratio CST2.

Hereinafter, a method of manufacturing the thin film transistor substrate of the liquid crystal display device of FIG. 1 will be described with reference to FIGS. 3A to 3E. FIG.

3A shows a gate line forming process. The gate line forming process forms a storage capacitor line 240 including the gate line 210 and the lower electrodes 242 and 244 including the gate electrodes 212 and 214 on the glass substrate. The storage capacitor lines 240 are formed in parallel with the gate lines 210. Specifically, a metal layer is deposited on a glass substrate by a method such as a sputtering method. The metal layer may have a single layer or a multilayer structure of molybdenum (Mo), aluminum (Al), chromium (Cr), and the like. Then, a metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate line 210 and a storage capacitor line 240. Here, the metal layer patterning is preferably performed such that the area of the lower electrode 244 of the first storage capacitor CST1 is formed larger than the area of the lower electrode 242 of the second storage capacitor CST2.

3B shows a process of forming an active layer. In the active layer forming step, a gate insulating film is formed on a glass substrate on which the gate line 210 and the storage capacitor line 240 are formed, and the active layers 230 and 232 are formed on the gate electrodes 212 and 214 in a second mask process . The active layers 230 and 232 may further include an ohmic contact layer. Specifically, a gate insulating film, an amorphous silicon layer, and an n ⁺ amorphous silicon layer are sequentially formed on a glass substrate subjected to a first mask process by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). The amorphous silicon layer and the n ⁺ amorphous silicon layer are formed as the active layers 230 and 232 by the photolithography process and the etching process using the second mask. The gate insulating film is preferably an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The active layer may also be formed at the intersection of the gate line 210 and the data line or at the intersection of the storage capacitor line 240 and the data line.

3C shows a source / drain pattern forming process. The source / drain pattern forming process step forms a source / drain metal pattern on the gate insulating film on which the active layers 230 and 232 are formed. The source / drain metal pattern includes a first data line 220, a source electrode 222 and a drain electrode 254 of the first thin film transistor, an upper electrode 250 of the first storage capacitor CST1, The drain line 252 connecting the drain electrode 254 of the first storage capacitor CST1 and the upper electrode 250 of the first storage capacitor CST1, the second data line 225, the source electrode of the second thin film transistor T2 And a drain line 257 connected to the drain electrode 259 of the second storage capacitor CST2 and the drain electrode 259 of the second storage capacitor CST2.

The first data line 220 is connected to the source electrode 222 of the first thin film transistor T 1 and the second data line 225 is connected to the source electrode 227 of the second thin film transistor T 2. The upper electrode 250 of the first storage capacitor CST1 is formed corresponding to the lower electrode 244 of the first storage capacitor CST1 and the upper electrode 255 of the second storage capacitor CST2 is formed corresponding to the And is formed corresponding to the lower electrode 242 of the storage capacitor CST2. Therefore, the area of the upper electrode 250 of the first storage capacitor CST1 is formed to be larger than the area of the upper electrode 255 of the second storage capacitor CST2.

Specifically, a source / drain metal layer is formed on a glass substrate subjected to a second mask process by a sputtering method. Then, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask. The ohmic contact layer exposed between the source electrodes 222 and 227 and the drain electrodes 254 and 259 is removed to separate the source electrodes 222 and 227 and the drain electrodes 254 and 259. A first thin film transistor T1 connected to the gate line 210 and the first data line 220 and a second thin film transistor T2 connected to the gate line 210 and the second data line 225 .

Fig. 3D shows a contact hole forming step. In the contact hole forming process, the organic insulating film 206 is formed on the gate insulating film on which the source / drain metal pattern is formed, and a part of the organic insulating film 206 is removed by the fourth mask process to form the first contact hole 268, A contact hole 264 and a third contact hole 266 are formed. The first contact hole 268 is formed to connect the drain electrode 254 of the first thin film transistor Tl to the upper electrode 250 of the first storage capacitor CST1 and the first pixel electrode to be formed in the next process. will be. The second contact hole 264 is for connecting the drain electrode 259 of the second thin film transistor T2 and the second pixel electrode to be formed in the next process. The third contact hole 266 is for connecting the second pixel electrode to the upper electrode 255 of the second storage capacitor CST2.

Specifically, an organic insulating material such as an acrylic organic compound is coated on a glass substrate subjected to a third mask process by a spin coating method or a spinless coating method to form an organic insulating film 206 . A part of the organic insulating film 206 is removed by a photolithography process and an etching process using the fourth mask to remove the upper electrode 250 of the first storage capacitor CST1 and the drain electrode 259 of the second thin film transistor T2, The second contact hole 264 and the third contact hole 266 by exposing the end of the drain line 257 connected to the first storage capacitor CST2 and the upper electrode 242 of the second storage capacitor CST2, .

3E shows a pixel electrode forming process. In the pixel electrode forming step, a first pixel electrode 260 and a second pixel electrode 262 of a transparent conductive pattern are formed on the organic insulating film. Specifically, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is applied on a glass substrate that has undergone a fourth mask process by a deposition method such as sputtering. Then, a first pixel electrode 260 and a second pixel electrode 262 are formed by patterning using a photolithography process and an etching process using a fifth mask.

The first pixel electrode 260 is connected to the upper electrode 250 of the first storage capacitor CST1 through the first contact hole 268 in the pixel electrode forming process. The second pixel electrode 262 is connected to the drain line 257 connected to the drain electrode 259 of the second thin film transistor T2 through the second contact hole 264 and the third contact hole 266 And is connected to the upper electrode 255 of the second storage capacitor CST2.

The thin film transistor substrate manufactured by the above-described method can be assembled with a color filter substrate on which a common electrode and a color filter are formed, and can be used in a manufacturing process of a liquid crystal display device.

4 is a block diagram illustrating a liquid crystal display device according to another embodiment of the present invention. 4, a liquid crystal display 300 according to an exemplary embodiment of the present invention includes a liquid crystal panel 310, a gate driver 320 for driving the gate lines GL1 to GL4 of the liquid crystal panel 310, A data driver 330 for driving the data lines DL1 and DL2 of the liquid crystal panel 310, a timing controller 340 for controlling the gate driver 320 and the data driver 330, And a gamma voltage unit 350 for selectively supplying the low-gradation gamma voltage.

The liquid crystal panel 310 includes a plurality of pixels P1 to P4 defined by two gate lines GL1, GL2, GL3 and GL4 and one data line DL1. One pixel P1 is connected to the first pixel electrode VH and the second pixel electrode VL, the first pixel electrode VH and the second pixel electrode VL formed in the low gradation region and the high gradation region, A first thin film transistor T1 and a second thin film transistor T2 which are independently connected and a data line DL1 commonly connected to the first thin film transistor T1 and the second thin film transistor T2, And gate lines GL1 and GL2 connected to the transistor T1 and the second thin film transistor T2, respectively. Here, the first pixel electrode (VH) and the second pixel electrode (VL) formed in the low gradation region and the high gradation region respectively represent data according to the gradation voltage generated by different gradation voltage curves (Gamma-curves).

The timing controller 340 generates a gate control signal and a data control signal and controls the gamma voltage switch 356 to switch the outputs of the high gray level gamma voltage portion 352 and the low gray level gamma voltage portion 354 during one horizontal period. ). The gamma voltage unit 350 receives the high gray level gamma voltage from the high gray level gamma voltage unit 352 during the 1/2 horizontal period period and the low gray level gamma voltage from the low gray level gamma voltage unit 354 during the remaining 1/2 horizontal period, The voltage is switched and supplied to the data driver 330.

The gate driver 320 applies a gate driving signal to the gate line GL1 for 1/2 horizontal period time in response to the gate control signal from the timing controller 340 and applies the gate driving signal to the gate line GL2 in sequence.

In response to the data control signal from the timing controller 340, the data driver 330 uses the high gray-scale gamma voltage during the 1/2 horizontal period to convert the data signal from the timing controller 340 into a high gray- And supplies the converted data signal to the data line DL1. The data signal from the timing controller 340 is converted into a low-gradation data signal by using the low-gradation gamma voltage during the remaining 1/2 horizontal period, and supplied to the data line DL1 do.

Referring to FIG. 5, the structure of a pixel of a liquid crystal display according to another embodiment of the present invention will be described in more detail. 5 is a plan view showing a structure of a pixel of the liquid crystal display device shown in FIG. As shown in FIG. The pixel of the liquid crystal display according to another embodiment of the present invention includes a first pixel electrode 460, a second pixel electrode 462, a first thin film transistor T1, a second thin film transistor T2, A first storage capacitor CST1, a second storage capacitor CST2, and a second storage capacitor CST2.

The first pixel electrode 460 is connected to the drain electrode 454 of the first transistor T1 through the contact hole 468 and the upper electrode 450 of the first storage capacitor CST1. The first pixel electrode 460 receives the high gray level data signal from the data line 420 through the first transistor T1 and expresses the high gray level data signal.

The second pixel electrode 462 is formed to be separated from the first pixel electrode 460 so as to surround the first pixel electrode 460. The second pixel electrode 462 is connected to the drain electrode 459 of the second transistor T2 through the contact hole 464 and is connected to the upper electrode 455 of the second storage capacitor CST2 through the contact hole 466. [ . The second pixel electrode 462 receives the low gray level data signal from the data line 420 through the second transistor T2 to represent the low gray level data signal.

The first thin film transistor T1 includes a gate electrode 412 connected to the first gate line 410, a source electrode 422 connected to the data line 520, a drain electrode connected to the drain line 452 And an active layer 430 overlapping the gate electrode 412 via an insulating layer. The first TFT T1 applies a high gray scale data signal supplied from the data line 420 during the 1/2 horizontal period to the drain electrode 454 in response to the gate driving signal applied to the first gate line 410 To the drain line 452.

The second thin film transistor T2 includes a gate electrode 414 connected to the second gate line 415, a source electrode 427 connected to the data line 420, a drain electrode connected to the drain line 457 459, and an active layer 432 overlapping the gate electrode 414 via an insulating layer. The second thin film transistor T2 responds to the gate driving signal applied to the second gate line 415 and supplies the high gray scale data signal supplied from the data line 420 to the drain electrode 459 To the drain line 457 through the drain line 457.

The first gate line 410 is connected to the gate electrode 412 of the first thin film transistor T1. The first gate line 410 applies a gate driving signal input from the gate driver during the 1/2 horizontal period to the gate electrode 412 of the first thin film transistor Tl.

The second gate line 415 is connected to the gate electrode 414 of the second thin film transistor T2. The second gate line 412 applies a gate driving signal input from the gate driver to the gate electrode 414 of the second thin film transistor T2 during the remaining 1/2 horizontal period.

The data line 520 is formed on one side of the pixel and is perpendicular to the first and second gate lines 410 and 412 so that the source electrode 422 of the first thin film transistor T1 and the second thin film transistor T2, respectively. The data line 420 applies a high gray level data signal input from the data driver during the 1/2 horizontal period period to the source electrode 422 of the first thin film transistor T1, To the source electrode 427 of the first thin film transistor T2.

The first storage capacitor CST1 includes a lower electrode 444 connected to the storage capacitor line 440 and an upper electrode 450 overlapping the lower electrode 444 via an insulating layer. The upper electrode 450 is integrated with the drain electrode 454 of the first thin film transistor Tl through the drain line 452. The lower electrode 444 and the upper electrode 450 of the first storage capacitor CST1 preferably have a larger area than the lower electrode 442 and the upper electrode 455 of the second storage capacitor CST2.

The upper electrode 450 connected to the drain line 452 is connected to the first pixel electrode 460 through the contact hole 468. [ The high gradation data signal inputted through the drain line 452 connected to the drain electrode 454 of the first thin film transistor T1 is applied to the first pixel electrode 460 and simultaneously stored in the first storage capacitor CST1 .

The second storage capacitor CST2 includes a lower electrode 442 connected to the storage capacitor line 440 and an upper electrode 455 overlapping the lower electrode 442 via an insulating layer. The upper electrode 455 is connected to the second pixel electrode 462 connected to the drain electrode 459 of the second thin film transistor T 2 through the contact hole 466. The low gray level data signal input through the drain line 457 connected to the drain electrode 459 of the second thin film transistor T2 is applied to the second pixel electrode 462 and accumulated in the second storage capacitor CST2 .

In another exemplary embodiment of the present invention, the contact hole for connecting the first pixel electrode 460 to the upper electrode 455 of the first storage capacitor CST1 is removed, and the first thin film transistor Since the drain electrode 454 of the first transistor T1 is directly connected to the upper electrode 450 of the first storage capacitor CST1, static electricity flows into the first thin film transistor T1 during the manufacturing process of the liquid crystal display device The path is blocked and the generated static electricity has a structure capable of being accumulated in the first storage capacitor CST1 before being introduced into the first thin film transistor T1. Accordingly, in the manufacturing process of the liquid crystal display device, a problem that a channel of a high gray scale transistor is short-circuited due to a channel short failure due to static electricity, particularly static electricity, can be solved.

As described above, the liquid crystal display according to the present invention has a structure in which the drain electrode of the transistor for switching the high gray level data signal is directly connected to the upper electrode of the storage capacitor, and the contact hole between the drain electrode and the high gray level pixel electrode is removed Therefore, the phenomenon that the channel of the thin film transistor for switching the high gray scale data signal is short-circuited by the static electricity flowing into the conventional contact hole is eliminated, and the yield is improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (25)

A first thin film transistor for applying a high gray scale data signal voltage input from a first data line to a first pixel electrode; A first terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to receive the high gray data signal voltage and a second terminal electrode connected to the storage capacitor line A first storage capacitor including a second terminal electrode, the first storage capacitor storing the high gradation data signal voltage; A second thin film transistor for applying a low gray level data signal voltage input from a second data line and lower in level than the high gray level data signal voltage to a second pixel electrode connected through a second contact hole; And A third terminal electrode connected to the second pixel electrode through the third contact hole to receive the low gray level data signal voltage, and a fourth terminal electrode insulated from the third terminal electrode and connected to the storage capacitor line, And a second storage capacitor for storing the low gray level data signal voltage, The first contact hole overlaps the first terminal electrode and the second terminal electrode, the third contact hole overlaps the third terminal electrode and the fourth terminal electrode, and the first contact hole and the second terminal electrode overlap each other, And the third contact hole overlaps the extension line of the storage capacitor line. The method according to claim 1, Wherein the high gray data signal voltage and the low gray data signal voltage are generated by different gray scale voltage curves. The thin film transistor of claim 2, And a source electrode connected to the first data line and a drain electrode connected directly to the first terminal electrode of the first storage capacitor. The thin film transistor of claim 3, And a source electrode connected to the second data line and a drain electrode connected to the second pixel electrode. 5. The semiconductor memory device according to claim 4, And the capacity is larger than the second storage capacity. The method of claim 5, wherein the first thin- Wherein the second thin film transistor applies the low gray level data signal voltage to the first pixel electrode during a certain period of a horizontal period during a certain period of the horizontal period, To the pixel electrode. A data driver for applying a high gradation data signal voltage to a first data line and applying a low gradation data signal voltage at a level lower than the high gradation data signal voltage to a second data line; A gate driver for applying a gate driving signal to the gate line; A first thin film transistor for applying the high gray level data signal voltage to the first pixel electrode in response to the gate driving signal; A first terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to receive the high gray data signal voltage and a second terminal electrode connected to the storage capacitor line, A first storage capacitor including a second terminal electrode connected thereto, the first storage capacitor storing the high gradation data signal voltage; A second thin film transistor for applying the low gray level data signal voltage to a second pixel electrode connected through a second contact hole in response to the gate driving signal; And A third terminal electrode connected to the second pixel electrode through the third contact hole to receive the low gray level data signal voltage, and a fourth terminal electrode insulated from the third terminal electrode and connected to the storage capacitor line, And a second storage capacitor for storing the low gray level data signal voltage, The first contact hole overlaps the first terminal electrode and the second terminal electrode, the third contact hole overlaps the third terminal electrode and the fourth terminal electrode, and the first contact hole and the second terminal electrode overlap each other, And the third contact hole overlaps the extension line of the storage capacitor line. 8. The method of claim 7, Wherein the high gray data signal voltage and the low gray data signal voltage are generated by different gray scale voltage curves. 9. The method of claim 8, And a gamma voltage unit for supplying a high gray level gamma voltage for generating the high gray level data signal voltage and a low gray level gamma voltage for generating the low gray level data signal voltage to the data driver. 10. The data driver of claim 9, Applying the high gray level data signal voltage to the first thin film transistor during a certain period of one horizontal period and applying the low gray level data signal voltage to the second thin film transistor during a remaining period of a certain period of the horizontal period, Wherein the gate driver applies the gate driving signal to the first thin film transistor and the second thin film transistor during the horizontal period. A plurality of first data lines for transmitting a high gray level data signal voltage, a plurality of second data lines for transmitting a low gray level data signal voltage of a level lower than the high gray level data signal voltage, and a plurality of gate lines A liquid crystal display device comprising a plurality of pixels defined by: The pixel includes: A first pixel electrode for displaying the high gray level data signal voltage; A first thin film transistor for applying the high gray level data signal voltage to the first pixel electrode; A first terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to receive the high gray data signal voltage and a second terminal electrode connected to the storage capacitor line A first storage capacitor including a second terminal electrode connected thereto, the first storage capacitor storing the high gradation data signal voltage; A second pixel electrode for displaying the low gray level data signal voltage; A second thin film transistor connected to the second pixel electrode through a second contact hole and applying the low gray level data signal voltage to the second pixel electrode; And A third terminal electrode connected to the second pixel electrode through the third contact hole to receive the low gray level data signal voltage, and a fourth terminal electrode insulated from the third terminal electrode and connected to the storage capacitor line, And a second storage capacitor for storing the low gray level data signal voltage, The first contact hole overlaps the first terminal electrode and the second terminal electrode, the third contact hole overlaps the third terminal electrode and the fourth terminal electrode, and the first contact hole and the second terminal electrode overlap each other, And the third contact hole overlaps the extension line of the storage capacitor line. 12. The method of claim 11, Wherein the high gray data signal voltage and the low gray data signal voltage are generated by different gray scale voltage curves. 13. The semiconductor memory according to claim 12, wherein the first terminal electrode and the second terminal electrode of the first storage capacitor each have an area larger than that of the third terminal electrode and the fourth terminal electrode of the second storage capacitor Liquid crystal display device. The liquid crystal display device according to claim 11, Wherein the first pixel electrode is formed separately from the first pixel electrode and surrounds the first pixel electrode. A gate line forming step of forming a storage capacitor line including a gate line including first and second gate electrodes and first and second terminal electrodes on a glass substrate; An active layer forming step of forming an active layer over the first and second gate electrodes with a gate insulating film interposed therebetween on a glass substrate on which the gate lines and the storage capacitor lines are formed; A first data line and a second data line for respectively transmitting a high gray-scale data signal voltage and a low gray-scale data signal voltage lower in level than the high gray-scale data signal voltage, a first data line and a second data line connected to the first data line, A second source electrode and a second drain electrode of the second transistor connected to the second data line, third and fourth terminal electrodes opposed to the first and second terminal electrodes, A source / drain forming step of forming a source / drain pattern including a first drain electrode and a drain line connecting the third terminal electrode; A first contact hole exposing the third terminal electrode, and a second contact hole exposing a drain line connected to the second drain electrode, the method comprising: forming an organic insulating layer on the glass substrate on which the source / drain pattern is formed, And a third contact hole exposing the fourth terminal electrode; And A first pixel electrode connected to the first contact hole and a second pixel electrode connected to the second contact hole, the first pixel electrode being connected to the first contact hole, And a pixel electrode forming step of forming a second pixel electrode connected to the third contact hole by transparent conductive patterning, The first contact hole overlaps the first terminal electrode and the third terminal electrode, the third contact hole overlaps the second terminal electrode and the fourth terminal electrode, and the first contact hole and the third terminal electrode overlap each other, And the third contact hole is overlapped with an extension line of the storage capacitor line. A first thin film transistor for applying a high gray level data signal voltage inputted from a data line to a first pixel electrode in response to a first gate driving signal; A first terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to receive the high gray data signal voltage and a second terminal electrode connected to the storage capacitor line A first storage capacitor including a second terminal electrode, the first storage capacitor storing the high gradation data signal voltage; A second thin film transistor which is supplied from the data line in response to a second gate driving signal and applies a low gray level data signal voltage lower in level than the high gray level data signal voltage to a second pixel electrode connected through a second contact hole; And A third terminal electrode connected to the second pixel electrode through a third contact hole and receiving the low gray level data signal voltage, and a fourth terminal electrode insulated from the third terminal electrode and connected to the storage capacitor line, And a second storage capacitor for storing the low gray level data signal voltage, The first contact hole overlaps the first terminal electrode and the second terminal electrode, the third contact hole overlaps the third terminal electrode and the fourth terminal electrode, and the first contact hole and the second terminal electrode overlap each other, And the third contact hole overlaps the extension line of the storage capacitor line. 17. The method of claim 16, Wherein the high gray data signal voltage and the low gray data signal voltage are generated by different gray scale voltage curves. 18. The method of claim 17, Wherein the first gate driving signal and the second gate driving signal are sequentially applied to the first thin film transistor and the second thin film transistor during one horizontal period time. delete delete delete delete delete delete delete

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