KR20070079614A - Liquid crystal display and method of manufacturing the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to form the first pixel electrode as a structure for encircling the second pixel electrode. Each sub pixel area of the LCD is divided into the first and second gradation areas. The first pixel electrode(40) is formed at the first gradation area of each sub pixel area. The second gradation area is surrounded with the first pixel electrode. The second pixel electrode(50) separated from the first pixel electrode is formed on the second gradation area. The first TFT(Thin Film Transistor)(T1) is connected with the first pixel electrode. The second TFT(Thin Film Transistor)(T2) is connected with the second pixel electrode. A gate line(2) and a data line(4) are connected with the first and second TFT and define each sub pixel area. A TFT is connected with the second pixel electrode. A coupling capacitor is formed at a drain electrode of the TFT and an overlap portion of the first pixel electrode. A gate line and a data line are connected with the TFT and define each sub pixel area.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view illustrating a structure of one sub-pixel in a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a sectional view of a sub pixel taken along the line II-II 'shown in FIG. 1; FIG.

3A and 3B are plan views for comparing and explaining parasitic capacitances of structures with and without a third connecting electrode of a first pixel electrode;

4A and 4B are plan and cross-sectional views illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

5A and 5B are plan and cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

6A and 6B are plan and cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

8A and 8B are plan and cross-sectional views illustrating a fifth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

9 is a plan view illustrating a structure of one sub pixel of a thin film transistor substrate according to another exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of a sub pixel taken along a line 'VIII' shown in FIG. 9; FIG.

 <Description of Symbols for Main Parts of Drawings>

2: gate line 4: data line

6, 16: gate electrode 8, 18: semiconductor layer

10, 20: source electrode 12, 22: drain electrode

15, 25: contact hole 27: capacitor hole

30: storage line 40, 50: pixel electrode

42: connection part 44, 46: slit

60: common line 70: insulated substrate

72 gate insulating film 74 organic insulating film

76: inorganic insulating film

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can prevent vertical crosstalk due to parasitic capacitance variation.

The liquid crystal display displays an image by using the electrical and optical characteristics of the liquid crystal. The liquid crystal display device includes a liquid crystal display panel for displaying an image through a pixel matrix using liquid crystal, a driving circuit for driving the liquid crystal display panel, and a backlight unit for supplying light to the liquid crystal display panel. The liquid crystal display is developing with a wide viewing angle technology in order to overcome a viewing angle limitation point in which an image is distorted depending on a position of a screen.

As a representative wide viewing angle technology of the liquid crystal display, a multi-domain VA (Multi-domain Vertical Alignment) mode is used. The multi-domain VA obtains a wide viewing angle by dividing each sub-pixel into multi-domains in which liquid crystal molecules are arranged in different directions to compensate for the change in transmittance. In particular, a patterned vertical alignment (PVA) mode in which a multi-domain is formed by a fringe field by slit of the common electrode and the pixel electrode is mainly used. However, the PVA mode has a problem in that the liquid crystal alignment is disturbed due to the Lateral Filed generated at the edges of the sub-pixels and thus the side visibility is poor.

In order to solve this problem, a method of dividing each sub-pixel having a multi-domain into two regions driven by different voltages and improving the visibility by gray level mixing of the two regions has been proposed. However, due to the division of each sub-pixel, the left and right parasitic capacitance variations due to the difference in length between the data lines on both sides and the adjacent pixel electrodes cause a problem of deterioration in image quality such as vertical crosstalk.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can prevent vertical crosstalk due to variations in parasitic capacitance.

To this end, the liquid crystal display according to the exemplary embodiment of the present invention may include a first pixel electrode formed in the first gray level region among the sub pixel regions divided into first and second gray level regions, and the first pixel electrode surrounded by the first pixel electrode. A second pixel electrode is formed separately from the first pixel electrode in the two gradation regions. And a first thin film transistor connected to the first pixel electrode, a second thin film transistor connected to the second pixel electrode, and a gate connected to the first and second thin film transistors to define each of the sub pixel regions. It further comprises a line and a data line. Alternatively, a thin film transistor connected to the second pixel electrode, a coupling capacitor formed at an overlapping portion of the drain electrode and the first pixel electrode of the thin film transistor, and the thin film transistor connected to the thin film transistor to define each of the sub pixel regions. It may further include a gate line and a data line.

The second pixel electrode includes a wing part which is inclined symmetrically with respect to a short axis direction of the sub pixel area. The first pixel electrode includes an upper electrode formed over the second pixel electrode, a lower electrode formed under the second pixel electrode, a center electrode formed between a wing of the second pixel electrode, and the upper electrode. And a first connection line connecting the center electrode, a second connection line connecting the lower electrode and the center electrode, and a third connection line connecting the upper electrode and the lower electrode.

The present invention further includes a first slit separating the first pixel electrode and the second pixel electrode from each other, wherein the first slit has a predetermined width along a side of the second pixel electrode and the second pixel electrode. It is formed in a structure surrounding the. In addition, a second slit formed in parallel with the first slit is further provided on each of the upper electrode and the lower electrode of the first pixel electrode.

First and second connection electrodes of the first pixel electrode are formed between the data lines adjacent to one side of the second pixel electrode, and the third connection electrode is formed between the data lines adjacent to the other side of the second pixel electrode. do. The third connection electrode reduces a difference between the length of one side adjacent to one data line and the length of the other side adjacent to the other data line in the first pixel electrode. An interval between one side of the second pixel electrode and an adjacent one data line and an interval between the other side of the second pixel electrode and another adjacent data line are the same.

The present invention further includes a storage line formed along a short direction of the sub pixel area and overlapping each of the first and second pixel electrodes. In addition, a first storage capacitor extending from the first thin film transistor and connected to the first pixel electrode, the first storage capacitor formed to overlap the storage line with an insulating layer interposed therebetween, and the first drain capacitor extending from the second thin film transistor to extend the first drain electrode. A second drain electrode connected to the second pixel electrode further includes a second storage capacitor formed to overlap the storage line with the insulating layer interposed therebetween. In contrast, the present invention further includes a storage capacitor which extends into the thin film transistor and is connected to the second pixel electrode and overlaps the storage line with a first insulating layer interposed therebetween. The drain electrode is extended to overlap the first pixel electrode with a second insulating film interposed therebetween.

In addition, the present invention includes an organic insulating layer covering the first and second thin film transistors and formed under the first and second pixel electrodes; A common line is formed on the organic insulating layer to overlap the gate line and the data line.

According to an exemplary embodiment of the present invention, a method of manufacturing a liquid crystal display device includes forming a first pixel electrode formed in the first gradation region among sub-pixel regions divided into first and second gradation regions, and surrounding the first pixel electrode. And forming a second pixel electrode separated from the first pixel electrode in the second gray area.

Other features and advantages of the present invention in addition to the above technical problem will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 10.

1 is a plan view illustrating a structure of one sub pixel in a thin film transistor substrate of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of one sub pixel along a line II-II ′ of FIG. 1. It is sectional drawing which shows the structure.

1 and 2 each of the sub-pixels includes first and second pixel electrodes 40 and 50 and the first and second pixel electrodes 40 and 50 independently formed in the low gray region and the high gray region, respectively. First and second thin film transistors T1 and T2 independently connected to the gate lines, and gate lines 2 and data lines 4 connected to the first and second thin film transistors T1 and T2.

In the thin film transistor substrate illustrated in FIGS. 1 and 2, one sub pixel is divided into a high gray level region and a low gray level region to which different data signals are applied to improve visibility. To this end, first and second pixel electrodes 40 and 50 are independently formed in each sub-pixel to define a low gray level region and a high gray level region, and each of the first and second pixel electrodes 40 and 50 may include a first pixel. And driven by the second thin film transistors T1 and T2, respectively, to receive different data signals.

The gate line 2 and the data line 4 are formed on the insulating substrate 70 so as to intersect with the gate insulating film 72 interposed therebetween. Each sub pixel area is defined by the intersection structure of the gate line 2 and the data line 4. The storage line 30 is formed on the insulating substrate 70 in parallel with the gate line 2 to cross the data line 4 and the gate insulating layer 72 while passing through the central portion of each sub-pixel in a short axis direction. do.

Each of the first and second thin film transistors T1 and T2 may include gate electrodes 6 and 16 connected to the gate line 2, source electrodes 10 and 20 connected to the data line 4, and first and second electrodes. Drain electrodes 12 and 22 connected to the two pixel electrodes 40 and 50, source electrodes 10 and 20, and semiconductor layers 8 and 18 connected to the drain electrodes 12 and 22 are provided. The semiconductor layers 8 and 18 include active layers 8A and 18A forming channels between the source electrodes 10 and 20 and drain electrodes 12 and 22, and active layers 8A and 18A and source electrodes 10 and 20. And ohmic contact layers 8B and 18B for ohmic contacts of the drain electrodes 12 and 22, respectively.

Each of the first and second pixel electrodes 40 and 50 is formed on an organic insulating layer 74 covering the thin film transistors T1 and T2 and passes through the organic insulating layer 74. 25) respectively connected to the drain electrodes 12 and 22 of the first and second thin film transistors T1 and T2. An inorganic insulating film may be further formed on and / or under the organic insulating film 74. The common line 60 overlapping the data line 4 and the gate line 2 is further formed on the organic insulating layer 74. The common line 60 has a wider line width than the data line 4 and a narrower line width than the gate line 2. The common line 60 is supplied with a common voltage that is the same as or similar to that of the upper common electrode (not shown). As a result, no electric field is formed between the common line 60 and the common electrode of the upper plate, or a weak electric field is formed, so that light leakage is blocked because the liquid crystal molecules vertically aligned therebetween are not driven.

The first pixel electrode 40 is formed in the low gradation region of each sub pixel region, and the second pixel electrode 50 is formed in the high gradation region. Since the high gradation region and the low gradation region of each sub pixel are preferably divided into 1: 2, which is an optimal ratio for improving visibility, the first pixel electrode 40 is divided into a low gradation region that is divided into two by dividing each sub pixel region into three divisions. The second pixel electrode 50 is formed in the high gradation region which is a single division region.

Each of the drain electrodes 12 and 22 of the first and second thin film transistors T1 and T2 extends to the center portion of the sub pixel in which the storage line 30 is formed and overlaps the storage line 30. The first and second pixel electrodes 40 and 50 are respectively connected through the contact holes 15 and 25. Each of the drain electrodes 12 and 22 of the first and second thin film transistors T1 and T2 is overlapped with the storage line 30 and the gate insulating layer 72 interposed therebetween, so that the first and second storage capacitors Cst1, Cst2) are formed respectively.

The second pixel electrode 50 of the high gradation region has a structure in which each of the sub-pixel regions has upper and lower wings 50A and 50B that are symmetrically inclined with respect to the short axis direction, that is, the storage line 30. It is formed into a "V" shaped structure rotated 90 degrees in the direction. The first pixel electrode 40 of the low gradation region is formed between the upper and lower portions divided by the second pixel electrode 50 in each sub pixel region, and between the wing portions 50A and 50B of the second pixel electrode 50. It is formed to be positioned in the center and has a structure symmetrical with respect to the storage line 30. In other words, the first pixel electrode 40 in the low gradation region is the upper electrode 40A positioned above the second pixel electrode 50 and the lower electrode 40B positioned below the second pixel electrode 50. ) And a center electrode 40C positioned between the wing portions 50A and 50B of the second pixel electrode 50. The first pixel electrode 40 may include a first connection electrode 40D connecting the upper electrode 40A and the center electrode 40C, a second connection electrode connecting the lower electrode 40B, and the center electrode 40C ( 40E). In addition, the first pixel electrode 40 includes a third connection electrode 40F connecting the upper electrode 40A and the lower electrode 40B.

A first slit 46 having a predetermined width is formed between the first pixel electrode 40 and the second pixel electrode 50, and the upper electrode 40A and the lower part of the first pixel electrode 40 in the low gradation region. In each of the electrodes 40B, a second slit 44 parallel to a part of the first slit 46 is formed to have a constant width. The first slit 46 between the first and second pixel electrodes 40 and 50 surrounds the side of the second pixel electrode 50, that is, has a constant width along the side of the second pixel electrode 50. As a result, the inclined angle of the second pixel electrode 50 is symmetric with respect to the storage line 30. Since the second slits 44 formed on the upper electrode 40A and the lower electrode 40B of the first pixel electrode 40 are also formed in parallel with a part of the first slit 46, the storage line 30 is referred to. Has a symmetrical tilt angle. The first slit 46 separates the first pixel electrode 40 and the second pixel electrode 50. In addition, the first and second slits 46 and 44 allow the first and second pixel electrodes 40 and 50 to form a fringe electric field with a common electrode formed on an upper substrate (not shown). 46 and 44, the liquid crystal molecules are symmetrically arranged to form a multi-domain. In addition, in order to form more domains, the common electrode slit may be formed on the common electrode of the upper plate in a structure parallel to the first and second slits 46 and 44.

A first connection electrode 40D connecting the upper electrode 40A and the center electrode 40C of the first pixel electrode 40, and a second connection electrode connecting the lower electrode 40B and the center electrode 40C ( 40E is formed in a space between the left data line 4 and the second pixel electrode 50. The third connection electrode 40F is formed in the space between the second pixel electrode 50 and the right data line 4. In other words, the first and second connection electrodes 40D may be connected to the first pixel electrode via the space between the left data line 4 and the one side side parallel to the left data line 4 in the second pixel electrode 50. The center electrode 40C of the 40 is connected to each of the upper electrode 40A and the lower electrode 40B. The third connection electrode 40F is an upper electrode of the first pixel electrode 40 via a space between the right side data line 4 and the second pixel electrode 50 that is parallel to the right side data line 4. 40A) and the lower electrode 40B are connected. The line widths of the first to third connection electrodes 40D, 40E, and 40F are the same. The third connection electrode 40F serves to reduce the deviation of the left and right parasitic capacitances Cds_L and Cds_R formed between the first and second pixel electrodes 40 and 50 and the left and right adjacent data lines 4. This prevents vertical crosstalk.

Specifically, as shown in FIG. 3A, when the third connection electrode 40F of the first pixel electrode 40 does not exist, the first pixel electrode 40 is disposed on the first and second connection electrodes 40D and 40E. As a result, the length of the left side adjacent to the left data line 4 becomes longer than the length of the right side adjacent to the right data line 4. Due to the difference in the length of the left and right sides of the first pixel electrode 40, the left parasitic capacitance Cds_L between the first pixel electrode 40 and the left data line 4, the first pixel electrode 40, and the right data line ( 4) deviation of the right parasitic capacitance Cds_R occurs. In addition, the second pixel electrode 50 is left than the gap between the right data line 4 and the second pixel electrode 50 by the first and second connection electrodes 40D and 40E of the first pixel electrode 40. The distance between the data line 4 and the second pixel electrode 50 increases. As a result, a deviation of the left parasitic capacitance Cds_L between the second pixel electrode 50 and the left data line 4 and the right parasitic capacitance Cds_R between the second pixel electrode 50 and the right data line 4 may occur. Is generated. As a result, when the data signal of opposite polarity is applied to the left and right data lines 4 for the polarity inversion, the data charged in the first and second pixel electrodes 40 and 50 with the deviation of the left and right parasitic capacitances Cds_L and Cds_R. Vertical crosstalk is caused by the failure of the coupling values of the parasitic capacitances Cds_L and Cds_R to distort the signal. In particular, in the case of column inversion driving in which the polarity is inverted in units of the data lines 4, vertical crosstalk becomes more severe as the deviation of the left and right parasitic capacitances Cds_L and Cds_R increases. This is because the amount of change ΔVp of the voltage charged in each sub-pixel causing vertical crosstalk is proportional to the deviation Cds_L-Cds_R of the left and right parasitic capacitances.

For example, the voltage change amount ΔVp of one sub-pixel by the two data lines 4 is determined by the voltage change amount ΔVp_L and the right data line 4 by the left data line 4 as shown in Equation 1 below. It is represented by the sum of the voltage change amount (DELTA) Vp_R.

ΔVp = ΔVp_L + ΔVp_R

ΔVp_L = Cds_L × ΔVdata_L / Ctotal

ΔVp_R = Cds_R × ΔVdata_R / Ctotal

Where ΔVdata_L is the amount of change in the data signal supplied to the left data line 4, ΔVdata_R is the amount of change in the data signal supplied to the right data line 4, and Ctotal is the total capacitance of one sub-pixel (Ctotal = Clc + Cst + Cds_L + Cds_R). Assuming that opposite data signals are supplied to both data lines 4, the voltage change amount ΔVp of one sub pixel causing vertical crosstalk is proportional to the deviation (Cds_L-Cds_R) of the left and right parasitic capacitances as shown in Equation 2 below. Will have

ΔVp = {Cds_L * ΔVdata_L / Ctotal} + {Cds_R * ΔVdata_R / Ctotal}

     = (Cds_L-Cds_R) * ΔVdata_R / Ctotal

Δ ΔVdata_L = -ΔVdata_R

As a result, when opposite data signals are supplied to both data lines 4 of the first and second pixel electrodes 40 and 50, the vertical crosstalk increases in proportion to the deviation of the left and right parasitic capacitances Cds_L-Cds_R. .

In order to prevent such vertical crosstalk, the liquid crystal display according to the present invention, as shown in FIG. 3B, is adjacent to the right data line 4 and the upper electrode 40A and the lower electrode of the first pixel electrode 40. The third connection electrode 40F connecting the 40B may be provided to minimize the deviation of the left and right parasitic capacitances Cds_L and Cds_R. Specifically, the first pixel electrode 40 is substantially equal to the length of the left side adjacent to the left data line 4 and the length of the right side adjacent to the right data line 4 by the third connection electrode 40F. In addition, the second pixel having the first and second connection electrodes 40D and 40E interposed between the third connection electrode 40F, that is, the first pixel electrode 40 surrounding the second pixel electrode 50. The spacing between the electrode 50 and the left data line 4 and the spacing between the second pixel electrode 50 and the right data line 4 with the third connection electrode 40F therebetween become equal. Accordingly, variations in the left and right parasitic capacitances Cds_L and Cds_R between the first and second pixel electrodes 40 and 50 and the data lines 4 adjacent to both sides can be minimized, thereby preventing vertical crosstalk.

As described above, each of the sub-pixels of the liquid crystal display according to the present invention has a structure in which the first pixel electrode 50 in the low gradation region surrounds the second pixel electrode 50 in the high gradation region and thus, the first and second pixels. Vertical crosstalk can be prevented by minimizing the variation in parasitic capacitance between the electrodes 40, 50 and the two data lines 4.

A method of manufacturing a thin film transistor substrate of a liquid crystal display according to the present invention will be described in detail with reference to FIGS. 4A to 8B.

4A and 4B, the gate electrodes 2 and 16 connected to the gate line 2, the gate line 2, and the gate line 2 are formed on the lower insulating substrate 70 in the first mask process. A gate metal pattern including side by side storage lines 30 is formed. Specifically, the gate metal layer is formed on the lower insulating substrate 70 through a deposition method such as a sputtering method. As the gate metal layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and the like and alloys thereof are laminated and used in a single layer or a multilayer structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate metal pattern including the gate line 2, the gate electrodes 6 and 16, and the storage line 30.

5A and 5B, a gate insulating layer 72 is formed on the lower insulating substrate 70 on which the gate metal pattern is formed, and the active layers 8A and 18A and the ohmic contact layer 8B are formed thereon by a second mask process. , The semiconductor layers 8 and 18 including 18B are formed to overlap with the gate line 2 and a part of the gate electrodes 6 and 16. In detail, the gate insulating layer 72, the amorphous silicon layer, and the n + amorphous silicon layer are sequentially formed on the lower insulating substrate 70 on which the gate metal pattern is formed by a deposition method such as PECVD. Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are patterned by a photolithography process and an etching process using a second mask to thereby include the semiconductor layers 8 and 18 including the active layers 8A and 18A and the ohmic contact layers 8B and 18B. Is formed. As the gate insulating layer 72, an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like is used.

6A and 6B, the data line 4, the source electrodes 10 and 20, and the drain electrodes 12 and 22 are formed on the gate insulating layer 72 on which the semiconductor layers 8 and 18 are formed in the third mask process. A source / drain metal pattern comprising a is formed. Specifically, a source / drain metal layer is formed on the gate insulating film 72 on which the semiconductor layers 8 and 18 are formed by a sputtering method. Subsequently, the source / drain metal layer is patterned by a photolithography process and an etching process using a third mask, thereby forming a source / drain metal pattern including the data line 4, the source electrodes 10 and 20, and the drain electrodes 12 and 22. Is formed. The ohmic contacts connected to the source electrodes 10 and 20 and the drain electrodes 12 and 22 are removed by removing the ohmic contact layers 8B and 18B exposed between the source electrodes 10 and 20 and the drain electrodes 12 and 22. The layers 8B and 18B are separated. As a result, first and second thin film transistors T1 and T2 connected to the gate line 2 and the data line 4 are formed. Here, the semiconductor layers 8 and 18 and the source / drain metal patterns may be formed in one mask process using a diffraction exposure mask or a half-tone mask.

7A and 7B, an organic insulating layer 74 is formed on a gate insulating layer 72 on which a source / drain metal pattern is formed, and first and second contact holes penetrating the organic insulating layer 74 by a fourth mask process. (15, 25) are formed. In detail, the organic insulating layer 74 is formed by coating an organic insulating material such as an acryl-based organic compound, BCB, or PFCB by spin coating, spinless coating, or the like. Subsequently, the photolithography and etching processes using the fourth mask may pass through the organic insulating layer 74 to expose the drain electrodes 12 and 22 of the first and second thin film transistors T1 and T2, respectively. 2 contact holes 15 and 25 are formed. Herein, an inorganic insulating film may be further formed on and / or under the organic insulating film 74, and the first and second contact holes 15 and 25 may be formed to penetrate the inorganic insulating film.

8A and 8B, a transparent conductive pattern including first and second pixel electrodes 40 and 50 and a common line 60 is formed on the organic insulating layer 74 in a fifth mask process. The first and second pixel electrodes 40 and 50 and the common line 60 are transparent on the organic insulating layer 74 such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and ITZO. The material is formed by applying a deposition method, such as sputtering, and then patterning the photolithography process and etching process using a fifth mask. The first and second pixel electrodes 40 and 50 are respectively connected to the drain electrodes 12 and 22 of the first and second thin film transistors T1 and T2 through the first and second contact holes 15 and 25, respectively. Connected.

FIG. 9 is a plan view illustrating the structure of one subpixel in a thin film transistor substrate of a liquid crystal display according to another exemplary embodiment. FIG. 10 is a cross-sectional view of one subpixel along the line 'VIII' shown in FIG. 9. It is sectional drawing which shows the structure.

9 and 10 have one thin film transistor T connected to the second pixel electrode 40 as compared with the sub pixel shown in FIGS. 1 and 2, and the first pixel electrode ( 40 has the same components except forming the drain electrode 22 of the thin film transistor T and the coupling capacitor Ccp, and thus descriptions of the overlapping components will be omitted. In other words, the first and second pixel electrodes 40 and 50 illustrated in FIGS. 1 and 2 are supplied with different data signals through the first and second thin film transistors T1 and T2, respectively. The first and second pixel electrodes 40 and 50 shown in FIG. 10 are supplied with different data signals through the coupling capacitor Ccp.

The second pixel electrode 50 defining the high gradation region is connected to the drain electrode 22 of the thin film transistor T through a contact hole 25 penetrating through the organic insulating film 74 and the inorganic insulating film 76. The data signal from the line 4 is supplied via the thin film transistor T. The first pixel electrode 40 defining the low gradation region forms a drain electrode 22 and a coupling capacitor Ccp and couples the data signal supplied to the second pixel electrode 50 through the thin film transistor T. Since the data is transmitted through the ring capacitor Ccp, the data signal lower than the second pixel electrode 50 is supplied. Accordingly, even though one thin film transistor T is used, a different data signal may be supplied to the first pixel electrode 40 in the low gradation region and the second pixel electrode 50 in the high gradation region by the coupling capacitor Ccp. It becomes possible.

The coupling capacitor Ccp overlaps the drain electrode 22 connected to the second pixel electrode 50 along the storage line 30 so that the first pixel electrode 40 and the inorganic insulating layer 76 are interposed therebetween. It is formed by. An inorganic insulating film 76 is added between the thin film transistor T and the organic insulating film 74 to prevent a chemical reaction between the organic insulating film 74 and the active layer 18A of the thin film transistor T. A capacitor hole 27 penetrating the organic insulating film 74 is formed to reduce the gap between the first pixel electrode 40 and the drain electrode 22 formed after the organic insulating film 74. Accordingly, the first pixel electrode 40 overlaps the drain electrode 22 with the relatively thin inorganic insulating film 76 therebetween via the capacitor hole 27 to supply the data signal supplied to the drain electrode 22. A coupling capacitor Ccp is formed which can drop and sufficiently transfer to the first pixel electrode 40.

As described above, the first pixel electrode 40 of the low gradation region is formed to surround the second pixel electrode 50 of the high gradation region so that the first and second pixel electrodes 40 and 50 and both data lines are formed. The variation in parasitic capacitance between (4) is minimized. In other words, the first pixel electrode 40 is connected to the first and second connection electrodes 40D and 40E adjacent to the left data line 4 and the third connection electrode 40F adjacent to the right data line 4. As a result, the length of the left side adjacent to the left data line 4 and the length of the right side adjacent to the right data line 4 become almost the same. In addition, the distance between the second pixel electrode 50 and the left data line 4 and the second pixel electrode 50 are defined by the first to third connection electrodes 40D, 40E, and 40F of the first pixel electrode 40. ) And the right data line 4 are equally spaced. As a result, variations in left and right parasitic capacitances between the first and second pixel electrodes 40 and 50 and the data lines 4 adjacent to both sides can be minimized, thereby preventing vertical crosstalk.

In addition, since the manufacturing method of the thin film transistor substrate illustrated in FIGS. 9 and 10 is similar to the manufacturing method of FIGS.

A gate metal including a gate line 2, a gate electrode 16 connected to the gate line 2, and a storage line 30 parallel to the gate line 2 on the lower insulating substrate 70 by a first mask process. A pattern is formed. The semiconductor layer including the active layer 18A and the ohmic contact layer 18B formed on the lower insulating substrate 70 on which the gate metal pattern is formed by the second mask process, and formed on the gate insulating layer 72 ( 18 is formed so as to overlap a part of the gate line 2 and the gate electrode 16. A source / drain metal pattern including the data line 4, the source electrode 20, and the drain electrode 22 is formed on the gate insulating layer 72 on which the semiconductor layer 18 is formed by the third mask process. Meanwhile, the semiconductor layer 18 and the source / drain metal pattern may be formed in one mask process using a diffraction exposure mask or a half-tone mask. An inorganic insulating layer 76 having a contact hole 25 exposing the drain electrode 22 is formed on the gate insulating layer 72 on which the source / drain metal pattern is formed by the fourth mask process. In the fifth mask process, the contact hole 25 is extended on the inorganic insulating layer 76 and the organic insulating layer 74 having the capacitor hole 27 is formed. In the seventh mask process, a transparent conductive pattern including the first and second pixel electrodes 40 and 50 and the common line 60 is formed on the organic insulating layer 74.

As described above, the liquid crystal display according to the present invention and the manufacturing method thereof according to the present invention have the first and the first pixel electrodes of the low gradation region in each sub-pixel so as to have a structure surrounding the second pixel electrode of the high gradation region. Vertical crosstalk can be prevented by minimizing the variation in parasitic capacitance between the two pixel electrode and both data lines.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (27)

A first pixel electrode formed in the first gradation region of each sub pixel region divided into first and second gradation regions; And a second pixel electrode formed separately from the first pixel electrode in the second gray area surrounded by the first pixel electrode. The method of claim 1, A first thin film transistor connected to the first pixel electrode; A second thin film transistor connected to the second pixel electrode; And a gate line and a data line connected to the first and second thin film transistors to define each of the sub-pixel regions. The method of claim 1, A thin film transistor connected to the second pixel electrode; A coupling capacitor formed at an overlapping portion of the drain electrode of the thin film transistor and the first pixel electrode; And a gate line and a data line connected to the thin film transistor to define each of the sub-pixel regions. The method according to any one of claims 2 and 3, The second pixel electrode And a wing portion inclined symmetrically with respect to the short axis direction of the sub pixel area. The method of claim 4, wherein The first pixel electrode An upper electrode formed on the second pixel electrode; A lower electrode formed under the second pixel electrode; A center electrode formed between the wing portions of the second pixel electrode; A first connection line connecting the upper electrode and the center electrode; A second connection line connecting the lower electrode and the center electrode; And a third connection line connecting the upper electrode and the lower electrode. The method of claim 5, And a first slit separating the first pixel electrode and the second pixel electrode from each other. The method of claim 6, And the first slit has a predetermined width along a side of the second pixel electrode and surrounds the second pixel electrode. The method of claim 6, And a second slit formed parallel to the first slit on each of the upper electrode and the lower electrode of the first pixel electrode. The method of claim 5, First and second connection electrodes of the first pixel electrode are formed between data lines adjacent to the second pixel electrode on one side, and the third connection electrode is formed between the data lines adjacent to the second pixel electrode on the other side. A liquid crystal display device, characterized in that. The method of claim 9, And the third connection electrode reduces a difference between a length of one side adjacent to one data line and a length of the other side adjacent to the other data line in the first pixel electrode. The method of claim 9, And a distance between one side of the second pixel electrode and an adjacent one data line and an interval between the other side of the second pixel electrode and another adjacent data line. The method of claim 5, And a storage line formed along a short direction of the sub pixel area and overlapping each of the first and second pixel electrodes. The method of claim 12, A first storage capacitor extending from the first thin film transistor and connected to the first pixel electrode and overlapping the storage line with an insulating layer interposed therebetween; And a second storage capacitor extending from the second thin film transistor and connected to the second pixel electrode, the second storage capacitor being formed to overlap the storage line with the insulating layer interposed therebetween. . The method of claim 12, A storage capacitor which is extended to the thin film transistor and is connected to the second pixel electrode and overlaps the storage line with a first insulating film interposed therebetween; The coupling capacitor is formed such that the drain electrode extends and overlaps the first pixel electrode with a second insulating layer interposed therebetween. The method of claim 12, An organic insulating layer covering the first and second thin film transistors and formed under the first and second pixel electrodes; And a common line formed on the organic insulating layer to overlap the gate line and the data line. Forming a first pixel electrode formed in the first gradation region of each sub pixel region divided into first and second gradation regions; And forming a second pixel electrode separated from the first pixel electrode in the second gray area surrounded by the first pixel electrode. The method of claim 16 A first thin film transistor connected to the first pixel electrode, a second thin film transistor connected to the second pixel electrode, a gate line connected to the first and second thin film transistors to define each of the sub pixel regions; A method of manufacturing a liquid crystal display device further comprising the step of forming a data line. The method of claim 16 A thin film transistor connected to the second pixel electrode, a coupling capacitor of an overlapping portion of the drain electrode of the thin film transistor and the first pixel electrode, a gate line and data connected to the thin film transistor to define each sub pixel region The method of manufacturing a liquid crystal display device, further comprising the step of forming a line. The method according to any one of claims 17 and 18, And the second pixel electrode is formed to have a wing portion symmetrically inclined with respect to a short axis direction of the sub pixel area. The method of claim 19, The first pixel electrode An upper electrode formed over the second pixel electrode, a lower electrode formed under the second pixel electrode, a center electrode formed between the wing of the second pixel electrode, and the upper electrode and the center electrode And a first connection line, a second connection line connecting the lower electrode and the center electrode, and a third connection line connecting the upper electrode and the lower electrode. . The method of claim 20, The first pixel electrode is separated from the second pixel electrode by a first slit that has a predetermined width along the side of the second pixel electrode and surrounds the second pixel electrode. . The method of claim 21, And a second slit parallel to the first slit is further formed on each of the upper electrode and the lower electrode of the first pixel electrode. The method of claim 20, First and second connection electrodes of the first pixel electrode are formed between data lines adjacent to the second pixel electrode on one side, and the third connection electrode is formed between the data lines adjacent to the second pixel electrode on the other side. The manufacturing method of the liquid crystal display device characterized by the above-mentioned. The method of claim 20, And forming a storage line overlapping each of the first and second pixel electrodes along a short axis direction of the sub pixel area. The method of claim 24, Forming a first storage capacitor by extending from the first thin film transistor so that a first drain electrode connected to the first pixel electrode overlaps the storage line with an insulating layer interposed therebetween; And forming a second storage capacitor by allowing the second drain electrode extending from the second thin film transistor to be connected to the second pixel electrode to overlap the storage line with the insulating layer interposed therebetween. The manufacturing method of the liquid crystal display device. The method of claim 24, Forming a storage capacitor by extending the thin film transistor so that the drain electrode connected to the second pixel electrode overlaps the storage line with a first insulating layer interposed therebetween; The coupling capacitor may be formed by overlapping the first pixel electrode with the drain electrode extending therebetween with a second insulating layer interposed therebetween. The method of claim 24, And forming a common line overlying the gate line and the data line with an insulating layer therebetween.

Images