KR101133193B1 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
KR101133193B1
KR101133193B1 KR1020050061355A KR20050061355A KR101133193B1 KR 101133193 B1 KR101133193 B1 KR 101133193B1 KR 1020050061355 A KR1020050061355 A KR 1020050061355A KR 20050061355 A KR20050061355 A KR 20050061355A KR 101133193 B1 KR101133193 B1 KR 101133193B1
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South Korea
Prior art keywords
gate
even
odd
pixel
gate line
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KR1020050061355A
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Korean (ko)
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KR20070006222A (en
Inventor
이계헌
이종환
이홍우
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삼성전자주식회사
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Priority to KR1020050061355A priority Critical patent/KR101133193B1/en
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F2001/133397Constructional arrangements; Manufacturing methods for suppressing after-image or image-sticking
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F2001/13606Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0233Improving the luminance or brightness uniformity across the screen

Abstract

A liquid crystal display device capable of preventing vertical streaks is provided. The liquid crystal display device includes a plurality of pixel electrodes connected to switching elements arranged in a matrix form, a plurality of gate lines connected to the switching elements, in which odd-numbered gate lines and even-numbered gate lines are extended in a row direction, and switching elements. And a plurality of data lines connected to each other and extending in a column direction, each of the first and second switching elements connected to both sides of the same data line among the switching elements, respectively, connected to an odd-numbered gate line and an even-numbered gate line. The first gate line and the even gate line are preferably disposed at one side of each pixel electrode.

Description

[0001] Liquid crystal display [0002]

FIG. 1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two pixels of the liquid crystal display shown in FIG. 3 is an equivalent circuit diagram of a thin film transistor array panel included in the liquid crystal display of FIG. 1.

4A is a layout view of a thin film transistor array panel used in the liquid crystal display according to the first embodiment of the present invention.

4B is a layout view of a color filter display panel used in the liquid crystal display according to the first embodiment of the present invention.

4C is a layout view of a liquid crystal display including the thin film transistor array panel of FIG. 4A and the color filter display panel of FIG. 4B.

5A is a cross-sectional view taken along line Va-Va ′ of the thin film transistor array panel of FIG. 4A.

5B is a cross-sectional view taken along line Vb-Vb ′ of the thin film transistor array panel of FIG. 4A.

6 is a layout view of a liquid crystal display according to a second exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

1: thin film transistor array panel 1a: pixel electrode

2: color filter display panel 2a: common electrode

2b: color filter 3: liquid crystal layer

4: gate driver 5: data driver

6: Timing controller 8: Gray voltage generator

22: gate line 22a: odd-numbered gate line

22b: Even-numbered gate line 24: End of gate line

26: gate electrode 28: holding capacitor wiring

30: gate insulating film 40: semiconductor layer

55, 56: ohmic contact layer pattern 62: data line

65, 265: source electrode 66, 266: drain electrode

70: protective film 74, 76, 78: contact hole

82: pixel electrode 82a: left pixel electrode

82b: right pixel electrode 83: incision pattern

86: end of the auxiliary gate line 88: end of the auxiliary data line

140: common electrode 142: incision pattern

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing vertical streaks.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

The thin film transistor array panel constituting the liquid crystal display includes pixels in which a gate line transmitting a scan signal and a data line transmitting an image signal cross each other to define pixels, and each pixel includes a thin film transistor and a thin film transistor connected to the gate line and the data line. Connected pixel electrodes are formed.

In this case, the thin film transistor includes a gate electrode and a semiconductor layer forming a channel, a source electrode and a drain electrode, and a gate insulating film, which are part of the data line, and are transferred through the data line according to a scan signal transmitted through the gate line. It is a switching element that transfers or blocks the image signal to the pixel electrode.

On the other hand, while the liquid crystal display device realizes high resolution and large area, the components mounted thereon are pursuing light and small size. For high resolution, data lines and gate lines inevitably increase. However, in particular, as the data line increases, the number of data drive ICs applying an image signal to the increased data line increases, thereby causing a problem in that the size of the liquid crystal display increases.

In order to reduce the size of the liquid crystal display while maintaining a high resolution, a liquid crystal display device providing a data signal from one data line to two adjacent pixels along the gate line has been developed.

In the conventional liquid crystal display, a pair of gate lines for providing a gate signal to each of these two pixels is disposed above and below the pixel. When the upper gate line is first turned on and the pixel voltage is charged, the pixel voltage is coupled to the lower gate line when the lower gate line is turned on, thereby causing the pixel voltage to drop. There arises a problem that the vertical line unevenness is recognized in the liquid crystal display due to the luminance deviation between the pixels.

An object of the present invention is to provide a liquid crystal display device capable of preventing vertical streaks.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of pixel electrodes connected to switching elements arranged in a matrix form, an odd-numbered gate line, and even-numbered gates connected to the switching elements. A plurality of gate lines in pairs extending in a row direction, and a plurality of data lines connected to the switching element and extending in a column direction, the first and second connected to both sides of the same data line among the switching elements, respectively. The switching element may be connected to the odd-numbered gate lines and the even-numbered gate lines, respectively, and the pair of odd-numbered gate lines and the even-numbered gate lines may be disposed on one side of each pixel electrode.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two pixels of the liquid crystal display shown in FIG. 3 is an equivalent circuit diagram of a thin film transistor array panel included in the liquid crystal display of FIG. 1.

1 to 3, the liquid crystal display includes a thin film transistor array panel 1, a gate driver 4 connected thereto, a data driver 5, and a gray voltage generator 8 connected to the data driver 5. ) And a timing controller 6 for controlling them.

The thin film transistor array panel 1 is connected to a plurality of display signal lines G1 (odd), G1 (even), ..., Gn (odd), Gn (even), D1, ..., Dm as an equivalent circuit. It includes a plurality of pixels Px arranged in an approximately matrix form.

The display signal lines G1 (odd), G1 (even), ..., Gn (odd), Gn (even), D1, ..., Dm are the plurality of gate lines G1 (odd) and G1 (even ), ..., Gn (odd), Gn (even), and data lines D1, ..., Dm for transmitting a data signal.

The gate lines G1 (odd), G1 (even), ..., Gn (odd), Gn (even) extend substantially in the row direction and are substantially parallel to each other, and each gate line is odd and even. ) Consists of signal lines. The data lines D1, ..., Dm extend substantially in the column direction and are substantially parallel to each other.

On the other hand, the gate lines (..., Gj-1 (odd), Gj-1 (even), Gj (odd), Gj (even), Gj + 1 (odd), Gj + of the thin film transistor array panel 1 of the present invention. In 1 (even), ..., odd-numbered gate lines and even-numbered gate lines are paired and arranged in the row direction. Here, the pair of gate lines are disposed in the same direction with respect to the pixel row corresponding thereto.

Each pixel Px includes switching elements Q1 and Q2 connected to the display signal lines G1 (odd), G1 (even), ..., Gn (odd), Gn (even), D1, ..., Dm and the liquid crystal connected thereto. A liquid crystal capacitor (Clc) and a storage capacitor (Cst).

Holding capacitor Cst can be omitted as needed.

The switching elements Q1 and Q2 are provided in the thin film transistor array panel 1, and the gate electrode and the source electrode are three-terminal elements, and the gate lines G1 (odd), G1 (even), ..., Gn (odd) are respectively. , Gn (even)) and data lines D1, ..., Dm, and the drain electrode is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The switching elements Q1 and Q2 are positioned on the left and right with respect to the data line, and the switching element Q1 located on the left side of the data line has a gate electrode connected to an odd gate line among a pair of gate lines, and is located on the right side of the data line. In the switching element Q2, a gate electrode is connected to an even gate line of a pair of gate lines to form one pixel row. The reverse is also possible. That is, the switching element Q1 located on the left side of the data line has a gate electrode connected to an even gate line among the pair of gate lines, and the switching element Q2 located on the right side of the data line has a gate connected to an odd gate line among the pair of gate lines. The electrodes may be connected to form one pixel row.

In addition, the switching element Q1 located on the left side of one data line is connected to the source electrode and the source electrode of the switching element Q2 located on the right side of the data line is connected to the one data line.

Here, the gate line is a pair of odd-numbered gate lines G1 (odd), ..., Gn (odd) and even-numbered gate lines G1 (even), ..., Gn (even), and a pair of gate lines A gate signal is respectively transmitted to a pair of source electrodes connected to one data line.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 1a of the thin film transistor array panel 1 and the common electrode 2a of the color filter display panel 2, and the liquid crystal layer 3 between the two electrodes 1a and 2a. Functions as a dielectric. The pixel electrode 1a is connected to the switching elements Q1 and Q2, and the common electrode 2a is formed on the front surface of the color filter display panel 2 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 2a may be provided in the thin film transistor array panel 1. In this case, both electrodes 1a and 2a may be linear or rod-shaped.

The storage capacitor Cst is formed by overlapping a separate signal line (not shown) and the pixel electrode 1a of the thin film transistor array panel 1, and a predetermined voltage such as a common voltage Vcom is applied to the separate signal line. Can be. In addition, the storage capacitor Cst may be formed such that the pixel electrode 1a overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is possible by providing a red, green, or blue color filter 2b in a region corresponding to the pixel electrode 1a. In FIG. 2, the color filter 2b is formed in a corresponding region of the color filter display panel 2, but may be formed above or below the pixel electrode 1a of the thin film transistor array panel 1.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the thin film transistor array panel 1 and the color filter display panel 2.

The gray voltage generator 8 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 4 is connected to the gate lines G1 (odd), G1 (even), ..., Gn (odd), and Gn (even) of the thin film transistor array panel 1 to provide a gate-on voltage Von from the outside. And a gate signal consisting of a combination of the gate off voltage Voff are applied to the gate lines G1 (odd), G1 (even), ..., Gn (odd), and Gn (even).

The data driver 5 is connected to the data lines D1, ..., Dm of the thin film transistor array panel 1, selects a gray voltage from the gray voltage generator 8, and applies the gray voltage to the pixel as a data signal. It consists of a circuit.

The timing controller 6 generates control signals for controlling operations of the gate driver 4 and the data driver 5, and provides the corresponding control signals to the gate driver 4 and the data driver 5.

The display operation of such a liquid crystal display device will now be described in detail.

The timing controller 6 includes an input control signal for controlling red, green, and blue image signals R, G, and B and its display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync. The horizontal synchronization signal Hsync, the main clock MCLK, and the data enable signal DE are provided. The timing controller 6 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the thin film transistor array panel 1. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 4, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 5.

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D1, ..., Dm. Signal (LOAD), an inverted signal (RVS) that inverts the polarity of the data voltage with respect to the common voltage (Vcom) (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage); Data clock signal HCLK and the like.

The data driver 5 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels in accordance with the data control signal CONT2 from the timing controller 6, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' from the gray level voltage from 8).

The gate driver 4 supplies the odd-numbered and even-numbered gate lines G1 with a gate-on voltage Von having a 1/2 H period according to the vertical synchronization start signal STV and the gate clock signal CPV from the timing controller 6. (odd), G1 (even), ..., Gn (odd), Gn (even) to apply this gate line G1 (odd), G1 (even), ..., Gn (odd), Gn (even) Turn on the switching elements Q1 and Q2 connected thereto. Here, the gate-on voltage Von may be applied to the gate lines G1 (odd), G1 (even), ..., Gn (odd), and Gn (even) in order in the pixel column direction, and the odd gate lines ( It may be sequentially applied to the G1 (odd), ..., Gn (odd) in the pixel column direction, and may be sequentially applied to the even-numbered gate lines G1 (even), ..., Gn (even) in the pixel column direction.

One row of switching elements Q1 and Q2 connected to and connected to the odd and even gate lines G1 (odd), G1 (even), ..., Gn (odd), and Gn (even). While is turned on, the data driver 5 supplies each data voltage to the corresponding data lines D1, ..., Dm. The data voltages supplied to the data lines D1, ..., Dm are applied to the corresponding pixels through the turned-on switching elements Q1, Q2.

The liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode 1a and the common electrode 2a, and thus the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 1 and 2.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 (odd), G1 (even), ..., Gn (odd), and Gn (even) during one frame, thereby all pixels. Apply a data voltage to it. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 5 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that in the previous frame (this is called frame inversion). Is called). In this case, the polarities of the data voltages flowing through one data line may be changed (called line inversion) or the polarities of the data voltages applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame. (This is called dot inversion).

Meanwhile, in the pixel array of the thin film transistor array panel 1 according to the exemplary embodiment of the present invention, the data voltage is transferred to a pair of pixels with respect to one data line, so the number of data lines is reduced by half, and the number of gate lines is two. Increase by 2X At this time, by integrating the gate driver 4 on one side or left and right sides of the thin film transistor array panel 1, it is possible to prevent the size of the thin film transistor array panel 1 from increasing.

Therefore, by doubling the number of pixels even in the same screen size, it is possible to realize twice as high resolution as before.

Hereinafter, various embodiments of the liquid crystal display of FIGS. 1 to 3 will be described with reference to FIGS. 4A to 8B.

First, the structure of the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A to 4C. 4A is a layout view of a thin film transistor array panel used in a liquid crystal display according to a first embodiment of the present invention, and FIG. 4B is a layout view of a color filter display panel used in a liquid crystal display according to a first embodiment of the present invention. 4C is a layout view of a liquid crystal display including the thin film transistor array panel of FIG. 4A and the color filter display panel of FIG. 4B. 5A is a cross-sectional view taken along line Va-Va 'of the thin film transistor array panel of FIG. 4A, and FIG. 5B is a cross-sectional view taken along line Vb-Vb' of the thin film transistor array panel of FIG. 4A.

4A, 4C, 5A, and 5B, gate wirings 22, 24, and 26 and a storage capacitor wiring 28 are formed on the insulating substrate 10. Here, the gate wirings 22, 24, 26 and the storage capacitor wiring 28 may be a single layer made of Al (Al alloy), or a double layer in which Al (Al alloy) and Mo (Mo alloy) are laminated. .

The gate wires 22, 24, and 26 are connected to the ends of the gate line 22 and the gate line 22 extending in the horizontal direction, and receive gate signals from the outside and transmit them to the gate line 22. And a gate electrode 26 of the thin film transistor connected to the gate 24 and the gate line 22. The gate line 22 is formed by pairing odd-numbered gate lines 22a and even-numbered gate lines 22b, and a pair of odd-numbered gate lines 22a and even-numbered gate lines 22b are formed in one pixel row. Are arranged together on either side.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate lines 22, 24, 26, and the storage capacitor line 28.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 of the gate electrode 26 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

The data lines 62, 65, 66, and 68 are formed on the ohmic contacts 55 and 56 and the gate insulating layer 30. The data lines 62, 65, 66, and 68 are formed in the vertical direction and intersect with the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 54. It is connected to one end of the source electrode 65 and the data line 62 extending to the upper part, and is separated from the data line end 68 and the source electrode 65 to which an image signal from the outside is applied, and the gate electrode 26. ) And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 65. At this time, the data line end 68 of the data line 62 is extended in width for connection with an external circuit. Here, the data lines 62, 65, 66, and 68 may have a single layer made of a conductive film such as Al (Al alloy) or Mo (Mo alloy), or a multilayer structure in which one or more of them are stacked.

As shown in FIG. 4A, the switching element including the source electrode 65, the drain electrode 66, and the gate electrode 26 is positioned at left and right about the data line 62. The switching element located on the left side of the data line 62 is connected to the gate electrode 26 extending from the odd-numbered gate line 22a, and the switching element located on the right side of the data line 62 is even. The gate electrode 26 extends from the first gate line 22b. Here, the pair of switching elements positioned on the left and right with respect to the data line 62 receives each data signal from the same one data line 62. The odd-numbered gate lines 22a and even-numbered gate lines 22b connected to the pair of switching elements are arranged adjacent to either one of the upper side and the lower side with respect to one pixel. That is, the odd-numbered gate lines 22a and the even-numbered gate lines 22b are arranged in pairs in the row direction, and the pair of odd-numbered and even-numbered gate lines 22a and 22b are identical with respect to the corresponding pixel row. Is placed in the direction.

The present invention is not limited to the arrangement of the switching elements described above, and the arrangement of the left and right switching elements can be changed around the data line 62.

In addition, referring to FIG. 3, the switch elements positioned in one pixel column may be alternately connected to odd-numbered gate lines and even-numbered gate lines every pixel row in order to prevent vertical line smearing or flickering. For example, in the case of the first pixel row, the switching element located on the left side of the data line is connected to the odd-numbered gate line, and the switching element located on the right side of the data line is connected to the even-numbered gate line. In the second pixel row, the switching element positioned on the left side of the data line is connected to the even gate line, and the switching element positioned on the right side of the data line is connected to the odd gate line.

The source electrode 65 overlaps at least a portion of the semiconductor layer 40, and the drain electrode 66 faces the source electrode 65 around the gate electrode 26 and at least a portion of the source electrode 65. Overlaps. In addition, portions of the source electrode 65 and the drain electrode 66 that face each other on the semiconductor layer 40 may be formed side by side.

The a-Si: C: O film deposited by the silicon nitride (SiNx) and plasma enhanced chemical vapor deposition (PECVD) methods on the data lines 62, 65, 66, and 68 and the semiconductor layer 40 exposed by them. Alternatively, a protective film 70 made of an a-Si: O: F film (low dielectric constant CVD film), an arcle-based organic insulating film, or the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 exposing the drain electrode 66 and the data line end 68 are formed, respectively, and the contact hole exposing the gate line end 24 together with the gate insulating layer 30 ( 74 is formed. In this case, the contact holes 74 and 78 exposing the ends 24 and 68 may have various angles or circular shapes.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel region is formed through the contact hole 76. In addition, the auxiliary gate line end 86 and the auxiliary data line end 88, which are connected to the gate line end 24 and the data line end 68, respectively, through the contact holes 74 and 78 on the passivation layer 70. Formed. Here, the pixel electrode 82, the auxiliary gates, and the data line ends 86 and 88 are made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO). An incision pattern 83 may be formed in the pixel electrode 82. The incision pattern 83 includes a horizontal incision pattern formed in a horizontal direction at a position half-dividing the pixel electrode 82 and an oblique incision pattern formed in diagonal directions in upper and lower portions of the half-divided pixel electrode 82, respectively. do. At this time, the upper and lower diagonal cut pattern may be formed to be substantially perpendicular to each other. This is to evenly distribute the direction of the fringe field in four directions.

Here, instead of the storage capacitor wiring 28 in the same layer as the gate wirings 22, 24, and 26, the pixel electrode 82 may be formed to overlap the gate line 22 to form a storage capacitor.

As described above, the pair of pixel electrodes 82a and 82b which are disposed left and right about the one data line 62 and use the data line 62 in common, are connected to the pair of pixel electrodes 82a and 82b. When a pair of gate lines 22a and 22b corresponding to each other are arranged adjacent to one side (upper or lower side) of the pair of pixel electrodes 82a and 82b, between the gate line 22 and the pixel electrode 82, respectively. Coupling can be reduced. This will be described in detail as follows. First, the odd-numbered gate line 22a is turned on so that the pixel voltage is first charged to the left pixel electrode 82a positioned on the left side of the data line 62. Thereafter, the even-numbered gate line 22b is turned on to charge the pixel voltage to the right pixel electrode 82b positioned on the right side of the data line 62. At this time, since the distance W between the left pixel electrode 82a already charged with the pixel voltage and the even-numbered gate line 22b is disposed far enough to ignore the coupling, the even-numbered gate line 22b is disposed. Even when turned on, the pixel voltage of the left pixel electrode 82a is not affected.

Therefore, since there is almost no coupling between the pixel electrode 82 and the gate line 22, the aperture ratio can be improved by reducing the separation distance between the pixel electrode 82 and the gate line 22. For example, a distance between the gate line positioned closer to the pixel electrode 82 of the odd-numbered gate line 22a and the even-numbered gate line 22b and the pixel electrode 82 may be about 8-13 μm. Conventionally, in order to prevent coupling between the pixel electrode 82 and the gate line 22, the pixel electrode 82 and the gate line 22 are disposed at least about 13 μm apart, but according to the liquid crystal display according to the present exemplary embodiment, Since the coupling is prevented, the separation distance between the pixel electrode 82 and the gate line 22 may be smaller than about 13 μm. However, in order to prevent a short between the pixel electrode 82 and the gate line 22, the pixel electrode 82 and the gate line 22 may be formed at a distance of about 8 μm or more.

4B and 4C, FIG. 4B is a layout view of a color filter display panel, in which a common electrode 140 made of a conductive material such as ITO or IZO is formed on a front surface thereof. Here, the cutting pattern 142 is formed on the common electrode 140. The incision pattern 142 includes a horizontal incision pattern formed in a horizontal direction at a position that divides the common electrode 140 up and down and an oblique incision pattern which is formed in diagonal directions at upper and lower portions of the divided common electrode 142, respectively. do. At this time, the upper and lower diagonal cut pattern may be formed to be substantially perpendicular to each other. This is to evenly distribute the direction of the fringe field in four directions. Although not shown, a black matrix (not shown) and a red, green, or blue color filter (not shown) are formed in an area corresponding to the periphery of the pixel area in the color filter display panel.

4C is a layout view of the thin film transistor array panel of FIG. 4A and the color filter panel of FIG. 4C. The diagonal cutout pattern 142 of the common electrode 140 has a diagonal cutout pattern 83 of the pixel electrode 82 at the center thereof. Arranged along the way.

When the thin film transistor array panel and the color filter substrate having such a structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, a basic structure of the liquid crystal display is provided. When the thin film transistor array panel and the color filter substrate are aligned, the cut pattern 83 of the pixel electrode 82 and the cut pattern 142 of the common electrode 140 divide the pixel region into a plurality of small domains. These small domains are classified into four types according to the average major axis direction of the liquid crystal molecules located therein.

As described above, the thin film transistor array panel of the present invention has been described using a PVA (Pattern Vertical Alignment) method for forming a cutting pattern on an electrode as a means for implementing a wide viewing angle. The present invention may also be applied to a multi-domain vertical alignment (MVA) method for implementing a wide viewing angle.

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 6. 6 is a layout view of a liquid crystal display according to a second exemplary embodiment of the present invention. For convenience of description, members having the same functions as the members shown in the drawings of the first embodiment are denoted by the same reference numerals, and therefore description thereof is omitted. As shown in FIG. 6, the liquid crystal display of this embodiment has a structure basically the same as that of the liquid crystal display shown in FIG. 4C except for the following. That is, as shown in FIG. 6, the drain electrode 266 is formed to completely cross over the gate electrode 26. As such, when the drain electrode 266 is formed to completely cross the gate electrode 26, a margin and an overlay of the photolithography process when forming the drain electrode 266 after the gate electrode 26 are formed. Even considering the mismatch of the gate electrode 26 and the drain electrode 266 is always completely overlapped. Thus, parasitic capacitance generated between the gate electrode 26 and the drain electrode 266 always has the same value for each pixel.

Referring back to FIG. 3, the gate voltage Vg is applied to the gate electrode of the switching element Q1, and the data voltage Vd is applied to the source electrode. The storage capacitor Cst and the liquid crystal capacitor Clc are connected to the drain electrode of the switching element Q1, and the sustain voltage Vcs is applied to the other terminal of the storage capacitor Cst, and the other of the liquid crystal capacitor Clc is applied. The common voltage Vcom is applied to the terminal. When the gate voltage Vg is turned on, the switching element Q1 is turned on to apply the data voltage Vd to the pixel electrode, thereby charging the liquid crystal capacitor Clc and the storage capacitor Cst. The voltage of the pixel electrode is expressed as the pixel voltage Vp and represents the actual voltage charged in the liquid crystal capacitor Clc. The polarity of the data voltage Vd is periodically inverted based on the common voltage Vcom. However, when the switching element Q1 is switched from the turn-on state to the turn-off state, the sudden decrease in the gate voltage Vg is caused by the coupling of the parasitic capacitance Cgd between the gate electrode and the drain electrode. The voltage actually charged in the liquid crystal capacitor Clc drops by the kickback voltage Vk due to the phenomenon of (coupling). Due to the kickback voltage, the amount of positive polarity and the amount of negative polarity charged in the liquid crystal capacitor do not exactly coincide with each other and are recognized as flickering. The kickback voltage Vk is expressed by the equation using the gate voltage Vg as follows.

Vk = {Cgd / (Clc + Cst + Cgd)} Vg

The kickback voltage Vk is influenced by the parasitic capacitance Cgd between the gate electrode and the drain electrode. If the parasitic capacitance Cgd is different for each pixel, the kickback voltage is different for each pixel, thereby causing flickering. This increases the quality of the entire thin film transistor array panel.

In the case of the liquid crystal display of the present invention, since the parasitic capacitance between the gate electrode 26 and the drain electrode 266 has substantially the same value for each pixel, the occurrence of flickering is suppressed, and the same image quality is maintained for each pixel. Can be implemented. In particular, in the case of a thin film transistor array panel having a different position of the switching element for each pixel, even if an overlay mismatch occurs between the gate wiring and the data wiring, the drain electrode 266 completely overlaps the gate electrode 26. There is little change. In addition, since the regions in which the source electrode 265 and the drain electrode 266 face each other are constant for each pixel, the W / L (width / length) values of the respective switching elements can be kept the same.

In addition, the drain electrode 266 may be formed to completely cross the semiconductor layer 40.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

As described above, according to the liquid crystal display according to the present invention, by reducing the coupling between the gate line and the pixel electrode, it is possible to prevent vertical streaks caused by the luminance deviation between pixels. In addition, the parasitic capacitance generated for each pixel may be maintained at the same level or the amount of change thereof may be minimized to prevent the flicker phenomenon and to achieve excellent image quality of the entire liquid crystal display.

Claims (10)

  1. A plurality of pixel electrodes connected to the switching elements arranged in a matrix form;
    A plurality of gate lines connected to the switching element and extending in a row direction in a pair of odd-numbered gate lines and even-numbered gate lines; And
    A plurality of data lines connected to the switching element and extending in a column direction,
    First and second switching elements respectively connected to both sides of the same data line among the switching elements are respectively connected to the odd and even gate lines,
    And a pair of odd-numbered gate lines and even-numbered gate lines are disposed on one side of each pixel electrode.
  2. The method according to claim 1,
    And a gate line positioned closer to the pixel electrode of the odd-numbered gate line and the even-numbered gate line is spaced apart from the pixel electrode by 8 to 13 μm.
  3. The method according to claim 1,
    And the switching elements positioned in one pixel column are alternately connected to the odd-numbered gate line and the even-numbered gate line every pixel row.
  4. The method according to claim 1,
    And a gate-on voltage are sequentially applied to the gate line in the pixel column direction.
  5. The method according to claim 1,
    And a gate on voltage is sequentially applied to the odd gate lines in the pixel column direction, and then sequentially applied to the even gate lines in the pixel column direction.
  6. The method according to claim 1,
    The data line is connected to the switching element by a source electrode branched from the data line, the gate line is connected to the switching element by a gate electrode branched from the gate line, and the pixel electrode is connected to the pixel electrode. Connected to the switching element by a connected drain electrode,
    And the drain electrode is opposite to the source electrode with respect to the gate electrode and completely crosses the gate electrode.
  7. The method according to claim 6,
    And a gate line positioned closer to the pixel electrode of the odd-numbered gate line and the even-numbered gate line is spaced apart from the pixel electrode by 8 to 13 μm.
  8. The method according to claim 6,
    And the switching elements positioned in one pixel column are alternately connected to the odd-numbered gate line and the even-numbered gate line every pixel row.
  9. The method according to claim 6,
    And a gate-on voltage are sequentially applied to the gate line in the pixel column direction.
  10. The method according to claim 6,
    And a gate on voltage is sequentially applied to the odd gate lines in the pixel column direction, and then sequentially applied to the even gate lines in the pixel column direction.
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Publication number Priority date Publication date Assignee Title
KR19990087992A (en) * 1998-05-11 1999-12-27 아베 아키라 A driving method for LCD device &driving circuit the same
KR20020072723A (en) * 2001-03-12 2002-09-18 삼성전자 주식회사 Liquid crystal display device and a driving method thereof

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
KR19990087992A (en) * 1998-05-11 1999-12-27 아베 아키라 A driving method for LCD device &driving circuit the same
KR20020072723A (en) * 2001-03-12 2002-09-18 삼성전자 주식회사 Liquid crystal display device and a driving method thereof

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