CN106023919B - Shift register and its driving method, driving circuit and display device - Google Patents
Shift register and its driving method, driving circuit and display device Download PDFInfo
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- CN106023919B CN106023919B CN201610509426.9A CN201610509426A CN106023919B CN 106023919 B CN106023919 B CN 106023919B CN 201610509426 A CN201610509426 A CN 201610509426A CN 106023919 B CN106023919 B CN 106023919B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention discloses a kind of shift register and its driving method, driving circuit and display device, is related to display field, solves existing GOA circuit noise problems of too.Shift register includes pull-up control module, pull-up module, pull-down control module and pull-down module, and pull-down control module includes: that first film transistor control terminal and first end link together and input the first clock signal；Second thin film transistor (TFT) control terminal receives the first input signal, and first end is connected with the second end of first film transistor, and second end accesses low level signal；Third thin film transistor (TFT) control terminal is connected with the second end of first film transistor, and first end accesses second clock signal；4th thin film transistor (TFT) control terminal accesses second clock signal, and first end is connected with the second end of third thin film transistor (TFT), and second end is connected with second node；First capacitor first end is connected with the control terminal of the second end of first film transistor, third thin film transistor (TFT), and second end accesses low level signal.
Description
Technical field
The present invention relates to display field more particularly to a kind of shift registers and its driving method, driving circuit and display
Device.
Background technique
Array substrate row drives (Gate Driver on Array, GOA) technology, is directly by gate driving circuit
(Gate driver ICs) is integrated in array substrate, to replace a kind of technology of external driving chip.The technology is answered
With can not only reduce production technology program, product cost is reduced, improves integrated level, and can accomplish that panel both sides are symmetrically beautiful
Design is seen, while also eliminating the binding region (Bonding) of grid circuit (Gate IC) and being fanned out to (Fan-out) wiring
Production capacity and yields are improved so that the design of narrow frame can be realized in space.
Tend to be fierce now with the competition of liquid crystal display panel industry, reduces panel cost and improving performance is wanted to become panel vendor
Competition spot, wherein the reduction of circuit noise and power consumption is the importance that GOA circuit performance is promoted specific to GOA circuit.
As shown in Figure 1, Fig. 2 shows timing when shift register work for one of existing GOA circuit shift register, it should
Shift register includes 10 TFT and 2 capacitors, and two clock signal clks 1 and CLK2, direct current high level letter are needed when work
Number VGH and direct current low level signal VGL, the input signal STV_IN of upper level, the output signal STV_N+1 signal of next stage,
Positive and negative low and high level the signal CN and CNB swept is controlled, if CN is high level, CNB is that low level is positive and sweeps, on the contrary then be anti-
It sweeps.There are noises when exporting low level by shift register output signal Out, influence panel performance and yield.
Summary of the invention
The present invention provides a kind of shift register and its driving method, driving circuit and display device, solves existing GOA
The excessive problem of circuit noise has the characteristics that noise is low, low in energy consumption, can promote panel performance and yield very well.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
The embodiment of the present invention provides a kind of shift register, comprising: pull-up control module, pull-up module, drop-down control
Module and pull-down module, the pull-up control module are linked together with the pull-up module by first node, the drop-down
Control module and the pull-down module are linked together by second node；The pull-up control module is to receive the displacement
First input signal of register, and raise under the action of first input signal current potential at the first node；Institute
It states pull-up module to be connected with the output end, to raise the output under the action of current potential at the first node
Current potential；The pull-down control module is lifted under the action of first input signal to receive first input signal
Current potential at the high second node；The pull-down module is connected with the output end, to the electricity at the second node
The current potential of the output is dragged down under the action of position；The pull-down control module, comprising: first film transistor, control
End and its first end link together, and input the first clock signal；Second thin film transistor (TFT), control terminal receive the first input
Signal, first end are connected with the second end of the first film transistor, and second end accesses low level signal；Third film
Transistor, control terminal are connected with the second end of the first film transistor, and first end accesses second clock signal；4th
Thin film transistor (TFT), control terminal access the second clock signal, the second end of first end and the third thin film transistor (TFT)
It is connected, second end is connected with the second node；The second of first capacitor, first end and the first film transistor
End, the control terminal of the third thin film transistor (TFT) are connected, and second end accesses low level signal；Wherein, the first clock letter
Number with the second clock signal inversion.
Further, the pull-down control module, further includes: the 5th thin film transistor (TFT), control terminal input described first
Input signal, first end are connected with the second node, and second end accesses low level signal；6th thin film transistor (TFT),
Control terminal is connected with the output end, and first end is connected with the second node, and second end accesses low level signal.
Preferably, the pull-up module, comprising: the 7th thin film transistor (TFT), control terminal are connected with the first node,
First end inputs first clock signal, and second end is connected with the output end；8th thin film transistor (TFT), control terminal with
The first node is connected, and first end links together with its second end, and the second end with the 7th thin film transistor (TFT)
And the output end is connected.
The pull-down module includes: the 9th thin film transistor (TFT), and control terminal is connected with the second node, first end with
The output end is connected, and second end accesses low level signal；Tenth thin film transistor (TFT), control terminal and the second node phase
Even, first end and its second end access low level signal.
Preferably, it is additionally provided between the pull-up module and the pull-up control module: the 11st thin film transistor (TFT),
Control terminal accesses high level signal, and first end is connected with the output end of the pull-up control module, second end and described the
Two nodes are connected.
Preferably, the pull-up control module, comprising: the 12nd thin film transistor (TFT), control terminal access described first are defeated
Enter signal, first end accesses high level signal；13rd thin film transistor (TFT), control terminal are connected with the second node,
Second end accesses low level signal, and first end and the second end of the 12nd thin film transistor (TFT) link together, and conduct
The output end of the pull-up control module is connected with the first node.
Optionally, the shift register, further includes: positive and negative to sweep control module, the positive and negative control module of sweeping includes:
Control signal is just being swept in 14 thin film transistor (TFT)s, control terminal access, and first end accesses the output letter of upper level shift register
Number；15th thin film transistor (TFT), control terminal access is counter to sweep control signal, and second end accesses the defeated of next stage shift register
Signal out, first end and the second end of the 14th thin film transistor (TFT) link together, and positive and negative sweep control as described
The output end of module exports first input signal to the pull-up control module.
The embodiment of the present invention provides a kind of driving circuit, including shift register described in any of the above embodiments.
The embodiment of the present invention provides a kind of display device, is provided with above-mentioned driving circuit.
The embodiment of the present invention also provides a kind of driving method of shift register, is suitable for shifting described in any of the above embodiments
Bit register, the driving method include: the first stage, and the first clock signal exports low level, and the output of second clock signal is high
Level, the first input signal are high level, and the first input signal opens the second thin film transistor (TFT) in pull-down control module, low
Level signal inputs the first end of first capacitor by the second thin film transistor (TFT), while pulling up control module in first input
The current potential at first node is raised under the action of signal；Second stage, the first clock signal export high level, second clock signal
Low level is exported, the first input signal is low level, and in the pull-down control module, the low level of the first input signal makes second
Thin film transistor (TFT) is closed, and the high level of the first clock signal output opens first film transistor, and first clock signal is defeated
High level out charges to first capacitor, while raising output end under high potential effect of the pull-up module at the first node
The current potential at place；Phase III, the first clock signal export low level, and second clock signal exports high level, the first input signal
For low level, in the pull-down control module, the low level of first input signal closes the second thin film transistor (TFT), described
The low level of first clock signal output closes first film transistor, and the high level of second clock signal output opens the
Four thin film transistor (TFT)s, since the current potential holding of first capacitor acts on, third thin film transistor (TFT) is also opened, the second clock signal
The high level of output through the third thin film transistor (TFT) and the 4th thin film transistor (TFT) input second node at, raise described the
Current potential at two nodes, current potential of the pull-down module at second node under the action of, drag down the current potential of output.
Preferably, the pull-down control module, further includes: driven described in the 5th thin film transistor (TFT) and the 6th thin film transistor (TFT)
In method, the first stage, the high level of first input signal keeps the 5th film in the pull-down control module brilliant
Body pipe is opened, and low voltage signal drags down the current potential of the second node；The second stage, the low electricity of first input signal
Flat to close the 5th thin film transistor (TFT) in the pull-down control module, the high potential of the input terminal opens the 6th film crystal
Pipe, low voltage signal continue to drag down the current potential of the second node；The phase III, the low level of first input signal
Close the 5th thin film transistor (TFT) in the pull-down control module, the low potential of the input terminal closes the 6th film crystal
Pipe.
Preferably, the pull-up module, comprising: the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), the driving method
In, the 8th thin film transistor (TFT) is equivalent to a capacitor.
Preferably, the pull-down module includes the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT), in the driving method,
Tenth thin film transistor (TFT) is equivalent to a capacitor.
Preferably, it is additionally provided between the pull-up module and the pull-up control module: the 11st thin film transistor (TFT), institute
It states in driving method, the pull-up control module, which is transmitted by a thin film transistor (TFT) in normally open to first node, to be believed
Number.
Preferably, the pull-up control module, comprising: the 12nd thin film transistor (TFT) and the 13rd thin film transistor (TFT), it is described
In driving method further include: the first stage, the high level of first input signal open the 12nd thin film transistor (TFT) and
5th thin film transistor (TFT), high level signal pass to the current potential that first node raises the first node, while low level signal
Pass to the current potential that second node drags down second node；The second stage, the low level of first input signal close the
12 thin film transistor (TFT)s and the 5th thin film transistor (TFT), the high level of the first clock signal opens the 7th thin film transistor (TFT), described
Output end exports high level, and the current potential of first node further increases, and the high level of input terminal opens the 6th thin film transistor (TFT), low
Level signal, which continues to pass to second node, makes second node continue to low potential；The phase III, first input
The low level of signal closes the 12nd thin film transistor (TFT) and the 5th thin film transistor (TFT), and it is brilliant that the low level of input terminal closes the 6th film
Body pipe, the high level of second node open the 13rd thin film transistor (TFT), and low level signal continues to pass to first node, drag down
The current potential of the first node.
The embodiment of the present invention provides a kind of shift register and its driving method, driving circuit and display device, the shifting
The pull-down control module of bit register includes: first to fourth thin film transistor (TFT) and first capacitor, wherein the first film crystal
The control terminal first end of pipe links together, and inputs the first clock signal；The control terminal of second thin film transistor (TFT) receives first
Input signal, first end are connected with the second end of first film transistor, and second end accesses low level signal；Third film crystal
The control terminal of pipe is connected with the second end of first film transistor, and first end accesses second clock signal；4th thin film transistor (TFT)
Control terminal access second clock signal, first end is connected with the second end of third thin film transistor (TFT), second end and second node
It is connected；The first end of first capacitor is connected with the control terminal of the second end of first film transistor, third thin film transistor (TFT), and second
It terminates into low level signal；When work, in the first stage, the first clock signal exports low level, and the output of second clock signal is high
Level, the first input signal is that high level opens the second thin film transistor (TFT) in pull-down control module, and low level signal passes through the
Two thin film transistor (TFT)s input the first end of first capacitor, while pulling up control module and raising current potential at first node；Second-order
Section, in pull-down control module, the first input signal is that low level closes the second thin film transistor (TFT), and the output of the first clock signal is high
Level opens first film transistor, and second clock signal exports low level and closes the 4th thin film transistor (TFT), the first clock signal
The high level of output charges to first capacitor, while raising output under high potential effect of the pull-up module at first node
Current potential；Phase III, in pull-down control module, the first input signal is that low level closes the second thin film transistor (TFT), first
Clock signal exports low level and closes first film transistor, and second clock signal exports high level and opens the 4th film crystal
Pipe, since the current potential holding of first capacitor acts on, third thin film transistor (TFT) is opened, and the high level of second clock signal output is through the
Three thin film transistor (TFT)s and the 4th thin film transistor (TFT) raise the current potential at second node, current potential of the pull-down module at second node
The current potential of output is dragged down under effect.The presence of first capacitor can stablize the grid voltage for keeping third thin film transistor (TFT),
Carry out the more preferable transmission so that second clock signal CK2 with this, stabilization draws high second node (PD point) voltage, keeps output end output steady
Fixed low-voltage solves the problems, such as that existing GOA circuit low pressure noise is excessive.Shift LD utensil provided in an embodiment of the present invention
Have the characteristics that noise is low, low in energy consumption, panel performance and yield can be promoted very well.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the circuit diagram of existing shift register；
Fig. 2 is the working timing figure of existing shift register；
Fig. 3 is the structural schematic diagram one of shift register provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram two of shift register provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram three of shift register provided in an embodiment of the present invention；
Fig. 6 is the structural schematic diagram four of shift register provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram five of shift register provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram six of shift register provided in an embodiment of the present invention；
Fig. 9 is the working timing figure of shift register shown in Fig. 8.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
Embodiment
The embodiment of the present invention provides a kind of shift register, as shown in Figure 3, comprising: pull-up control module 10, upper drawing-die
Block 20, pull-down control module 30 and pull-down module 40, pull-up control module 10 are connected to pull-up module 20 by first node
Together, pull-down control module 30 and pull-down module 40 are linked together by second node, wherein first node also known as pulls up
Node, abbreviation PU node, second node are also known as pull-down node, abbreviation PD node；Pull-up control module 10 is to receive displacement
First input signal of register, and raise under the action of the first input signal the current potential of PU node；Pull-up module 20 with it is defeated
Outlet OUT is connected, to raise the current potential at output end OUT under the action of the current potential of PU node；Pull-down control module 30 is used
To receive the first input signal, the current potential at PD node is raised under the action of the first input signal；Pull-down module 40, with output
OUT is held to be connected, to drag down the current potential at output end OUT under the action of current potential at PD node；Pull-down control module 30, packet
Include: first film transistor T1, control terminal and its first end link together, and input the first clock signal clk 1；Second
Thin film transistor (TFT) T2, control terminal receive the first input signal, and first end is connected with the second end of first film transistor T1,
Its second end accesses low level signal VGL；Third thin film transistor (TFT) T3, the second end of control terminal and first film transistor T1
It is connected, first end accesses second clock signal CLK2；4th thin film transistor (TFT) T4, control terminal access second clock signal
CLK2, first end are connected with the second end of third thin film transistor (TFT) T3, and second end is connected with PD node；First capacitor C1,
Its first end is connected with the control terminal of the second end of first film transistor T1, third thin film transistor (TFT) T3, second end access
Low level signal VGL；Wherein, the first clock signal clk 1 and second clock signal CLK2 reverse phase.
It should be noted that the first above-mentioned input signal is the output signal of upper level shift register (to the first order
It is frame start signal for shift register), the first input signal is specifically corresponding lastrow gate line signals or next line grid
Line signal, which is work depending on shift register, just to be swept mode or counter is sweeping mode.
The embodiment of the present invention also provides a kind of driving method of above-mentioned shift register, referring to shown in Fig. 3 and Fig. 9, the drive
Dynamic method includes:
101, first stage T1, the first clock signal clk 1 export low level, and second clock signal CLK2 exports high level,
First input signal is high level, and the first input signal opens the second thin film transistor (TFT) T2 in pull-down control module 30, low
Level signal VGL inputs the first end of first capacitor C1, first capacitor C1 electric discharge, third film by the second thin film transistor (TFT) T2
Transistor T3 is closed, and the 4th thin film transistor (TFT) T4 is opened；Control module 10 is pulled up simultaneously to lift under the action of the first input signal
Current potential at high PU node；
102, second stage T2, the first clock signal clk 1 export high level, and second clock signal CLK2 exports low level,
First input signal is low level, and in pull-down control module 30, the low level of the first input signal makes the second thin film transistor (TFT) T2
It closes, the high level of the first clock signal clk 1 output opens first film transistor T1, the output of the first clock signal clk 1
High level charges to first capacitor C1, lifts between the current potential of the first end (being located at the endpoint above C1 in figure) of first capacitor C1
The control terminal potential of height, third thin film transistor (TFT) T3 increases, and the 4th thin film transistor (TFT) T4 is defeated in second clock signal CLK2
Low level effect out is lower to close；Meanwhile it being raised at output end OUT under high potential effect of the pull-up module 20 at PU node
Current potential, output end OUT export high level；
103, phase III T3, the first clock signal clk 1 export low level, and second clock signal CLK2 exports high level,
First input signal is low level, and in pull-down control module 30, the low level of the first input signal makes the second thin film transistor (TFT) T2
It closes, the low level of the first clock signal clk 1 output closes first film transistor T1, second clock signal CLK2 output
High level opens the 4th thin film transistor (TFT) T4, in third thin film transistor (TFT) T3 control terminal on the basis of second stage is raised, due to
The current potential holding of first capacitor C1 acts on, and third thin film transistor (TFT) T3 is kept open, second clock signal CLK2 output
High level inputs at PD node through third thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4, gradually raises the electricity at PD node
Position, current potential of the pull-down module 40 at PD node under the action of, drag down current potential output end OUT at, the low electricity of output end OUT output
It is flat.
The addition that this step course of work can be seen that first capacitor C1 can be used to stablize to keep third thin film transistor (TFT)
The current potential of T3 control terminal carrys out the more preferable transmission so that second clock signal CLK2 with this, and existing in order to stabilize draw high PD point current potential
There is technology to compare, PD point current potential can more rapidly be drawn high, it is more able to maintain stabilization after drawing high, and pull-down module 40 is at PD node
Control of Electric potentials under drag down current potential at output end OUT, the low level incipient stability of output end OUT output faster, is stablized as a result,
Noise is lower afterwards.
Those skilled in the art come it is understood that the present embodiment shift register can also include unmentioned other
Module, in addition, pull-up control module 10 can also include unmentioned other circuit component parts, these unmentioned other moulds
The specific structure of block and other built-up circuit parts and pull-up module 20, pull-down control module 30 and pull-down module 40, this reality
Example is applied without limitation, as long as not influencing the realization of each functions of modules described above.
Illustratively, as shown in figure 3, above-mentioned pull-down control module 30 may also include that the 5th thin film transistor (TFT) T5, control
The first input signal of end input, first end are connected with PD node, and second end accesses low level signal VGL；6th film is brilliant
Body pipe T6, control terminal are connected with output end OUT, and first end is connected with PD node, and second end accesses low level signal
VGL。
In shift register work, in the above-mentioned first stage, the high level of the first input signal keeps the 5th film brilliant
Body pipe T5 is opened, and low voltage signal drags down the current potential of PD node, and pull-down module 40 does not work, and guarantees that higher level's input signal does not influence
Output end；In above-mentioned second stage, the low level of the first input signal closes the 5th thin film transistor (TFT) T5, the height of input terminal
Current potential opens the 6th thin film transistor (TFT) T6, and low voltage signal continues to drag down the current potential of PD node, and same pull-down module 40 does not work,
Guarantee that higher level's input signal does not influence output end；Phase III, pull-down module 40 drag down defeated under the control of Electric potentials at PD node
Current potential at outlet OUT, the low level of the first input signal close the 5th thin film transistor (TFT) T5, and the low potential of input terminal is closed
6th thin film transistor (TFT) T6.
As shown in figure 4, the area in another shift register for meeting the present embodiment, with shift register shown in Fig. 3
It is not, pull-up module 20 includes: the 7th thin film transistor (TFT) T7, and control terminal is connected with PU node, first end input first
Clock signal clk 1, second end is connected with output end OUT；8th thin film transistor (TFT) T8, control terminal are connected with PU node,
First end links together with its second end, and is connected with the second end of the 7th thin film transistor (TFT) T7 and output end OUT.
When the shift register works, the 8th thin film transistor (TFT) T8 is equivalent to a capacitor, the 8th thin film transistor (TFT) T8's
Control terminal is equivalent to a pole plate of capacitor, and the first, second end of the 8th thin film transistor (TFT) T8 links together, and is equivalent to capacitor
Another pole plate.Passive device capacitor is substituted with thin film transistor (TFT), noise and power consumption can be effectively reduced, to promote display
The performance and stability of device gate driving, meanwhile, thin film transistor (TFT) occupied space is smaller, manufacture craft also with circuit other parts
It is compatible, it can manufacture synchronous with other thin film transistor (TFT)s of circuit.
When the shift register works, the first stage pulls up control module 10 under the action of the first input signal, PU section
Current potential at point is gradually raised, but the first clock signal clk 1 exports low level, therefore can guarantee that output end OUT is low level；
Second stage, the first clock signal clk 1 export high level, since the 8th thin film transistor (TFT) T8 is equivalent to a capacitor, when first
When clock signal CLK1 exports high level, the current potential at PU node continues to be elevated, and the 7th thin film transistor (TFT) T7 is opened, output end
OUT exports high level, i.e. pull-up module 20 realizes the function of drawing high output end OUT current potential；Phase III, the first clock signal
CLK1 exports low level, while the current potential of PD node is low potential, and the 7th thin film transistor (TFT) T7 is closed.The work of circuit rest part
Process is roughly the same with shift register shown in Fig. 3, and details are not described herein again.
As shown in figure 5, the area in another shift register for meeting the present embodiment, with shift register shown in Fig. 4
It is not, pull-down module 40 includes: the 9th thin film transistor (TFT) T9, and control terminal is connected with PD node, first end and output end
OUT is connected, and second end accesses low level signal VGL；Tenth thin film transistor (TFT) T10, control terminal are connected with PD node, the
One end and its second end access low level signal VGL.
When the shift register works, the tenth thin film transistor (TFT) T10 is equivalent to a capacitor.Specifically, first stage, PD
Current potential at node is low level, and the 9th thin film transistor (TFT) T9 is closed；Second stage, the current potential at PD node are low level, the
One clock signal CLK1 exports high level, and the 9th thin film transistor (TFT) T9 is closed；Phase III, the current potential of PD node are high potential,
When the tenth thin film transistor (TFT) T10 equivalent capacity keeps PD node high potential, the 9th thin film transistor (TFT) T9 keeps it turning on shape
State, low level signal VGL export low level to output end OUT by the 9th thin film transistor (TFT) T9, drag down output end OUT current potential.
As shown in fig. 6, the area in another shift register for meeting the present embodiment, with shift register shown in Fig. 5
It is not, is additionally provided between pull-up module 20 and pull-up control module 10: the 11st thin film transistor (TFT) T11, control termination
Enter high level signal VGH, first end is connected with the output end OUT of pull-up control module 10, and second end is connected with PD node.
When work, pull-up control module 10 passes through the thin film transistor (TFT) (i.e. T11) in normally open to PU node-node transmission signal.
In the embodiment, increase a thin film transistor (TFT) (i.e. T11) conduct between pull-up module 20 and pull-up control module 10
Single tube transmission gate can reduce the noise of PU point, and the noise of output end is effectively reduced, and enhance the Lossless transport of signal, thus more
Good solves the excessive technical problem of GOA noise power consumption.
As shown in fig. 7, the area in another shift register for meeting the present embodiment, with shift register shown in Fig. 6
It is not, pulls up control module 10, comprising: the 12nd thin film transistor (TFT) T12, control terminal access the first input signal, the
High level signal VGH is accessed in one end；13rd thin film transistor (TFT) T13, control terminal are connected with PD node, and second end access is low
Level signal VGL, first end and the second end of the 12nd thin film transistor (TFT) T12 link together, and control mould as pull-up
The output end OUT of block 10 is connected with PU node.When work: the first stage, it is thin that the high level of the first input signal opens the 12nd
Film transistor T12 and the 5th thin film transistor (TFT) T5, high level signal VGH pass to the current potential that PU node raises PU node, simultaneously
Low level signal VGL passes to the current potential that PD node drags down PD node；Second stage, the low level of the first input signal close the
The high level of 12 thin film transistor (TFT) T12 and the 5th thin film transistor (TFT) T5, the first clock signal clk 1 make the 7th thin film transistor (TFT)
T7 is opened, and output end OUT exports high level, and the current potential of PU node further increases, and the high level of input terminal opens the 6th film
Transistor T6, low level signal VGL, which continue to pass to PD node, makes PD node continue to low potential；Phase III, first is defeated
The low level for entering signal closes the 12nd thin film transistor (TFT) T12 and the 5th thin film transistor (TFT) T5, and the low level of input terminal closes the
The high level of six thin film transistor (TFT) T6, PD nodes opens the 13rd thin film transistor (TFT) T13, and low level signal VGL continues to transmit
PU node is given, the current potential of PU node is dragged down.
As shown in figure 8, the area in another shift register for meeting the present embodiment, with shift register shown in Fig. 7
It is not, shift register further include: positive and negative to sweep control module 50, positive and negative control module 50 of sweeping includes: the 14th film crystal
Control signal CN is just swept in pipe T14, control terminal access, and first end accesses the output signal of upper level shift register；Tenth
Five thin film transistor (TFT)s, control terminal access is counter to sweep control signal CNB, and second end accesses the output letter of next stage shift register
Number, first end and the second end of the 14th thin film transistor (TFT) T14 link together, and sweep the defeated of control module 50 as positive and negative
Outlet OUT pulls up control module 10 and exports the first input signal.
CN and CNB is the positive and negative low and high level swept of control, such as, it is specified that CNB is that low level is positive if CN is high level
It sweeps, it is on the contrary then sweep to be counter；STV_IN is the output signal of upper level, and STV_N+1 is the output signal of next stage.When CN is high electricity
Flat, when CNB is low level, the 14th thin film transistor (TFT) T14 is normally opened, and the 15th thin film transistor (TFT) T15 is often closed, positive and negative to sweep control mould
Block 50 pulls up control module 10, pull-down control module 30 exports the output signal STV_IN of upper level, i.e. the first input signal
For the output signal STV_IN of upper level, shift register operating mode is positive the mode of sweeping；When CN is low level, CNB is high electricity
Usually, the 14th thin film transistor (TFT) T14 is often closed, and the 15th thin film transistor (TFT) T15 is normally opened, and positive and negative control module 50 of sweeping pulls up control
Molding block 10, pull-down control module 30 export the output signal STV_N+1 of next stage, i.e. the first input signal is the defeated of upper level
Signal STV_N+1 out, shift register operating mode sweep mode to be counter.It can be seen that by setting just sweep control signal CN and
It is counter to sweep control signal CNB, positive and negative scan can be carried out to shift register operating mode and selected.
Fig. 9 is the working timing figure of shift register provided in this embodiment, and specific work process is big with above-described embodiment
Cause identical, illustrated for just sweeping: CN is high level at this time, and CNB is low level, and STV_IN is higher level's output signal, STV_N+1
For junior's output signal.At the T1 moment, STV_IN is high level, and CK1, CK2 are low level, and T14 is opened, and STV_IN passes through
T14 opens simultaneously T12, T2, T5, and PU node is promoted, and PD node is low level；T2 moment, STV_IN are low level, CK1
For high level, CK2 is low level, and T1, T3, T7, T8 are opened, and the further staged of PU increases, this makes output end OUT output high
Level, OUT output high level open T6, and T6 is opened so that PD continues to drag down, while C1 charging keeps T3 normally opened；When T3
It carves, CK2 is high level, and CK1 is low level, and STV_N+1 is high level, and T3, T4 are opened, and CK2 beats T13, T9 by T3, T4
It opens, T13, T9 are opened so that PD node is raised, and PU node and output end OUT are pulled low.
Shift register provided in this embodiment can effectively be dropped by the way that passive device capacitor is replaced with thin film transistor (TFT)
Low noise and power consumption to promote the performance and stability of display apparatus grid driving, while can also reduce cost；First capacitor
The addition of C1 is used to stablize the grid voltage for keeping T3, is come with this so that the more preferable transmission stabilization of CK2 draws high PD point voltage；In addition
The shift register is additionally added a T11 pipe as single tube transmission gate and making an uproar for output end is effectively reduced to reduce the noise of PU point
Sound enhances the Lossless transport of signal, to preferably solve the excessive technical problem of GOA noise power consumption.Fig. 9 is low compared with Fig. 2
Level noise is almost without the PU point voltage decline stage is steeper more smooth, this illustrates that PU point voltage noise more low performance is more preferable, PD
The point voltage decline stage is steeper more smooth, and high pressure is more stable, these advantages of PU point voltage and PD point voltage, makes output end signal
Noise is lower, and performance is more excellent, to promote the performance and stability of display apparatus grid driving.
The embodiment of the present invention also provides a kind of driving circuit, including shift register described in any of the above embodiments.The drive
Dynamic circuit due to using shift register described in any of the above embodiments, thus has the characteristics that noise is low, low in energy consumption, can be with
Panel performance and yield are promoted very well.Driving circuit provided in this embodiment is particularly suitable in GOA scheme.
The embodiment of the present invention also provides a kind of display device, due to being provided with above-mentioned any driving circuit, face
Plate performance and yield are promoted.The display device can be with are as follows: liquid crystal display panel, Electronic Paper, oled panel, mobile phone, plate electricity
Any products or components having a display function such as brain, television set, display, laptop, Digital Frame, navigator.
Although it should be noted that be illustrated by taking N-type TFT as an example in this specification embodiment and attached drawing,
But those skilled in the art, which know, can replace with P-type TFT for part or all of pipe, due to pipe type selecting and
Thus caused circuit connection changes, and is that those skilled in the art can easily expect according to the present disclosure, belongs to
It is also interior with belonging to the scope of protection of the present invention in obvious Variations similar of the invention or related expanding.
In addition, using first, second in the present invention for the ease of clear explanation and printed words being waited to carry out classification to similar item
It distinguishes, which does not limit the invention quantitatively, only illustrating to a kind of preferred mode
Bright, those skilled in the art are according to the present disclosure, it is contemplated that obvious Variations similar or related expanding belong to
In in protection scope of the present invention.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (15)
1. a kind of shift register, comprising: pull-up control module, pull-up module, pull-down control module and pull-down module, it is described on
Control module is drawn to link together with the pull-up module by first node, the pull-down control module and the pull-down module
It is linked together by second node；First input signal of the pull-up control module to receive the shift register,
And the current potential at the first node is raised under the action of first input signal；The pull-up module and output end phase
Even, to raise the current potential of the output under the action of current potential at the first node；The pull-down control module,
To receive first input signal, the current potential at the second node is raised under the action of first input signal；
The pull-down module is connected with the output end, to drag down the output under the action of current potential at the second node
Current potential at end；It is characterized in that, the pull-down control module, comprising:
First film transistor, control terminal and its first end link together, and input the first clock signal；
Second thin film transistor (TFT), control terminal receive the first input signal, and the of first end and the first film transistor
Two ends are connected, and second end accesses low level signal；
Third thin film transistor (TFT), control terminal are connected with the second end of the first film transistor, first end access second
Clock signal；
4th thin film transistor (TFT), control terminal access the second clock signal, first end and the third thin film transistor (TFT)
Second end be connected, second end is connected with the second node；
First capacitor, second end, the control terminal of the third thin film transistor (TFT) of first end and the first film transistor
It is connected, second end accesses low level signal；
Wherein, first clock signal and the second clock signal inversion.
2. shift register according to claim 1, which is characterized in that the pull-down control module, further includes:
5th thin film transistor (TFT), control terminal input first input signal, and first end is connected with the second node,
Second end accesses low level signal；
6th thin film transistor (TFT), control terminal are connected with the output end, and first end is connected with the second node, and second
It terminates into low level signal.
3. shift register according to claim 1 or 2, which is characterized in that the pull-up module, comprising:
7th thin film transistor (TFT), control terminal are connected with the first node, and first end inputs first clock signal,
Second end is connected with the output end；
8th thin film transistor (TFT), control terminal are connected with the first node, and first end links together with its second end, and
It is connected with the second end of the 7th thin film transistor (TFT) and the output end.
4. shift register according to claim 1 or 2, which is characterized in that the pull-down module includes:
9th thin film transistor (TFT), control terminal are connected with the second node, and first end is connected with the output end, and second
It terminates into low level signal；
Tenth thin film transistor (TFT), control terminal are connected with the second node, and first end and its second end access low level
Signal.
5. shift register according to claim 1 or 2, which is characterized in that the pull-up module and the pull-up control
It is additionally provided between module:
11st thin film transistor (TFT), control terminal access high level signal, the output of first end and the pull-up control module
End is connected, and second end is connected with the second node.
6. shift register according to claim 2, which is characterized in that the pull-up control module, comprising:
12nd thin film transistor (TFT), control terminal access first input signal, and first end accesses high level signal；
13rd thin film transistor (TFT), control terminal are connected with the second node, second end access low level signal, and first
It holds and links together with the second end of the 12nd thin film transistor (TFT), and output end and institute as the pull-up control module
First node is stated to be connected.
7. shift register according to claim 1 or 2, which is characterized in that the shift register, further includes: positive and negative
Control module is swept, the positive and negative control module of sweeping includes:
Control signal is just being swept in 14th thin film transistor (TFT), control terminal access, and first end accesses upper level shift register
Output signal；
15th thin film transistor (TFT), control terminal access is counter to sweep control signal, and second end accesses next stage shift register
Output signal, first end and the second end of the 14th thin film transistor (TFT) link together, and positive and negative sweep control as described
The output end of molding block exports first input signal to the pull-up control module.
8. a kind of driving circuit, which is characterized in that including the described in any item shift registers of claim 1-7.
9. a kind of display device, which is characterized in that be provided with driving circuit according to any one of claims 8.
10. a kind of driving method of shift register is suitable for the described in any item shift registers of claim 1-7, special
Sign is that the driving method includes:
First stage, the first clock signal export low level, and second clock signal exports high level, and the first input signal is high electricity
Flat, the first input signal opens the second thin film transistor (TFT) in pull-down control module, and low level signal is brilliant by the second film
Body pipe inputs the first end of first capacitor, while pulling up control module and raising first segment under the action of first input signal
Current potential at point；
Second stage, the first clock signal export high level, and second clock signal exports low level, and the first input signal is low electricity
Flat, in the pull-down control module, the low level of the first input signal closes the second thin film transistor (TFT), and the first clock signal is defeated
High level out opens first film transistor, and the high level of the first clock signal output charges to first capacitor, simultaneously
Pull-up module raises the current potential of output under the high potential effect at the first node；
Phase III, the first clock signal export low level, and second clock signal exports high level, and the first input signal is low electricity
Flat, in the pull-down control module, the low level of first input signal closes the second thin film transistor (TFT), when described first
The low level of clock signal output closes first film transistor, and the high level of the second clock signal output opens the 4th film
Transistor, since the current potential holding of first capacitor acts on, third thin film transistor (TFT) is also opened, the second clock signal output
High level inputs at second node through the third thin film transistor (TFT) and the 4th thin film transistor (TFT), raises the second node
The current potential at place, current potential of the pull-down module at second node under the action of, drag down the current potential of output.
11. driving method according to claim 10, which is characterized in that the driving method is suitable for claim 2 institute
The shift register stated, wherein
The first stage, the high level of first input signal make the 5th thin film transistor (TFT) in the pull-down control module
It opens, low voltage signal drags down the current potential of the second node；
The second stage, the low level of first input signal make the 5th thin film transistor (TFT) in the pull-down control module
It closes, the high potential of the output end opens the 6th thin film transistor (TFT), and low voltage signal continues to drag down the electricity of the second node
Position；
The phase III, the low level of first input signal make the 5th thin film transistor (TFT) in the pull-down control module
It closes, the low potential of the output end closes the 6th thin film transistor (TFT).
12. driving method according to claim 10, which is characterized in that the driving method is suitable for claim 3 institute
The shift register stated, wherein in the driving method, the 8th thin film transistor (TFT) is equivalent to a capacitor.
13. driving method according to claim 10, which is characterized in that the driving method is suitable for claim 4 institute
The shift register stated, wherein in the driving method, the tenth thin film transistor (TFT) is equivalent to a capacitor.
14. driving method according to claim 10, which is characterized in that the driving method is suitable for claim 5 institute
The shift register stated, wherein in the driving method, the pull-up control module by the 11st thin film transistor (TFT) to
First node transmits signal.
15. driving method according to claim 10, which is characterized in that the driving method is suitable for claim 6 institute
The shift register stated, wherein in the driving method further include:
The high level of the first stage, first input signal open the 12nd thin film transistor (TFT) and the 5th film crystal
Pipe, high level signal passes to the current potential that first node raises the first node, while low level signal passes to the second section
Point drags down the current potential of second node；
The low level of the second stage, first input signal closes the 12nd thin film transistor (TFT) and the 5th film crystal
Pipe, the high level of the first clock signal open the 7th thin film transistor (TFT), and the output end exports high level, the electricity of first node
Position further increases, and the high level of output end opens the 6th thin film transistor (TFT), and low level signal, which continues to pass to second node, to be made
Second node continues to low potential；
The low level of the phase III, first input signal close the 12nd thin film transistor (TFT) and the 5th film crystal
Pipe, the low level of output end close the 6th thin film transistor (TFT), and the high level of second node opens the 13rd thin film transistor (TFT), low
Level signal continues to pass to first node, drags down the current potential of the first node.
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| CN108428425B (en) * | 2017-02-15 | 2022-03-08 | 上海和辉光电股份有限公司 | Scanning driving circuit, shift register and driving method thereof |
| CN107945732B (en) * | 2017-03-21 | 2020-04-03 | 北京大学深圳研究生院 | Gate drive circuit |
| CN106683617B (en) * | 2017-03-22 | 2021-01-01 | 京东方科技集团股份有限公司 | Shifting register unit, array substrate and display device |
| CN106940977B (en) * | 2017-05-16 | 2019-07-19 | 京东方科技集团股份有限公司 | Shift register, array substrate gate driving circuit and display device |
| CN107154236B (en) * | 2017-07-24 | 2020-01-17 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, scanning driving circuit and display device |
| CN107452425B (en) * | 2017-08-16 | 2021-02-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN107689219A (en) * | 2017-09-12 | 2018-02-13 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| CN107610736B (en) * | 2017-09-27 | 2021-09-14 | 京东方科技集团股份有限公司 | Shifting register, grid driving circuit and display device |
| CN107516505B (en) | 2017-10-19 | 2021-01-15 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display panel |
| CN109389927B (en) * | 2018-02-09 | 2020-04-24 | 京东方科技集团股份有限公司 | Shift register, driving method thereof and grid driving circuit |
| CN108172169B (en) * | 2018-03-26 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | Shift register and its driving method, launch driving circuit and display device |
| CN110875002B (en) * | 2018-08-30 | 2021-04-13 | 合肥鑫晟光电科技有限公司 | Gate driving unit and driving method thereof, gate driving circuit and display device |
| CN110517620B (en) * | 2019-08-30 | 2022-11-29 | 成都辰显光电有限公司 | Shift register and display panel |
| CN111081183B (en) | 2019-12-19 | 2023-07-25 | 武汉华星光电技术有限公司 | GOA device and display panel |
| CN111445866B (en) | 2020-05-08 | 2021-04-13 | 京东方科技集团股份有限公司 | Shift register, driving method, driving control circuit and display device |
| CN113377337B (en) * | 2021-07-07 | 2022-11-04 | 山东方寸微电子科技有限公司 | True random number generator and chip |
| CN114333701B (en) * | 2022-01-10 | 2023-03-28 | 信利(仁寿)高端显示科技有限公司 | Grid driving circuit and method |
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| CN103226981B (en) * | 2013-04-10 | 2015-09-16 | 京东方科技集团股份有限公司 | A kind of shift register cell and gate driver circuit |
| KR102040659B1 (en) * | 2013-05-20 | 2019-11-05 | 엘지디스플레이 주식회사 | Scan Driver and Display Device Using the same |
| CN105493195B (en) * | 2013-07-25 | 2019-08-02 | 夏普株式会社 | Shift register and display device |
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| CN105609136A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN105469738B (en) * | 2016-01-19 | 2017-12-12 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display device |
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