CN105427789B - Driving circuit, array substrate and display device - Google Patents
Driving circuit, array substrate and display device Download PDFInfo
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- CN105427789B CN105427789B CN201511031628.9A CN201511031628A CN105427789B CN 105427789 B CN105427789 B CN 105427789B CN 201511031628 A CN201511031628 A CN 201511031628A CN 105427789 B CN105427789 B CN 105427789B
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- shift register
- stage shift
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
- G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
Abstract
The present invention provides a kind of driving circuit, array substrate and display devices, wherein driving circuit includes at least one level vitual stage shift register；And the shift register group being electrically connected in cascaded fashion with the vitual stage shift register；Wherein, the shift register group includes first order shift register to N grades of shift registers, and the occupancy chip area for occupying chip area and being less than the i-stage shift register of the vitual stage shift register, N are the integer not less than 2, i is the positive integer no more than N.Occupancy chip area of the chip area less than i-stage shift register is occupied due to vitual stage shift register, the frame area of display device can be reduced relatively, meet the narrow frame demand of display device.
Description
Technical field
The present invention relates to field of display technology, more specifically, are related to a kind of driving circuit, array substrate and display dress
It sets.
Background technique
Existing display device, including display area and positioned at the frame region of the display area surrounding.The display device
In, driving chip provides driving signal to the pixel unit of display area by being integrated in the driving circuit of frame region, to control
Pixel unit processed carries out the display of picture.
In the prior art, for provide reset signal to the shift register in driving circuit in case error signal output,
Vitual stage shift register would generally be added in the driving circuit, which is located at multiple grades in driving circuit
The one or both ends of the shift register of connection, to provide reset signal to shift register.But since vitual stage displacement is posted
The frame that the introducing of storage will lead to display device is wider, therefore, is unfavorable for the narrow frame design of display device.
Summary of the invention
In view of this, the present invention provides a kind of driving circuit, array substrate and display device, it is empty due to introducing to solve
The wider problem of display device frame caused by quasi- grade shift register.
To achieve the above object, technical solution provided by the invention is as follows:
A kind of driving circuit, comprising:
At least one level vitual stage shift register；
And the shift register group being electrically connected in cascaded fashion with the vitual stage shift register；
Wherein, the shift register group includes first order shift register to N grades of shift registers, and described virtual
The occupancy chip area for occupying chip area and being less than the i-stage shift register of grade shift register, N are not less than 2
Integer, i are the positive integer no more than N.
A kind of array substrate, the gate driving circuit including display area and positioned at the display area periphery are described
Gate driving circuit provides grid signal to the display area, wherein the gate driving circuit is driving as described above
Circuit.
A kind of display device, the display device include array substrate as described above.
Compared to the prior art, technical solution provided by the invention has at least the following advantages:
Driving circuit, array substrate and display device provided by the invention, driving circuit include that at least one level vitual stage is moved
Bit register and the shift register group being electrically connected in cascaded fashion with vitual stage shift register, the shift register group packet
First order shift register is included to N grades of shift registers, since the occupancy chip area of vitual stage shift register is less than i-th
Therefore the occupancy chip area of grade shift register can reduce the frame area of display device relatively, meet display device
Narrow frame demand.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of driving circuit provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another driving circuit provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another driving circuit provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another driving circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The one side of the embodiment of the present invention provides a kind of driving circuit, which includes that at least one level vitual stage is moved
Bit register and the shift register group being electrically connected in cascaded fashion with vitual stage shift register, wherein the displacement is posted
Storage group includes first order shift register to N grades of shift registers, this N number of shift register is also electric in cascaded fashion
Connection.
In the present embodiment, vitual stage shift register is identical as the internal circuit configuration of i-stage shift register, different
Place is only that the occupancy chip area of the vitual stage shift register in the present embodiment is less than accounting for for i-stage shift register
With chip area, i.e. the occupancy domain face for occupying chip area and being less than any level shift register of vitual stage shift register
Product, wherein N is the integer not less than 2, and i is the positive integer no more than N.That is, being moved in the present invention by reducing vitual stage
The occupancy chip area of bit register reduces the frame area of display device.
As shown in FIG. 1, FIG. 1 is a kind of structural schematic diagrams of driving circuit provided in an embodiment of the present invention.In driving electricity
In the plane of road, vitual stage shift register and N number of shift register are arranged along first direction Y, and vitual stage shift register edge
The length L1 of first direction Y is less than i-stage shift register along the length L2 of first direction Y, so as to by reducing vitual stage
The length L1 of shift register Y in a first direction, to reduce the length of the frame of display device in a first direction on Y.
In another embodiment of the embodiment of the present invention, the length L3 of vitual stage shift register X in a second direction is small
In or equal to i-stage shift register X in a second direction length L4, wherein first direction Y and second direction X are vertical, from
And it can be by reducing vitual stage shift register in the length L3 of second direction X, to reduce the frame of display device in second party
Length on X.
Alternatively, in the another embodiment of the embodiment of the present invention, length of the vitual stage shift register along first direction Y
L1 is less than i-stage shift register along the length L2 of first direction Y, meanwhile, vitual stage shift register X in a second direction
Length L3 is less than or equal to the length L4 of i-stage shift register X in a second direction, wherein first direction Y and second direction
X is vertical, so as to by reducing the vitual stage shift register length L1 of Y and in the length of second direction X in a first direction
L3, to reduce the length of the frame of display device in a first direction on Y and second direction X.
Optionally, in the present embodiment, the chip area that occupies of vitual stage shift register is i-stage shift register
Occupy 0.6~0.8 times of chip area, including endpoint value.Specifically, the inside of vitual stage shift register and shift register
Structure is similar, the route comprising several transistors, capacitance structure and the above-mentioned transistor of connection, capacitance structure, because of vitual stage
Shift register does not need to provide effective driving signal to the pixel of display area, therefore, vitual stage shift register it is interior
Portion's structure and arrangement appropriately adjust, for example, length of its internal transistor in a first direction on Y can be suitably reduced, or
Person reduces the quantity along the first direction Y transistor arranged, so as to reduce vitual stage shift register along first direction Y's
Length L1；Similarly, the length of its internal transistor X in a second direction can be suitably reduced, or reduces X in a second direction and arranges
The quantity of the transistor of column, so as to reduce the length L3 of vitual stage shift register X in a second direction.
In the present embodiment, as shown in Figure 1, because Y is arranged shift register along a first direction, when vitual stage shift LD
When device reduces along the length L1 of first direction Y, the frame area at driving circuit both ends can be effectively reduced, realizes display panel
Narrow frame.
Further, in the present embodiment, inventor studies through many experiments, the results showed that, when vitual stage shift LD
When occupancy 0.6~0.8 times of chip area for occupying that chip area is i-stage shift register of device, above structure have compared with
Good narrow frame effect.Specifically, the chip area that occupies when vitual stage shift register is less than i-stage shift register
When occupying 0.6 times of chip area, the transistor size inside vitual stage shift register is too small, is not enough to support driving circuit
Signal input/output and transistor arrangement in required vitual stage shift register too closely also make inside it
The mutual crosstalk of route interferes the normal operation of vitual stage shift register.And work as the occupancy domain face of vitual stage shift register
When product is greater than 0.8 times of the occupancy chip area of i-stage shift register, vitual stage shift register occupies chip area and reduces
Expected effect cannot be played for the narrow frameization of display panel.To sum up, when the occupancy domain face of vitual stage shift register
When product is 0.6~0.8 times of the occupancy chip area of i-stage shift register, above structure is imitated with preferable narrow frameization
Fruit.
Certainly, the present invention is not limited to this, in other embodiments, can be according to the specific knot of vitual stage shift register
Structure carries out the setting of its area.Specifically, the length of reduction vitual stage shift register can be passed through in the embodiment of the present invention
And/or width, to reduce the occupancy chip area of vitual stage shift register.
In addition, the driving circuit in the present embodiment may include that primary virtual grade shift register i.e. first order vitual stage is moved
Bit register.As shown in Figure 1, first order vitual stage shift register and N grades of shift registers cascade, and first order displacement is posted
Storage cascades between adjacent two-stage shift register into N grades of shift registers, for example, first order shift register and second
Grade shift register cascade, second level shift register and the cascade of third level shift register.
Wherein, first order vitual stage shift register and N grades of shift register cascades refer to that first order vitual stage shifts
The output end OUT of register is connect with the reset terminal RESET of N grades of shift registers, the output end of N grades of shift registers
OUT is connect with the input terminal SET of first order vitual stage shift register, thus, N grades of shift registers are to first order vitual stage
Shift register provides an input signal, and first order vitual stage shift register provides one to N grades of shift registers and resets letter
Number, to reset to the cascade shift registers at different levels of N grades of shift registers, avoid the output of error signal.
In another embodiment of the embodiment of the present invention, with reference to Fig. 2, Fig. 2 is another kind provided in an embodiment of the present invention
The structural schematic diagram of driving circuit, wherein driving circuit includes two-stage vitual stage shift register, and the displacement of this two-stage vitual stage is posted
Storage is respectively first order vitual stage shift register and second level vitual stage shift register.Wherein, first order vitual stage is moved
Cascaded between bit register and first order shift register, second level vitual stage shift register and N grades of shift registers it
Between cascade, and first order shift register cascades between adjacent two-stage shift register into N grades of shift registers, for example,
First order shift register and the cascade of second level shift register, second level shift register and third level shift register grade
Connection.
Wherein, cascade refers to first order vitual stage between first order vitual stage shift register and first order shift register
The output end OUT of shift register is connect with the input terminal SET of first order shift register, the output of first order shift register
End OUT is connect with the reset terminal RESET of first order vitual stage shift register, thus, first order shift register is to the first order
Vitual stage shift register provides an input signal, and first order vitual stage shift register provides one to first order shift register
Reset signal, to be reset to the cascade shift registers at different levels of first order shift register, avoid mistake in reverse scan
The output of error signal；Cascade refers to second level vitual stage between second level vitual stage shift register and N grades of shift registers
The output end OUT of shift register is connect with the reset terminal RESET of N grades of shift registers, the output of N grades of shift registers
End OUT is connect with the input terminal SET of second level vitual stage shift register, thus, N grades of shift registers are virtual to the second level
Grade shift register provides an input signal, and second level vitual stage shift register provides one to N grades of shift registers and resets
Signal, to be reset to the cascade shift registers at different levels of N grades of shift registers, avoid wrong letter in forward scan
Number output.
Alternatively, Fig. 3 is the structural schematic diagram of another driving circuit provided in an embodiment of the present invention with reference to Fig. 3, wherein
It is cascaded between first order vitual stage shift register and N-1 grades of shift registers, second level vitual stage shift register and N
It is cascaded between grade shift register, and first order shift register all odd level shift LDs into N grades of shift registers
It is mutually cascaded between adjacent two-stage shift register in device, for example, first order shift register and third level shift register grade
Connection, third level shift register and level V shift register cascade；And adjacent two-stage in all even level shift registers
It is mutually cascaded between shift register, for example, second level shift register and fourth stage shift register cascade, fourth stage displacement
Register and the 6th grade of shift register cascade.
Similarly, cascade refers to that the first order is virtual between first order vitual stage shift register and N-1 grades of shift registers
The output end OUT of grade shift register is connect with the reset terminal RESET of N-1 grades of shift registers, N-1 grades of shift registers
Output end OUT connect with the input terminal SET of first order vitual stage shift register；Second level vitual stage shift register and
Cascade refers to the output end OUT and N grades of shift registers of second level vitual stage shift register between N grades of shift registers
Reset terminal RESET connection, the output end OUT of N grades of shift registers and the input terminal SET of second level vitual stage shift register
Connection, thus, N-1 grades of shift registers provide an input signal to first order vitual stage shift register, and the first order is virtual
Grade shift register provides a reset signal to N-1 grades of shift registers, to be moved to N-1 grades in forward scan
The cascade shift registers at different levels of bit register are reset, and avoid the output of error signal；Similarly, N grades of shift registers to
Second level vitual stage shift register provides an input signal, and second level vitual stage shift register is to N grades of shift registers
One reset signal is provided, to be reset to the cascade shift registers at different levels of N grades of shift registers in forward scan,
Avoid the output of error signal.
In a further embodiment of the embodiment of the present invention, with reference to Fig. 4, Fig. 4 be it is provided in an embodiment of the present invention another
The structural schematic diagram of driving circuit, wherein driving circuit includes level Four vitual stage shift register, and the displacement of this level Four vitual stage is posted
Storage is respectively first order vitual stage shift register, second level vitual stage shift register, third level vitual stage shift LD
Device and fourth stage vitual stage shift register.Wherein, between first order vitual stage shift register and first order shift register
Cascade, cascades, third level vitual stage shift register between second level vitual stage shift register and second level shift register
It cascades between N-1 grades of shift registers, is cascaded between fourth stage vitual stage shift register and N grades of shift registers,
And first order shift register adjacent two-stage shift register in all odd level shift registers into N grades of shift registers
Between mutually cascade, and, mutually cascaded between adjacent two-stage shift register in all even level shift registers.
Similarly, cascade refers to first order vitual stage between first order vitual stage shift register and first order shift register
The output end OUT of shift register is connect with the input terminal SET of first order shift register, the output of first order shift register
End OUT is connect with the reset terminal RESET of first order vitual stage shift register；Second level vitual stage shift register and the second level
Cascade refers to the defeated of the output end OUT of second level vitual stage shift register and second level shift register between shift register
Enter SET is held to connect, the output end OUT of second level shift register and the reset terminal RESET of second level vitual stage shift register
Connection；Cascade refers to that the displacement of third level vitual stage is posted between third level vitual stage shift register and N-1 grades of shift registers
The output end OUT of storage is connect with the reset terminal RESET of N-1 grades of shift registers, the output end of N-1 grades of shift registers
OUT is connect with the input terminal SET of third level vitual stage shift register；Fourth stage vitual stage shift register and N grades of displacements
Cascade refers to the reset terminal of the output end OUT and N grades of shift registers of fourth stage vitual stage shift register between register
The output end OUT of RESET connection, N grades of shift registers is connect with the input terminal SET of fourth stage vitual stage shift register.
To which first order shift register provides an input signal, the displacement of first order vitual stage to first order vitual stage shift register
Register provides a reset signal to first order shift register, so as in reverse scan, to first order shift register
Cascade shift register at different levels is reset, and avoids the output of error signal；Similarly, second level shift register is empty to the second level
Quasi- grade shift register provides an input signal, and second level vitual stage shift register provides one to second level shift register and answers
Position signal, to be reset to the cascade shift registers at different levels of second level shift register, avoid mistake in reverse scan
The output of signal；N-1 grades of shift registers provide an input signal to third level vitual stage shift register, and the third level is virtual
Grade shift register provides a reset signal to N-1 grades of shift registers, to be moved to N-1 grades in forward scan
The cascade shift registers at different levels of bit register are reset, and avoid the output of error signal；N grades of shift registers are empty to the fourth stage
Quasi- grade shift register provides an input signal, and fourth stage vitual stage shift register provides one to N grades of shift registers and answers
Position signal, to be reset to the cascade shift registers at different levels of N grades of shift registers, avoid mistake in forward scan
The output of signal.
It should be noted that in the present embodiment, forward scan refers in shift register group, signal is shifted from the first order
The case where register is to N grades of shift register propagations；Reverse scan refers in shift register group that signal is shifted from N grades
The case where register is to first order shift register propagation.And in the case where forward scan, above-mentioned shift register and virtual
The input terminal SET of grade shift register is to receive input signal, and reset terminal RESET is to receive reset signal；Reversely sweeping
In the case where retouching, the reset terminal RESET of above-mentioned shift register and vitual stage shift register is inputted to receive input signal
Hold SET to receive reset signal.
In any of the above-described embodiment, i-stage shift register and the connection between its cascade shift register
Relationship are as follows: the output end OUT of i-stage shift register is connect with the input terminal SET of the cascade shift register of its next stage, under
The output end OUT of the cascade shift register of level-one is connect with the reset terminal RESET of i-stage shift register, meanwhile, i-stage
The output end OUT of shift register is connect with the reset terminal RESET of the cascade shift register of its upper level, and upper level is cascade
The output end OUT of shift register is connect with the input terminal SET of i-stage shift register.
In addition, vitual stage shift register and first order shift register in the present embodiment are to N grades of shift LDs
The clock signal terminal CK of device passes through the clock signal output terminal connection of the driving chip of signal wire CK1 and display device, virtually
Another clock signal terminal CKB of grade shift register and first order shift register to N grades of shift registers passes through letter
Another clock signal output terminal of number line CKB and driving chip connects.
Driving circuit provided in this embodiment, including at least one level vitual stage shift register and with vitual stage displacement post
The shift register group that storage is electrically connected in cascaded fashion, the shift register group include first order shift register to N grades
Shift register, due to the occupancy domain face for occupying chip area and being less than i-stage shift register of vitual stage shift register
Therefore product can reduce the frame area of display device relatively, meet the narrow frame demand of display device.
The another aspect of the embodiment of the present invention provides a kind of array substrate, is that the embodiment of the present invention mentions with reference to Fig. 5, Fig. 5
A kind of structural schematic diagram of the array substrate supplied.As shown in figure 5, the array substrate include display area 1 and be located at display area 1
The frame region 2 of periphery, frame region 2, which has to display area 1, provides the gate driving circuit 3 of grid signal, which drives
Dynamic circuit 3 is the driving circuit that any of the above-described embodiment provides.Specifically, gate driving circuit 3 passes through grid line 30 to picture
Plain unit 4 provides grid signal.
The another aspect of the embodiment of the present invention provides a kind of display device, which includes array as described above
Substrate.
Array substrate and display device provided in an embodiment of the present invention, driving circuit therein include at least one level vitual stage
Shift register and the shift register group being electrically connected in cascaded fashion with vitual stage shift register, the shift register group
Including first order shift register to N grades of shift registers, since the occupancy chip area of vitual stage shift register is less than
Therefore the occupancy chip area of i-stage shift register can reduce the frame area of display device relatively, meet display dress
The narrow frame demand set.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (7)
1. a kind of driving circuit characterized by comprising
At least one level vitual stage shift register；
And the shift register group being electrically connected in cascaded fashion with the vitual stage shift register；
Wherein, the shift register group includes first order shift register to N grades of shift registers, and the vitual stage is moved
0.6~0.8 times for occupying the occupancy chip area that chip area is i-stage shift register of bit register, including endpoint value,
N is the integer not less than 2, and i is the positive integer no more than N；
Driving circuit institute planar, the vitual stage shift register and the shift register are arranged along first direction
Column, the vitual stage shift register are less than the i-stage shift register along described first along the length of the first direction
The length in direction, and the quantity of the transistor inside the vitual stage shift register in said first direction is less than described the
The quantity of the transistor of the inside of i grades of shift registers in said first direction；
And the length of the vitual stage shift register in a second direction is less than the i-stage shift register along described second
The length in direction, and the quantity of the transistor inside the vitual stage shift register in this second direction is less than described the
The quantity of the transistor of the inside of i grades of shift registers in this second direction；
Wherein, the first direction and the second direction are vertical.
2. driving circuit according to claim 1, which is characterized in that the driving circuit includes that the displacement of primary virtual grade is posted
Storage is first order vitual stage shift register；
Wherein, the first order vitual stage shift register and the N grades of shift registers cascade, and the first order shifts
Register cascades between adjacent two-stage shift register into N grades of shift registers.
3. driving circuit according to claim 1, which is characterized in that the driving circuit includes that the displacement of two-stage vitual stage is posted
Storage, respectively first order vitual stage shift register and second level vitual stage shift register；
Wherein, it is cascaded between the first order vitual stage shift register and first order shift register, the second level is virtual
It is cascaded between grade shift register and N grades of shift registers, and the first order shift register is to N grades of shift registers
In cascade between adjacent two-stage shift register.
4. driving circuit according to claim 1, which is characterized in that the driving circuit includes that the displacement of two-stage vitual stage is posted
Storage, respectively first order vitual stage shift register and second level vitual stage shift register；
Wherein, it is cascaded between the first order vitual stage shift register and N-1 grades of shift registers, the second level is virtual
It is cascaded between grade shift register and N grades of shift registers, and the first order shift register is to N grades of shift registers
In mutually cascaded between adjacent two-stage shift register in all odd level shift registers, and, all even levels displacements are posted
It is mutually cascaded between adjacent two-stage shift register in storage.
5. driving circuit according to claim 1, which is characterized in that the driving circuit includes that the displacement of level Four vitual stage is posted
Storage, respectively first order vitual stage shift register, second level vitual stage shift register, third level vitual stage shift LD
Device and fourth stage vitual stage shift register；
Wherein, it is cascaded between the first order vitual stage shift register and first order shift register, the second level is virtual
It is cascaded between grade shift register and second level shift register, the third level vitual stage shift register and N-1 grades of shiftings
It cascades between bit register, is cascaded between the fourth stage vitual stage shift register and N grades of shift registers, and described
Level-one shift register is into N grades of shift registers in all odd level shift registers between adjacent two-stage shift register
Mutually cascade, and, it is mutually cascaded between adjacent two-stage shift register in all even level shift registers.
6. a kind of array substrate, the gate driving circuit including display area and positioned at the display area periphery, the grid
Pole driving circuit provides grid signal to the display area, wherein the gate driving circuit is that claim 1-5 is any one
Driving circuit described in.
7. a kind of display device, which is characterized in that the display device includes array substrate as claimed in claim 6.
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| CN105719593A (en) * | 2016-04-29 | 2016-06-29 | 上海中航光电子有限公司 | Grid electrode driving circuit, display panel and electronic equipment |
| KR20180067948A (en) * | 2016-12-13 | 2018-06-21 | 엘지디스플레이 주식회사 | Shift register and gate driving circuit including the same |
| CN113808517B (en) * | 2018-10-18 | 2023-08-08 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109243399B (en) * | 2018-11-22 | 2021-02-19 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN109507839A (en) * | 2018-12-27 | 2019-03-22 | 惠科股份有限公司 | Array substrate and display device |
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