CN108665845B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN108665845B CN108665845B CN201810689236.9A CN201810689236A CN108665845B CN 108665845 B CN108665845 B CN 108665845B CN 201810689236 A CN201810689236 A CN 201810689236A CN 108665845 B CN108665845 B CN 108665845B
- Authority
- CN
- China
- Prior art keywords
- clock
- clock signal
- signal line
- shift register
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0252—Improving the response speed
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises an array substrate; a plurality of scanning lines extending along a first direction on the array substrate; the first cascaded shift register units are electrically connected with the odd-numbered scanning lines; the plurality of cascaded second shift register units are electrically connected with the even-numbered scanning lines; a first clock signal line and a third clock signal line; a first clock shift circuit group; the input end of the first clock shift circuit group is connected with the first clock signal line and the third clock signal line, and the output end of the first clock shift circuit group is connected with the clock signal input end of the second shift register unit. The display device comprises the display panel. The invention can achieve the effect of signal synchronization and stabilization, and improve the display quality, thereby avoiding the problem of poor picture display quality caused by signal delay, and reducing the proportion of the width occupied by the signal lines in the non-display area of the display panel, thereby realizing the narrow frame of the display panel.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the continuous development of science and technology, more and more electronic devices with display functions are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present. The display panel is a main component of the electronic device that realizes a display function. The related art display panel generally includes: a display area and a non-display area surrounding the display area, the non-display area being provided with some driving circuits, signal lines, and the like. However, with the development of display technologies, the number of integrated functions in the display panel is increased, the number of signal lines in the corresponding display panel is also increased, and the size of the driving circuit chip is decreased, so that the proportion of the width occupied by the signal lines in the display panel is increased, the reduction of the frame width of the display panel is limited, and the development of the narrow frame of the display panel is not facilitated.
Therefore, it is an urgent need to provide a display panel and a display device, which can reduce the width of the non-display area signal lines, realize a narrow frame of the display panel, and avoid the influence of signal delay on the display function.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device to solve the problems in the prior art.
The invention discloses a display panel, comprising: an array substrate; a plurality of scanning lines extending along a first direction on the array substrate; the first cascaded shift register units are electrically connected with the odd-numbered scanning lines; the plurality of cascaded second shift register units are electrically connected with the even-numbered scanning lines; a first clock signal line and a third clock signal line; a first clock shift circuit group; the clock signal input end of the first shift register unit is respectively connected with the first clock signal line and the third clock signal line; the input end of the first clock shift circuit group is connected with the first clock signal line and the third clock signal line, and the output end of the first clock shift circuit group is connected with the clock signal input end of the second shift register unit.
The invention also discloses a display device which comprises the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the first clock shift circuit group is used for converting clock signals of the first clock signal line and the third clock signal line into clock signals required for driving the second shift register unit and inputting the clock signals through the clock signal input end of the second shift register unit; therefore, clock signals of the first shift register unit and the second shift register unit can be input from the same first clock signal line and the same third clock signal line, the clock signal input end of the second shift register unit does not need to be additionally connected with other clock signal lines, the effects of signal synchronization and signal stability can be achieved, the display quality is improved, the problem of poor picture display quality caused by signal delay is avoided, the proportion of the occupied width of the signal lines in the non-display area of the display panel can be reduced simultaneously, the frame width of the display panel is reduced, and the narrow frame of the display panel is further realized.
Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first clock shift circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 6 is a timing diagram of a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a shift register according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, where the display panel includes:
an array substrate 00;
a plurality of scanning lines G extending in a first direction X on the array substrate 00;
a plurality of cascade first shift register units 1 electrically connected to the odd-numbered scanning lines G;
a plurality of cascade second shift register units 2 electrically connected to the even-numbered scanning lines G;
a first clock signal line CKV1, a third clock signal line CKV 3;
a first clock shift circuit group 01;
the clock signal input end of the first shift register unit 1 is respectively connected with the first clock signal line CKV1 and the third clock signal line CKV 3;
the input end of the first clock shift circuit group 01 is connected to the first clock signal line CKV1 and the third clock signal line CKV3, and the output end is connected to the clock signal input end of the second shift register unit 2.
Specifically, in this embodiment, the plurality of cascaded first shift register units 1 of the display panel are electrically connected to odd-numbered scan lines G, and the plurality of cascaded second shift register units 2 are electrically connected to even-numbered scan lines G, where the odd-numbered scan lines are scan lines numbered 1, 2, 3, and 4 … … n sequentially along the direction in which the scan lines are arranged, and then the scan lines numbered as odd numbers are scan lines of odd rows, and the scan lines numbered as even numbers are scan lines of even rows; the display panel adopts the staggered driving mode, so that signals of driving scanning lines G at two sides of the display panel are not interfered with each other and are staggered in time, and the purpose of sequential driving is achieved. The input end of the first clock shift circuit group 01 is connected with the first clock signal line CKV1 and the third clock signal line CKV3, the output end is connected with the clock signal input end of the second shift register unit 2, the first clock shift circuit group 01 is used for converting the clock signals of the first clock signal line CKV1 and the third clock signal line CKV3 into the clock signals required for driving the second shift register unit 2 and inputting the clock signals through the clock signal input end of the second shift register unit 2, the design can lead the clock signals of the first shift register unit 1 and the second shift register unit 2 to be input from the same first clock signal line CKV1 and the same third clock signal line CKV3, and the clock signal input end of the second shift register unit 2 does not need to be additionally connected with other clock signal lines, the effects of signal synchronization and stabilization can be achieved, and the display quality is improved, thereby avoiding the problem of poor picture display quality caused by signal delay.
In some optional embodiments, please refer to fig. 2, fig. 2 is a schematic structural diagram of another display panel provided in the embodiments of the present invention, in which the display panel includes a first region 11 and a second region 12;
the first area 11 comprises a first edge 10, the first edge 10 is recessed towards the second area 12, so that the first area 11 forms a notch 100, and because the notch 100 has no sub-pixels, the number of sub-pixels in any row in the first area 11 is less than that in any row in the second area 12; the first region 11 includes a first display area AA1, a second display area AA2, and the first display area AA1 and the second display area AA2 are respectively located at both sides of the notch 100 along the first direction X; the second area 12 comprises a third display area AA 3;
the scanning lines G include a first scanning line G1, a second scanning line G2, and a third scanning line G3, the first scanning line G1 is located in the first display area AA1, the second scanning line G2 is located in the second display area AA2, and the third scanning line G3 is located in the third display area AA 3;
the display panel further includes a non-display area BB disposed around the first display area AA1, the second display area AA2, and the third display area AA 3; the non-display area BB comprises a first non-display area BB1 and a second non-display area BB 2;
in the first direction X, the first non-display area BB1 is located on a side of the first display area AA1 away from the notch 100, and the second non-display area BB2 is located between the notch 100 and the first display area AA 1;
the first shift register unit 1 is located in the first non-display area BB1 and is connected to the first scan line G1 of the odd-numbered row and the third scan line G3 of the odd-numbered row;
the second shift register unit 2 is located in the second non-display area BB2 and is connected to the first scan lines G1 of even rows.
In this embodiment, the first clock shift circuit group 01 is applied to the display panel with the special-shaped notch shown in fig. 2, which not only can bring the function of the first clock shift circuit group 01 shown in fig. 1, but also the principle thereof is not described herein again, and reference can be made to the description of the embodiment shown in fig. 1, so that the effect of signal synchronization and stabilization can be achieved, the display quality is improved, and the problem of poor image display quality caused by signal delay is avoided, and for example, the first shift register unit 1 of the first non-display area BB1 needs to be connected to the third non-display area BB3 through a pull line to access the clock signal for driving the even-numbered rows of the first scan lines G1, so that the proportion of the width occupied by the non-display area signal lines corresponding to the notch 100 is reduced, thereby reducing the frame width of the display panel with the special-shaped notch, and realizing a narrow frame of the display panel.
In some alternative embodiments, please continue to refer to fig. 2, in the present embodiment, the first scan line G1 is not connected to the second scan line G2.
The present embodiment further defines that the scanning lines G on both sides of the notch of the special-shaped notched display panel are not connected in the first direction X, and further explains the arrangement structure of the scanning lines G for the special-shaped notched display panel.
In some optional embodiments, please refer to fig. 3, fig. 3 is a schematic structural diagram of another display panel provided in the embodiments of the present invention, in the present embodiment, the first area 11 further includes a fifth non-display area BB 5;
the fifth non-display area BB5 is located on the side of the first display area AA1 away from the third display area AA3 in the second direction Y, the first clock shift circuit group 01 is located in the fifth non-display area BB5, and the first clock shift circuit group 01 includes a first clock shift circuit 011 and a second clock shift circuit 012.
In this embodiment, the fifth non-display area BB5 of the first clock shift circuit group 01 disposed on the display panel is further described for converting the clock signals of the first clock signal line CKV1 and the third clock signal line CKV3 into the clock signals required for driving the second shift register unit 2, so that the clock signals of the first shift register unit 1 and the second shift register unit 2 are input from the same first clock signal line CKV1 and the same third clock signal line CKV 3. Meanwhile, it is specifically described that the first clock shift circuit group 01 includes a first clock shift circuit 011 and a second clock shift circuit 012, which are respectively used for converting the clock signals of the first clock signal line CKV1 and the third clock signal line CKV3 into the clock signals required for driving the second shift register unit 2, and inputting the clock signals through two clock signal input terminals of the second shift register unit 2.
In some optional embodiments, please continue to refer to fig. 2, in the present embodiment, the non-display area BB further includes a third non-display area BB3 and a fourth non-display area BB 4;
in the first direction X, the fourth non-display area BB4 is located on the side of the second display area AA2 away from the notch 100, and the third non-display area BB3 is located between the notch 100 and the second display area AA 2;
a plurality of cascaded third shift register units 3, wherein the third shift register units 3 are located in the third non-display area BB3 and are connected to the second scanning lines G2 of the odd-numbered rows;
a plurality of cascade-connected fourth shift register units 4, the fourth shift register units 4 being located in the fourth non-display area BB4 and connected to the second scanning lines G2 of the even-numbered rows and the third scanning lines G3 of the even-numbered rows;
a second clock signal line CKV2, a fourth clock signal line CKV 4;
a second clock shift circuit group 02;
the clock signal input end of the fourth shift register unit 4 is connected to the second clock signal line CKV2 and the fourth clock signal line CKV4, respectively;
the input terminals of the second clock shift circuit group 02 are connected to the second clock signal line CKV2 and the fourth clock signal line CKV4, respectively, and the output terminals are connected to the clock signal input terminals of the third shift register unit 3.
In this embodiment, the second clock shift circuit group 02 is applied to the display panel with notches in the abnormal shape shown in fig. 2, the plurality of cascaded first shift register cells 3 of the display panel are connected to the second scan line G2 in the odd-numbered rows, the plurality of cascaded second shift register cells 4 are connected to the second scan line G2 in the even-numbered rows and the third scan line G3 in the even-numbered rows, the input end of the second clock shift circuit group 02 is connected to the second clock signal line CKV2 and the fourth clock signal line CKV4, the output end is connected to the clock signal input end of the third shift register cell 3, the second clock shift circuit group 02 is configured to convert the clock signals of the second clock signal line CKV2 and the fourth clock signal line CKV4 into the clock signals required for driving the third shift register cell 3 and input through the clock signal input end of the third shift register cell 3, the clock signals of the third shift register unit 3 and the fourth shift register unit 4 can be input from the same second clock signal line CKV2 and the same fourth clock signal line CKV4, and the clock signal input end of the third shift register unit 3 is not required to be additionally connected with other clock signal lines, so that the signal synchronization and stabilization effects are achieved, the display quality is improved, the problem of poor picture display quality caused by signal delay can be avoided, the proportion of the occupied width of the non-display area signal lines of the display panels on the two sides of the notch can be reduced simultaneously, the frame width of the display panel with the notch in the special shape is reduced, and the narrow frame of the display panel is further realized.
In some optional embodiments, please continue to refer to fig. 3, in the present embodiment, the first area 11 further includes a sixth non-display area BB 6;
the sixth non-display area BB6 is located on the side of the second display area AA2 away from the third display area AA3 in the second direction Y, the second clock shift circuit group 02 is located in the sixth non-display area BB6, and the second clock shift circuit group 02 includes a third clock shift circuit 021 and a fourth clock shift circuit 022.
In this embodiment, a sixth non-display BB6 where the second clock shift circuit group 02 is disposed on the display panel is further described, which is used to convert the clock signals of the second clock signal line CKV2 and the fourth clock signal line CKV4 into the clock signals required for driving the third shift register unit 3, so that the clock signals of the third shift register unit 3 and the fourth shift register unit 4 are inputted from the same second clock signal line CKV2 and the same fourth clock signal line CKV 4. Meanwhile, it is specifically described that the second clock shift circuit group 02 includes a third clock shift circuit 021 and a fourth clock shift circuit 022, which are respectively used for converting the clock signals of the second clock signal line CKV2 and the fourth clock signal line CKV4 into clock signals required for driving the third shift register unit 3, and the clock signals are input through two clock signal input terminals of the third shift register unit 3.
In some optional embodiments, please refer to fig. 4, fig. 4 is a schematic structural diagram of a first clock shift circuit 011 according to an embodiment of the present invention, in which the first clock shift circuit 011 includes a first input terminal 1, a second input terminal 2, a first switch transistor T1, a second switch transistor T2, a first voltage signal terminal VGL, a second voltage signal terminal VGH, an inverter 0111, a clock inverter 0112, and a first output terminal output;
a gate of the first switching transistor T1 is connected to the first input terminal 1, a source thereof is connected to the first voltage signal terminal VGL, and a drain thereof is connected to the first terminal of the clock inverter 0112;
the second end of the clock inverter 0112 is connected with the first output end output, and the third end of the clock inverter 0112 is connected with the first input end 1;
a first end of the inverter 0111 is connected with the first input end 1, and a second end of the inverter 0111 is connected with a fourth end of the clock inverter 0112;
the gate of the second switching transistor T2 is connected to the second input terminal input2, the source is connected to the second voltage signal terminal VGH, and the drain is connected to the first terminal of the clock inverter 0112.
In this embodiment, a specific circuit structure of the first clock shift circuit 011 used in the above embodiments is further described;
the first input terminal 1 is connected to the gate of the first switch transistor T1, and is used to control the on/off of the first switch transistor T1, and when turned on, transmits the signal of the first voltage signal terminal VGL to the first terminal of the clock inverter 0112;
the second input terminal 2 is connected to the gate of the second switch transistor T2, and is used to control the on/off of the second switch transistor T2, and when turned on, transmits the signal of the second voltage signal terminal VGH to the first terminal of the clock inverter 0112;
the first end of the inverter 0111 is opposite to the second end of the inverter 0111 in potential, that is, if the first end of the inverter 0111 is inputted with a high potential, the second end of the inverter 0111 is outputted with a low potential, and vice versa;
the clock inverter 0112 has two working states, namely if the third end of the clock inverter 0112 is a low potential and the fourth end of the clock inverter 0112 is a high potential, the two working states are equivalent to an inverter, namely the first end of the clock inverter 0112 is opposite to the second end of the clock inverter 0112 in potential; if the third terminal of the clock inverter 0112 is at a high potential and the fourth terminal of the clock inverter 0112 is at a low potential, the output of the second terminal of the clock inverter 0112 is independent of the first terminal of the clock inverter 0112, and the second terminal of the clock inverter 0112 is equivalent to a suspended open circuit.
In some optional embodiments, please refer to fig. 4, in the present embodiment, the first clock shift circuit 011, the second clock shift circuit 012, the third clock shift circuit 021 and the fourth clock shift circuit 022 have the same structure, that is, the first clock shift circuit 011, the second clock shift circuit 012, the third clock shift circuit 021 and the fourth clock shift circuit 022 have the same circuit connection structure, so as to realize the same function of converting the clock signal.
In some alternative embodiments, with reference to fig. 4, in the present embodiment, the first switch transistor T1 and the second switch transistor T2 are both N-type switch transistors.
In this embodiment, it is further limited that the first switch transistor T1 and the second switch transistor T2 are both N-type switch transistors, and when the gate of the first switch transistor T1 and the gate of the second switch transistor T2 input high-level signals, the first switch transistor T1 and the second switch transistor T2 are turned on, otherwise, the first switch transistor T1 and the second switch transistor T2 are turned off.
It should be noted that, the present embodiment is only to exemplify the types of the first switch transistor T1 and the second switch transistor T2, and the first switch transistor T1 and the second switch transistor T2 may also be P-type switch transistors, and those skilled in the art may adjust the circuit of the present embodiment according to different types of switch transistors according to actual situations to implement the same function of converting signals of the circuit, and the circuit adjustment known to those skilled in the art is within the protection scope of the embodiment of the present invention.
In some optional embodiments, please refer to fig. 4, in the present embodiment, the first voltage signal input from the first voltage signal terminal VGL is at a low level, and the second voltage signal input from the second voltage signal terminal VGH is at a high level.
In this embodiment, it is further limited that the first voltage signal input from the first voltage signal terminal VGL is at a low potential, and the second voltage signal input from the second voltage signal terminal VGH is at a high potential, that is, the first terminal of the clock inverter 0112 can input different high potential or low potential signals by controlling the on/off of the first switch transistor T1 and the second switch transistor T2, so that the first output terminal output connected to the second terminal of the clock inverter 0112 outputs a required signal.
In some optional embodiments, please refer to fig. 5, fig. 5 is a schematic structural diagram of another display panel provided in the embodiments of the present invention, in order to clearly illustrate the circuit connection structure of the present embodiment, the notch and the array substrate of the display panel in fig. 5 are not illustrated, and other structures not illustrated of the display panel of the present embodiment can be understood by referring to fig. 3; in this embodiment, the first input end 1 of the first clock shift circuit 011 is connected to the first clock signal line CKV1, the second input end 2 is connected to the third clock signal line CKV3, and the first output end output is connected to one clock signal input end of the second shift register unit 2;
the first input terminal input1 of the second clock shift circuit 012 is connected to the third clock signal line CKV3, the second input terminal input2 is connected to the first clock signal line CKV1, and the first output terminal output is connected to the other clock signal input terminal of the second shift register unit 2;
the first input terminal input1 of the third clock shift circuit 021 is connected to the second clock signal line CKV2, the second input terminal input2 is connected to the fourth clock signal line CKV4, and the first output terminal output is connected to one clock signal input terminal of the third shift register unit 3;
the first input terminal input1 of the fourth clock shift circuit 022 is connected to the fourth clock signal line CKV4, the second input terminal input2 is connected to the second clock signal line CKV2, and the first output terminal output is connected to the other clock signal input terminal of the third shift register unit 3.
In this embodiment, how the first clock shift circuit 011, the second clock shift circuit 012, the third clock shift circuit 021 and the fourth clock shift circuit 022 are connected to the clock signal lines to complete the conversion of the first clock signal line CKV1 and the third clock signal line CKV3 into the clock signals required by the second shift register unit 2 and identical to the clock signals output by the second clock signal line CKV2 and the fourth clock signal line CKV4 is further described.
Specifically, to explain the technical solution of the present embodiment more clearly, please refer to fig. 6, fig. 6 is a timing diagram corresponding to the first clock signal line CKV1, the second clock signal line CKV2, the third clock signal line CKV3 and the fourth clock signal line CKV4 according to the embodiment of the present invention, and the operation principle of the clock shift circuit is further explained with the timing diagram shown in fig. 6.
As shown in fig. 6, the timing diagram can be divided into seven time periods t0-t6 for explanation, in this embodiment, for convenience of explanation, the high potential is defined as 1, and the low potential is defined as 0, taking the connection structure of the first clock shift circuit 011 as an example, if the first input terminal input1 of the first clock shift circuit 011 is connected to the first clock signal line CKV1, the second input terminal input2 is connected to the third clock signal line CKV3, and the first output terminal of the first clock shift circuit 011 is output1, then:
at stage T0, input1 is 0, input2 is 0, and although the clock inverter 0112 is turned on, the first switching transistor T1 and the second switching transistor T2 are both turned off, and no signal is input, so output1 is 0;
at stage T1, input1 is 1, input2 is 0, although the first switch transistor T1 is turned on, and the low voltage level 0 of the first voltage signal terminal VGL is transmitted to the first terminal of the clock inverter 0112, the clock inverter 0112 is opened, and output1 is still 0;
at stage t2, input1 is 0, input2 is 0, and clock inverter 0112 is turned on, and since the first end of clock inverter 0112 is 0 at this time, output1 is 1;
at stage T3, input1 is 0, input2 is 1, the clock inverter 0112 is turned on, the first switch transistor T1 is turned off, the second switch transistor T2 is turned on, the high potential 1 of the second voltage signal terminal VGH is transmitted to the first terminal of the clock inverter 0112, the first terminal of the clock inverter 0112 is pulled up to 1, and therefore output1 is 0;
at stage T4, input1 is 0, input2 is 0, clock inverter 0112 is turned on, first switch transistor T1 and second switch transistor T2 are both turned off, and since the first end of clock inverter 0112 is 1 at this time, output1 is 0;
at stage T5, when input1 is 1, input2 is 0, the first switch transistor T1 is turned on, and the second switch transistor T2 is turned off, at this time, the first end of the clock inverter 0112 is pulled low to 0 by the first voltage signal terminal VGL, but the clock inverter 0112 is opened, so output1 is 0;
at stage T6, input1 is 0, input2 is 0, clock inverter 0112 is turned on, first switch transistor T1 and second switch transistor T2 are both turned off, and since the first end of clock inverter 0112 is 0 at this time, output1 is 1;
the cycle continues as follows.
As can be seen from the above, the signals of the first clock signal line CKV1 and the third clock signal line CKV3 are converted into clock signals in accordance with the signal output from the second clock signal line CKV2 by the first clock shift circuit 011 for connection to one clock signal input terminal of the second shift register unit 2.
It should be noted that, in this embodiment, no details are given to the working principle of the second clock shift circuit 012, the third clock shift circuit 021, and the fourth clock shift circuit 022, and those skilled in the art can combine the description of the first clock shift circuit 011 with the timing diagram shown in fig. 6, where the first output terminal of the second clock shift circuit 012 is output2, the first output terminal of the third clock shift circuit 021 is output3, and the first output terminal of the fourth clock shift circuit 022 is output4, so that it can be known that the second clock shift circuit 012 converts the signals of the third clock signal line CKV3 and the first clock signal line CKV1 into a clock signal consistent with the signal output by the fourth clock signal line CKV4, that is, the signal output by output2, and is used for being connected to another clock signal input terminal of the second shift register unit 2; the third clock shift circuit 021 converts the signals of the second clock signal line CKV2 and the fourth clock signal line CKV4 into a clock signal consistent with the signal output by the first clock signal line CKV1, namely, a signal output by an output3, and is used for being connected with one clock signal input end of the third shift register unit 3; the fourth clock shift circuit 022 converts the signals of the fourth clock signal line CKV4 and the second clock signal line CKV2 into a clock signal identical to the signal output from the third clock signal line CKV3, i.e., a signal output from an output4, and is used for connection to the other clock signal input terminal of the third shift register unit 3.
In some alternative embodiments, please refer to fig. 5 and fig. 7 in combination, fig. 7 is a schematic structural diagram of a shift register according to an embodiment of the present invention, in this embodiment,
the first shift register unit 1, the second shift register unit 2, the third shift register unit 3 and the fourth shift register unit 4 comprise the same shift register;
the shift register comprises a first signal output end OUT1, a second signal output end OUT2, a signal input end STV, a first clock signal input end CLK1 and a second clock signal input end CLK 2;
the first signal output end OUT1 of each stage of shift register is connected with the scanning line G;
the second signal output end OUT2 of each stage of shift register is connected with the signal input end STV of the next stage of shift register;
the first clock signal input terminal CLK1 of the first shift register unit 1 of the odd-numbered stage is connected to the third clock signal line CKV3, and the second clock signal input terminal CLK2 is connected to the first clock signal line CKV 1; the first clock signal input terminal CLK1 of the first shift register unit 1 of the even-numbered stage is connected to the first clock signal line CKV1, and the second clock signal input terminal CLK2 is connected to the third clock signal line CKV 3;
the first clock signal input terminal CLK1 of the second shift register unit 2 of the odd-numbered stage is connected to the first output terminal output of the second clock shift circuit 012, and the second clock signal input terminal CLK2 is connected to the first output terminal output of the first clock shift circuit 011; the first clock signal input terminal CLK1 of the second shift register unit 2 of the even-numbered stage is connected to the first output terminal output of the first clock shift circuit 011, and the second clock signal input terminal CLK2 is connected to the first output terminal output of the second clock shift circuit 012;
the first clock signal input terminal CLK1 of the third shift register unit 3 of the odd-numbered stage is connected to the first output terminal output of the fourth clock shift circuit 022, and the second clock signal input terminal CLK2 is connected to the first output terminal output of the third clock shift circuit 021; the first clock signal input terminal CLK1 of the third shift register unit 3 of the even-numbered stage is connected to the first output terminal output of the third clock shift circuit 021, and the second clock signal input terminal CLK2 is connected to the first output terminal output of the fourth clock shift circuit 022;
the first clock signal input terminal CLK1 of the fourth shift register unit 4 of the odd-numbered stage is connected to the fourth clock signal line CKV4, and the second clock signal input terminal CLK2 is connected to the second clock signal line CKV 2; the first clock signal input terminal CLK1 of the fourth shift register unit 4 of the even-numbered stage is connected to the second clock signal line CKV2, and the second clock signal input terminal CLK2 is connected to the fourth clock signal line CKV 4.
In this embodiment, a specific connection structure of four shift register units, four clock signal lines, and four clock shift circuits is further explained, and it should be noted that this embodiment only discloses the above connection structure, but is not limited to this structure, and may also be other structures known to those skilled in the art, and this embodiment is not described herein again.
In some alternative embodiments, please continue to refer to fig. 5 and fig. 7, in this embodiment, the signal input terminal STV of the first stage shift register inputs the start shift signal.
In this embodiment, the signal input terminal STV of the first stage shift register inputs the start shift signal, and is used to transmit the start shift signal provided by the driving chip on the display panel to the shift register.
In some alternative embodiments, with continuing reference to fig. 5 and fig. 7, in this embodiment, the shift register further includes a reset terminal RST, the reset terminal RST is connected to the reset signal line, and the reset terminal RST is used for transmitting the reset signal provided by the driving chip on the display panel to the shift register, so as to implement the reset operation of each shift register unit.
In some alternative embodiments, referring to fig. 6, in the present embodiment, the pulse width L and the period T of the effective pulse signals output from the first clock signal line CKV1, the second clock signal line CKV2, the third clock signal line CKV3 and the fourth clock signal line CKV4 are the same.
Specifically, the falling edge of the effective pulse signal output from the first clock signal line CKV1 is aligned with the rising edge of the effective pulse signal output from the second clock signal line CKV2, the falling edge of the effective pulse signal output from the second clock signal line CKV2 is aligned with the rising edge of the effective pulse signal output from the third clock signal line CKV3, the falling edge of the effective pulse signal output from the third clock signal line CKV3 is aligned with the rising edge of the effective pulse signal output from the fourth clock signal line CKV4, and the falling edge of the effective pulse signal output from the fourth clock signal line CKV4 is aligned with the rising edge of the effective pulse signal output from the first clock signal line CKV 1.
In this embodiment, the widths of the effective pulse signals output by the four clock signal lines are consistent, so that the scanning time intervals of the display panel are consistent, and the effect of stabilizing the driving signals of the scanning lines is achieved.
In some optional embodiments, please refer to fig. 8, where fig. 8 is a schematic structural diagram of a display device 0000 according to an embodiment of the present invention, and the display device 0000 according to the embodiment includes the display panel 000 according to the embodiment of the present invention. The embodiment of fig. 8 only takes a mobile phone as an example to describe the display device 0000, and it should be understood that the display device 0000 provided in the embodiment of the present invention may be other display devices 0000 having a display function, such as a computer, a television, a vehicle-mounted display device, and the present invention is not limited thereto. The display device 0000 provided in the embodiment of the present invention has the beneficial effect of the display panel 000 provided in the embodiment of the present invention, and specific descriptions of the display panel 000 in the above embodiments may be specifically referred to, and this embodiment is not described herein again.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
the input end of the first clock shifting circuit group is connected with a first clock signal line and a third clock signal line, the output end of the first clock shifting circuit group is connected with the clock signal input end of the second shifting register unit, the input end of the second clock shifting circuit group is connected with a second clock signal line and a fourth clock signal line, and the output end of the second clock shifting circuit group is connected with the clock signal input end of the third shifting register unit; the first clock shift circuit group is used for converting clock signals of the first clock signal line and the third clock signal line into clock signals required for driving the second shift register unit and inputting the clock signals through a clock signal input end of the second shift register unit, and the second clock shift circuit group is used for converting clock signals of the second clock signal line and the fourth clock signal line into clock signals required for driving the third shift register unit and inputting the clock signals through a clock signal input end of the third shift register unit; this makes it possible to input the clock signals of the first shift register unit and the second shift register unit from the same first clock signal line and third clock signal line, the clock signals of the third shift register unit and the fourth shift register unit from the same second clock signal line and fourth clock signal line, and the clock signal input end of the second shift register unit and the clock signal input end of the third shift register unit do not need to be additionally connected with other clock signal lines, thereby achieving the effects of signal synchronization and stabilization, improving the display quality, thereby avoiding the problem of poor picture display quality caused by signal delay, reducing the proportion of the width occupied by the signal lines in the non-display area of the display panel at the two sides of the gap, thereby reduce this dysmorphism display panel's of taking the breach frame width, further realize the narrow frame of display panel.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (16)
1. A display panel, comprising:
an array substrate;
a plurality of scanning lines extending along a first direction on the array substrate;
the first cascaded shift register units are electrically connected with the scanning lines in the odd rows;
the plurality of cascaded second shift register units are electrically connected with the scanning lines in the even rows;
a first clock signal line and a third clock signal line;
a first clock shift circuit group;
a clock signal input end of the first shift register unit is respectively connected with the first clock signal line and the third clock signal line;
the input end of the first clock shift circuit group is connected with the first clock signal line and the third clock signal line, and the output end of the first clock shift circuit group is connected with the clock signal input end of the second shift register unit;
the display panel includes a first region and a second region; the first region comprises a first edge, and the first edge is sunken towards the second region to enable the first region to form a notch; the number of any row of sub-pixels in the first area is less than that of any row of sub-pixels in the second area;
the first area comprises a first display area and a second display area, and the first display area and the second display area are respectively positioned on two sides of the notch along the first direction; the second region comprises a third display region;
the display panel further comprises a non-display area, wherein the non-display area is arranged around the first display area, the second display area and the third display area; the non-display area comprises a first non-display area and a second non-display area; in the first direction, the first non-display area is positioned on one side of the first display area, which is far away from the gap, and the second non-display area is positioned between the gap and the first display area;
the first region further comprises a fifth non-display region; the fifth non-display area is positioned on one side, away from the third display area, of the first display area in the second direction, the first clock shift circuit group is positioned in the fifth non-display area, and the first clock shift circuit group comprises a first clock shift circuit and a second clock shift circuit.
2. The display panel according to claim 1,
the scanning lines comprise a first scanning line, a second scanning line and a third scanning line, the first scanning line is located in the first display area, the second scanning line is located in the second display area, and the third scanning line is located in the third display area;
the first shift register unit is positioned in the first non-display area and is connected with the first scanning line of the odd-numbered row and the third scanning line of the odd-numbered row;
the second shift register unit is located in the second non-display area and is connected with the first scanning lines of even rows.
3. The display panel according to claim 2, wherein the first scan line and the second scan line are not connected.
4. The display panel according to claim 3, wherein the non-display region further comprises a third non-display region, a fourth non-display region;
in the first direction, the fourth non-display area is positioned on one side of the second display area far away from the notch, and the third non-display area is positioned between the notch and the second display area;
a plurality of cascaded third shift register units, wherein the third shift register units are positioned in the third non-display area and are connected with the second scanning lines of odd rows;
a plurality of cascaded fourth shift register units, wherein the fourth shift register units are located in the fourth non-display area and connected with the second scanning lines in the even-numbered rows and the third scanning lines in the even-numbered rows;
a second clock signal line and a fourth clock signal line;
a second clock shift circuit group;
a clock signal input end of the fourth shift register unit is respectively connected with the second clock signal line and the fourth clock signal line;
the input end of the second clock shift circuit group is respectively connected with the second clock signal line and the fourth clock signal line, and the output end of the second clock shift circuit group is connected with the clock signal input end of the third shift register unit.
5. The display panel according to claim 4, wherein the first region further comprises a sixth non-display region;
the sixth non-display area is located on one side, away from the third display area, of the second display area in the second direction, the second clock shift circuit group is located in the sixth non-display area, and the second clock shift circuit group comprises a third clock shift circuit and a fourth clock shift circuit.
6. The display panel according to claim 5, wherein the first clock shift circuit comprises a first input terminal, a second input terminal, a first switching transistor, a second switching transistor, a first voltage signal terminal, a second voltage signal terminal, an inverter, a clock inverter, a first output terminal;
the grid electrode of the first switch transistor is connected with the first input end, the source electrode of the first switch transistor is connected with the first voltage signal end, and the drain electrode of the first switch transistor is connected with the first end of the clock reverser;
the second end of the clock reverser is connected with the first output end, and the third end of the clock reverser is connected with the first input end;
the first end of the phase inverter is connected with the first input end, and the second end of the phase inverter is connected with the fourth end of the clock reverser;
and the grid electrode of the second switching transistor is connected with the second input end, the source electrode of the second switching transistor is connected with the second voltage signal end, and the drain electrode of the second switching transistor is connected with the first end of the clock reverser.
7. The display panel according to claim 6, wherein the first clock shift circuit, the second clock shift circuit, the third clock shift circuit, and the fourth clock shift circuit are identical in structure.
8. The display panel according to claim 6, wherein the first switching transistor and the second switching transistor are both N-type switching transistors.
9. The display panel according to claim 6, wherein a first voltage signal inputted from the first voltage signal terminal is at a low voltage level, and a second voltage signal inputted from the second voltage signal terminal is at a high voltage level.
10. The display panel according to claim 7,
a first input end of the first clock shift circuit is connected with the first clock signal line, a second input end of the first clock shift circuit is connected with the third clock signal line, and a first output end of the first clock shift circuit is connected with one clock signal input end of the second shift register unit;
a first input end of the second clock shift circuit is connected with the third clock signal line, a second input end of the second clock shift circuit is connected with the first clock signal line, and a first output end of the second clock shift circuit is connected with the other clock signal input end of the second shift register unit;
a first input end of the third clock shift circuit is connected with the second clock signal line, a second input end of the third clock shift circuit is connected with the fourth clock signal line, and a first output end of the third clock shift circuit is connected with one clock signal input end of the third shift register unit;
and a first input end of the fourth clock shift circuit is connected with the fourth clock signal line, a second input end of the fourth clock shift circuit is connected with the second clock signal line, and a first output end of the fourth clock shift circuit is connected with the other clock signal input end of the third shift register unit.
11. The display panel according to claim 10,
the first shift register unit, the second shift register unit, the third shift register unit and the fourth shift register unit comprise the same shift register;
the shift register comprises a first signal output end, a second signal output end, a signal input end, a first clock signal input end and a second clock signal input end;
the first signal output end of each stage of the shift register is connected with the scanning line;
the second signal output end of the shift register of each stage is connected with the signal input end of the shift register of the next stage;
the first clock signal input end of the first shift register unit of the odd-numbered stage is connected with the third clock signal line, and the second clock signal input end is connected with the first clock signal line; the first clock signal input end of the first shift register unit of the even-numbered stage is connected with the first clock signal line, and the second clock signal input end is connected with the third clock signal line;
the first clock signal input end of the second shift register unit of the odd-numbered stage is connected with the first output end of the second clock shift circuit, and the second clock signal input end is connected with the first output end of the first clock shift circuit; the first clock signal input end of the second shift register unit of the even-numbered stage is connected with the first output end of the first clock shift circuit, and the second clock signal input end is connected with the first output end of the second clock shift circuit;
the first clock signal input end of the third shift register unit of the odd-numbered stage is connected with the first output end of the fourth clock shift circuit, and the second clock signal input end is connected with the first output end of the third clock shift circuit; the first clock signal input end of the third shift register unit of the even-numbered stage is connected with the first output end of the third clock shift circuit, and the second clock signal input end is connected with the first output end of the fourth clock shift circuit;
the first clock signal input end of the odd-numbered fourth shift register unit is connected with the fourth clock signal line, and the second clock signal input end is connected with the second clock signal line; and the first clock signal input end of the fourth shift register unit of the even-numbered stage is connected with the second clock signal line, and the second clock signal input end is connected with the fourth clock signal line.
12. The display panel according to claim 11, wherein the signal input terminal of the shift register of the first stage inputs a start shift signal.
13. The display panel according to claim 11, wherein the shift register further comprises a reset terminal, and the reset terminal is connected to a reset signal line.
14. The display panel according to claim 11, wherein the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line output valid pulse signals having the same pulse width and period.
15. The display panel according to claim 14, wherein a falling edge of the effective pulse signal output from the first clock signal line is aligned with a rising edge of the effective pulse signal output from the second clock signal line, wherein a falling edge of the effective pulse signal output from the second clock signal line is aligned with a rising edge of the effective pulse signal output from the third clock signal line, wherein a falling edge of the effective pulse signal output from the third clock signal line is aligned with a rising edge of the effective pulse signal output from the fourth clock signal line, and wherein a falling edge of the effective pulse signal output from the fourth clock signal line is aligned with a rising edge of the effective pulse signal output from the first clock signal line.
16. A display device characterized by comprising the display panel according to any one of claims 1 to 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810689236.9A CN108665845B (en) | 2018-06-28 | 2018-06-28 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810689236.9A CN108665845B (en) | 2018-06-28 | 2018-06-28 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108665845A CN108665845A (en) | 2018-10-16 |
| CN108665845B true CN108665845B (en) | 2021-04-30 |
Family
ID=63773477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810689236.9A Active CN108665845B (en) | 2018-06-28 | 2018-06-28 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108665845B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377929A (en) * | 2018-11-22 | 2019-02-22 | 南京中电熊猫平板显示科技有限公司 | A kind of gate driving circuit and special-shaped screen display panel |
| CN109935173B (en) * | 2019-03-29 | 2021-10-26 | 上海天马微电子有限公司 | Display module and display device |
| CN113011353B (en) * | 2021-03-25 | 2022-10-11 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113593462B (en) * | 2021-07-28 | 2024-03-22 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN113781913B (en) * | 2021-09-10 | 2023-04-11 | 厦门天马显示科技有限公司 | Display panel and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060187175A1 (en) * | 2005-02-23 | 2006-08-24 | Wintek Corporation | Method of arranging embedded gate driver circuit for display panel |
| CN103928001B (en) * | 2013-12-31 | 2016-12-07 | 上海天马微电子有限公司 | Grid driving circuit and display device |
| US10062317B2 (en) * | 2014-10-16 | 2018-08-28 | Lg Display Co., Ltd. | Panel array for display device with narrow bezel |
| KR102582642B1 (en) * | 2016-05-19 | 2023-09-26 | 삼성디스플레이 주식회사 | Display device |
| CN107123388A (en) * | 2017-06-29 | 2017-09-01 | 厦门天马微电子有限公司 | A kind of array base palte and display device |
-
2018
- 2018-06-28 CN CN201810689236.9A patent/CN108665845B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108665845A (en) | 2018-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108665845B (en) | Display panel and display device | |
| CN104978943B (en) | A kind of shift register, the driving method of display floater and relevant apparatus | |
| CN104966506B (en) | The driving method and relevant apparatus of a kind of shift register, display panel | |
| EP3836133A1 (en) | Shift register unit, gate drive circuit, display device, and driving method | |
| US9563396B2 (en) | Gate driving circuit and display device | |
| CN105096889B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| US9666152B2 (en) | Shift register unit, gate driving circuit and display device | |
| CN104134430B (en) | A kind of shift register, gate driver circuit and display device | |
| CN107633834B (en) | Shift register unit, driving method thereof, grid driving circuit and display device | |
| EP3229226A1 (en) | Shift register unit, driving method therefor, gate drive circuit, and display device | |
| US11200860B2 (en) | Shift register unit, gate driving circuit and driving method thereof | |
| US10984738B2 (en) | Driving device and driving method of display panel | |
| WO2016176972A1 (en) | Gate drive circuit, display panel and touch control display device | |
| CN110299116B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN109272921A (en) | A kind of gate driving circuit and its driving method, display panel, display device | |
| CN104966503B (en) | A kind of gate driving circuit and its driving method, level shifter | |
| CN108806581B (en) | Scanning driving circuit and display panel | |
| CN110322847B (en) | Gate drive circuit, display device and drive method | |
| US20210233483A1 (en) | Shift register, driving method thereof, gate driver circuit and display device | |
| KR102705644B1 (en) | Gate integrated driving circuit, display panel and display device | |
| CN112599071B (en) | Display panel and display device | |
| CN105788509A (en) | GOA scanning unit, GOA scanning circuit, display panel and display device | |
| CN111883041B (en) | Driving circuit, display panel and electronic equipment | |
| US20170047128A1 (en) | Shift register circuit | |
| US10453405B2 (en) | GOA circuit and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |