CN113593462B

CN113593462B - Array substrate, display panel and display device

Info

Publication number: CN113593462B
Application number: CN202110855637.9A
Authority: CN
Inventors: 吴浩
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2024-03-22
Anticipated expiration: 2041-07-28
Also published as: CN113593462A

Abstract

The application discloses an array substrate, a display panel and display equipment. The array substrate comprises a first display area and a second display area; the array substrate further includes: the sub-pixels in the first display area are respectively connected with the corresponding first shift register units, and the first shift register units are used for outputting first scanning signals; the sub-pixels in the second display area are respectively connected with the corresponding second shift register units, and the second shift register units are used for outputting second scanning signals; wherein the signal delay of the first high level signal is smaller than the signal delay of the second high level signal. According to the embodiment of the application, the signal delay of the second high-level signal is set to be larger than that of the first high-level signal, so that the same column of sub-pixels in the two display areas have the same feed-through voltage, and the flicker phenomenon is avoided during display.

Description

Array substrate, display panel and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate, a display panel and display equipment.

Background

At present, as the application field of electronic products is continuously expanded, the shape of the display screen of the electronic products is also changed along with the application field.

In some application fields, for example in the field of vehicle-mounted display screens, the shape of the display screen is designed as a shaped screen, such as a "T" screen or an "L" screen, etc. The existing T-shaped screen or L-shaped screen can be spliced by two screens, or can be a complete T-shaped screen or L-shaped screen. The special-shaped screens obtained by splicing the two screens have optical and color differences, synchronous and coordinated display is not easy to realize, and black edges exist at the junction of the two screens, so that the overall display effect is affected. Therefore, a screen design is generally adopted to obtain a special-shaped screen such as a T-shaped screen or an L-shaped screen.

However, there is a feedthrough voltage in the pixel voltages received by the sub-pixels in the array substrate. Because in the special-shaped screen such as a T-shaped screen or an L-shaped screen, the number of pixels in the pixel rows in different areas is different. For a plurality of sub-pixels in the same column, if the sub-pixels are located in different areas, the corresponding feed-through voltages in the received pixel voltages are also different, so that gate delay time of the gate of the sub-pixel receiving a pull-up signal or a pull-down signal is also different, and a flicker phenomenon is easy to occur during display.

Disclosure of Invention

The embodiment of the application provides an array substrate, a display panel and display equipment, which can solve the technical problems that different pixel rows in a special-shaped screen have different feed-through voltages and flicker phenomenon occurs easily when the feed-through voltages are different.

In a first aspect, an embodiment of the present application provides an array substrate, where the array substrate includes a first display area and a second display area, each of the first display area and the second display area includes a plurality of arrayed sub-pixels, and the number of pixels of each row of sub-pixels in the first display area is greater than the number of pixels of each row of sub-pixels in the second display area; the array substrate further includes:

the sub-pixels in the first display area are respectively connected with the corresponding first shift register units, and the first shift register units are used for outputting first scanning signals which comprise first low-level signals and first high-level signals;

the sub-pixels in the second display area are respectively connected with the corresponding second shift register units, and the second shift register units are used for outputting second scanning signals which comprise second low-level signals and second high-level signals; wherein the signal delay of the first high level signal is smaller than the signal delay of the second high level signal.

In a second aspect, embodiments of the present application provide a display panel including an array substrate as above.

In a third aspect, embodiments of the present application provide a display device including the display panel as above.

Compared with the prior art, the array substrate, the display panel and the display device provided by the embodiment of the application are respectively provided with the corresponding shift register units for two display areas with different pixel numbers in each row. The first display area outputs signals by the first shift register unit, the second display area outputs signals by the second shift register unit, and the signal delay of the second high-level signal of the second shift register unit is larger than that of the first high-level signal of the first shift register unit, so that the feed-through voltage of the sub-pixels of the first display area is similar to or consistent with that of the corresponding sub-pixels in the second display area, and the abnormal screen is prevented from flickering during display.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the positions of sub-pixels according to an embodiment of the present disclosure;

FIG. 3 is a waveform diagram of a gate delay time according to an embodiment of the present application;

fig. 4 is a schematic circuit diagram of a first shift register unit according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram of a first output module according to an embodiment of the present application;

FIG. 6 is a schematic circuit diagram of a second shift register unit according to an embodiment of the present disclosure;

fig. 7 is a schematic circuit diagram of a second output module according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a first winding according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of connection of clock signal lines according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a CMOS circuit architecture according to an embodiment of the present application;

FIG. 11 is a schematic diagram of an NMOS circuit architecture according to an embodiment of the present application;

FIG. 12 is a schematic view of the shape of an array substrate according to an embodiment of the present disclosure;

FIG. 13 is a schematic view of the shape of an array substrate according to another embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present application.

In the accompanying drawings: 1. a first display area; 2. a second display area; 3. a sub-pixel; 10. a first shift register unit; 20. a second shift register unit; 11. a first logic circuit module; 12. a first output module; 21. a second logic circuit module; 22. a second output module; 30. a first winding; t1, a first transistor; t2, a second transistor; t3, third transistor; t4, fourth transistor; VGL1, a first low level signal terminal; VGL2, the second low level signal terminal; VGH1, a first high level signal end; VGH2, the second high level signal end; CKV1, first clock signal line; CKV2, a second clock signal line; CKV3, third clock signal line; CKV4, fourth clock signal line; l1, a first side; l2, a second side; l3, third side; l4, fourth; l5, a fifth side; p1, a first endpoint; p2, the second endpoint; s1, a first line segment.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing an example of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.

Currently, existing display product screens are typically rectangular in shape. Along with the continuous expansion of the application field of the display product, the appearance of the display product is also changed continuously. For example, in the field of vehicle-mounted display products, a special-shaped screen such as a "T" type display screen or an "L" type display screen, which is created to meet the needs of users, is becoming popular.

The existing special-shaped screens such as a T-shaped display screen or an L-shaped display screen have two design realization modes: one is obtained by splicing two screens, and the other is designed by adopting one screen to carry out special-shaped screen design. In a shaped screen obtained by splicing two screens, there are several problems: the synchronicity of the two screens is difficult to coordinate, and synchronous display cannot be realized; the two screens have optical differences and color differences and need to be subjected to coordination and adaptation treatment; the black frame area exists at the joint of the two screens, and the overall display effect is affected. Therefore, the existing special-shaped screen is usually designed in a special-shaped mode by adopting one screen.

However, the inventors have found that for a shaped screen such as a "T" type display screen or an "L" type display screen, there are at least two display areas in which the number of pixels of the pixel rows is not uniform, for example, the number of pixels per row in the upper half of the "T" type display screen is greater than the number of pixels per row in the lower half of the "T" type display screen. In each pixel row of the array substrate, a parasitic capacitance exists in a thin film transistor TFT in a pixel circuit, so that a feed-through feedback effect can occur on the received pixel voltage, that is, a voltage deviation value exists on the pixel voltage actually received by each pixel, and the deviation value is the feed-through voltage of the pixel. In the same pixel row, the grid electrode of each pixel has impedance, and the grid electrode and the pixel electrode have capacitance reactance, so that an RC delay circuit consisting of a delay resistor and a delay capacitor is generated. Due to the presence of this RC circuit, the feed-through voltages of different pixels are also not uniform in the same pixel row. Moreover, the feed-through voltage of the pixel at the near end of the shift register unit is larger than that of the pixel at the far end, so that the actual driving voltages of the scanning signals received by the near end and the far end are not consistent.

In different areas of the special-shaped screen, because the quantity of pixels at intervals between the same pixel column and the shift register unit is inconsistent, feed-through voltages of different pixels in the same pixel column are inconsistent, gate Delay waveforms of Gate circuits in the pixels are also inconsistent, and a flicker phenomenon easily occurs during display.

In order to solve the technical problems, an embodiment of the application provides an array substrate, a display panel and display equipment. The following first describes an array substrate provided in an embodiment of the present application.

Referring to fig. 1, fig. 1 shows an array substrate provided in an embodiment of the present application, where the array substrate includes a first display area 1 and a second display area 2, each of the first display area 1 and the second display area 2 includes a plurality of sub-pixels 3 arranged in an array, and the number of pixels of each row of sub-pixels 3 in the first display area 1 is greater than the number of pixels of each row of sub-pixels 3 in the second display area 2; the array substrate further includes:

a plurality of first shift register units 10, wherein the sub-pixels 3 in the first display area 1 are respectively connected with the corresponding first shift register units 10, and the first shift register units 10 are used for outputting first scanning signals, wherein the first scanning signals comprise a first low-level signal and a first high-level signal;

The sub-pixels 3 in the second display area 2 are respectively connected with the corresponding second shift register units 20, and the second shift register units 20 are used for outputting second scanning signals, wherein the second scanning signals comprise second low-level signals and second high-level signals; wherein the signal delay of the first high level signal is smaller than the signal delay of the second high level signal.

The array substrate comprises a first display area 1 and a second display area 2, the first display area 1 and the second display area 2 comprise a plurality of sub-pixels 3 which are arranged in an array mode, and the number of pixels of each row of sub-pixels 3 in the first display area 1 is larger than that of pixels of each row of sub-pixels 3 in the second display area 2. That is, the width of the first display area 1 is larger than the width of the second display area 2.

The number of the first shift register units 10 may be set to be equal to the number of pixel rows of the first display area 1, and each row of the sub-pixels 3 in the first display area 1 may be connected to the corresponding first shift register unit 10, respectively. The first shift register unit 10 may output a first scan signal to the gate line of each sub-pixel 3 through the scan line corresponding to the pixel row. The first scan signal may include a first low level signal and a first high level signal.

The number of the second shift register units 20 may be set to be equal to the number of pixel rows of the second display area 2, and each row of the sub-pixels 3 in the second display area 2 may be connected to the corresponding second shift register unit 20, respectively. The second shift register unit 20 may output the second scan signal to the gate line of each sub-pixel 3 through the scan line corresponding to the pixel row. The second scan signal may include a second low level signal and a second high level signal. Wherein the signal delay of the first high level is less than the signal delay of the second high level.

It will be appreciated that the first shift register cell 10 and the second shift register cell 20 may be cascade-connected in sequence.

The number of pixels per row of sub-pixels 3 in the first display area 1 is larger than the number of pixels per row of sub-pixels 3 in the second display area 2. Referring to fig. 2, taking a T-shaped screen as an example, (1) (2) (3) is three sub-pixels 3 connected at intervals of a certain row in the first display area 1, (1) is similar to a pixel distance of the first shift register unit 10 and (4) is similar to a pixel distance of the second shift register unit 20, (4) (5) is two sub-pixels 3 connected at intervals of a certain row in the second display area 2, and (2) and (4) are located in the same column, (3) and (5) are located in the same column.

The sub-pixels 3 in a certain column in the first display area 1 are (2), and the sub-pixels 3 in the same column as (2) in the second display area 2 are (4). (2) The number of pixels spaced from the first shift register unit 10 is x, and the number of pixels spaced from the second shift register unit 20 is y, it can be determined that the numbers of x and y are not the same, and x > y. Therefore, in the same column of the sub-pixels 3, since the number of sub-pixels separated from the shift register unit is different, the feed-through voltages respectively corresponding to the two sub-pixels (2) and (4) located on the same column of the different display areas are not the same.

When the signal delays of the first high level and the second high level are equal, as described in the above embodiment, for the same column of sub-pixels 3, the feedthrough voltage corresponding to (2) in the first display area 1 is smaller than the feedthrough voltage corresponding to (4) in the second display area 2. In each row of sub-pixels 3 the feed-through voltage is inversely related to the gate delay time, and as the feed-through voltage increases the corresponding gate delay time decreases. The Gate delay time is a delay time of a signal rising transition and a signal falling transition when a Gate (Gate) of each sub-pixel connected to the scan line receives the scan signal. (4) When the feedthrough voltage of (2) is greater than the feedthrough voltage of (4), the gate delay time of (4) is less than the gate delay time of (2). When the gate delay times of (2) and (4) are different and the difference is large, the light emission times of (2) and (4) are not synchronized, and the light emission luminance also varies. When the gate delay time difference exists in each row of sub-pixels in the array substrate, the phenomenon of uneven flicker occurs, so that the visual effect is reduced.

And when the signal delay of the second high level signal is larger than the signal delay of the first high level signal, the received scanning signal of (4) has delay relative to the received scanning signal of (2), and the gate delay time of (4) is increased due to the signal delay of the second high level signal, so that the gate delay time of (4) is close to the gate delay time of (2). When the gate delay time of (4) is similar to or consistent with that of (2), the feed-through voltage of (4) is also similar to that of (2), so that the sub-pixels (2) and (4) on the same column can generate the same feed-through voltage, and the phenomenon of flicker caused by large difference of the feed-through voltages of the sub-pixels on the same column during display is avoided.

It can be understood that when the signal delay of the first high level signal is set to be smaller than the signal delay of the second high level signal, the feedthrough voltage of (4) can be made to approach to the feedthrough voltage of (2), and when the voltage difference between the feedthrough voltages of (2) and (4) is kept within the preset range, the flicker phenomenon can be eliminated.

In the array substrate provided in the embodiment of the present application, for the first display area 1 and the second display area 2 in which the number of the sub-pixels 3 in each row is different, the corresponding first shift register unit 10 and second shift register unit 20 are respectively set to output the scan signal. The first scan signal output from the first shift register unit 10 includes a first low level signal and a first high level signal, and the second scan signal output from the second shift register unit 20 includes a second low level signal and a second high level signal. The signal delay of the first high-level signal is smaller than that of the second high-level signal, and then the second scanning signal received by the 3 rows of sub-pixels corresponding to the second shift register has signal delay compared with the first scanning signal. Since the subpixels 3 in the second display area 2 have smaller gate delay times and larger feedthrough voltages than the subpixels 3 located on the same column in the first display area 1. After the signal delay of the second high-level signal, the gate delay time of the sub-pixel 3 in the first display area 1 and the gate delay time of the sub-pixel 3 in the same column in the second display area 2 can be similar or identical, so that the feed-through voltage of the sub-pixel 3 in the same column is kept similar or identical, the sub-pixels 3 in the same column in the first display area 1 and the second display area 2 can synchronously emit light, and the flicker phenomenon caused by the large difference of the gate delay time of the sub-pixels 3 in the same column is avoided.

As shown in fig. 3, the gate delay time of the sub-pixel 3 may include a signal rising delay Tr and a falling delay Tf. When the relative signal delay of the first high level signal and the first high level signal is not adjusted, according to the gate delay time waveform of each sub-pixel, the gate delay time of each sub-pixel can be obtained as follows:

subpixel (1): tr=2.01 μs, tf=1.94 μs;

subpixel (2): tr=2.21 μs, tf=2.15 μs;

subpixel (3): tr=2.63 μs, tf=2.42 μs;

the gate delay time of the sub-pixel (4) is similar to that of the sub-pixel (1), and the gate delay time of the sub-pixel (5) is similar to that of the sub-pixel (2).

When the signal delay of the first high level signal is smaller than the signal delay of the second high level signal, the gate delay time of the sub-pixels (4) (5) can be obtained as follows:

subpixel (4): tr=2.25 μs, tf=2.20 μs;

subpixel (5): tr=2.66 μs, tf=2.47 μs;

in this case, the gate delay time of the sub-pixel (4) is similar to that of the sub-pixel (2), and the gate delay time of the sub-pixel (5) is similar to that of the sub-pixel (3). Therefore, the gate delay time of the same column of the sub-pixels in different display areas is approximately or equal, and the sub-pixels (4) and the sub-pixels (2) have the same or similar feed-through voltage, so that the display flicker phenomenon caused by the difference of the feed-through voltages is avoided.

In some embodiments, referring to fig. 4 to 5, the first shift register unit 10 may include: a first logic circuit module 11 for outputting a first pulse signal including a first signal and a second signal;

the controlled end of the first output module 12 is connected with the first logic circuit module 11, the first input end of the first output module 12 is connected with the first low-level signal end VGL1, and the second input end of the first output module 12 is connected with the first high-level signal end VGH 1.

The first logic circuit module 11 may be connected to a clock signal line of the array substrate, and generate and output a corresponding first pulse signal to the first output module 12 according to the received clock signal, and the first pulse signal may include a first signal and a second signal that are alternately output. The first output module 12 may send a corresponding first low level signal or a first high level signal to a scan line connected to the first shift register unit 10 according to the received first pulse signal, and output a scan signal corresponding to the row of sub-pixels 3 through a GOUT1 port, where the sub-pixels 3 may control the light emitting devices in the sub-pixels 3 to emit light according to the received scan signal.

When the first output module 12 receives the first pulse signal output by the first logic circuit module 11 as the first signal, the first output module 12 may connect the first input end thereof with the output end, so that the first output module 12 sends the first low level signal sent by the first low level signal end VGL1 to the corresponding scan line and transmits the first low level signal to the gate line of the row of sub-pixels 3.

Similarly, when the first output module 12 receives the first pulse signal output by the first logic circuit module 11 as the second signal, the first output module 12 may connect the second input end thereof with the output end, so that the first output module 12 sends the first high level signal sent by the first high level signal end VGH1 to the corresponding scan line through the GOUT1 port and transmits the first high level signal to the gate line of the row of sub-pixels 3.

In some embodiments, referring to fig. 5, the first output module 12 may include:

a first transistor T1, a first pole of the first transistor T1 is connected to the first low level signal terminal VGL1, a second pole of the first transistor T1 is connected to the output terminal GOUT1 of the first output module 12, and a gate of the first transistor T1 is connected to the first logic circuit module 11; the first transistor T1 is turned on when receiving the first signal and turned off when receiving the second signal.

A first pole of the second transistor T2 is connected to the first high level signal terminal VGH1, a second pole of the second transistor T2 is connected to the output terminal GOUT1 of the first output module 12, and a gate of the second transistor T2 is connected to the first logic circuit module 11; the second transistor T2 is turned off when receiving the first signal and turned on when receiving the second signal.

The first transistor T1 and the second transistor T2 may be TFTs (Thin Film Transistor, thin film transistors). The first transistor T1 is turned on when the grid receives a first signal, and turned off when the grid receives a second signal; the second transistor T2 is turned on when the gate receives the second signal and turned off when the gate receives the first signal.

It will be appreciated that since the on states of the first transistor T1 and the second transistor T2 are opposite when the same signal is received, one of the first transistor T1 and the second transistor T2 may be a P-type transistor, and the other may be an N-type transistor.

When the first logic circuit module 11 sends a first signal to the first output module 12, the first transistor T1 is turned on, and the second transistor T2 is turned off, and at this time, the output end of the first output module 12 outputs a first high level signal; when the first logic circuit sends the second signal to the first output module 12, the first transistor T1 is turned off, and the second transistor T2 is turned on, and the signal output by the first output module 12 is the first low level signal. The first logic circuit module 11 can cause the first output module 12 to transmit a first scan signal composed of a first high level signal and a first low level signal to the scan line according to the first pulse signal by alternately outputting the first pulse signal composed of the first signal and the second signal, thereby controlling the row of sub-pixels 3 to emit light.

In some embodiments, referring to fig. 6 to 7, the second shift register unit 20 may include:

a second logic circuit module 21 for outputting a second pulse signal including a third signal and a fourth signal;

the second output module 22, the controlled end of the second output module 22 is connected with the second logic circuit module 21, the first input end of the second output module 22 is connected with the second low level signal end VGL2, and the second input end of the second output module 22 is connected with the second high level signal end VGH 2.

In this embodiment, the second logic circuit module 21 may be connected to the clock signal line of the array substrate, and generate and output a corresponding second pulse signal according to the received clock signal. The second pulse signal may include a third signal and a fourth signal alternately output. The second output module 22 may send a corresponding second low level signal or a second high level signal to the scan line connected to the second shift register unit 20 according to the received second pulse signal, so as to form a second scan signal corresponding to the row of sub-pixels 3.

When the second output module 22 receives the second pulse signal output by the second logic circuit module 21, if the second pulse signal is the third signal, the first input end of the second output module 22 is connected with the output end of the second output module 22, so that the second output module 22 sends the second low-level signal sent by the second low-level signal end VGL2 to the corresponding scanning line and transmits the second low-level signal to the grid line of the row of sub-pixels 3; if the fourth signal is the fourth signal, the second input end of the second output module 22 is connected to the output end of the second output module 22, so that the second output module 22 sends the second high-level signal sent by the second high-level signal end VGH2 to the corresponding scan line and transmits the second high-level signal to the gate line of the row of sub-pixels 3.

In some embodiments, referring to fig. 7, the second output module 22 may include:

the first pole of the third transistor T3 is connected to the second low level signal terminal VGL2, the second pole of the third transistor T3 is connected to the output terminal GOUT2 of the second output module 22, and the gate of the third transistor T3 is connected to the first signal output terminal of the second logic circuit module 21.

The first pole of the fourth transistor T4 is connected to the second high-level signal terminal VGH2, the second pole of the fourth transistor T4 is connected to the output terminal GOUT2 of the second output module 22, and the gate of the fourth transistor T4 is connected to the second signal output terminal of the second logic circuit module 21.

The third transistor T3 and the fourth transistor T4 may be TFTs (Thin Film Transistor, thin film transistors). The third signal is an on signal output by the first signal output end of the second logic circuit module 21, and an off signal is output by the second signal output end of the second logic circuit module 21; the fourth signal is a turn-off signal output from the first signal output end of the second logic circuit module 21, and a turn-on signal output from the second signal output end of the second logic circuit module 21.

When the second logic circuit module 21 outputs the third signal, the third transistor T3 is turned on and the fourth transistor T4 is turned off; while the second logic circuit module 21 outputs the fourth signal, the fourth transistor T4 is turned on and the third transistor T3 is turned off. Likewise, the corresponding scan line of the second shift register unit 20 can receive the second scan signal composed of the second high level signal and the second low level signal, thereby controlling the corresponding sub-pixel 3 row to emit light.

It should be noted that, in the second logic circuit module 21, the signals output by the first signal output terminal and the second signal output terminal may be the same signal or different signals. For example, when the signals output from the first signal output terminal and the second signal output terminal are the same, one of the third transistor T3 and the fourth transistor T4 may be set to be N-type and the other to be P-type, so that the on states of the third transistor T3 and the fourth transistor T4 are always opposite.

When the signals output by the first signal output end and the second signal output end are different, the third transistor T3 and the fourth transistor T4 may be set to be N-type transistors or P-type transistors, and at this time, the conducting states of the third transistor T3 and the fourth transistor T4 are opposite, so as to realize alternative conduction of the third transistor T3 and the fourth transistor T4.

It can be understood that in the first display area 1, the scan signal received by the sub-pixel 3 is a first scan signal composed of a first low level signal and a first high level signal. In the second display area 2, the scan signal received by the sub-pixel 3 is a second scan signal composed of a second low level signal and a second high level signal. When the second high level signal has a signal delay relative to the first high level signal, the gate delay time of the scan signal received by the same row of sub-pixels 3 in the first display area 1 and the second display area 2 can be kept approximately or consistent, and when the gate delay time is the same, the feedthrough voltages generated by the same row of sub-pixels 3 are also the same according to the corresponding relation between the feedthrough voltages and the gate delay time, so that the display flicker phenomenon generated by the difference of the feedthrough voltages is avoided.

In some embodiments, referring to fig. 8, the array substrate may further include:

the first end of the first winding 30 is connected with the second input end of the second output module 22, and the second end of the first winding 30 is connected with the second high-level signal end VGH 2;

the first winding 30 is used for increasing the equivalent load on the scanning line corresponding to the second shift register unit 20.

In this embodiment, the gate line of each sub-pixel 3 has an impedance and a capacitance, so as to generate an equivalent RC delay circuit, and the equivalent RC load on one scan line is positively correlated with the number of sub-pixels 3 on the scan line. Since the number of sub-pixels 3 per row in the first display area 1 is greater than the number of sub-pixels 3 per row in the second display area 2, the equivalent RC load on the scan line in the first display area 1 is greater than the equivalent RC load on the scan line in the second display area 2. In order to eliminate or reduce the signal error caused by the difference of the equivalent RC loads of the first display area 1 and the second display area 2, a first winding 30 may be added between the second input terminal of the second output module 22 and the second high-level signal terminal VGH2, and the equivalent load on the scan lines corresponding to the second shift register unit 20 may be increased through the first winding 30, so that the equivalent RC load on each scan line in the second display area 2 is increased to be equal to or similar to the equivalent RC load on each scan line in the first display area 1, thereby eliminating the signal error caused by the difference of the equivalent RC loads on the scan lines in the first display area 1 and the second display area 2.

In some embodiments, the first shift register units 10 and the second shift register units 20 may be electrically connected sequentially. That is, the plurality of first shift register units 10 in the first display area 1 are electrically connected in sequence, the plurality of second shift register units 20 in the second display area 2 are electrically connected in sequence, and the first shift register closest to the second display area 2 in the first display area 1 is electrically connected to the second shift register closest to the first display area 1 in the second display area 2.

In some embodiments, referring to fig. 9, the array substrate may further be provided with a first clock signal line CKV1, a second clock signal line CKV2, a third clock signal line CKV3, and a fourth clock signal line CKV4.

The two input ends of the first shift register unit 10 are respectively connected with two of the first clock signal line CKV1, the second clock signal line CKV2, the third clock signal line CKV3 and the fourth clock signal line CKV4, and the four input ends of the second shift register unit 20 are respectively connected with the first clock signal line CKV1, the second clock signal line CKV2, the third clock signal line CKV3 and the fourth clock signal line CKV4. As shown in fig. 10, the first shift register unit 10 may adopt a CMOS circuit architecture, where VGH and VHL in fig. 10 are a first low-level signal terminal VGL1 and a first high-level signal terminal VGH1; as shown in fig. 11, the second shift register unit 20 may employ an NMOS circuit structure, and VGL and OUT in fig. 11 are the second low-level signal terminal VGL2 and the second high-level signal terminal VGH2. The first shift register may generate the corresponding first pulse signal through two clock signal lines connected thereto among the four clock signal lines. The second shift register can generate corresponding second pulse signals through four clock signal lines.

In some embodiments, the first high-level signal may be a power signal, and the second high-level signal may be a clock signal. For example, the second high level signal may be a clock signal line connected to the second input terminal of the second output module 22 among the four clock signal lines. Compared with the power supply signal, the clock signal output by the clock signal line has signal delay, so that the signal delay of the second high-level signal is larger than that of the second high-level signal, and the feed-through voltage of the sub-pixel 3 in the second display area 2 is similar to or consistent with that of the sub-pixel 3 in the first display area 1.

In some embodiments, the first low-level signal and the second low-level signal may be the same low-level signal. That is, the signal delays of the first low-level signal and the second low-level signal remain identical. The first low level signal and the second low level signal may be power signals.

In some embodiments, referring to fig. 12, the first display area 1 may include a first side L1 and a second side L2 disposed opposite to each other, and the second display area 2 may include a third side L3 and a fourth side L4 disposed opposite to each other. The second side L2 includes a first end P1 near the second display area 2, the fourth side L4 includes a second end P2 far from the first display area 1, the first end P1 and the second end P2 are located on the first line segment S1, and the fourth side L4 is located on one side of the first line segment S1 near the display area.

In the above embodiment, the second side L2 and the fourth side L4 may be further connected by the fifth side L5, and the fifth side L5 is located at a side of the first line segment S1 near the display area.

In the present embodiment, the number of sub-pixels 3 in each row in the first display area 1 is greater than the number of sub-pixels 3 in each row in the second display area 2, and the fourth side L4 of the second display area 2 is located at a side of the first line segment S1 near the display area. In addition to the above-described embodiments and the "T" type display area described in the corresponding drawings, the display area formed by the first display area 1 and the second display area 2 in the present application may be other special shapes that satisfy the above-described features. For example, referring to fig. 13, when the overall display area formed by the first display area 1 and the second display area 2 is inverted "L", it is also satisfied that the fourth side L4 and the fifth side L5 are located at a side of the first line segment S1 near the display area.

In some embodiments, the number of pixels in each row in the first display area 1 is m, and the number of pixels in each row in the second display area 2 is n. Where m > n and where m differs significantly from n, for example, m.gtoreq.3n may be set, i.e. the number of pixels per row in the first display area 1 is at least 3 times the number of pixels per row in the second display area 2. In an embodiment, the number of row pixels of the first display area 1 and the second display area 2 may also be set to n.ltoreq.0.95 m or n.ltoreq.0.9 m. The pixel means a pixel unit capable of emitting white light, that is, one pixel includes RGB sub-pixels or RGBW sub-pixels. When the number difference of pixels in each row of the two display areas is large, the load difference driven by the scanning lines is large, and when delay adjustment is not performed on the first high-level signal and the second high-level signal, the flicker phenomenon is likely to occur due to different feed-through voltages of the pixels 3.

In some embodiments, the first side L1 and the second side L2 of the first display area 1 opposite to each other may be provided with a plurality of first shift register units 10, so as to implement bilateral driving of the same row of sub-pixels 3. Similarly, a plurality of second shift register units 20 may be disposed on the third side L3 and the fourth side L4 disposed opposite to each other in the second display area 2, respectively, to achieve bilateral driving.

Based on the same inventive concept, the embodiment of the application also provides a display panel, which comprises any one of the array substrates provided by the embodiment of the application.

Because the display panel provided in the embodiment of the present application includes any one of the array substrates provided in the embodiment of the present application, the display panel has the technical features corresponding to the array substrate included therein, and can achieve the same effects, which are not described herein again.

The embodiment of the application also provides a display device, please refer to fig. 14, which may be a PC, a television, a display, a mobile terminal, a tablet computer, a wearable device, etc., and the display device may include the display panel provided in the embodiment of the application.

The functional blocks shown in the above-described structural block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. The foregoing is merely a preferred embodiment of the present application, and it should be noted that, due to the limited text expressions, there is objectively no limit to the specific structure, and it will be apparent to those skilled in the art that numerous modifications, adaptations or variations can be made thereto and that the above-described features can be combined in a suitable manner without departing from the principles of the present application; such modifications, variations, or combinations, or the direct application of the concepts and aspects of the present application to other applications without modification, are intended to be within the scope of the present application.

Claims

1. The array substrate is characterized by comprising a first display area and a second display area, wherein the first display area and the second display area comprise a plurality of sub-pixels arranged in an array, and the number of pixels of each row of sub-pixels in the first display area is larger than that of pixels of each row of sub-pixels in the second display area; the array substrate further includes:

the sub-pixels in the second display area are respectively connected with the corresponding second shift register units, and the second shift register units are used for outputting second scanning signals which comprise second low-level signals and second high-level signals; wherein the signal delay of the first high level signal is less than the signal delay of the second high level signal.

2. The array substrate of claim 1, wherein the first shift register unit comprises:

The first logic circuit module is used for outputting a first pulse signal, and the first pulse signal comprises a first signal and a second signal;

the controlled end of the first output module is connected with the first logic circuit module, the first input end of the first output module is connected with the first low-level signal end, and the second input end of the first output module is connected with the first high-level signal end;

the first output module is used for connecting the first input end of the first output module with the output end of the first output module when the first signal is received; and when the second signal is received, connecting the second input end of the first output module with the output end of the first output module.

3. The array substrate of claim 2, wherein the first output module comprises:

the first electrode of the first transistor is connected with the first low-level signal end, the second electrode of the first transistor is connected with the output end of the first output module, and the grid electrode of the first transistor is connected with the first logic circuit module; the first transistor is turned on when receiving a first signal and turned off when receiving a second signal;

The first electrode of the second transistor is connected with the first high-level signal end, the second electrode of the second transistor is connected with the output end of the first output module, and the grid electrode of the second transistor is connected with the first logic circuit module; the second transistor is turned off when receiving the first signal and turned on when receiving the second signal.

4. The array substrate of claim 3, wherein one of the first transistor and the second transistor is a P-type transistor and the other is an N-type transistor.

5. The array substrate of claim 1, wherein the second shift register unit comprises:

the second logic circuit module is used for outputting a second pulse signal, and the second pulse signal comprises a third signal and a fourth signal;

the controlled end of the second output module is connected with the second logic circuit module, the first input end of the second output module is connected with the second low-level signal end, and the second input end of the second output module is connected with the second high-level signal end;

the second output module is used for connecting the first input end of the second output module with the output end of the second output module when the third signal is received; and when the fourth signal is received, connecting the second input end of the second output module with the output end of the second output module.

6. The array substrate of claim 5, wherein the second output module comprises:

a third transistor having a first electrode connected to the second low level signal terminal, a second electrode connected to the output terminal of the second output module, and a gate connected to the first signal output terminal of the second logic circuit module;

the first pole of the fourth transistor is connected with the second high-level signal end, the second pole of the fourth transistor is connected with the output end of the second output module, and the grid electrode of the fourth transistor is connected with the second signal output end of the second logic circuit module;

the third signal is a conducting signal output by the first signal output end of the second logic circuit module, and a cutting-off signal is output by the second signal output end of the second logic circuit module;

the fourth signal is a cut-off signal output by the first signal output end of the second logic circuit module, and a cut-on signal is output by the second signal output end of the second logic circuit module.

7. The array substrate of claim 6, wherein the third transistor and the fourth transistor are each N-type transistors.

8. The array substrate of claim 5, further comprising:

the first end of the first winding is connected with the second input end of the second output module, and the second end of the first winding is connected with the second high-level signal end;

the first winding is used for increasing the equivalent load on the scanning line corresponding to the second shift register unit.

9. The array substrate according to any one of claims 1 to 8, wherein a plurality of the first shift register cells and a plurality of the second shift register cells are sequentially electrically connected.

10. The array substrate according to any one of claims 1 to 8, wherein a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line are provided on the array substrate, two input terminals of the first shift register unit are respectively connected to two of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line, and four input terminals of the second shift register unit are respectively connected to the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line.

11. The array substrate according to any one of claims 1 to 8, wherein the first high-level signal is a power signal and the second high-level signal is a clock signal.

12. The array substrate of any one of claims 1 to 8, wherein the first low-level signal and the second low-level signal are the same low-level signal.

13. The array substrate of any one of claims 1 to 8, wherein the first display region comprises a first side and a second side disposed opposite to each other, the second display region comprises a third side and a fourth side disposed opposite to each other, the second side comprises a first end point near the second display region, the fourth side comprises a second end point far from the first display region, the first end point and the second end point are located on a first line segment, and the fourth side is located on a side of the first line segment near the display region.

14. A display panel, characterized in that it comprises an array substrate according to any one of claims 1 to 13.

15. A display device comprising the display panel of claim 14.