CN108665845A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN108665845A CN108665845A CN201810689236.9A CN201810689236A CN108665845A CN 108665845 A CN108665845 A CN 108665845A CN 201810689236 A CN201810689236 A CN 201810689236A CN 108665845 A CN108665845 A CN 108665845A
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- shift register
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0252—Improving the response speed
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of display panel and display device, display panel, including array substrate；The multi-strip scanning line extended in a first direction in array substrate；Multiple cascade first shift register cells, are electrically connected with odd number horizontal scanning line；Multiple cascade second shift register cells, are electrically connected with even number horizontal scanning line；First clock cable, third clock cable；First clock displacement group；The input terminal of first clock displacement group is connect with the first clock cable and third clock cable, and output end is connect with the clock signal input terminal of the second shift register cell.Display device includes above-mentioned display panel.The present invention can achieve the effect that signal is synchronous and stablizes, improve display quality, to avoid the occurrence of the bad problem of picture display quality caused by signal delay, the ratio of width shared by display panel non-display area signal wire can also be reduced, to realize display panel narrow frame.
Description
Technical field
The present invention relates to display technology fields, more particularly, to a kind of display panel and display device.
Background technology
With the continuous development of science and technology, more and more the electronic equipment with display function is widely used
In daily life and work, huge facility is brought for daily life and work, becomes current
The indispensable important tool of people.Display panel is the critical piece that electronic equipment realizes display function.It is in the prior art
Display panel generally includes：Viewing area and non-display area around viewing area, non-display area is for being arranged some driving circuits, letter
Number line etc..But with the development of display technology, the function of being integrated in display panel is more and more, in corresponding display panel
Signal wire quantity it is also more and more, and the size of drive circuit chip is smaller and smaller, so that signal wire in display panel
The ratio of shared width is increasing, limits the diminution of display floater frame width, is unfavorable for the hair of display panel narrow frame
Exhibition.
Therefore it provides a kind of display panel and display device, can reduce the ratio of width shared by non-display area signal wire,
Realize display panel narrow frame, and be avoided that because signal delay cause influence display function the case where, just become this field skill
Art personnel technical problem urgently to be resolved hurrily.
Invention content
In view of this, the present invention provides a kind of display panel and display device, to solve existing in the prior art ask
Topic.
A kind of display panel disclosed by the invention, including：Array substrate；It is extended in a first direction in array substrate
Multi-strip scanning line；Multiple cascade first shift register cells, are electrically connected with odd number horizontal scanning line；Multiple cascade second move
Bit register unit is electrically connected with even number horizontal scanning line；First clock cable, third clock cable；First Clock-lag
Circuit group；The clock signal input terminal of first shift register cell respectively with the first clock cable and third clock cable
Connection；The input terminal of first clock displacement group is connect with the first clock cable and third clock cable, output end with
The clock signal input terminal of second shift register cell connects.
Invention additionally discloses a kind of display device, including above-mentioned display panel.
Compared with prior art, display panel provided by the invention and display device at least realize following beneficial effect
Fruit：
It is connect with the first clock cable and third clock cable by the input terminal of the first clock displacement group, it is defeated
Outlet is connect with the clock signal input terminal of the second shift register cell, and the first clock displacement group is used for the first clock
The clock signal of signal wire and third clock cable is converted into the clock signal needed for the second shift register cell of driving, and
It is inputted by the clock signal input terminal of the second shift register cell；It can make the first shift register cell and second in this way
The clock signal of shift register cell is inputted from identical first clock cable and third clock cable, and the second displacement
It is synchronous and stablize can to reach signal without in addition connecting other clock cables for the clock signal input terminal of register cell
Effect improves display quality, to avoid the occurrence of the bad problem of picture display quality caused by signal delay, also
The ratio that width shared by display panel non-display area signal wire can be reduced simultaneously, to reduce the border width of display panel,
Further realize display panel narrow frame.
Certainly, implementing any of the products of the present invention specific needs while must not reach above all technique effects.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become apparent.
Description of the drawings
It is combined in the description and the attached drawing of a part for constitution instruction shows the embodiment of the present invention, and even
With its explanation together principle for explaining the present invention.
Fig. 1 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another display panel provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another display panel provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of first clock displacement provided in an embodiment of the present invention；
Fig. 5 is other a kind of structural schematic diagrams of display panel provided in an embodiment of the present invention；
Fig. 6 is a kind of first clock cable provided in an embodiment of the present invention, second clock signal wire, third clock signal
Line, the corresponding sequence diagram of the 4th clock cable；
Fig. 7 is a kind of structure principle chart of shift register provided in an embodiment of the present invention；
Fig. 8 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific implementation mode
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be noted that：Unless in addition having
Body illustrates that the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
It is illustrative to the description only actually of at least one exemplary embodiment below, is never used as to the present invention
And its application or any restrictions that use.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, technology, method and apparatus should be considered as part of specification.
In shown here and discussion all examples, any occurrence should be construed as merely illustrative, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined, then it need not be further discussed in subsequent attached drawing in a attached drawing.
Referring to FIG. 1, Fig. 1 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention, the present embodiment carries
A kind of display panel supplied, including：
Array substrate 00；
The multi-strip scanning line G extended positioned at 00 upper edge first direction X of array substrate；
Multiple cascade first shift register cells 1, are electrically connected with odd number horizontal scanning line G；
Multiple cascade second shift register cells 2, are electrically connected with even number horizontal scanning line G；
First clock cable CKV1, third clock cable CKV3；
First clock displacement group 01；
The clock signal input terminal of first shift register cell 1 respectively with the first clock cable CKV1 and third clock
Signal wire CKV3 connections；
The input terminal of first clock displacement group 01 and the first clock cable CKV1 and third clock cable CKV3
Connection, output end are connect with the clock signal input terminal of the second shift register cell 2.
Specifically, in the present embodiment, multiple cascade first shift register cells 1 of display panel are swept with odd-numbered line
Line G electrical connections are retouched, multiple cascade second shift register cells 2 are electrically connected with even number horizontal scanning line G, wherein so-called odd number
Horizontal scanning line be exactly 1,2,3,4 ... n are numbered to the scan line of every row successively along the direction that scan line is arranged, then, compile
Number it is odd number horizontal scanning line for the scan line of odd number, number is that the scan line of even number is even number horizontal scanning line；Display panel
By the way of this staggeredly driving, so that the signal of display panel both sides driving scan line G is not interfere with each other, interlocks in time,
To achieve the purpose that sequence drives.And the input terminal of the first clock displacement group 01 and the first clock cable CKV1 and third
Clock cable CKV3 connections, output end are connect with the clock signal input terminal of the second shift register cell 2, and the first clock moves
Position circuit group 01 by the clock signal of the first clock cable CKV1 and third clock cable CKV3 for being converted into driving the
Clock signal needed for two shift register cells 2, and it is defeated by the clock signal input terminal of the second shift register cell 2
Enter, such design, the clock signal of the first shift register cell 1 and the second shift register cell 2 can be made from identical
The first clock cable CKV1 and third clock cable CKV3 input, and the clock signal of the second shift register cell 2
Input terminal is not necessarily in addition connect other clock cables, can achieve the effect that signal is synchronous and stablizes, improve display quality,
To avoid the occurrence of the bad problem of picture display quality caused by signal delay.
In some optional embodiments, referring to FIG. 2, Fig. 2 is another display panel provided in an embodiment of the present invention
Structural schematic diagram, in the present embodiment, display panel includes the first area 11 and the second area 12；
First area 11 includes first edge 10, and first edge 10 makes the first area 11 form notch towards the second area 12 recess
100, because notch 100 does not have sub-pixel, the quantity of arbitrary row sub-pixel is less than appointing in the second area 12 in the first area 11
The quantity of meaning row sub-pixel；First area 11 includes the first viewing area AA1, the second viewing area AA2, the first viewing area AA1 and second
Viewing area AA2 is located at the both sides of the notch 100 on first direction X；Second area 12 includes third viewing area AA3；
Scan line G includes the first scan line G1, the second scan line G2, third scan line G3, and the first scan line G1 is located at the
One viewing area AA1, the second scan line G2 are located at the second viewing area AA2, and third scan line G3 is located at third viewing area AA3；
Display panel further includes non-display area BB, and non-display area BB is around the first viewing area AA1, the second viewing area AA2, the
Three viewing area AA3 are arranged；Non-display area BB includes the first non-display area BB1, the second non-display area BB2；
In a first direction on X, the first non-display area BB1 is located at the first sides of the viewing area AA1 far from notch 100, and second
Non-display area BB2 is located between notch 100 and the first viewing area AA1；
First shift register cell 1 is located at the first non-display area BB1, and with the first scan line G1 and odd number of odd-numbered line
Capable third scan line G3 connections；
Second shift register cell 2 is located at the second non-display area BB2, and is connect with the first scan line G1 of even number line.
In the present embodiment, the first clock displacement group 01 is applied to the notched display panel of abnormity shown in Fig. 2
In, the function of the first clock displacement group 01 shown in FIG. 1 can be not only brought, therefore not to repeat here for principle, can refer to
The explanation of embodiment illustrated in fig. 1, you can to achieve the effect that signal is synchronous and stablizes, promote display quality, avoid the occurrence of due to
The bad problem of picture display quality caused by signal delay can also avoid for example, the first non-display area BB1's first moves
Bit register unit 1 is needed through bracing wire to third non-display area BB3, is used for driving the first scan line of even number line G1's with access
Clock signal reduces the ratio of width shared by 100 corresponding non-display area signal wire of notch, to reduce abnormity band notch
Display panel border width, realize display panel narrow frame.
In some optional embodiments, with continued reference to FIG. 2, in the present embodiment, the first scan line G1 and the second scan line
G2 is not attached to.
The present embodiment is further defined along first direction X, the notch both sides of the notched display panel of the abnormity
Scan line G be not attached to, further explained the scan line G of setting knot to(for) the notched display panel of the abnormity
Structure.
In some optional embodiments, referring to FIG. 3, Fig. 3 is another display panel provided in an embodiment of the present invention
Structural schematic diagram, in the present embodiment, the first area 11 further includes the 5th non-display area BB5；
5th non-display area BB5 is located at the first sides of the viewing area AA1 far from third viewing area AA3 on second direction Y,
First clock displacement group 01 is located in the 5th non-display area BB5, and the first clock displacement group 01 is moved including the first clock
Position circuit 011 and second clock shift circuit 012.
In the present embodiment, it is non-aobvious to further illustrate the first clock displacement group 01 is set on display panel the 5th
Show area BB5, the clock signal of the first clock cable CKV1 and third clock cable CKV3 are converted into driving second
Clock signal needed for shift register cell 2, make the first shift register cell 1 and the second shift register cell 2 when
Clock signal is inputted from identical first clock cable CKV1 and third clock cable CKV3.Meanwhile specifically illustrating first
Clock displacement group 01 includes the first clock displacement 011 and second clock shift circuit 012, when being respectively used to first
The clock signal of clock signal wire CKV1 and third clock cable CKV3 are converted into needed for the second shift register cell 2 of driving
Clock signal, and inputted by two clock signal input terminals of the second shift register cell 2.
In some optional embodiments, with continued reference to FIG. 2, in the present embodiment, non-display area BB further includes that third is non-aobvious
Show area BB3, the 4th non-display area BB4；
In a first direction on X, the 4th non-display area BB4 is located at the second viewing area AA2 far from 100 side of notch, and third is non-
Viewing area BB3 is located between notch 100 and the second viewing area AA2；
Multiple cascade third shift register cells 3, third shift register cell 3 are located at third non-display area BB3,
And it is connect with the second scan line G2 of odd-numbered line；
Multiple cascade 4th shift register cells 4, the 4th shift register cell 4 are located at the 4th non-display area BB4,
And it is connect with the third scan line G3 of the second scan line G2 of even number line and even number line；
Second clock signal wire CKV2, the 4th clock cable CKV4；
Second clock shift circuit group 02；
The clock signal input terminal of 4th shift register cell 4 respectively with second clock signal wire CKV2 and the 4th clock
Signal wire CKV4 connections；
The input terminal of second clock shift circuit group 02 respectively with second clock signal wire CKV2 and the 4th clock cable
CKV4 connections, output end are connect with the clock signal input terminal of third shift register cell 3.
In the present embodiment, second clock shift circuit group 02 is applied to the notched display panel of abnormity shown in Fig. 2
In, multiple cascade first shift register cells 3 of display panel are connect with the second scan line G2 with odd-numbered line, Duo Geji
Second shift register cell 4 of connection is connect with the third scan line G3 of the second scan line G2 of even number line and even number line, and
The input terminal of second clock shift circuit group 02 is connect with second clock signal wire CKV2 and the 4th clock cable CKV4, output
End is connect with the clock signal input terminal of third shift register cell 3, when second clock shift circuit group 02 is used for second
The clock signal of clock signal wire CKV2 and the 4th clock cable CKV4 are converted into needed for driving third shift register cell 3
Clock signal, and inputted by the clock signal input terminal of third shift register cell 3, such design can make third
The clock signal of shift register cell 3 and the 4th shift register cell 4 is from identical second clock signal wire CKV2 and
Four clock cable CKV4 inputs, and in addition the clock signal input terminal of third shift register cell 3 is without when connecting other
Clock signal wire achievees the effect that signal is synchronous and stablizes, display quality is improved, to avoid the occurrence of since signal prolongs
The bad problem of caused picture display quality late, can also reduce notch both sides display panel non-display area signal wire simultaneously
It is narrow to further realize display panel to reduce the border width of the notched display panel of the abnormity for the ratio of shared width
Frame.
In some optional embodiments, with continued reference to FIG. 3, in the present embodiment, the first area 11 further includes the 6th non-display
Area BB6；
6th non-display area BB6 is located at the second sides of the viewing area AA2 far from third viewing area AA3 on second direction Y,
Second clock shift circuit group 02 is located in the 6th non-display area BB6, and second clock shift circuit group 02 is moved including third clock
Position circuit 021 and the 4th clock displacement 022.
In the present embodiment, it is non-aobvious to further illustrate the second clock shift circuit group 02 is set on display panel the 6th
Show area BB6, the clock signal of second clock signal wire CKV2 and the 4th clock cable CKV4 are converted into driving third
Clock signal needed for shift register cell 3, make third shift register cell 3 and the 4th shift register cell 4 when
Clock signal is inputted from identical second clock signal wire CKV2 and the 4th clock cable CKV4.Meanwhile specifically illustrating second
Clock displacement group 02 includes third clock displacement 021 and the 4th clock displacement 022, when being respectively used to second
The clock signal of clock signal wire CKV2 and the 4th clock cable CKV4 are converted into needed for driving third shift register cell 3
Clock signal, and inputted by two clock signal input terminals of third shift register cell 3.
In some optional embodiments, referring to FIG. 4, Fig. 4 is a kind of first Clock-lag provided in an embodiment of the present invention
The structural schematic diagram of circuit 011, in the present embodiment, the first clock displacement 011 includes first input end input1, second defeated
Enter to hold input2, first switch transistor T1, second switch transistor T2, first voltage signal end VGL, second voltage signal end
VGH, phase inverter 0111, clock reverser 0112, the first output end output；
The grid of first switch transistor T1 is connect with first input end input1, source electrode and first voltage signal end VGL
Connection, drain electrode are connect with 0112 first end of clock reverser；
0112 second end of clock reverser is connect with the first output end output, 0112 third end of clock reverser and first
Input terminal input1 connections；
0111 first end of phase inverter is connect with first input end input1,0111 second end of phase inverter and clock reverser
0112 the 4th end connects；
The grid of second switch transistor T2 is connect with the second input terminal input2, source electrode and second voltage signal end VGH
Connection, drain electrode are connect with 0112 first end of clock reverser.
In the present embodiment, the specific of the first clock displacement 011 used in above-described embodiment is further illustrated
Circuit structure；
Wherein, first input end input1 is connect with the grid of first switch transistor T1, to control first switch crystalline substance
The on or off of body pipe T1, when conducting, by the signal transmission of first voltage signal end VGL to clock reverser 0,112 first
End；
Second input terminal input2 is connect with the grid of second switch transistor T2, to control second switch transistor T2
On or off, when conducting, by the signal transmission of second voltage signal end VGH to 0112 first end of clock reverser；
The current potential of the first end of phase inverter 0111 and the second end of phase inverter 0111 is on the contrary, even the first of phase inverter 0111
End input is high potential, then the second end output of phase inverter 0111 is low potential, and vice versa；
Clock reverser 0112 is low potential there are two types of working condition, even 0112 third end of clock reverser, and clock is anti-
When to the 4th end of device 0112 being high potential, it is equivalent to a phase inverter, i.e. 0112 first end of clock reverser and clock reverser
The current potential of 0112 second end is opposite；If 0112 third end of clock reverser is high potential, the 4th end of clock reverser 0112 is low
When current potential, the output of 0112 second end of clock reverser is unrelated with 0112 first end of clock reverser, clock reverser 0,112
Two ends are equivalent to hanging open circuit.
In some optional embodiments, with continued reference to FIG. 4, in the present embodiment, the first clock displacement 011, second
Clock displacement 012, third clock displacement 021,022 structure of the 4th clock displacement are identical, i.e. the first clock moves
Position circuit 011, second clock shift circuit 012, third clock displacement 021, the connection of 022 circuit of the 4th clock displacement
Structure is identical, to realize the function of identical change over clock signal.
In some optional embodiments, with continued reference to FIG. 4, in the present embodiment, first switch transistor T1, second switch
Transistor T2 is N-type switching transistor.
In the present embodiment, first switch transistor T1 is further defined, second switch transistor T2 is that N-type switch is brilliant
Body pipe, when the input of the grid of the grid of first switch transistor T1, second switch transistor T2 is high potential signal, first opens
Pass transistor T1, second switch transistor T2 are just connected, and otherwise end.
It should be noted that the present embodiment is merely illustrative of first switch transistor T1, second switch transistor T2
Type, first switch transistor T1, second switch transistor T2 are alternatively p-type switching transistor, and those skilled in the art can root
The circuit of the present embodiment is adjusted for different types of switching transistor according to actual conditions, to realize that the circuit is identical
The function of conversion signal, above well known to a person skilled in the art the regulation of electrical circuit within protection domain of the embodiment of the present invention.
In some optional embodiments, with continued reference to FIG. 4, in the present embodiment, the of first voltage signal end VGL input
One voltage signal is low potential, and the second voltage signal of second voltage signal end VGH inputs is high potential.
In the present embodiment, the first voltage signal for further defining the VGL inputs of first voltage signal end is low potential, the
The second voltage signal of two voltage signal end VGH inputs is high potential, i.e. 0112 first end of clock reverser, passes through first switch
The control of transistor T1, second switch transistor T2 on or off, can input different high potential or low-potential signal,
To the signal for making the first output end output outputs being connect with 0112 second end of clock reverser need.
In some optional embodiments, referring to FIG. 5, Fig. 5 is other a kind of display panels provided in an embodiment of the present invention
Structural schematic diagram, for the circuit connection structure of clear signal the present embodiment, the notch and array base of the display panel in Fig. 5
Plate is not illustrated, and understands the display panel of the present embodiment other structures for not illustrating in combination with Fig. 3；In the present embodiment, when first
The first input end input1 of clock shift circuit 011 is connect with the first clock cable CKV1, the second input terminal input2 and
Three clock cable CKV3 connections, a clock signal input of the first output end output and the second shift register cell 2
End connection；
The first input end input1 of second clock shift circuit 012 is connect with third clock cable CKV3, and second is defeated
Enter to hold input2 to be connect with the first clock cable CKV1, the first output end output is another with the second shift register cell 2
One clock signal input terminal connection；
The first input end input1 of third clock displacement 021 is connect with second clock signal wire CKV2, and second is defeated
Enter to hold input2 to be connect with the 4th clock cable CKV4, the first output end output and the one of third shift register cell 3
A clock signal input terminal connection；
The first input end input1 of 4th clock displacement 022 is connect with the 4th clock cable CKV4, and second is defeated
Enter to hold input2 to be connect with second clock signal wire CKV2, the first output end output is another with third shift register cell 3
One clock signal input terminal connection.
In the present embodiment, when further illustrating the first clock displacement 011, second clock shift circuit 012, third
Clock shift circuit 021, the 4th clock displacement 022 are how to be connect with clock cable, to complete the first clock signal
Line CKV1 and third clock cable CKV3 be converted into it is needed for the second shift register cell 2 and with second clock signal wire
The identical clock signal of clock signal that CKV2, the 4th clock cable CKV4 are exported.
Specifically, for the clearer technical solution for explaining the present embodiment, referring to FIG. 6, Fig. 6 is implementation of the present invention
The first clock cable of one kind CKV1, second clock signal wire CKV2, third clock cable CKV3, the 4th clock of example offer
The corresponding sequence diagrams of signal wire CKV4, the present embodiment further explain above-mentioned Clock-lag electricity with sequence diagram shown in fig. 6
The operation principle on road.
It is illustrated as shown in fig. 6, the sequence diagram can be divided into seven periods of t0-t6, in the present embodiment, for convenience of saying
It is bright, high potential is defined as 1, low potential is defined as 0, by taking the connection structure of the first clock displacement 011 as an example, the first clock
The first input end input1 of shift circuit 011 is connect with the first clock cable CKV1, the second input terminal input2 and third
First output end of clock cable CKV3 connections, the first clock displacement 011 is output1, then：
The t0 stages, input1 0, input2 0, although clock reverser 0112 is connected, first switch transistor
T1 and second switch transistor T2 are turned off, and are inputted without signal, therefore output1 is 0；
T1 stages, input1 1, input2 0, although the T1 conductings of first switch transistor, first voltage signal end VGL
Low potential 0 be transmitted to 0112 first end of clock reverser, but clock reverser 0112 is opened a way, therefore output1 is still 0；
T2 stages, input1 0, input2 0, clock reverser 0112 are connected, due to clock reverser 0112 at this time
First end is 0, so output1 is 1；
T3 stages, input1 0, input2 1, clock reverser 0112 are connected, the T1 cut-offs of first switch transistor, the
Two switching transistor T2 conductings, the high potential 1 of second voltage signal end VGH are transmitted to 0112 first end of clock reverser, clock
0112 first end of reverser is pulled to 1, so output1 is 0；
T4 stages, input1 0, input2 0, clock reverser 0112 are connected, and first switch transistor T1, second open
It closes transistor T2 to be turned off, since 0112 first end of clock reverser is 1 at this time, so output1 is 0；
The t5 stages, input1 1, input2 0, the T1 conductings of first switch transistor, the T2 cut-offs of second switch transistor,
0112 first end of clock reverser is by first voltage signal end VGL down for 0 at this time, but clock reverser 0112 is opened a way, institute
With output1 for 0；
T6 stages, input1 0, input2 0, clock reverser 0112 are connected, and first switch transistor T1, second open
It closes transistor T2 to be turned off, since 0112 first end of clock reverser is 0 at this time, so output1 is 1；
It continues cycling through below.
From the foregoing, it will be observed that by the first clock displacement 011 by the first clock cable CKV1 and third clock cable
The signal of CKV3 can be exchanged into the clock signal consistent with the signal of second clock signal wire CKV2 outputs, for being shifted with second
One clock signal input terminal of register cell 2 connects.
It should be noted that the present embodiment at this to second clock shift circuit 012, third clock displacement 021,
The operation principle of four clock displacements 022 does not repeat, and those skilled in the art can pass through above first clock displacement
011 explanation combines sequence diagram shown in fig. 6, and the first output end of second clock shift circuit 012 is output2, when third
First output end of clock shift circuit 021 is output3, and the first output end of the 4th clock displacement 022 is output4,
It can be seen that second clock shift circuit 012 is to convert the signal of third clock cable CKV3 and the first clock cable CKV1
For the signal of the clock signal, that is, output2 output consistent with the signal of the 4th clock cable CKV4 outputs, it is used for and second
Another clock signal input terminal of shift register cell 2 connects；Third clock displacement 021 is by second clock signal
When the signal of line CKV2 and the 4th clock cable CKV4 are converted to consistent with the signal of the first clock cable CKV1 output
The signal of clock signal, that is, output3 outputs, for being connect with a clock signal input terminal of third shift register cell 3；
4th clock displacement 022 is to be converted to the signal of the 4th clock cable CKV4 and second clock signal wire CKV2 and the
The signal of the consistent clock signal, that is, output4 outputs of signal of three clock cable CKV3 outputs, for being posted with third displacement
Another clock signal input terminal of storage unit 3 connects.
In some optional embodiments, incorporated by reference to being a kind of displacement provided in an embodiment of the present invention with reference to figure 5 and Fig. 7, Fig. 7
The structure principle chart of register, in the present embodiment,
First shift register cell 1, the second shift register cell 2, third shift register cell the 3, the 4th shift
Register cell 4 includes identical shift register；
Shift register includes the first signal output end OUT1, second signal output end OUT2, signal input part STV, the
One clock signal input terminal CLK1, second clock signal input part CLK2；
It is connect with scan line G per the first signal output end OUT1 of level-one shift register；
Per the signal input part STV of the second signal output end OUT2 and next stage shift register of level-one shift register
Connection；
First clock signal input terminal CLK1 of the first shift register cell 1 of odd level and third clock cable
CKV3 connections, second clock signal input part CLK2 are connect with the first clock cable CKV1；First shift LD of even level
First clock signal input terminal CLK1 of device unit 1 is connect with the first clock cable CKV1, second clock signal input part
CLK2 is connect with third clock cable CKV3；
First clock signal input terminal CLK1 of the second shift register cell 2 of odd level and second clock shift circuit
012 the first output end output connections, the first of second clock signal input part CLK2 and the first clock displacement 011 are defeated
Outlet output connections；The the first clock signal input terminal CLK1 and the first clock of second shift register cell 2 of even level
First output end output connections of shift circuit 011, second clock signal input part CLK2 and second clock shift circuit 012
The first output end output connections；
First clock signal input terminal CLK1 of the third shift register cell 3 of odd level and the 4th clock displacement
022 the first output end output connections, the first of second clock signal input part CLK2 and third clock displacement 021 are defeated
Outlet output connections；First clock signal input terminal CLK1 of the third shift register cell 3 of even level and third clock
First output end output connections of shift circuit 021, second clock signal input part CLK2 and the 4th clock displacement 022
The first output end output connections；
The the first clock signal input terminal CLK1 and the 4th clock cable of 4th shift register cell 4 of odd level
CKV4 connections, second clock signal input part CLK2 are connect with second clock signal wire CKV2；4th shift LD of even level
First clock signal input terminal CLK1 of device unit 4 is connect with second clock signal wire CKV2, second clock signal input part
CLK2 is connect with the 4th clock cable CKV4.
In the present embodiment, further explained four shift register cells and four clock cables, four when
The specific connection structure of clock shift circuit, it should be noted that the present embodiment is not only to disclose one of the above connection structure, but not
It is only limitted to this structure, or well known to a person skilled in the art other structures, therefore not to repeat here for the present embodiment.
In some optional embodiments, please continue to refer to Fig. 5 and Fig. 7, in the present embodiment, the letter of first order shift register
Number input terminal STV input starting shift signals.
In the present embodiment, the signal input part STV input starting shift signals of first order shift register, for that will show
The starting shift signal that driving chip on panel provides is transmitted to shift register.
In some optional embodiments, please continue to refer to Fig. 5 and Fig. 7, in the present embodiment, shift register further includes resetting
RST, reset terminal RST is held to be connect with reseting signal line, the reset that reset terminal RST is used to provide the driving chip on display panel
Signal transmission is to shift register, to realize that the reset of each shift register cell operates.
In some optional embodiments, with continued reference to FIG. 6, in the present embodiment, when the first clock cable CKV1, second
The pulse for the effective impulse signal that clock signal wire CKV2, third clock cable CKV3, the 4th clock cable CKV4 are exported is wide
Spend L and cycle T all same.
Specifically, the failing edge and second clock signal wire of the effective impulse signal of the first clock cable CKV1 outputs
The rising edge alignment of the effective impulse signal of CKV2 outputs, the decline of the effective impulse signal of second clock signal wire CKV2 outputs
The rising edge alignment on edge and the effective impulse signal of third clock cable CKV3 outputs, the CKV3 outputs of third clock cable
The rising edge alignment of the failing edge of effective impulse signal and the effective impulse signal of the 4th clock cable CKV4 outputs, when the 4th
The effective impulse signal of the failing edge of the effective impulse signal of clock signal wire CKV4 outputs and the first clock cable CKV1 outputs
Rising edge alignment.
In the present embodiment, the effective impulse signal equivalent width for making four clock cables export can make display panel
Trace interval is consistent, plays the role of stable scan line driving signal.
In some optional embodiments, referring to FIG. 8, Fig. 8 is a kind of display device 0000 provided in an embodiment of the present invention
Structural schematic diagram, display device 0000 provided in this embodiment, include the above embodiment of the present invention provide display panel
000.Fig. 8 embodiments illustrate display device 0000, it is to be understood that the embodiment of the present invention carries only by taking mobile phone as an example
The display device 0000 of confession can be other display devices with display function such as computer, TV, display device for mounting on vehicle
0000, the present invention is not specifically limited this.Display device 0000 provided in an embodiment of the present invention, carries with the embodiment of the present invention
The advantageous effect of the display panel 000 of confession can specifically refer to the various embodiments described above illustrating for display panel 000,
Details are not described herein for the present embodiment.
By above-described embodiment it is found that display panel provided by the invention and display device, at least realizing following has
Beneficial effect：
It is connect with the first clock cable and third clock cable by the input terminal of the first clock displacement group, it is defeated
Outlet is connect with the clock signal input terminal of the second shift register cell, second clock shift circuit group input terminal and when second
Clock signal wire and the connection of the 4th clock cable, output end are connect with the clock signal input terminal of third shift register cell；
First clock displacement group is used to the clock signal of the first clock cable and third clock cable being converted into driving the
Clock signal needed for two shift register cells, and inputted by the clock signal input terminal of the second shift register cell,
Second clock shift circuit group is used to the clock signal of second clock signal wire and the 4th clock cable being converted into driving the
Clock signal needed for three shift register cells, and inputted by the clock signal input terminal of third shift register cell；
The clock signal of first shift register cell and the second shift register cell can in this way believed from identical first clock
Number line and the input of third clock cable, the clock signal slave phase of third shift register cell and the 4th shift register cell
Same second clock signal wire and the input of the 4th clock cable, and the clock signal input terminal of the second shift register cell,
The clock signal input terminal of third shift register cell can reach signal synchronization without in addition connecting other clock cables
With stable effect, display quality is improved, it is bad to avoid the occurrence of picture display quality caused by signal delay
The problem of, the ratio of width shared by the display panel non-display area signal wire of notch both sides can also be reduced simultaneously, it should to reduce
The border width of the notched display panel of abnormity, further realizes display panel narrow frame.
Although some specific embodiments of the present invention are described in detail by example, the skill of this field
Art personnel it should be understood that example above merely to illustrating, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above example.This hair
Bright range is defined by the following claims.
Claims (17)
1. a kind of display panel, which is characterized in that including：
Array substrate；
The multi-strip scanning line extended in a first direction in the array substrate；
Multiple cascade first shift register cells, are electrically connected with scan line described in odd-numbered line；
Multiple cascade second shift register cells, are electrically connected with scan line described in even number line；
First clock cable, third clock cable；
First clock displacement group；
The clock signal input terminal of first shift register cell respectively with first clock cable and the third
Clock cable connects；
The input terminal of the first clock displacement group connects with first clock cable and the third clock cable
It connects, output end is connect with the clock signal input terminal of second shift register cell.
2. display panel according to claim 1, which is characterized in that the display panel includes the firstth area and the secondth area；
Firstth area includes first edge, and so that firstth area is formed scarce towards secondth area recess for the first edge
Mouthful；Quantity of the quantity of arbitrary row sub-pixel less than the arbitrary row sub-pixel in secondth area in firstth area；Described
One area includes the first viewing area, the second viewing area, and first viewing area and second viewing area are located at along described the
The both sides of the notch on one direction；Secondth area includes third viewing area；
The scan line includes the first scan line, the second scan line, third scan line, and first scan line is located at described first
Viewing area, second scan line are located at second viewing area, and the third scan line is located at the third viewing area；
The display panel further includes non-display area, the non-display area around first viewing area, second viewing area,
The third viewing area setting；The non-display area includes the first non-display area, the second non-display area；
In said first direction, first non-display area is located at the side of first viewing area far from the notch, institute
The second non-display area is stated between the notch and first viewing area；
First shift register cell is located at first non-display area, and with first scan line of odd-numbered line and strange
Several rows of third scan line connection；
Second shift register cell is located at second non-display area, and connects with first scan line of even number line
It connects.
3. display panel according to claim 2, which is characterized in that first scan line and second scan line are not
It is connected.
4. display panel according to claim 2, which is characterized in that firstth area further includes the 5th non-display area；
5th non-display area is located at side of first viewing area far from the third viewing area in second direction, institute
It states the first clock displacement group to be located in the 5th non-display area, the first clock displacement group includes the first clock
Shift circuit and second clock shift circuit.
5. display panel according to claim 4, which is characterized in that the non-display area further include third non-display area,
4th non-display area；
In said first direction, the 4th non-display area is located at second viewing area far from the notch side, described
Third non-display area is between the notch and second viewing area；
Multiple cascade third shift register cells, the third shift register cell are located at the third non-display area,
And it is connect with second scan line of odd-numbered line；
Multiple cascade 4th shift register cells, the 4th shift register cell are located at the 4th non-display area,
And it is connect with the third scan line of second scan line of even number line and even number line；
Second clock signal wire, the 4th clock cable；
Second clock shift circuit group；
The clock signal input terminal of 4th shift register cell respectively with the second clock signal wire and the described 4th
Clock cable connects；
The input terminal of the second clock shift circuit group respectively with the second clock signal wire and the 4th clock signal
Line connects, and output end is connect with the clock signal input terminal of the third shift register cell.
6. display panel according to claim 5, which is characterized in that firstth area further includes the 6th non-display area；
6th non-display area is located at one of second viewing area in the second direction far from the third viewing area
Side, the second clock shift circuit group are located in the 6th non-display area, and the second clock shift circuit group includes the
Three clock displacements and the 4th clock displacement.
7. display panel according to claim 6, which is characterized in that first clock displacement includes the first input
It is end, the second input terminal, first switch transistor, second switch transistor, first voltage signal end, second voltage signal end, anti-
Phase device, clock reverser, the first output end；
The grid of the first switch transistor is connect with the first input end, and source electrode connects with the first voltage signal end
It connects, drain electrode is connect with the clock reverser first end；
The clock reverser second end is connect with first output end, the clock reverser third end and described first defeated
Enter end connection；
The phase inverter first end is connect with the first input end, the phase inverter second end and the clock reverser the 4th
End connection；
The grid of the second switch transistor is connect with second input terminal, and source electrode connects with the second voltage signal end
It connects, drain electrode is connect with the clock reverser first end.
8. display panel according to claim 7, which is characterized in that first clock displacement, it is described second when
Clock shift circuit, the third clock displacement, the 4th clock displacement structure are identical.
9. display panel according to claim 7, which is characterized in that the first switch transistor, the second switch
Transistor is N-type switching transistor.
10. display panel according to claim 7, which is characterized in that the first electricity of the first voltage signal end input
Pressure signal is low potential, and the second voltage signal of the second voltage signal end input is high potential.
11. display panel according to claim 8, which is characterized in that
The first input end of first clock displacement is connect with first clock cable, the second input terminal with it is described
Third clock cable connects, and a clock signal input terminal of the first output end and second shift register cell connects
It connects；
The first input end of the second clock shift circuit is connect with the third clock cable, the second input terminal with it is described
First clock cable connects, another clock signal input terminal of the first output end and second shift register cell connects
It connects；
The first input end of the third clock displacement is connect with the second clock signal wire, the second input terminal with it is described
4th clock cable connects, and a clock signal input terminal of the first output end and the third shift register cell connects
It connects；
The first input end of 4th clock displacement is connect with the 4th clock cable, the second input terminal with it is described
Second clock signal wire connects, another clock signal input terminal of the first output end and the third shift register cell connects
It connects.
12. display panel according to claim 11, which is characterized in that
It is first shift register cell, second shift register cell, the third shift register cell, described
4th shift register cell includes identical shift register；
The shift register is defeated including the first signal output end, second signal output end, signal input part, the first clock signal
Enter end, second clock signal input part；
First signal output end of shift register described in per level-one is connect with the scan line；
The signal of the second signal output end of shift register and shift register described in next stage described in per level-one
Input terminal connects；
First clock signal input terminal of first shift register cell of odd level connects with the third clock cable
It connects, second clock signal input part is connect with first clock cable；First shift register cell of even level
The first clock signal input terminal connect with first clock cable, second clock signal input part and the third clock
Signal wire connects；
First clock signal input terminal of second shift register cell of odd level and the second clock shift circuit
The connection of the first output end, second clock signal input part connect with the first output end of first clock displacement；It is even
First clock signal input terminal of second shift register cell of several levels and the first of first clock displacement
Output end connects, and second clock signal input part is connect with the first output end of the second clock shift circuit；
First clock signal input terminal of the third shift register cell of odd level and the 4th clock displacement
The connection of the first output end, second clock signal input part connect with the first output end of the third clock displacement；It is even
First clock signal input terminal of the third shift register cell of several levels and the first of the third clock displacement
Output end connects, and second clock signal input part is connect with the first output end of the 4th clock displacement；
First clock signal input terminal of the 4th shift register cell of odd level connects with the 4th clock cable
It connects, second clock signal input part is connect with the second clock signal wire；The 4th shift register cell of even level
The first clock signal input terminal connect with the second clock signal wire, second clock signal input part and the 4th clock
Signal wire connects.
13. display panel according to claim 12, which is characterized in that the signal of shift register described in the first order
Input terminal input starting shift signal.
14. display panel according to claim 12, which is characterized in that the shift register further includes reset terminal, institute
Reset terminal is stated to connect with reseting signal line.
15. display panel according to claim 12, which is characterized in that first clock cable, it is described second when
Clock signal wire, the third clock cable, the 4th clock cable output effective impulse signal pulse width and
Period all same.
16. display panel according to claim 15, which is characterized in that effective arteries and veins of the first clock cable output
Rush the rising edge alignment of the failing edge and the effective impulse signal of second clock signal wire output of signal, the second clock
The rising of the failing edge of the effective impulse signal of signal wire output and the effective impulse signal of third clock cable output
Along alignment, failing edge and the 4th clock cable output of the effective impulse signal of the third clock cable output
The rising edge alignment of effective impulse signal, the failing edge of the effective impulse signal of the 4th clock cable output and described the
The rising edge alignment of the effective impulse signal of one clock cable output.
17. a kind of display device, which is characterized in that including claim 1-16 any one of them display panels.
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| CN201810689236.9A CN108665845B (en) | 2018-06-28 | 2018-06-28 | Display panel and display device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377929A (en) * | 2018-11-22 | 2019-02-22 | 南京中电熊猫平板显示科技有限公司 | A kind of gate driving circuit and special-shaped screen display panel |
| CN109935173A (en) * | 2019-03-29 | 2019-06-25 | 上海天马微电子有限公司 | A kind of display module and display device |
| CN113011353A (en) * | 2021-03-25 | 2021-06-22 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113593462A (en) * | 2021-07-28 | 2021-11-02 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN113781913A (en) * | 2021-09-10 | 2021-12-10 | 厦门天马显示科技有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060187175A1 (en) * | 2005-02-23 | 2006-08-24 | Wintek Corporation | Method of arranging embedded gate driver circuit for display panel |
| CN103928001A (en) * | 2013-12-31 | 2014-07-16 | 上海天马微电子有限公司 | Grid driving circuit and display device |
| CN105527739A (en) * | 2014-10-16 | 2016-04-27 | 乐金显示有限公司 | Panel array for display device with narrow bezel |
| CN107123388A (en) * | 2017-06-29 | 2017-09-01 | 厦门天马微电子有限公司 | A kind of array base palte and display device |
| CN107403604A (en) * | 2016-05-19 | 2017-11-28 | 三星显示有限公司 | Display device |
-
2018
- 2018-06-28 CN CN201810689236.9A patent/CN108665845B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060187175A1 (en) * | 2005-02-23 | 2006-08-24 | Wintek Corporation | Method of arranging embedded gate driver circuit for display panel |
| CN103928001A (en) * | 2013-12-31 | 2014-07-16 | 上海天马微电子有限公司 | Grid driving circuit and display device |
| CN105527739A (en) * | 2014-10-16 | 2016-04-27 | 乐金显示有限公司 | Panel array for display device with narrow bezel |
| CN107403604A (en) * | 2016-05-19 | 2017-11-28 | 三星显示有限公司 | Display device |
| CN107123388A (en) * | 2017-06-29 | 2017-09-01 | 厦门天马微电子有限公司 | A kind of array base palte and display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109377929A (en) * | 2018-11-22 | 2019-02-22 | 南京中电熊猫平板显示科技有限公司 | A kind of gate driving circuit and special-shaped screen display panel |
| CN109935173A (en) * | 2019-03-29 | 2019-06-25 | 上海天马微电子有限公司 | A kind of display module and display device |
| CN109935173B (en) * | 2019-03-29 | 2021-10-26 | 上海天马微电子有限公司 | Display module and display device |
| CN113011353A (en) * | 2021-03-25 | 2021-06-22 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113011353B (en) * | 2021-03-25 | 2022-10-11 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113593462A (en) * | 2021-07-28 | 2021-11-02 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN113593462B (en) * | 2021-07-28 | 2024-03-22 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN113781913A (en) * | 2021-09-10 | 2021-12-10 | 厦门天马显示科技有限公司 | Display panel and display device |
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|---|---|
| CN108665845B (en) | 2021-04-30 |
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