CN114333731A

CN114333731A - Scanning driving circuit and array substrate

Info

Publication number: CN114333731A
Application number: CN202111676601.0A
Authority: CN
Inventors: 金秉勋; 卢昭阳; 田尚益; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12
Anticipated expiration: 2041-12-31
Also published as: CN114333731B

Abstract

The embodiment of the application discloses a scanning drive circuit, which comprises n scanning drive units and two virtual scanning drive units which are sequentially arranged and cascaded, wherein each scanning drive unit is used for outputting two scanning drive signals with preset time intervals, and each virtual scanning drive unit is used for outputting two stage transmission signals with preset time intervals. The two virtual scanning driving units are respectively connected with the (n-1) th scanning driving unit and the nth scanning driving unit and respectively output two second-stage transmission signals to the (n-1) th scanning driving unit and the nth scanning driving unit so as to drive the scanning driving units to output scanning driving signals. The virtual scanning driving unit is only needed to be arranged at the tail end of the cascaded scanning driving units to control the stage transmission of the scanning driving signals, so that the number of the virtual scanning driving units and the occupied space are effectively reduced. The embodiment of the application also discloses an array substrate comprising the scanning driving circuit.

Description

Scanning driving circuit and array substrate

Technical Field

The present application relates to the field of display technologies, and in particular, to a scan driving circuit and an array substrate for use in a display panel.

Background

Liquid crystal displays have been widely used in many fields because of their thin body, power saving, non-radiative, and other advantages. Such as: liquid crystal televisions, mobile phones, electronic watches, digital cameras, computer screens, and the like.

The GDL Circuit (less Gate Driver technology) is a driving Circuit for horizontal scanning lines of the original array process of the lcd panel fabricated on the substrate around the display area, so that the GDL Circuit can replace an external IC (Integrated Circuit) to drive the horizontal scanning lines. The GDL technology reduces the welding process of an external IC, improves the productivity, reduces the product cost and enables the liquid crystal display panel to develop towards the main stream appearance direction of a narrow frame or no frame.

At present, two opposite sides of a display panel are respectively provided with a GDL circuit, and the GDL circuits on the two opposite sides are used for outputting corresponding scanning driving signals in a matching manner. The GDL circuits on each side are connected in a cascade connection mode. In order to characterize the cascade of GDL circuits at the head and tail positions among the GDL circuits, a dummy GDL circuit that does not need to output a scan driving signal but is used only for cascade driving needs to be additionally provided at the head and tail positions. Obviously, the way of setting the virtual GDL circuits end to end easily causes the wiring space of the display panel to be limited, and simultaneously, the design space of the narrow frame of the display panel is limited.

Disclosure of Invention

In view of the shortcomings of the prior art, the present application proposes a scan driving circuit and an array substrate that occupy a small space.

The embodiment of the application provides a scanning drive circuit, including arranging and cascaded n scanning drive unit and two virtual scanning drive units in proper order, every scanning drive unit is used for exporting the scanning drive signal of two interval default times, every virtual scanning drive unit is used for exporting the stage biography signal of two interval default times. The x-th scanning driving unit is cascaded to the x-2 th scanning driving unit, the x-th scanning driving unit outputs two first-stage transmission signals to the x-2 th scanning driving unit, and x is more than 2 and less than or equal to n. The two virtual scanning driving units are respectively connected with the nth-1 level scanning driving unit and the nth level scanning driving unit and respectively output two second level transmission signals to the nth-1 level scanning driving unit and the nth level scanning driving unit, and the first level transmission signals and the second level transmission signals are used for driving the scanning driving units to output the scanning driving signals.

In this embodiment, the scan driving circuit only needs to set two virtual scan driving units at the ends of the n scan driving units, and the two virtual scan driving units are respectively connected to the two scan driving units at the ends of the n scan driving units, and output corresponding second-stage transmission signals to drive the scan driving units to accurately output the scan driving signals. The number of the virtual scanning driving units is reduced, so that the space occupied by the virtual scanning driving units is correspondingly reduced, and the design space of the narrow frame of the display panel is improved.

Optionally, the n scan driving units and the two virtual scan driving units are divided into 4y groups, each group receives eight clock signals, each scan driving unit and each virtual scan driving unit receive two clock signals, and y is a positive integer.

Because the n scanning driving units and the two virtual scanning driving units correspond to the clock signals and are divided into 8y groups, each group of GDL circuits can accurately correspond to 8 clock signals, and the compatibility of the scanning driving circuit and other functional circuits is effectively improved.

Optionally, each scan driving unit includes two GDL circuits connected to each other, each GDL circuit is configured to output one scan driving signal, and the n scan driving units include 2n GDL circuits cascaded to each other, where the x-th scan driving unit includes a2 x-th stage GDL circuit and a2 x-1-th stage GDL circuit, the 2 x-th stage GDL circuit is cascaded to the 2 x-4-th stage GDL circuit, the 2 x-1-th stage GDL circuit is cascaded to the 2 x-5-th stage GDL circuit, the 2 x-1-th stage GDL circuit is a first GDL circuit, and the 2 x-th stage GDL circuit is a second GDL circuit. The first GDL circuit is used for receiving a 2x-5 level first level transmission signal transmitted by the 2x-5 level GDL circuit and outputting a 2x-1 level first level transmission signal and a scanning driving signal according to the 2x-5 level first level transmission signal. The second GDL circuit is used for receiving the 2x-4 level first level transmission signal transmitted by the 2x-4 level GDL circuit and outputting a 2x level first level transmission signal and a scanning driving signal according to the 2x-4 level first level transmission signal.

In this embodiment, four GDL circuits are spaced between the 2n mutually cascaded GDL circuits, which effectively ensures the output duration of the first-stage transmission signal and the scan driving signal, and improves the output efficiency of the scan driving signal, i.e., effectively improves the output frequency of the scan driving signal, thereby providing a larger space for improving the refresh rate of image display.

Optionally, the first GDL circuit includes a first pull-up control module, a first pull-up module, a first pull-down control module, a second pull-down control module, a first pull-down module, a first node, and a second node. The first pull-up control module, the first pull-up module and the first pull-down control module are electrically connected to the first node. The first pull-up control module is used for pulling up the potential of the first node to a first potential according to the received 2x-5 stage first stage transmission signal. When the potential of the first node is a first potential, the first pull-up module outputs a 2x-1 level first level transmission signal with the first potential, the 2x-1 level first level transmission signal is used for controlling a 2x-5 level GDL circuit in an x-2 level scanning driving unit to output a 2x-5 level first level transmission signal with a second potential and stop outputting the scanning driving signal, and controlling a 2x +3 level GDL circuit in an x +2 level scanning driving unit to output a 2x +3 level first level transmission signal with the first potential and output the scanning driving signal. The first pull-down control module is used for pulling down the potential of the first node to a second potential, the second pull-down control module and the first pull-down module are electrically connected to the second node, the second pull-down control module is used for pulling up the potential of the second node to the first potential, and when the potential of the second node is the first potential, the first pull-down module outputs a 2x-1 stage first-level transmission signal with the second potential.

Optionally, the second GDL circuit includes a second pull-up control module, a second pull-up module, a third pull-down control module, a fourth pull-down control module, a second pull-down module, a third node, and a fourth node, and the first pull-down module is electrically connected to the fourth node. The second pull-up control module, the second pull-up module and the third pull-down control module are electrically connected to the third node. The second pull-up control module is used for pulling up the potential of the third node to a first potential according to a received 2x-4 level first level transmission signal, when the third node is the first potential, the second pull-up module outputs a 2x level first level transmission signal with the first potential, the 2x level first level transmission signal is used for controlling a 2x-4 level GDL circuit in the x-2 level scanning driving unit to output a 2x-4 level first level transmission signal of the second potential and stop outputting the scanning driving signal, and controlling a 2x +4 level GDL circuit in the x +2 level scanning driving unit to output a 2x +4 level first level transmission signal of the first potential and output the scanning driving signal. The second pull-down control module is used for pulling down the potential of the third node to a second potential. The fourth pull-down control module and the second pull-down module are electrically connected to the fourth node, the fourth pull-down control module is used for pulling up the potential of the fourth node to the first potential, and when the potential of the fourth node is the first potential, the second pull-down module outputs a2 x-level first-level transmission signal with the second potential.

In this embodiment, the first GDL circuit effectively ensures the stability of the voltages of the first node and the second node through the cooperation of the functional modules, and ensures the accurate output of the first-stage transmission signal and the scanning driving signal. The second GDL circuit effectively ensures the stability of the voltage of the third node and the fourth node through the cooperation of the functional modules, and ensures the accurate output of the first-stage transmission signal and the scanning driving signal.

Optionally, the first GDL circuit further includes a first pull-down maintaining module electrically connected to the first node, the second node, and the third node. When the first node is at a first potential, the first pull-down maintaining module pulls down the potential of the second node to a second potential, and the first pull-down module stops outputting the 2x-1 stage first stage transmission signal and the scanning driving signal. When the third node is at the first potential, the first pull-down maintaining module controls the second node to stop receiving the power supply voltage, and the first pull-down module stops outputting the 2x-1 stage first stage transmission signal and the scanning driving signal.

The second GDL circuit further includes a second pull-down maintaining module electrically connected to the first node, the third node, and the fourth node, and a fifth node electrically connected to the third pull-down control module and the second pull-down module. When the first node is at the first potential, the second pull-down maintaining module controls the fourth node to stop receiving the power supply voltage, and the second pull-down module stops outputting the 2 x-th-stage first-stage transmission signal and the scanning driving signal. When the third node is at the first potential, the second pull-down maintaining module pulls down the potential of the fourth node to a second potential, and the second pull-down module stops outputting the 2 x-th-level first-level transmission signal and the scanning driving signal. And when the potential of the second node is the first potential, the potential of the fifth node is the first potential so as to control the second pull-down module to output a2 x-th-level first-level transmission signal with the second potential and stop outputting the scanning driving signal.

In this embodiment, the first pull-down maintaining module in the first GDL circuit and the second pull-down maintaining module in the second GDL circuit can accurately maintain the output of the first-stage transmission signal and the scanning driving signal stopped in the current scanning driving unit by accessing the first-stage transmission signal provided by the corresponding cascaded GDL circuit, so as to improve the accuracy of the output timing sequence of the scanning driving signal of each scanning driving unit.

Optionally, when x is greater than 2 and less than or equal to 4, the first pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, and a third pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, and the drain electrode of the first pull-down control transistor is connected to a first low-voltage power supply end and is connected to a first low-voltage potential. The grid electrode of the second pull-down control transistor is connected with a first-stage transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, and the drain electrode of the second pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential.

The third pull-down control module comprises a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor. The gate of the sixth pull-down control transistor is electrically connected to the fourth node, the source of the sixth pull-down control transistor is electrically connected to the third node, and the drain of the sixth pull-down control transistor is connected to the first low-voltage potential. The grid electrode of the seventh pull-down control transistor is connected with the first-stage transmission signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with the first low-voltage potential. A gate of the eighth pull-down control transistor is electrically connected to the fifth node, a source of the eighth pull-down control transistor is electrically connected to the third node, and a drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

In this embodiment, for any x-level scan driving unit of the n scan driving units, when x is greater than 2 and less than or equal to 4, that is, in the 1 st to 8 th-level GDL circuits, the first pull-down control module and the third pull-down control module respectively include three pull-down control transistors, and the resistance-capacitance loads (RC loading) of the 1 st to 8 th-level GDL circuits are similar, so that the working stability of the 1 st to 8 th-level GDL circuits is better. Optionally, the first pull-up control module is further configured to access a start signal, and is configured to pull up the potential of the first node to a first potential. When the first node is at the first potential, the first pull-up module outputs a first-stage transmission signal with the first potential, and the second pull-up control module is further used for accessing a starting signal and pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a first level transmission signal with the first potential.

In this embodiment, the first pull-up control module and the second pull-up control module are directly connected to the start signal, so that the potentials of the first node and the third node can be accurately pulled up to the first potential, and the first pull-up module and the second pull-up module are accurately and quickly controlled to output the corresponding first-stage transmission signal and the corresponding scan driving signal.

Optionally, when x is greater than 2 and less than or equal to 4, the first pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, the drain electrode of the first pull-down control transistor is connected to a first low-voltage potential, and the grid electrode of the second pull-down control transistor is connected to a first-stage transmission signal. The source of the second pull-down control transistor is electrically connected to the first node, and the drain of the second pull-down control transistor is connected to a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the fourth pull-down control transistor is connected with a reset signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

the third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor. The grid electrode of the fifth pull-down control transistor is connected with a reset signal, the source electrode of the fifth pull-down control transistor is electrically connected with the third node, and the drain electrode of the fifth pull-down control transistor is connected with the first low-voltage potential. The gate of the sixth pull-down control transistor is electrically connected to the fourth node, the source of the sixth pull-down control transistor is electrically connected to the third node, and the drain of the sixth pull-down control transistor is connected to the first low-voltage potential. The grid electrode of the seventh pull-down control transistor is connected with the first-stage transmission signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with the first low-voltage potential. The gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

In this embodiment, for any x-level scan driving unit of the n scan driving units, when x is greater than 2 and less than or equal to 4, that is, in the 1 st to 8 th-level GDL circuits, the first pull-down control module and the third pull-down control module respectively include four pull-down control transistors and are connected to a reset signal, and when the first pull-down module or the second pull-down module is abnormal, each pull-down control transistor of the first pull-down control module and the third pull-down control module can accurately control the first-level transmission signal and the scan driving signal to stop outputting according to the reset signal. Correspondingly, in the 9 th-2 n-level GDL circuits, the first pull-down control module and the third pull-down control module also respectively comprise four pull-down control transistors, so that the resistance-capacitance loads (RC loading) of each level of GDL circuit are close, and the transistors and other electronic elements in each GDL circuit in the 2 n-level GDL circuit are the same, and the integrity and the working stability are better.

Optionally, the first pull-up control module is further configured to access a start signal, and is configured to pull up the potential of the first node to a first potential. When the first node is at the first potential, the first pull-up module outputs a first-stage transmission signal with the first potential, and the second pull-up control module is further used for accessing a starting signal and pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a first level transmission signal with the first potential.

Optionally, when x is greater than 4 and less than or equal to n, the first pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, and a fourth pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, and the drain electrode of the first pull-down control transistor is connected to a first low-voltage potential. The grid electrode of the second pull-down control transistor is connected with a first-stage transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, and the drain electrode of the second pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the fourth pull-down control transistor is connected with a starting signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

the third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor. The gate of the fifth pull-down control transistor is connected to a start signal, the source of the fifth pull-down control transistor is electrically connected to the third node, and the drain of the fifth pull-down control transistor is connected to the first low-voltage potential. The gate of the sixth pull-down control transistor is electrically connected to the fourth node, the source of the sixth pull-down control transistor is electrically connected to the third node, and the drain of the sixth pull-down control transistor is connected to the first low-voltage potential. The gate of the seventh pull-down control transistor is connected to the first-stage transmission signal, the source of the seventh pull-down control transistor is electrically connected to the third node, and the drain of the seventh pull-down control transistor is connected to the first low-voltage potential. The gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

In this embodiment, for any x-level scan driving unit of the n scan driving units, when x is greater than 4 and less than or equal to n, that is, in the 9 th to 2 n-level GDL circuits, the first pull-down control module and the third pull-down control module respectively include four pull-down control transistors and are connected to a reset signal, and when the first pull-down module or the second pull-down module is abnormal, each pull-down control transistor in the first pull-down control module and the third pull-down control module can accurately control the first-level transmission signal and the scan driving signal to stop outputting according to the reset signal. Meanwhile, the resistance-capacitance loads (RC loading) of each stage of GDL circuit are close, so that the electronic elements such as transistors in each GDL circuit in the 2n stage of GDL circuit are the same, and the integrity and the working stability are better. Optionally, the first pull-up control module is further configured to access the 2x-5 th stage first level transmission signal, and is configured to pull up the potential of the first node to a first potential. When the electric potential of the first node is a first electric potential, the first pull-up module outputs a 2x-1 stage first stage transmission signal with the first electric potential. The second pull-up control module is further used for accessing a 2x-4 stage first-stage transmission signal and pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a2 x-th-stage first-stage transmission signal with the first potential.

In this embodiment, four GDL circuits are spaced between the mutually cascaded GDL circuits to transmit the stage transmission signal, so that the output duration of the first stage transmission signal and the scan driving signal is effectively ensured, and the output efficiency of the scan driving signal is improved.

Optionally, each of the dummy scan driving units includes two dummy GDL circuits, and the four dummy GDL circuits are sequentially arranged. The four virtual GDL circuits are respectively connected with two GDL circuits in the nth-level scanning driving unit and two GDL circuits in the nth-1-level scanning driving unit, and respectively output the second-level transmission signal to the two GDL circuits in the nth-level scanning driving unit and the two GDL circuits in the nth-1-level scanning driving unit so as to drive the two GDL circuits in the nth-level scanning driving unit and the two GDL circuits in the nth-1-level scanning driving unit to stop outputting the scanning driving signal.

In this embodiment, the two virtual GDL circuits are respectively connected to and output the second-level transmission signal to the nth-1-level scan driving unit and the nth-level scan driving unit, so as to drive the nth-1-level scan driving unit and the nth-level scan driving unit to accurately output the scan driving signal.

Optionally, the two dummy GDL circuits of the dummy scan driving unit include a first dummy GDL circuit and a second dummy GDL circuit. The first virtual GDL circuit includes a first virtual pull-up control module, a first virtual pull-up module, a first virtual pull-down control module, a second virtual pull-down control module, a first virtual pull-down module, a first virtual node, and a second virtual node. The first virtual pull-up control module, the first virtual pull-up module and the first virtual pull-down control module are electrically connected to the first virtual node. The first virtual pull-up control module is configured to pull up a potential of the first virtual node to a first potential, and when the potential of the first virtual node is the first potential, the first virtual pull-up module outputs the second-stage transmission signal having the first potential, and the second-stage transmission signal is configured to control one of the nth-stage scan driving unit and the nth-1 st-stage scan driving unit, where the GDL circuit outputs the first-stage transmission signal having the second potential and stops outputting the scan driving signal. The first virtual pull-down control module is used for pulling down the electric potential of the first virtual node to a second electric potential. The second virtual pull-down control module and the first virtual pull-down module are electrically connected to the second virtual node, the second virtual pull-down control module is used for pulling up the potential of the second virtual node to a first potential, and when the potential of the second virtual node is the first potential, the first virtual pull-down module outputs a second level transmission signal with a second potential. Optionally, the second virtual GDL circuit includes a second virtual pull-up control module, a second virtual pull-up module, a third virtual pull-down control module, a fourth virtual pull-down control module, a second virtual pull-down module, a third virtual node, and a fourth virtual node. The first virtual pull-down module is electrically connected with the fourth virtual node. The second virtual pull-up control module, the second virtual pull-up module and the third virtual pull-down control module are electrically connected to the third virtual node. The second virtual pull-up control module is configured to pull up a potential of the third virtual node to a first potential, and when the potential of the third virtual node is the first potential, the second virtual pull-up module outputs a second level transmission signal having the first potential, where the second level transmission signal is configured to control one of the nth level scan driving unit and the n-1 th level scan driving unit, where the GDL circuit outputs the first level transmission signal having the second potential and stops outputting the scan driving signal. The second virtual pull-down control module is used for pulling down the potential of the third virtual node to a second potential. The fourth virtual pull-down control module and the second virtual pull-down module are electrically connected to the fourth virtual node, the fourth virtual pull-down control module is used for pulling up the potential of the fourth virtual node to a first potential, and when the potential of the fourth virtual node is the first potential, the second virtual pull-down module outputs a second level transmission signal with a second potential.

In this embodiment, the two virtual GDL circuits effectively ensure the stability of the voltages of the first virtual node and the second virtual node through the cooperation of the functional modules, and ensure the accurate output of the second-level transmission signal.

Optionally, the first dummy GDL circuit further includes a first dummy pull-down maintaining module electrically connected to the first dummy node, the second dummy node, and the third dummy node. When the potential of the first virtual node is a first potential, the first virtual pull-down maintaining module pulls down the potential of the second virtual node to a second potential, and the first virtual pull-down module stops outputting a second pass signal. When the potential of the third virtual node is a first potential, the first virtual pull-down maintaining module controls the second virtual node to stop receiving the power supply voltage, and the first virtual pull-down module stops outputting a second pass signal. The second virtual GDL circuit further includes a second virtual pull-down maintenance module electrically connected to the first virtual node, the third virtual node, and the fourth virtual node. When the potential of the first virtual node is a first potential, the second virtual pull-down maintaining module controls the fourth virtual node to stop receiving the power supply voltage, and the second virtual pull-down module stops outputting a second pass signal. When the potential of the third virtual node is the first potential, the second virtual pull-down maintaining module pulls down the fourth virtual node to a second potential, and the second virtual pull-down module stops outputting a second pass signal.

In this embodiment, the first virtual pull-down maintaining module in the first virtual GDL circuit and the second virtual pull-down maintaining module in the second virtual GDL circuit can accurately maintain the output of the second-stage transmission signal stopped in the current virtual scanning driving unit by accessing the first-stage transmission signal provided by the corresponding cascaded GDL circuit, so as to improve the accuracy of the output timing sequence of the second-stage transmission signal of each virtual scanning driving unit.

Optionally, the present application further provides an array substrate including the foregoing scanning driving circuit, the array substrate includes 2n scanning lines, a plurality of pixel units arranged in an array and the scanning driving circuit described above, the 2n scanning lines are respectively connected to the n scanning driving units, and respectively sequentially receive 2n scanning driving signals from the n scanning driving units, and the pixel units receive image data and display images under the control of the 2n scanning driving signals.

Optionally, the present application further provides a display terminal including the foregoing scan driving circuit.

Compared with the prior art, the scanning driving circuit in the array substrate and the display terminal only needs to arrange the virtual scanning driving unit at the tail end of the cascaded scanning driving units to control the level transmission of the scanning driving signals, so that the number of the virtual scanning driving units and the occupied space are effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic side view of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic plan view of an array substrate of the display panel shown in FIG. 1;

FIG. 3 is a schematic connection diagram of the scan driving circuit shown in FIG. 2 according to an embodiment of the present disclosure;

FIG. 4 is a schematic circuit diagram of a scan driving unit of the scan driving units GDL 5-GDL 1080 as shown in FIG. 3 according to a first embodiment of the present disclosure;

FIG. 5 is a circuit diagram of one of the scan driving units GDL 1-GDL 4 shown in FIG. 3;

FIG. 6 is a circuit diagram of one of the dummy scan driver cells GDL1 and GDL2 shown in FIG. 3;

FIG. 7 is a schematic diagram of layout structures of the scan driving units GDL 1-GDL 4 shown in FIG. 5;

FIG. 8 is a circuit layout diagram of the scan driving units GDL 1-GDL 4 shown in FIG. 5;

FIG. 9 is a schematic diagram of a layout structure of any four scan driving units GDL 5-GDL 1080 as shown in FIG. 4;

FIG. 10 is a circuit layout diagram of any four scan driving units GDL 5-GDL 1080 as shown in FIG. 4;

FIG. 11 is a schematic layout diagram of the dummy scan driving units GDL1 and GDL2 shown in FIG. 6;

FIG. 12 is a circuit layout diagram of the dummy scan driving units GDL1 and GDL2 shown in FIG. 6;

FIG. 13 is a timing diagram of one frame of image display process of any one of the scan driving units GDL 1-GDL 1080;

fig. 14 is a circuit structure diagram of one scan driving unit among the scan driving units GDL 1-GDL 4 shown in fig. 3 according to a second embodiment of the present application.

Reference numerals:

1000-display terminal, 900-display panel, 900 a-image display area, 900 b-non-display area, 900 c-array substrate, 900 d-object substrate, 900e display medium layer, P-pixel unit, 120-data line, 130-scanning line, 101-time sequence control circuit, 102-data drive circuit, 103-scanning drive circuit, G1-G2 n-scanning drive signal;

CK (e) -e-th clock signal, STV-start signal, VDD-power voltage, Vss 1-first low-voltage potential, Vss 2-second low-voltage potential, Reset-Reset signal;

100-scan driving module, 200-virtual scan driving module, 100A-first GDL circuit, 100B-second GDL circuit, 10-first pull-up control module, 20-first pull-up module, 30A-first pull-down control module, 30B-second pull-down control module, 40-first pull-down module, 50-first pull-down maintaining module, Q (2c-1) (Q (2i-1)) -first node, Qb (2c-1) (Qb (2i-1)) -second node, 60-second pull-up control module, 70-second pull-up module, 80A-third pull-down control module, 80B-fourth pull-down control module, 90-second pull-down module, 55-second pull-down maintaining module, Q (2c) (Q (2i)) -third node, qb (2C) (Qb (2i)) -a fourth node, Qb (2C +1) (Qb (2i +1)) -a fifth node, C (2C-1) -2C-1 st stage transfer signal, C (2C) -2C-2 nd stage transfer signal, G (2C-1) -2C-1 nd stage scan driving signal, G (2C) -2C-1 nd stage scan driving signal, C (2i-1) -2 i-1 th stage transfer signal, C (2i) -2 i th stage transfer signal, G (2i-1) -2 i-1 th stage scan driving signal, G (2i) -2 i stage scan driving signal;

200A-a first virtual GDL circuit, 200B-a second virtual GDL circuit, 210-a first virtual pull-up control module, 220-a first virtual pull-up module, 230A-a first virtual pull-down control module, 230B-a second virtual pull-down control module, 240-a first virtual pull-down module, 250-a first virtual pull-down maintenance module, P (2j-1) -a first virtual node, Pb (2j-1) a second virtual node, 260-a second virtual pull-up control module, 270-a second virtual pull-up module, 280A-a third virtual pull-down control module, 280B-a fourth virtual pull-down control module, 290-a second virtual pull-down module, 255-a second virtual pull-down maintenance module, P (2j) -a third virtual node, Pb (2j) -a fourth virtual node, pb (2j +1) -fifth virtual node; ca (1) -Ca (4) -virtual cascade signal;

t11-eleventh transistor, T21-twenty-first transistor, T22-twenty-second transistor, T31-thirty-first transistor, T32-thirty-second transistor, T33-thirty-third transistor, T34-thirty-fourth transistor, T35-thirty-fifth transistor, T36-thirty-sixth transistor, T37-thirty-seventh transistor, T41-forty-first transistor, T42-forty-second transistor, T43-forty-third transistor, T44-forty-fourth transistor, T51-fifty-first transistor, T52-fifty-second transistor, T53-fifty-third transistor, T61-sixty-first transistor, T71-seventy-first transistor, T72-seventy-seventh transistor, T81-eighty-first transistor, T82-eighty-first transistor, t83-eighty-three transistor, T84-eighty-four transistor, T85-eighty-five transistor, T86-eighty-six transistor, T87-eighty-seven transistor, T91-ninety-first transistor, T92-ninety-second transistor, T93-ninety-third transistor, T94-ninety-fourth transistor, T95-ninety-fifth transistor, T96-ninety-sixth transistor, T97-ninety-seventh transistor.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). Directional phrases used in this application, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the application and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the application.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises," "comprising," "includes," "including," or "including," when used in this application, specify the presence of stated features, operations, elements, and/or the like, but do not limit one or more other features, operations, elements, and/or the like. Furthermore, the terms "comprises" or "comprising" indicate the presence of the respective features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic side view of a display terminal according to an embodiment of the present application. As shown in FIG. 1, display terminal 1000 can include a display panel 900 and other components (not shown) including a power module, a signal processor module, a signal sensing module, and the like.

The display panel 900 includes an image display region 900a and a non-display region 900 b. The image display region 900a is used for displaying an image, and the non-display region 900b is disposed around the image display region 900a to dispose other auxiliary components or modules. Specifically, the display panel 900 includes an array substrate 900c and an opposite substrate 900d, and a display medium layer 900e sandwiched between the array substrate 900c and the opposite substrate 900 d. In this embodiment, the display medium in the display medium layer is a Liquid Crystal (Liquid Crystal), that is, the display panel 900 in this embodiment is a Liquid Crystal display panel.

Please refer to fig. 2, which is a schematic plan view of the array substrate of the display panel shown in fig. 1. As shown in fig. 2, the corresponding image display region 900a of the array substrate 900c includes a plurality of m × n Pixel units (pixels) P, m Data lines (Data lines) 120 and n Scan driving lines (Scan lines) 130 arranged in a matrix, where m and n are natural numbers greater than 1.

The display terminal 1000 further includes a timing control circuit 101, a Data Driver circuit (Data Driver)102, and a Scan Driver circuit (Scan Driver)103 for driving the pixel units to display images, disposed on the array substrate 900c corresponding to the non-display region 900b of the display panel 900.

The data driving circuit 102 is electrically connected to the data lines 120, and is configured to transmit image data to be displayed to the pixel units P through the data lines 120 in the form of data voltages.

The scan driving circuit 103 is electrically connected to the plurality of scan driving lines 130, and is used for outputting a scan driving signal G2n through the plurality of scan driving lines 130 to control when the pixel unit P receives image data. The scan driving circuit 103 sequentially outputs scan driving signals G1, G2, … G32, …, Gn from the plurality of scan driving lines G1, G2, … G32, …, Gn in a scan cycle from the plurality of scan driving lines 130 in the position arrangement order.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scan driving circuit 103, respectively, and is configured to control the working timings of the data driving circuit 102 and the scan driving circuit 103, that is, to output corresponding timing control signals (clock signals) to the scan driving circuit 103 and the data driving circuit 102, so as to control when to output the corresponding scan driving signals Gn.

In this embodiment, the scan driving circuit 103 is disposed in the area corresponding to the array substrate 900c by a gate driver on array (GOA) technique and a manufacturing process, and preferably, the scan driving circuit 103 may further employ a gate driver less technique (GDL) disposed in the area corresponding to the array substrate 900 c.

It can be understood that the display terminal 1000 further includes other auxiliary circuits for jointly completing the display of the image, for example, an image receiving Processing circuit (GPU), a power circuit, and the like, which are not described in detail in this embodiment.

Referring to fig. 3, fig. 3 is a connection diagram of the scan driving circuit shown in fig. 2 according to an embodiment of the present disclosure, in which the scan driving circuit 103 includes a scan driving module 100, a dummy scan driving module 200, and eight clock signals ck (e) (1, 2, …, and 8).

In other embodiments of the present application, the scan driving circuit 103 receives 8 clock signals from the timing control circuit 101, and may respectively represent eight clock signals ck (e) (1, 2, …, and 8), and may be adjusted according to actual requirements, for example, 4 clock signals, 6 clock signals, 10 clock signals, and 12 clock signals, and the number of the clock signals is different to correspond to the display panels with different resolutions. Further, the scan driving circuit 103 also receives a start signal STV, a Reset signal Reset, a first low voltage potential Vss1, a second low voltage potential Vss2, and a power supply high voltage VDD from the timing control circuit 101.

The scan driving module 100 outputs a plurality of scan driving signals G1-G2 n, where n is 1080 in the present embodiment, and the plurality of scan driving signals may be represented as G1-G2160 corresponding to 2160 scan lines 130 shown in fig. 2. In other embodiments of the present application, the number of the scan lines may be set according to the actual resolution, and is not limited thereto.

Specifically, the scan driving module 100 includes a plurality of scan driving units GDL1 to GDL1080 sequentially cascaded, and the dummy scan driving module 200 includes two dummy scan driving units GDLa1 to GDLa 2. Each of the dummy scan driver cells GDLa 1-GDLa 2 includes a first dummy GDL circuit 200A (fig. 6) and a second dummy GLD circuit 200B (fig. 6).

In the embodiment of the present application, a specific manner of cascading the scan driving units GDL 1-GDL 1080 with each other may be that any one scan driving unit is cascaded with scan driving units separated by 1 scan driving unit, for example, the first stage scan driving unit GDL1 is cascaded with the third stage scan driving unit GDL3, the second stage scan driving unit GDL2 is cascaded with the fourth stage scan driving unit GDL4, and so on, the nth-5 stage scan driving unit GDLn-5 is cascaded with the nth-3 stage scan driving unit GDLn-3, and the nth-4 stage scan driving unit GDLn-4 is cascaded with the nth-2 stage scan driving unit GDLn-2. The nth-1-stage scan driving unit GDLn-1 and the nth-stage scan driving unit GDLn are respectively connected to the two dummy scan driving units GDLa 1-GDLa 2 in the dummy scan driving module 200, and accurately output corresponding scan driving signals under the driving of the second-stage signals output by the two dummy scan driving units GDLa 1-GDLa 2. In this embodiment, the two dummy scan driving units GDLa 1-GDLa 2 in the dummy scan driving module 200 are only used for driving the nth-1 stage scan driving unit GDLn-1 and the nth stage scan driving unit GDLn in cascade without outputting a scan driving signal.

Specifically, the nth-1-stage scan driving unit GDLn-1 and the nth-stage scan driving units GDLn are cascaded to the dummy scan driving units GDLa1 to GDLa2 in such a manner that the first-stage dummy scan driving unit GDLa1 is connected to the nth-1-stage scan driving unit GDLn-1 (scan driving unit GDL1079) and the second-stage dummy scan driving unit GDLa2 is connected to the nth-stage scan driving unit GDLn (scan driving unit GDL 1080).

In this embodiment, the scan driving units GDL1 to GDL1080 are sequentially cascaded, specifically, each scan driving unit outputs a stage transmission signal, and the stage transmission signal drives the cascaded scan driving unit to pull up a node voltage of one node connected to the cascaded scan driving unit, so that the connected scan driving unit accurately outputs the scan driving signal and the stage transmission signal.

For example, the stage-by-stage signal output from the first stage scan driving unit GDL1 can pull up the node voltage of the third stage scan driving unit GDL3, thereby causing the scan driving signal and the stage-by-stage signal to be output. The stage driving signal output from the second stage scan driving unit GDL2 can pull up the node voltage of the second stage scan driving unit GDL4, so that the scan driving signal and the stage driving signal are output, and so on.

More specifically, any one of the scan driving units GDL includes a scan driving circuit outputting two stages of scan driving signals, and for convenience of description, the GDL circuit is hereinafter abbreviated as GDL circuit. Each stage of GDL circuit outputs one scan driving signal correspondingly, so that one scan driving unit GDL outputs two scan driving signals. For example, the scan driving unit GDL1 outputs a scan driving signal G1 and a scan driving signal G2, the scan driving unit GDL2 outputs a scan driving signal G3 and scan driving signals G4, … …, the scan driving unit GDL1079 outputs a scan driving signal G2157 and a scan driving signal G2158, and the scan driving unit GDL1080 outputs a scan driving signal G2159 and a scan driving signal G2160. The dummy scan driving module 200 includes a first-stage dummy scan driving unit GDLa1 and a second-stage dummy scan driving unit GDLa 2.

In this embodiment, since the scan driving units GDL1 to GDLn (scan driving units GDL1 to GDL1080) are sequentially cascaded with each other, the 2n (2060) GDL circuits included in the scan driving units GDL1 to GDL1080 should also be sequentially cascaded with each other. For convenience of illustration, the 2n GDL circuits may be defined as a first stage GDL circuit, a second stage GDL circuit, a third stage GDL circuit, a fourth stage GDL circuit, … …, a 2n-1 stage GDL circuit, and a 2n stage GDL circuit, respectively. Correspondingly, the GDL circuit of the first stage outputs a scan driving signal G1, the GDL circuit of the second stage outputs scan driving signals G2, … …, and the GDL circuit of the 2 nth stage outputs a scan driving signal G2 n. In this embodiment, the specific cascade of the 2n GDL circuits may be that any one GDL circuit is cascaded with the scan driving circuit separated by 4 GDL circuits. In this embodiment, among the n scan driving units, the scan driving units that are cascaded with each other are separated by one scan driving unit, that is, the xth scan driving unit is cascaded with the xth-2 scan driving unit, where x is greater than 2 and less than or equal to n. Correspondingly, when the x-th scanning driving unit is cascaded to the x-2-th scanning driving unit, the x-th scanning driving unit outputs two first-stage transmission signals to the x-2-th scanning driving unit, so that the x-2-th scanning driving unit is driven to output scanning driving signals.

In this embodiment, the scan driving circuit 103 only needs to provide two dummy scan driving units GDLa1 to GDLa2 at the ends of the n scan driving units GDL1 to GDLn, the two dummy scan driving units GDLa1 to GDLa2 are respectively connected to the two scan driving units GDLn-1 to GDLn at the ends of the n scan driving units, and output corresponding second stage transmission signals to drive the scan driving units GDLn-1 to GDLn to accurately output the scan driving signals. The number of the virtual scanning driving units GDLa 1-GDLa 2 is small, so that the space occupied by the virtual scanning driving units is correspondingly reduced, and the design space of the narrow frame of the display panel is improved.

Correspondingly, in the 2 n-stage GDL circuits, four GDL circuits are spaced between the mutually cascaded GDL circuits, namely, the 2 x-stage GDL circuit is cascaded with the 2 x-4-stage GDL circuit. More specifically, the two GDL circuits in each scan driving unit are respectively defined as a first GDL circuit and a second GDL circuit. Then, for 2 × n GDL circuits cascaded with each other, any one of the first GDL circuits is configured to receive the stage transmission signal transmitted by the 2x-4 stage GDL circuit, and the second GDL circuit is configured to receive the stage transmission signal transmitted by the 2x-3 stage GDL circuit.

When x is equal to n, that is, for the 2n-3 rd to 2 n-th stage GDL circuits in the n-1 st and nth stage GDLn, the four dummy GDL circuits included in the dummy scan driving units GDLa1 to GDLa2, that is, the dummy first and second

dummy GDL circuits

200A and 200B included in the dummy scan driving units GDLa1 to GDLa2, respectively, are connected. The two virtual scan driving units GDLa 1-GDLa 2 respectively output two second-level signals to drive to the 2n-3 th-level GDL circuit-2 n-level GDL circuit, and the 2n-3 th-level GDL circuit-2 n-level GDL circuit accurately output corresponding scan driving signals under the control of the second-level signals. For example, the first stage GDL circuit is cascaded with the fifth stage GDL circuit, the fourth stage GDL circuit is cascaded with the eighth stage GDL circuit, and so on, and the description of this embodiment is omitted.

Eight clock signals ck (e) are used to provide scan driving timing for the scan driving units GDL1 through GDLn (scan driving units GDL1 through GDL1080) and the two dummy scan driving units GDLa1 through GDLa2 in the scan driving circuit 103, where e is 1, 2, … …, 8. In the embodiment of the present application, the clock signal ck (e) is used to provide clock signals for the multiple stages of the scan driving unit GDL and the multiple stages of the dummy scan driving unit GDLa.

Specifically, the n scan driving units and the two dummy scan driving units are divided into 4y groups, that is, the first to 2 n-th stage GDL circuits and the four dummy GDL circuits are divided into 4(2y) groups, where y is a positive integer. Each group respectively receives eight clock signals, and each scan driving unit and each virtual scan driving unit respectively receive two clock signals CK, that is, each group of GDL circuits or virtual GDL circuits respectively receive one clock signal, so that the first to 2 n-th GDLn circuits and the four virtual GDL circuits are just divided into 8y groups, and each group of GDL circuits can accurately correspond to 8 clock signals, for example, the first to eighth GDL circuits respectively correspond to clock signals CK (1) to CK (8), the ninth to sixteenth GDL circuits respectively correspond to clock signals CK (1) to CK (8), so. It can be seen that the first stage GDL circuit starts to directly correspond to the clock signal CK (1), which effectively improves the mutual compatibility between the scan driving circuit 103 and the timing control circuit 101.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of a scan driving unit of the scan driving units GDL 5-GDL 1080 shown in fig. 3 according to a first embodiment of the present application. Take the scanning driving unit GDLc as an example, where c is greater than 4 and less than n-1, and is a positive integer. The scan driving unit GDLc includes two GDL circuits, which may be defined as a first GDL circuit 100A and a second GDL circuit 100B, respectively, the first GDL circuit 100A of the scan driving unit GDLc outputs a 2C-1 th scan driving signal G (2C-1) and outputs a 2C-1 th stage transfer signal C (2C-1), and the second GDL circuit 100B of the scan driving unit GDLc outputs a 2C th scan driving signal G (2C) and outputs a 2C nd stage transfer signal C (2C). In this embodiment, the 2C-1 st stage transmission signal C (2C-1) and the 2C 2 d stage transmission signal C (2C) are first stage transmission signals.

The first GDL circuit 100A includes a first pull-up control module 10, a first pull-up module 20, a first pull-down control module 30A, a second pull-down control module 30B, a first pull-down module 40, a first pull-down maintaining module 50, a first node Q (2c-1) and a second node Qb (2 c-1).

The first pull-up control module 10 is electrically connected to the stage transmission signal output terminal (C (2C-5)) and the first node Q (2C-1), and is connected to the 2C-5 stage transmission signal C (2C-5). The first pull-up control module 10 utilizes the 2C-5 th level transmission signal C (2C-5) to pull up the potential of the first node Q (2C-1) to a first potential, where the first potential is a high point and the second potential is a low potential.

The first pull-up module 20 is connected to the e-th clock signal ck (e) and electrically connected to the first node Q (2C-1), the stage signal output terminal (C (2C-1)) and the scan driving signal output terminal (G (2C-1)). The first pull-up module 20 is configured to output a 2C-1 stage transmission signal C (2C-1) and a 2C-1 stage scanning driving signal G (2C-1) according to an e-th clock signal ck (e) under the potential control of the first node Q (2C-1).

The first pull-down control module 30A is connected to the start signal STV, and is electrically connected to the first node Q (2C-1), the second node Qb (2C-1), the first low voltage power terminal, and the stage transmission signal output terminal (C (2C +3)), and is connected to the first low voltage potential Vss1 from the first low voltage power terminal and is connected to the 2C +3 th stage transmission signal C (2C +3) from the stage transmission signal output terminal (C (2C +3)), and the first pull-down control module 30A pulls down the potential of the first node Q (2C-1) by using the start signal STV, and pulls down the potential of the first node Q (2C-1) to the second potential by using the 2C +3 rd stage transmission signal C (2C + 3).

If the circuit shown in fig. 4 is a schematic circuit diagram of the scan driver cells GDL 5-GDL 1078, the first pull-down control module 30A of the first GDL circuit 100A receives the start signal STV. If the circuit shown in fig. 4 is a schematic circuit structure diagram of the scan driving unit GDL1079, the first pull-down control module 30A of the first GDL circuit 100A is connected to the stage signal of the first dummy GDL circuit of the dummy scan driving unit GDL 1. If the circuit shown in fig. 4 is a schematic circuit structure diagram of the scan driving unit GDL1080, the first pull-down control module 30A of the first GDL circuit 100A is connected to the stage signal of the first virtual GDL circuit of the virtual scan driving unit GDL 2.

The second pull-down control module 30B is connected to the power high voltage VDD, electrically connected to the first node Q (2c-1), and electrically connected to the second node Qb (2 c-1). The second pull-down control module 30B pulls up the potential of the second node Qb (2c-1) to the first potential using the low level of the first node Q (2c-1) and the power high voltage VDD.

The first pull-down module 40 is electrically connected to the second node Qb (2C-1), the stage signal output terminal (C (2C-1)), the scan driving signal output terminal (G (2C-1)), the first low voltage power source terminal (not labeled) and the second low voltage power source terminal (not labeled), and is connected to the first low voltage potential Vss1 from the first low voltage power source terminal and connected to the second low voltage potential Vss2 from the second low voltage power source terminal. The first pull-down module 40 outputs the 2C-1 th-level transfer signal C (2C-1) using the first potential of the second node Qb (2C-1), and outputs the 2C-1 th-level scan driving signal G (2C-1) using the first potential of the second node Qb (2C-1).

The first pull-down sustain module 50 is electrically connected to the first node Q (2C-1), the second node Qb (2C-1), the stage signal output terminal (C (2C-5)), and the first low voltage power terminal, and is connected to the first low voltage Vss1 from the first low voltage power terminal and is connected to the 2C-5 th stage signal C (2C-5) from the stage signal output terminal (C (2C-5)). The first pull-down maintaining module 50 maintains the levels of the first node Q (2C-1) and the second node Qb (2C-1) using the 2C-5 th stage transfer signal C (2C-5). The first pull-down maintaining module 50 is configured to pull down the potential of the second node Qb (2C-1) to a second potential when the first node Q (2n-1) is at the first potential, and the first pull-down module 40 stops outputting the 2C-1 th level transmission signal C (2C-1) and the scan driving signal G (2C-1).

In this embodiment, the 2C-5 th stage transmission signal C (2C-5) and the 2C +3 th stage transmission signal C (2C +3) are first stage transmission signals. The stage transmission signal of the first virtual GDL circuit is a second stage transmission signal.

The first GDL circuit 100A effectively ensures the stability of the voltages of the first node Q (2c-1) and the second node Qb (2c-1) through the cooperation of the functional modules, and ensures the accurate output of the first-stage transmission signal and the scanning driving signal. Specifically, the first pull-up control module 10 includes an eleventh transistor T11. The eleventh transistor T11 has a gate and a source electrically connected to the stage signal output terminal (C (2C-5)), and receives the stage 2C-5 signal C (2C-5), and a drain electrically connected to the first node Q (2C-1).

The first pull-up module 20 includes twenty-first and twenty-second transistors T21 and T22. The twenty-first transistor T21 has a source connected to the e-th clock signal ck (e), a gate electrically connected to the first node Q (2C-1), and a drain electrically connected to the stage signal output terminal (C (2C-1)). The twenty-second transistor T22 has a source connected to the e-th clock signal ck (e), a gate electrically connected to the first node Q (2C-1), and a drain electrically connected to the stage signal output terminal (C (2C-1)).

The first pull-down control module 30A includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The gate of the thirty-first transistor T31 is connected to the start signal STV, the source is electrically connected to the first node Q (2c-1), the drain is electrically connected to the first low voltage power source terminal, and the first low voltage power source terminal is connected to the first low voltage potential Vss 1. The thirty-second transistor T32 has a gate electrically connected to the second node Qb (2c-1), a source electrically connected to the first node Q (2c-1), and a drain electrically connected to the first low voltage power terminal and connected to the first low voltage Vss1 from the first low voltage power terminal. The gate of the thirty-third transistor T33 is electrically connected to the stage signal output terminal (C (2C +3)), and is connected to the 2C +3 rd stage signal C (2C +3), the source is electrically connected to the first node Q (2C-1), the drain is electrically connected to the first low voltage power source terminal, and is connected to the first low voltage Vss1 from the first low voltage power source terminal. The gate of the thirty-fourth transistor T34 is electrically connected to the second node Qb (2c-1), the source is electrically connected to the first node Q (2c-1), and the drain is electrically connected to the first low voltage power terminal and is connected to the first low voltage Vss1 from the first low voltage power terminal. For convenience of understanding and explanation, the thirtieth transistor T32 may be defined as a first pull-down control transistor, the thirtieth transistor T33 may be defined as a second pull-down control transistor, the thirty-fourth transistor T34 may be defined as a third pull-down control transistor, and the thirty-first transistor T31 may be defined as a fourth pull-down control transistor.

If the circuit shown in fig. 4 is a circuit connection structure of the scan driving units GDL5 to GDL1078, the gate of the thirty-third transistor T33 of the first GDL circuit 100A is connected to the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, the gate of the thirty-third transistor T33 of the first GDL circuit 100A is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the first dummy GDL circuit of the dummy scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, the gate of the thirty-third transistor T33 of the first GDL circuit 100A is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the first dummy GDL circuit of the dummy scan driving unit GDL 2.

The second pull-down control module 30B includes thirty-fifth, thirty-sixth, and thirty-seventh transistors T35, T36, and T37. The source and the gate of the thirty-fifth transistor T35 are electrically connected to the power voltage VDD, and the drain is electrically connected to the gate of the thirty-sixth transistor T36 and the source of the thirty-seventh transistor T37. The source of the thirty-sixth transistor T36 is electrically connected to the power voltage VDD, and the drain is electrically connected to the second node Qb (2 c-1). The thirty-seventh transistor T37 has a gate electrically connected to the first node Q (2c-1), a drain electrically connected to the first low voltage power source terminal, and a first low voltage Vss1 connected from the first low voltage power source terminal.

The first pull-down module 40 includes a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, and a forty-fourth transistor T44. The gate of the forty-first transistor T41 is electrically connected to the second node Qb (2C-1), the source is electrically connected to the stage signal output terminal (C (2C-1)), and the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage Vss1 from the first low voltage power source terminal. The gate of the forty-second transistor T42 is electrically connected to the second node Qb (2c-1), the source is electrically connected to the scan driving signal output terminal (G (2c-1)), and the drain is electrically connected to the second low voltage power source terminal and is connected to the second low voltage Vss2 from the second low voltage power source terminal. The gate of the forty-third transistor T43 is electrically connected to the fourth node Qb (2c), the source is electrically connected to the scan driving signal output terminal (G (2c-1)), and the drain is electrically connected to the second low voltage power source terminal and is connected to the second low voltage Vss2 from the second low voltage power source terminal. The gate of the forty-fourth transistor T44 is electrically connected to the fourth node Qb (2C), the source is electrically connected to the stage signal output terminal (C (2C-1)), and the drain is electrically connected to the second low voltage power source terminal and is connected to the second low voltage Vss2 from the second low voltage power source terminal.

The first pull-down maintaining module 50 includes a fifty-first transistor T51, a fifty-second transistor T52, and a fifty-third transistor T53. The fifty-first transistor T51 has a gate electrically connected to the first node Q (2c-1), a source electrically connected to the second node Qb (2c-1), and a drain electrically connected to the first low voltage power source terminal and connected to the first low voltage Vss1 from the first low voltage power source terminal. The gate of the fifty-second transistor T52 is electrically connected to the stage signal output terminal (C (2C-5)) and is connected to the stage 2C-5 signal C (2C-5), the drain is electrically connected to the first low-voltage power source terminal and is connected to the first low-voltage Vss1 from the first low-voltage power source terminal, and the source is electrically connected to the second node Qb (2C-1). The gate of the fifty-third transistor T53 is electrically connected to the third node Q (2c), the source is electrically connected to the drain of the thirty-fifth transistor T35, and the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage Vss1 from the first low voltage power source terminal.

The second GDL circuit 100B includes a second pull-up control module 60, a second pull-up module 70, a third pull-down control module 80A, a fourth pull-down control module 80B, a second pull-down module 90, a second pull-down maintaining module 55, a third node Q (2c), a fourth node Qb (2c), and a fifth node Qb (2c + 1).

The second pull-up control module 60 is electrically connected to the stage signal output terminal (C (2C-4)) and the third node Q (2C), and is connected to the 2C-4 th stage signal C (2C-4) from the stage signal output terminal (C (2C-4)). The second pull-up control module 60 utilizes the 2C-4 th level transmission signal C (2C-4) to pull up the potential of the third node Q (2C) to a first potential, where the first potential is a high point and the second potential is a low potential.

The second pull-up module 70 is connected to the e +1 th clock signal CK (e +1) and electrically connected to the third node Q (2C), the stage signal output terminal (C (2C)) and the scan driving signal output terminal (G (2C)). The second pull-up module 70 is configured to output a 2C-th stage transmission signal C (2C) and a 2C-th stage scanning driving signal G (2C) through the first potential of the third node Q (2C) under the control of the e + 1-th clock signal CK (e + 1).

The third pull-down control module 80A is connected to the start signal STV, and is electrically connected to the third node Q (2C), the fourth node Qb (2C), the first low voltage power source terminal, and the stage transmission signal output terminal (C (2C +4)), and is connected to the first low voltage potential Vss1 from the first low voltage power source terminal and connected to the 2C +4 th stage transmission signal C (2C +4) from the stage transmission signal output terminal (C (2C +4)), the third pull-down control module 80A pulls down the potential of the third node Q (2C) by using the start signal STV, and pulls down the potential of the third node Q (2C) to the second potential by using the 2C +4 th stage transmission signal C (2C + 4).

The third pull-down control module 80A and the second pull-down module 90 are connected to the fifth node Qb (2c +1), the fifth node Qb (2c +1) is electrically connected to the second node Qb (2c-1), and when the second node Qb (2c-1) is the first potential, the potential of the fifth node Qb (2c +1) is also the first potential, so as to control the second pull-down module 90 to output the 2 x-th-stage first-stage transmission signal having the second potential and stop outputting the scan driving signal.

If the circuit shown in fig. 4 is a circuit connection structure of the scan driver units GDL5 to GDL1078, the third pull-down control module 80A of the second GDL circuit 100B receives the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, the third pull-down control module 80A of the second GDL circuit 100B is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the second dummy GDL circuit of the dummy scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, the third pull-down control module 80A of the second GDL circuit 100B is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the second dummy GDL circuit of the dummy scan driving unit GDL 2.

The fourth pull-down control module 80B is connected to the power supply high voltage VDD, electrically connected to the third node Q (2c), and electrically connected to the fourth node Qb (2 c). The fourth pull-down control module 80B pulls up the potential of the fourth node Qb (2c) to the first potential using the low level of the third node Q (2c) and the power high voltage VDD.

The second pull-down module 90 is electrically connected to the fourth node Qb (2C), the stage signal output terminal (C (2C)), the scan driving signal output terminal (G (2C)), the first low voltage power source terminal, and the second low voltage power source terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power source terminal and the second low voltage potential Vss2 from the second low voltage power source terminal. The second pull-down module 90 outputs the 2C-th stage transmission signal C (2C) using the first potential of the fourth node Qb (2C), and outputs the 2C-th stage scanning driving signal G (2C) using the first potential of the fourth node Qb (2C).

The second pull-down sustain module 55 is electrically connected to the third node Q (2C), the fourth node Qb (2C), the stage signaling output terminal (C (2C-5)), and the first low voltage power terminal, and is connected to the first low voltage Vss1 from the first low voltage power terminal and to the 2C-5 th stage signaling signal C (2C-5) from the stage signaling output terminal (C (2C-5)). The levels of the third node Q (2C) and the fourth node Qb (2C) are maintained by the level 2C-5 stage pass signal C (2C-5). The first pull-down maintaining module 50 is configured to pull down the potential of the fourth node Qb (2c) to the second potential when the third node Q (2c) is at the first potential.

In this embodiment, the 2C-4 th stage transmission signal C (2C-4) and the 2C +4 th stage transmission signal C (2C +4) are first stage transmission signals. The stage signal of the second virtual GDL circuit is a second stage signal.

The second GDL circuit 100B effectively ensures the stability of the voltages of the third node Q (2c) and the fourth node Qb (2c) by the cooperation of the functional modules, and ensures the accurate output of the first-stage transmission signal and the scanning driving signal.

In an exemplary embodiment, when the first node Q (2c-1) is at the first potential, the first pull-down maintaining module 50 pulls down the potential of the second node Qb (2c-1) to the second potential, the first pull-down module 40 stops outputting the first stage transmission signal and the scan driving signal, when the third node Q (2c) is at the first potential, the first pull-down maintaining module 50 controls the second node Qb (2c-1) to stop receiving the power supply voltage, and the first pull-down module 40 stops outputting the first stage transmission signal and the scan driving signal. When the first node Q (2c-1) is at the first potential, the second pull-down maintaining module 55 controls the fourth node Qb (2c) to stop receiving the power voltage, the second pull-down module 90 stops outputting the first level pass signal and the scan driving signal, when the third node Q (2c) is at the first potential, the second pull-down maintaining module 55 pulls down the potential of the fourth node Qb (2c) to the second potential, and the second pull-down module 90 stops outputting the first level pass signal and the scan driving signal.

In this embodiment, the first pull-down maintaining module 50 in the first GDL circuit 100A and the second pull-down maintaining module 55 in the second GDL circuit 100B are connected to the first stage transmission signal provided by the corresponding cascaded GDL circuit, so that the output of the first stage transmission signal and the scan driving signal in the current scan driving unit can be accurately maintained, and the accuracy of the output timing sequence of the scan driving signal of each scan driving unit is improved.

The second pull-up control module 60 includes a sixty-first transistor T61. The sixty-first transistor T61 has a gate and a source electrically connected to the stage signal output terminal (C (2C-4)), and is connected to the 2C-4 stage signal C (2C-4), and a drain electrically connected to the third node Q (2C).

The second pull-up module 70 includes a seventy-first transistor T71 and a seventy-second transistor T72. The source of the seventy-first transistor T71 is connected to the e +1 th clock signal CK (e +1), the gate thereof is electrically connected to the third node Q (2C), and the drain thereof is electrically connected to the stage signal output terminal (C (2C)). The seventy-second transistor T72 has a source connected to the (e +1) th clock signal CK (e +1), a gate electrically connected to the third node Q (2C), and a drain electrically connected to the stage signal output terminal (C (2C)).

The third pull-down control module 80A includes an eighty-first transistor T81, an eighty-second transistor T82, an eighty-third transistor T83, and an eighty-fourth transistor T84. The gate of the eighty-first transistor T81 is connected to the start signal STV, the source is electrically connected to the third node Q (2c), and the drain is electrically connected to the first low-voltage power source terminal and to the first low-voltage potential Vss1 from the first low-voltage power source terminal. The eighty-second transistor T82 has a gate electrically connected to the fourth node Qb (2c), a source electrically connected to the third node Q (2c), and a drain electrically connected to the first low voltage power source terminal and connected to the first low voltage potential Vss1 from the first low voltage power source terminal. The gate of the eighty-third transistor T83 is electrically connected to the stage signal output terminal (C (2C +4)), and is connected to the 2C +4 th stage signal C (2C +4), the source is electrically connected to the third node Q (2C), and the drain is electrically connected to the first low voltage power source terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power source terminal. The eighty-fourth transistor T84 has a gate electrically connected to the fifth node Qb (2c +1), a source electrically connected to the third node Q (2c), and a drain electrically connected to the first low voltage power source terminal and connected to the first low voltage potential Vss1 from the first low voltage power source terminal.

In this embodiment, the first pull-down control module 30A and the third pull-down control module 80A in the 9-2 n-th stage GDL circuit respectively include four pull-down control transistors and access a Reset signal Reset, and when the first pull-down module 20 or the second pull-down module 70 is abnormal, the pull-down control transistors in the first pull-down control module 30A and the third pull-down control module 80A can accurately control the stop of the output of the first stage transmission signal and the scan driving signal according to the Reset signal Reset. Meanwhile, the resistance-capacitance loads (RC loading) of each stage of GDL circuit are close, so that the electronic elements such as transistors in each GDL circuit in the 2n stage of GDL circuit are the same, and the integrity and the working stability are better.

For convenience of understanding and explanation, the eighty-first transistor may be defined as a fifth pull-down control transistor, the eighty-second transistor may be defined as a sixth pull-down control transistor, the eighty-third transistor may be defined as a seventh pull-down control transistor, and the eighty-fourth transistor may be defined as an eighth pull-down control transistor.

If the circuit shown in fig. 4 is a circuit connection structure of the scan driver cells GDL5 to GDL1078, the gate of the eighty-first transistor T81 of the second GDL circuit 100B is connected to the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, the gate of the eighty-first transistor T81 of the second GDL circuit 100B is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the second dummy GDL circuit of the dummy scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, the gate of the eighty-first transistor T81 of the second GDL circuit 100B is electrically connected to the dummy stage signal output terminal and is connected to the stage signal of the second dummy GDL circuit of the dummy scan driving unit GDL 2.

The fourth pull-down control module 80B includes an eighty-five transistor T85, an eighty-six transistor T86, and an eighty-seven transistor T87. The source and the gate of the eighty-five transistor T85 are connected to the power voltage VDD, and the drain of the eighty-five transistor T85 is electrically connected to the gate of the eighty-six transistor T86 and the source of the eighty-seven transistor T87. The source of the eighty-sixth transistor T86 is connected to the power voltage VDD, and the drain is electrically connected to the fourth node Qb (2 c). The eighty-seventh transistor T87 has a gate electrically connected to the third node Q (2c), a drain electrically connected to the first low voltage power source terminal, and a first low voltage Vss1 connected from the first low voltage power source terminal.

The second pull-down module 90 includes a ninety first transistor T91, a ninety second transistor T92, a ninety third transistor T93, and a ninety fourth transistor T94. The gate of the ninety-first transistor T91 is electrically connected to the fourth node Qb (2C), the source is electrically connected to the stage signal output terminal (C (2C)), and the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage Vss1 from the first low voltage power source terminal. The gate of the ninety second transistor T92 is electrically connected to the fourth node Qb (2c), the source outputs the 2 c-th scan driving signal G (2c), and the drain is connected to the second low voltage Vss 2. The gate of the ninety-third transistor T93 is electrically connected to the fifth node Qb (2c +1), the source is electrically connected to the scan driving signal output terminal (G (2c)), and the drain is electrically connected to the second low voltage power source terminal and is connected to the second low voltage Vss2 from the second low voltage power source terminal. The gate of the ninety-fourth transistor T94 is electrically connected to the fifth node Qb (2C +1), the source is electrically connected to the stage signal output terminal (C (2C)), and the drain is electrically connected to the second low voltage power source terminal and is connected to the second low voltage Vss2 from the second low voltage power source terminal.

The second pull-down maintenance module 55 includes a ninety-fifth transistor T95, a ninety-sixth transistor T96, and a ninety-seventh transistor T97. The gate of the ninety-fifth transistor T95 is electrically connected to the third node Q (2c), the source is electrically connected to the fourth node Qb (2c), and the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage Vss1 from the first low voltage power source terminal. The gate of the ninety-sixth transistor T96 is electrically connected to the stage signal output terminal (C (2C-5)) and is connected to the stage 2C-5 signal C (2C-5), the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage Vss1 from the first low voltage power source terminal, and the source is electrically connected to the fourth node Qb (2C). The gate of the ninety-seventh transistor T97 is electrically connected to the first node Q (2c-1), the source is electrically connected to the drain of the eighty-fifth transistor T85, and the drain is electrically connected to the first low voltage power source terminal and is connected to the first low voltage potential Vss1 from the first low voltage power source terminal.

Referring to fig. 5, fig. 5 is a circuit diagram of one of the scan driving units GDL 1-GDL 4 shown in fig. 3. Taking the scanning driving unit GDLi as an example, i is 1, 2, 3, 4. The first GDL circuit 100A of the scan driving unit GDLi is different from the first GDL circuit 100A of the scan driving unit GDLc in that: the thirty-first transistor T31 is not designed in the first pull-down control module 30A of the first GDL circuit 100A of the scan driving unit GDLi and the start signal STV is not inputted. The second GDL circuit 100B of the scan driving unit GDLi is different from the second GDL circuit 100B of the scan driving unit GDLc in that: the eighty-first transistor T81 is not designed in the second pull-down control module 80A of the second GDL circuit 100B of the scan driving unit GDLi and the start signal STV is not accessed. In this embodiment, that is, in the 1 st to 8 th-level GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A respectively include three pull-down control transistors, and the resistance-capacitance loads (RC loading) of the 1 st to 8 th-level GDL circuits are close to each other, so that the working stability of the 1 st to 8 th-level GDL circuits is better.

Specifically, in the embodiment of the present application, the first pull-up control module 10 in the scan driving units GDL 1-GDL 4 accesses the start signal STV for pulling up the potential of the first node Q (2i-1) to the first potential, and when the first node Q (2i-1) is the first potential, the first pull-up module 20 outputs the level transmission signal with the first potential. That is, the gate and source of the eleventh transistor T11 of the scan driving units GDL1 to GDL4 receive the start signal STV. The first pull-down sustain module 50 in the scan driving units GDL1 and GDL2 is connected to the start signal STV, the first pull-down sustain module 50 in the scan driving units GDL3 and GDL4 is electrically connected to the stage signal output terminal (C (2i-5)) and is connected to the 2i-5 th stage signal C (2i-5), that is, the gate of the fifty-th transistor T52 in the scan driving units GDL1 and GDL2 is connected to the start signal STV, and the gates of the fifty-th transistor T52 in the scan driving units GDL3 and GDL4 are electrically connected to the stage signal output terminal (C (2i-5)) and are connected to the 2i-5 th stage signal C (2 i-5).

In this embodiment, the 2i-1 st stage transmission signal C (2i-1) and the 2i stage transmission signal C (2i) are first stage transmission signals.

The second pull-up control module 60 of the scan driving units GDL 1-GDL 4 receives a start signal STV for pulling up the voltage level of the third node Q (2i) to a first voltage level, and when the voltage level of the third node Q (2i) is the first voltage level, the second pull-up module 70 outputs a level transmission signal having the first voltage level. That is, the gate and source of the sixty-first transistor T61 in the scan driving units GDL1 to GDL4 are connected to the start signal STV. The second pull-down sustain module 55 in the scan driving units GDL1 and GDL2 receives the start signal STV, the second pull-down sustain module 55 in the scan driving units GDL3 and GDL4 receives the stage signal output terminal (C (2i-5)) and receives the 2i-5 th stage transmission signal C (2i-5), i.e., the gate of the ninety-sixth transistor T96 in the scan driving units GDL1 and GDL2 receives the start signal STV, the gate of the ninety-sixth transistor T96 in the scan driving units GDL3 and GDL4 receives the stage transmission signal output terminal (C (2i-5)), and the 2i-5 th stage transmission signal C (2 i-5).

The first pull-up control module 10 and the second pull-up control module 60 are directly connected to the start signal, so that the potentials of the first node Q (2i-1) and the third node Q (2i) can be accurately pulled up to the first potential, and the first pull-up module 20 and the second pull-up module 70 are accurately and rapidly controlled to output corresponding first-stage transmission signals and scanning driving signals.

Referring to fig. 6, fig. 6 is a circuit diagram of one of the dummy scan driving units GDL1 and GDL2 shown in fig. 3.

Each of the dummy scan driving units includes two dummy GDL circuits, the four dummy GDL circuits are sequentially arranged, and the four dummy GDL circuits are respectively connected to two GDL circuits in the nth stage scan driving unit and two GDL circuits in the nth-1 stage scan driving unit, and respectively output the second stage transmission signal to two GDL circuits in the nth stage scan driving unit and two GDL circuits in the nth-1 stage scan driving unit, so as to drive the two GDL circuits in the nth stage scan driving unit and the two GDL circuits in the nth-1 stage scan driving unit to stop outputting the scan driving signal.

The dummy scan driver cells GDL 1-GDL 2 also include a first dummy GDL circuit 200A and a second dummy GLD circuit 200B, respectively.

The first dummy GDL circuit 200A includes a first dummy pull-up control module 210, a first dummy pull-up module 220, a first dummy pull-down control module 230A, a second dummy pull-down control module 230B, a first dummy pull-down module 240, a first dummy pull-down maintenance module 250, a first dummy node P (2j-1), and a second dummy node Pb (2 j-1).

The first virtual pull-up control module 210, the first virtual pull-up module 220 and the first virtual pull-down control module 230A are electrically connected to the first virtual node P (2 j-1).

The first dummy pull-up control module 210 is configured to pull up the potential of the first dummy node P (2j-1) to a first potential, and when the potential of the first dummy node P (2j-1) is the first potential, the first dummy pull-up module 220 outputs the second stage transmission signal having the first potential, and the second stage transmission signal is configured to control one of the GDL circuits in the nth stage scan driving unit and the nth-1 stage scan driving unit to output the first stage transmission signal having the second potential and stop outputting the scan driving signal.

The first dummy pull-down control module 230A is configured to pull down the potential of the first dummy node P (2j-1) to a second potential.

The second dummy pull-down control module 230B and the first dummy pull-down module 240 are electrically connected to the second dummy node Pb (2j-1), the second dummy pull-down control module 230B is configured to pull up the potential of the second dummy node Pb (2j-1) to a first potential, and when the potential of the second dummy node Pb (2j-1) is the first potential, the first dummy pull-down module 240 outputs the second pass signal having a second potential.

The second dummy GDL circuit 200B includes a second dummy pull-up control module 260, a second dummy pull-up module 270, a third dummy pull-down control module 280A, a fourth dummy pull-down control module 280B, a second dummy pull-down module 290, a second dummy pull-down maintenance module 255, a third dummy node P (2j), a fourth dummy node Pb (2j), and a fifth dummy node Pb (2j +1), and the first dummy pull-down module 240 is electrically connected to the fourth dummy node Pb (2 j).

The second virtual pull-up control module 260, the second virtual pull-up module 270, and the third virtual pull-down control module 280A are electrically connected to the third virtual node P (2 j).

The second virtual pull-up control module 260 is configured to pull up the potential of the third virtual node P (2j) to a first potential, and when the potential of the third virtual node P (2j) is the first potential, the second virtual pull-up module 270 outputs a second level transmission signal having the first potential, where the second level transmission signal is configured to control one of the nth level scan driving unit and the n-1 th level scan driving unit to output the first level transmission signal having the second potential and stop outputting the scan driving signal.

The second dummy pull-down control module 290 is configured to pull down the potential of the third dummy node P (2j) to a second potential.

The fourth dummy pull-down control module 280B and the second dummy pull-down module 290 are electrically connected to the fourth dummy node Pb (2j), the fourth dummy pull-down control module 280B is configured to pull up the potential of the fourth dummy node Pb (2j) to a first potential, and when the potential of the fourth dummy node Pb (2j) is the first potential, the second dummy pull-down module 290 outputs the second level transmission signal having a second potential.

The first dummy pull-down maintaining module 250 is electrically connected to the first dummy node P (2j-1), the second dummy node Pb (2j-1), and the third dummy node P (2j), when the potential of the first dummy node P (2j-1) is a first potential, the first dummy pull-down maintaining module 250 pulls down the potential of the second dummy node Pb (2j-1) to a second potential, the first dummy pull-down maintaining module 240 stops outputting the second level transmission signal, when the potential of the third dummy node P (2j) is the first potential, the first dummy pull-down maintaining module 250 controls the second dummy node Pb (2j-1) to stop receiving the power voltage, and the first dummy pull-down maintaining module 240 stops outputting the second level transmission signal.

The second virtual pull-down maintaining module 290 is electrically connected to the first virtual node P (2j-1), the third virtual node P (2j) and the fourth virtual node Pb (2j), when the potential of the first virtual node P (2j-1) is the first potential, the second virtual pull-down maintaining module 255 controls the fourth virtual node Pb (2j) to stop receiving the power voltage, the second virtual pull-down module 290 stops outputting the second level transmission signal, when the potential of the third virtual node P (2j) is the first potential, the second virtual pull-down maintaining module 255 pulls down the fourth virtual node Pb (2j) to the second potential, and the second virtual pull-down module 290 stops outputting the second level transmission signal.

The third dummy pull-down control module 280A and the second dummy pull-down module 290 are connected to the fifth dummy node Pb (2j +1), the fifth dummy node Pb (2j +1) is electrically connected to the second dummy node Pb (2j-1), and when the second dummy node Pb (2j-1) is the first potential, the potential of the fifth dummy node Pb (2j +1) is also the first potential, so as to control the second dummy pull-down module 290 to output the second pass signal having the second potential.

In this embodiment, the two virtual GDL circuits effectively ensure the stability of the voltages of the first virtual node P (2j-1) and the second virtual node Pb (2j-1) through the cooperation of the functional modules, and ensure the accurate output of the second-stage transmission signal.

In this embodiment, the first dummy pull-down maintaining module 250 in the first dummy GDL circuit 200A and the second dummy pull-down maintaining module 255 in the second dummy GDL circuit 200B are connected to the first stage transmission signal provided by the corresponding cascaded GDL circuit, so that the output of the second stage transmission signal in the current dummy scan driving unit can be accurately maintained, and the accuracy of the output timing sequence of the second stage transmission signal of each dummy scan driving unit is improved.

Specifically, the first dummy GDL circuit 200A of the dummy scan driving unit GDL1 outputs a first dummy stage transfer signal Ca (1) and a first dummy stage scan driving signal Ga (1), the second dummy GDL circuit 200B of the dummy scan driving unit GDL1 outputs a first dummy stage transfer signal Ca (2) and a first dummy stage scan driving signal Ga (2), the first dummy GDL circuit 200A of the dummy scan driving unit GDL2 outputs a third dummy stage transfer signal Ca (3) and a third dummy stage scan driving signal Ga (3), and the second dummy GDL circuit 200A of the dummy scan driving unit GDL2 outputs a fourth dummy stage transfer signal Ca (1) and a fourth dummy stage scan driving signal Ga (1).

In this embodiment, the first to fourth dummy stage signals Ca (1) to Ca (4) are second stage signals.

The first dummy GDL circuit 200A has the same structure as the first GDL circuit 100A, and the second dummy GDL circuit 200B has the same structure as the second GDL circuit 100B. That is, the first virtual pull-up control module 210 has the same circuit structure as the first pull-up control module 10, the first virtual pull-up module 220 has the same circuit structure as the first pull-up module 20, the first virtual pull-down control module 230A has the same circuit structure as the first pull-down control module 30A, the second virtual pull-down control module 230B has the same circuit structure as the second pull-down control module 30B, the first virtual pull-down module 240 has the same circuit structure as the first pull-down module 40, and the first virtual pull-down maintaining module 250 has the same circuit structure as the first pull-down maintaining module 50.

The second virtual pull-up control module 260 has the same circuit structure as the second pull-up control module 60, the second virtual pull-up module 270 has the same circuit structure as the second pull-up module 70, the third virtual pull-down control module 280A has the same circuit structure as the third pull-down control module 80A, the fourth virtual pull-down control module 280B has the same circuit structure as the fourth pull-down control module 80B, the second virtual pull-down module 290 has the same circuit structure as the second pull-down module 90, and the second virtual pull-down maintaining module 255 has the same circuit structure as the second pull-down maintaining module 55.

Since the first GDL circuit 100A and the second GDL circuit 100B have been described in detail above, they are not described herein again.

The virtual scan driving unit GDL is different from the scan driving unit GDL in that: the stage transfer signal is not received in the first pull-down control block 230A of the first dummy GDL circuit 200A of the dummy scan driving units GDL 1-GDL 2, and the Reset signal Reset is received. The stage signals are not received in the first dummy pull-down control modules 280A of the dummy scan driving units GDL 1-GDL 2, and the Reset signal Reset is received.

Specifically, in the present embodiment, the gates of the thirty-first transistor T31 and the thirty-third transistor T33 of the first virtual GDL circuit 200A of the virtual scan driving units GDL 1-GDL 2 are connected to the Reset signal Reset and the start signal STV, respectively. The gates of the eighty-first transistor T81 and the eighty-third transistor T83 of the second virtual GDL circuit 200B of the virtual scan driving units GDL 1-GDL 2 are turned on the Reset signal Reset and the start signal STV, respectively.

The gate of the eleventh transistor T11 of the first dummy GDL circuit 200A of the dummy scan driving unit GDL1 is electrically connected to the stage signal output terminal (C (2157)) and is connected to the 2157 th stage signal C (2157), the gate of the sixty-first transistor T61 of the second dummy GDL circuit 200B of the dummy scan driving unit GDL1 is electrically connected to the stage signal output terminal (C (2158)) and is connected to the 2158 th stage signal C (2158), the gate of the eleventh transistor T11 of the first dummy GDL circuit 200A of the dummy scan driving unit GDL2 is electrically connected to the stage signal output terminal (C (2159)) and is connected to the 2159 th stage signal C (2159), the gate of the second dummy GDL circuit 200B of the dummy scan driving unit GDL2 is electrically connected to the stage signal output terminal (C (2160)) and is connected to the 2160 th stage signal C (2160).

The gate of the fifty-second transistor T52 of the first dummy GDL circuit 200A of the dummy scan driving unit GDL1 is electrically connected to the stage signal output terminal (C (2157)), and is connected to the 2157 th stage transmission signal C (2157), the gate of the ninety-sixth transistor T96 of the second virtual GDL circuit 200B of the virtual scan driving unit GDL1 is electrically connected to the stage transmission signal output terminal (C (2157)), and is connected to the 2157 stage transmission signal C (2157), the gate of the fifty-second transistor T52 of the first virtual GDL circuit 200A of the virtual scan driving unit GDL2 is electrically connected to the stage transmission signal output terminal (C (2159)), and is connected to the 2159 th-stage transmission signal C (2159), the gate of the ninety-sixth transistor T96 of the second virtual GDL circuit 200B of the virtual scan driver unit GDL2 is electrically connected to the stage transmission signal output terminal (C (2157)), and is connected to the 2159 th-stage transmission signal C (2159).

Referring to fig. 7 and 8 together, fig. 7 is a schematic diagram illustrating a layout structure of the scan driving units GDL 1-GDL 4 shown in fig. 5, and fig. 8 is a circuit layout diagram of the scan driving units GDL 1-GDL 4 shown in fig. 5.

As shown in fig. 7 and 8, the first GDL circuit 100A and the second GDL circuit 100B of the scan driver GDL1 to the first GDL circuit 100A and the second GDL circuit 100B of the scan driver GDL4 respectively correspond to the access clock signals CK (1) -CK (8), so that the first GDL circuit 100A of the scan driver GDL1 directly corresponds to the first clock signal CK (1) and better matches with the timing control circuit 101.

The first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL1 to the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL4 are both connected to the first low voltage potential Vss1 and the second low voltage potential Vss 2. Two of the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL1 and the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL2 are connected to the start signal STV, and only one of the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL3 and the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL4 is connected to the start signal STV, because the circuits of the scan driving units GDL3 and GDL4 realize pull-down through the level signals of the scan driving units GDL1 and GDL 2.

Referring to fig. 9 and 10 together, fig. 9 is a schematic diagram illustrating a layout structure of any four scan driving units GDL 5-GDL 1080 as shown in fig. 4, and fig. 10 is a circuit layout diagram illustrating any four scan driving units GDL 5-GDL 1080 as shown in fig. 4.

As shown in fig. 9 and 10, the 8k +1 th to 8k +8 th GDL circuits respectively access the clock signals CK (1) to CK (8), for example, the 8k +1 th GDL circuit accesses the first clock signal CK (1), and the 8k +5 th GDL circuit accesses the fifth clock signal CK (5).

The 8k +1 stage GDL circuit to the 8k +8 stage GDL are connected with a first low voltage potential Vss1, a second low voltage potential Vss2 and a start signal STV. The 8k +1 th stage GDL circuit outputs an 8k +1 th stage transfer signal C (8k +1) and an 8k +1 th stage scan driving signal G (8k +1), the 8k +2 th stage GDL circuit outputs an 8k +2 th stage transfer signal C (8k +2) and an 8k +2 th stage scan driving signal G (8k +2), … …, and the 8k +8 th stage GDL circuit outputs an 8k +8 th stage transfer signal C (8k +1) and an 8k +8 th stage scan driving signal G (8k + 1).

Referring to fig. 11 and 12 together, fig. 11 is a schematic diagram illustrating a layout structure of the dummy scan driving cells GDL1 and GDL2 shown in fig. 6, and fig. 12 is a circuit layout diagram of the dummy scan driving cells GDL1 and GDL2 shown in fig. 6.

As shown in fig. 11 and 12, the first-stage virtual GDL circuit to the fourth-stage virtual GDL circuit are respectively connected to clock signals CK (1) to CK (4), and the first-stage virtual GDL circuit to the fourth-stage virtual GDL circuit are connected to a first low-voltage potential Vss1, a second low-voltage potential Vss2, a start signal STV, and a Reset signal Reset. The first-stage dummy GDL circuit outputs a first dummy stage transfer signal Ca (1) and a first dummy stage scan driving signal Ga (1), … …, and the fourth-stage dummy GDL circuit outputs a fourth dummy stage transfer signal Ca (4) and a fourth dummy stage scan driving signal Ga (4).

Referring to FIG. 13, FIG. 13 is a timing diagram illustrating a circuit-frame image display process of any one of the scan driving units GDL 1-GDL 1080. As shown in fig. 13, C (2n-5) is the stage transfer signal C (2n-5) of the 2n-5 th stage GDL circuit, C (2n-4) is the stage transfer signal C (2n-4) of the 2n-4 th stage GDL circuit, and STV is the start signal. Q (2n-1) is a first node Q (2n-1) of the first GDL circuit of the scan driving unit GDLn, and Q (2n) is a third node Q (2n) of the second GDL circuit of the scan driving unit GDLn. G (2n-1) is a 2n-1 th-stage scan driving signal G (2n-1) output from the first GDL circuit of the scan driving unit GDLn, and G (2n) is a2 n-th-stage scan driving signal G (2n) output from the second GDL circuit of the scan driving unit GDLn.

In the scan driving unit GDL1, the potential of the first node Q (1) is pulled up by the start signal STV, the first stage scan driving signal G (1) is output under the control of the clock signal ck (e), the potential of the third node Q (2) is pulled up by the start signal STV, and the first stage scan driving signal G (2) is output under the control of the clock signal ck (e).

In the scanning driving unit GDL2, the potential of the first node Q (3) is pulled up by the start signal STV, the third-stage scanning driving signal G (3) is output under the control of the clock signal ck (e), the potential of the third node Q (4) is pulled up by the start signal STV, and the fourth-stage scanning driving signal G (4) is output under the control of the clock signal ck (e).

In any of the scan driving units GDL3 to GDL1080, the potential of the first node Q (2n-1) is pulled up by the 2n-5 th stage transfer signal C (2n-5), and the 2n-1 st stage scan driving signal G (2n-1) is output under the control of the clock signal ck (e). The potential of the third node Q (2n) is pulled up by the 2n-4 th stage transfer signal C (2n-4), and the 2 n-th stage scan driving signal G (2n) is output under the control of the clock signal CK (e + 1).

Specifically, in the embodiment, when the start signal STV is high in the scan driving units GDL1 to GDL2, the eleventh transistor T11 is turned on, the first node is raised to a high potential, the twentieth transistor T22 is turned on, and the scan driving signal is output under the control of the clock signal ck (e). When the start signal STV is at a high level, the sixty-first transistor T61 is turned on, the third node rises to a high level, the seventy-second transistor T72 is turned on, and the scan driving signal is output under the control of the clock signal ck (e). In the scanning driving units GDL3 to GDL1080, when the 2n-5 th stage transfer signal C (2n-5) is at a high potential, the eleventh transistor T11 is turned on, the first node Q (2n-1) rises to a high potential, the twentieth transistor T22 is turned on, and the 2n-1 th stage scanning driving signal G (2n-1) is output under the control of the clock signal ck (e). When the 2n-4 th stage transfer signal C (2n-4) is at a high level, the sixty-first transistor T61 is turned on, the third node Q (2n) rises to a high level, the seventy-second transistor T72 is turned on, and the 2n-1 th stage scan driving signal G (2n-1) is output under the control of the clock signal CK (e + 1).

To sum up, in the embodiment of the present application, the scan driving circuit 103 includes a scan driving module 100 and a virtual scan driving module 200, the scan driving unit GDL 1-GDL 8 in the scan driving module 100 has a start signal STV accessed in the first pull-down control module 30A and the second pull-down control module 80A, so that the scan driving circuit 103 can be normally driven, and since only the virtual scan driving unit is needed to be arranged at the end of the cascaded scan driving unit to control the level transmission of the scan driving signal, the number of the virtual scan driving units and the occupied space are effectively reduced.

Further, in the 1 st to 8 th-stage GDL circuits, that is, the 2i-1 st-stage GDL circuit, the first pull-down control module 30A is not provided with the thirty-first transistor T31, and the second pull-down control module 80A is not provided with the eighty-first transistor T81, where i is 1, 2, 3, 4. The number of the transistors of each stage of scanning driving unit GDL is ensured to be consistent, and the stability of the circuit structure can be effectively improved.

Referring to fig. 14, fig. 14 is a circuit diagram of a scan driving unit of the scan driving units GDL 1-GDL 4 shown in fig. 3 according to a second embodiment of the present application. The embodiments of the present application are different from the first embodiment in the scan driving units GDL 1-GDL 4 shown in fig. 5 in that: the first pull-down control module 30A of the second embodiment of the scan driving units GDL 1-GDL 4 is provided with a thirty-first transistor T31 and receives a Reset signal Reset, and the second pull-down control module 80A of the second embodiment of the scan driving units GDL 1-GDL 4 is provided with an eighty-first transistor T81 and receives a Reset signal Reset.

Specifically, in the present embodiment, the gate of the thirty-first transistor T31 of the scan driving units GDL 1-GDL 4 of the second embodiment is connected to the Reset signal Reset, the source is electrically connected to the first node Q (2i-1), the drain is electrically connected to the first low voltage power source terminal, and the first low voltage power source terminal is connected to the first low voltage Vss 1. The gate of the eighty-first transistor T81 of the scan driving units GDL 1-GDL 4 of the second embodiment is connected to the Reset signal Reset, the source is electrically connected to the third node Q (2i), the drain is electrically connected to the first low voltage power source terminal, and the first low voltage power source terminal is connected to the first low voltage Vss 1.

Furthermore, the GDL circuit or the virtual GDL circuit in each group respectively receives a clock signal, and at the same time, the first GDL circuit can receive the first clock signal CK (1), that is, the first stage GDL circuit directly corresponds to the first clock CK (1), so that the matching degree between the scan driving circuit 103 and the timing control circuit 101 and other functional circuits using clock signals is better.

In the embodiment of the present application, in the 1 st to 8 th stage GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A respectively include four pull-down control transistors and access a Reset signal Reset, and when the first pull-down module 20 or the second pull-down module 70 is abnormal, each of the pull-down control transistors in the first pull-down control module 30A and the third pull-down control module 80A can accurately control the stop output of the first stage transmission signal and the scan driving signal according to the Reset signal Reset. Correspondingly, in the 9 th-2 n-level GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A also include four pull-down control transistors, so that the resistance-capacitance loads (RC loading) of each level of GDL circuit are close, and therefore, the transistors and other electronic elements in each GDL circuit in the 2 n-level GDL circuit are the same, and the integrity and the working stability are better.

In the description herein, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that the application of the present application is not limited to the above examples, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims. Those skilled in the art will recognize that all or a portion of the above-described embodiments can be practiced without departing from the spirit and scope of the present disclosure, which is encompassed by the claims.

Claims

1. A scanning drive circuit comprises n scanning drive units and two virtual scanning drive units which are sequentially arranged and cascaded, wherein each scanning drive unit is used for outputting two scanning drive signals with preset time intervals, each virtual scanning drive unit is used for outputting two stage transmission signals with preset time intervals,

the x-th scanning driving unit is cascaded to the x-2 th scanning driving unit and outputs two first-stage transmission signals to the x-2 th scanning driving unit, wherein x is more than 2 and is not more than n;

the two virtual scanning driving units are respectively connected with the nth-1 level scanning driving unit and the nth level scanning driving unit and respectively output two second level transmission signals to the nth-1 level scanning driving unit and the nth level scanning driving unit, and the first level transmission signals and the second level transmission signals are used for driving the scanning driving units to output the scanning driving signals.

2. The scan driver circuit according to claim 1,

the n scanning driving units and the two virtual scanning driving units are divided into 4y groups, each group respectively receives eight clock signals, each scanning driving unit and each virtual scanning driving unit respectively receive two clock signals, and y is a positive integer.

3. The scan driving circuit according to any one of claims 1 to 2,

each scan driving unit comprises two mutually connected GDL circuits, each GDL circuit is used for outputting one scan driving signal, the n scan driving units comprise 2n mutually cascaded GDL circuits, wherein the x-th scan driving unit comprises a2 x-level GDL circuit and a2 x-1-level GDL circuit, the 2 x-level GDL circuit is cascaded with a2 x-4-level GDL circuit, the 2 x-1-level GDL circuit is cascaded with a2 x-5-level GDL circuit, the 2 x-1-level GDL circuit is a first GDL circuit, the 2 x-level GDL circuit is a second GDL circuit,

the first GDL circuit is used for receiving a 2x-5 level first level transmission signal transmitted by the 2x-5 level GDL circuit and outputting a 2x-1 level first level transmission signal and a scanning driving signal according to the 2x-5 level first level transmission signal;

the second GDL circuit is used for receiving the 2x-4 level first level transmission signal transmitted by the 2x-4 level GDL circuit and outputting a 2x level first level transmission signal and a scanning driving signal according to the 2x-4 level first level transmission signal.

4. The scan drive circuit according to claim 3,

the first GDL circuit comprises a first pull-up control module, a first pull-up module, a first pull-down control module, a second pull-down control module, a first pull-down module, a first node and a second node,

the first pull-up control module, the first pull-up module and the first pull-down control module are electrically connected to the first node,

the first pull-up control module is used for pulling up the potential of the first node to a first potential according to a received 2x-5 level first level transmission signal, when the potential of the first node is the first potential, the first pull-up module outputs a 2x-1 level first level transmission signal with the first potential, the 2x-1 level first level transmission signal is used for controlling a 2x-5 level GDL circuit in the x-2 level scanning driving unit to output a 2x-5 level first level transmission signal of a second potential and stop outputting the scanning driving signal, and controlling a 2x +3 level GDL circuit in the x +2 level scanning driving unit to output a 2x +3 level first level transmission signal of the first potential and output the scanning driving signal;

the first pull-down control module is used for pulling down the electric potential of the first node to a second electric potential,

the second pull-down control module and the first pull-down module are electrically connected to the second node, the second pull-down control module is used for pulling up the potential of the second node to a first potential, and when the potential of the second node is the first potential, the first pull-down module outputs a 2x-1 stage first-stage transmission signal with a second potential.

5. The scan driver circuit according to claim 4,

the second GDL circuit includes a second pull-up control module, a second pull-up module, a third pull-down control module, a fourth pull-down control module, a second pull-down module, a third node, and a fourth node,

the first pull-down module is electrically connected with the fourth node, the second pull-up control module, the second pull-up module and the third pull-down control module are electrically connected with the third node,

the second pull-up control module is used for pulling up the potential of the third node to a first potential according to a received 2x-4 level first level transmission signal, when the third node is at the first potential, the second pull-up module outputs a 2x level first level transmission signal with the first potential, the 2x level first level transmission signal is used for controlling a 2x-4 level GDL circuit in the x-2 level scanning driving unit to output a 2x-4 level first level transmission signal of a second potential and stop outputting the scanning driving signal, and controlling a 2x +4 level GDL circuit in the x +2 level scanning driving unit to output a 2x +4 level first level transmission signal of the first potential and output the scanning driving signal,

the second pull-down control module is used for pulling down the electric potential of the third node to a second electric potential,

the fourth pull-down control module and the second pull-down module are electrically connected to the fourth node, the fourth pull-down control module is used for pulling up the potential of the fourth node to the first potential, and when the potential of the fourth node is the first potential, the second pull-down module outputs a2 x-level first-level transmission signal with the second potential.

6. The scan driver circuit according to claim 5,

the first GDL circuit further includes a first pull-down maintaining module electrically connected to the first node, the second node, and the third node, wherein when the first node is at a first potential, the first pull-down maintaining module pulls down a potential of the second node to a second potential, the first pull-down module stops outputting the 2x-1 th level first level transmission signal and the scan driving signal, when the third node is at the first potential, the first pull-down maintaining module controls the second node to stop receiving the power supply voltage, and the first pull-down module stops outputting the 2x-1 th level first level transmission signal and the scan driving signal,

the second GDL circuit further includes a second pull-down maintaining module electrically connected to the first node, the third node, and the fourth node, and a fifth node electrically connected to the second pull-down maintaining module,

when the first node is at a first potential, the second pull-down maintaining module controls the fourth node to stop receiving the power supply voltage, the second pull-down maintaining module stops outputting the 2 x-level first-level transmission signal and the scanning driving signal, when the third node is at the first potential, the second pull-down maintaining module pulls down the potential of the fourth node to a second potential, and the second pull-down module stops outputting the 2 x-level first-level transmission signal and the scanning driving signal;

and when the potential of the second node is the first potential, the potential of the fifth node is the first potential so as to control the second pull-down module to output a2 x-th-level first-level transmission signal with the second potential and stop outputting the scanning driving signal.

7. The scan driver circuit according to claim 6,

when x is more than 2 and less than or equal to 4,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor and a third pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low-voltage power supply end and is connected with a first low-voltage potential, the grid electrode of the second pull-down control transistor is connected with a first-level transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with the first low-voltage potential,

the third pull-down control module comprises a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, a gate of the sixth pull-down control transistor is electrically connected to the fourth node, a source of the sixth pull-down control transistor is electrically connected to the third node, the drain electrode of the sixth pull-down control transistor is connected with a first low-voltage potential, the grid electrode of the seventh pull-down control transistor is connected with a first-stage transmission signal, a source of the seventh pull-down control transistor is electrically connected to the third node, a drain of the seventh pull-down control transistor is connected to the first low-voltage potential, a gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

8. The scan driver circuit according to claim 7,

the first pull-up control module is further configured to access a start signal and configured to pull up the potential of the first node to a first potential, when the first node is the first potential, the first pull-up module outputs a first level transmission signal having the first potential, the second pull-up control module is further configured to access the start signal and configured to pull up the potential of the third node to the first potential, and when the potential of the third node is the first potential, the second pull-up module outputs the first level transmission signal having the first potential.

9. The scan driver circuit according to claim 6,

when x is more than 2 and less than or equal to 4,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low-voltage potential, the grid electrode of the second pull-down control transistor is connected with a first-stage transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the fourth pull-down control transistor is connected with a reset signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

the third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, wherein the grid electrode of the fifth pull-down control transistor is connected with a reset signal, the source electrode of the fifth pull-down control transistor is electrically connected with the third node, the drain electrode of the fifth pull-down control transistor is connected with a first low-voltage potential, the grid electrode of the sixth pull-down control transistor is electrically connected with the fourth node, the source electrode of the sixth pull-down control transistor is electrically connected with the third node, the drain electrode of the sixth pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the seventh pull-down control transistor is connected with a first-level transmission signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with the first low-voltage potential, the gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

10. The scan driver circuit according to claim 9,

11. The scan driver circuit according to claim 6,

when x is more than 4 and less than or equal to n,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low-voltage potential, the grid electrode of the second pull-down control transistor is connected with a first-stage transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the fourth pull-down control transistor is connected with a starting signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

the third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, wherein the grid electrode of the fifth pull-down control transistor is connected with a starting signal, the source electrode of the fifth pull-down control transistor is electrically connected with the third node, the drain electrode of the fifth pull-down control transistor is connected with a first low-voltage potential, the grid electrode of the sixth pull-down control transistor is electrically connected with the fourth node, the source electrode of the sixth pull-down control transistor is electrically connected with the third node, the drain electrode of the sixth pull-down control transistor is connected with the first low-voltage potential, the grid electrode of the seventh pull-down control transistor is connected with the first-level transmission signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with the first low-voltage potential, the gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low-voltage potential.

12. The scan driver circuit according to claim 11,

the first pull-up control module is further configured to access the 2x-5 th-level first-level transmission signal, and is configured to pull up the potential of the first node to a first potential, and when the potential of the first node is the first potential, the first pull-up module outputs a 2x-1 th-level first-level transmission signal having the first potential,

the second pull-up control module is further configured to access a 2x-4 th-level first-level transmission signal, and is configured to pull up the potential of the third node to a first potential, and when the potential of the third node is the first potential, the second pull-up module outputs a2 x-level first-level transmission signal having the first potential.

13. The scan drive circuit according to claim 3,

14. The scan driver circuit according to claim 13,

the dummy scan driving unit includes two dummy GDL circuits including a first dummy GDL circuit and a second dummy GDL circuit,

the first virtual GDL circuit includes a first virtual pull-up control module, a first virtual pull-up module, a first virtual pull-down control module, a second virtual pull-down control module, a first virtual pull-down module, a first virtual node and a second virtual node,

the first virtual pull-up control module, the first virtual pull-up module and the first virtual pull-down control module are electrically connected to the first virtual node,

the first virtual pull-up control module is configured to pull up a potential of the first virtual node to a first potential, and when the potential of the first virtual node is the first potential, the first virtual pull-up module outputs the second-stage transmission signal having the first potential, and the second-stage transmission signal is configured to control one of the n-th stage scan driving unit and the n-1 th stage scan driving unit to output the first-stage transmission signal having the second potential and stop outputting the scan driving signal,

the first virtual pull-down control module is used for pulling down the electric potential of the first virtual node to a second electric potential,

the second virtual pull-down control module and the first virtual pull-down module are electrically connected to the second virtual node, the second virtual pull-down control module is used for pulling up the potential of the second virtual node to a first potential, and when the potential of the second virtual node is the first potential, the first virtual pull-down module outputs a second level transmission signal with a second potential.

15. The scan driver circuit according to claim 14,

the second virtual GDL circuit comprises a second virtual pull-up control module, a second virtual pull-up module, a third virtual pull-down control module, a fourth virtual pull-down control module, a second virtual pull-down module, a third virtual node and a fourth virtual node, the first virtual pull-down module is electrically connected with the fourth virtual node,

the second virtual pull-up control module, the second virtual pull-up module and the third virtual pull-down control module are electrically connected to the third virtual node,

the second virtual pull-up control module is configured to pull up a potential of the third virtual node to a first potential, and when the potential of the third virtual node is the first potential, the second virtual pull-up module outputs a second level transmission signal having the first potential, where the second level transmission signal is configured to control one of the n-th level scan driving unit and the n-1 th level scan driving unit to output the first level transmission signal having the second potential and stop outputting the scan driving signal,

the second virtual pull-down control module is used for pulling down the electric potential of the third virtual node to a second electric potential,

the fourth virtual pull-down control module and the second virtual pull-down module are electrically connected to the fourth virtual node, the fourth virtual pull-down control module is used for pulling up the potential of the fourth virtual node to a first potential, and when the potential of the fourth virtual node is the first potential, the second virtual pull-down module outputs a second level transmission signal with a second potential.

16. The scan driver circuit according to claim 15,

the first virtual GDL circuit further includes a first virtual pull-down maintaining module, the first virtual pull-down maintaining module is electrically connected to the first virtual node, the second virtual node, and the third virtual node, when the potential of the first virtual node is a first potential, the first virtual pull-down maintaining module pulls down the potential of the second virtual node to a second potential, the first virtual pull-down module stops outputting a second pass signal, when the potential of the third virtual node is the first potential, the first virtual pull-down maintaining module controls the second virtual node to stop receiving the power supply voltage, and the first virtual pull-down module stops outputting the second pass signal; the second virtual GDL circuit further includes a second virtual pull-down maintaining module electrically connected to the first virtual node, the third virtual node, and the fourth virtual node, wherein when the potential of the first virtual node is the first potential, the second virtual pull-down maintaining module controls the fourth virtual node to stop receiving the power voltage, the second virtual pull-down module stops outputting the second pass signal, and when the potential of the third virtual node is the first potential, the second virtual pull-down maintaining module pulls down the fourth virtual node to the second potential, and the second virtual pull-down module stops outputting the second pass signal.

17. An array substrate, comprising 2n scan lines, a plurality of pixel units arranged in an array, and the scan driving circuit according to any one of claims 1 to 13, wherein the 2n scan lines are respectively connected to the n scan driving units and respectively receive 2n scan driving signals from the n scan driving units in sequence, and the pixel units receive image data and display images under the control of the 2n scan driving signals.