CN110379390B

CN110379390B - Display panel, driving method thereof and display device

Info

Publication number: CN110379390B
Application number: CN201910586415.4A
Authority: CN
Inventors: 张彬; 蔡大能; 钟本顺; 秦锋
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-07-01
Filing date: 2019-07-01
Publication date: 2022-01-04
Anticipated expiration: 2039-07-01
Also published as: CN110379390A

Abstract

The invention discloses a display panel, a driving method thereof and a display device, and relates to the technical field of display. In the embodiment of the present invention, each gate line group sequentially inputs a gate-on signal, each gate line in the gate line group sequentially inputs a gate-on signal, and the data line may input a data signal of the same polarity to each sub-pixel electrically connected to the data line and electrically connected to each gate line in the same gate line group, where the sub-pixel has the same color. Therefore, the sub-pixels which are electrically connected with the same data line and are electrically connected with the grid lines in the same grid line group and have the same color are enabled to sequentially input the data signals with the same polarity, so that the polarity switching times of the data signals are reduced to the maximum extent, the power consumption of the display panel is reduced, the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

The liquid crystal display is a non-self-luminous device, needs to be provided with a backlight module, and realizes a display function by utilizing a backlight source provided by the backlight module.

In order to increase the screen ratio of the display, the display panel may be designed to be a dual gate structure, such as the structural diagram of the display panel shown in fig. 1, wherein each data line 10 may be electrically connected to two columns of sub-pixels adjacent to each other on the left and right, and each gate line is sequentially input with a gate-on signal under the control of each shift register. In addition, referring to the timing diagram shown in fig. 2, which shows the timing of the data signals input to the corresponding connected sub-pixels P by the data lines labeled S1 when displaying a red screen, it is obvious that when the gate-on signals are sequentially input to the gate lines, the data signals transmitted on the data lines S1 need to be switched continuously, so that the number of times of switching the data signals is large, which results in the increase of power consumption of the display panel.

Therefore, how to reduce the power consumption of the display panel with the dual-gate structure is an urgent technical problem to be solved by the embodiments of the present invention.

Disclosure of Invention

The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for reducing the power consumption of the display panel with a double-gate structure.

In a first aspect, an embodiment of the present invention provides a method for driving a display panel, where the display panel includes:

the pixel comprises at least three sub-pixels with different colors, each column of sub-pixels consists of sub-pixels with the same color, and the polarities of data signals input by any two adjacent sub-pixels in the row direction and the column direction are opposite;

the array substrate comprises a plurality of data lines which are arranged along the row direction and extend along the column direction, two columns of sub-pixels are arranged between any two adjacent data lines, and each data line is electrically connected with the sub-pixels in the columns;

the grid lines are arranged along the column direction and extend along the row direction, two grid lines are arranged between any two adjacent rows of sub-pixels, and one side, away from the last row of sub-pixels, of the first row of sub-pixels and one side, away from the first row of sub-pixels, of the last row of sub-pixels are respectively provided with one grid line; all the grid lines are divided into a plurality of grid line groups, each grid line group comprises a plurality of grid lines, and at least one row of sub-pixels are arranged between the sub-pixels electrically connected with any two adjacent grid lines in the grid line groups;

the driving method includes:

and the data lines input data signals with the same polarity to the sub-pixels which are electrically connected with the data lines and are electrically connected with the gate lines in the same gate line group and have the same color.

In a second aspect, an embodiment of the present invention provides a display device, including a display panel;

the display panel is driven by the driving method provided by the embodiment of the invention.

In a third aspect, an embodiment of the present invention provides a display panel, including:

a plurality of shift register groups, each shift register group including a plurality of cascaded shift registers;

the clock signal line group is correspondingly and electrically connected with the shift register group and is used for providing clock signals for the shift registers which are correspondingly and electrically connected;

each grid line is electrically connected with one shift register, and each grid line in the grid line group is correspondingly and electrically connected with the shift register at the same level in different shift register groups;

and sequentially inputting a grid opening signal to each grid line group, and sequentially inputting a grid opening signal to each grid line in the grid line group so that the sub-pixels which are electrically connected with the same data line and are electrically connected with each grid line in the same grid line group have the same color and input the data signals with the same polarity.

The invention has the following beneficial effects:

in the display panel, the driving method thereof and the display device provided by the embodiment of the invention, all grid lines are divided into a plurality of grid line groups, each grid line group comprises a plurality of grid lines, at least one row of sub-pixels is arranged between sub-pixels electrically connected with any two adjacent grid lines in the grid line groups, in the driving process of the display panel, grid opening signals are sequentially input into each grid line group, and when each grid line in the grid line groups sequentially inputs the grid opening signals, the data lines can input data signals with the same polarity to the sub-pixels which are electrically connected with the data lines and are electrically connected with the grid lines in the same grid line group. Therefore, the sub-pixels which are electrically connected with the same data line and are electrically connected with the grid lines in the same grid line group and have the same color are enabled to sequentially input the data signals with the same polarity, so that the polarity switching times of the data signals are reduced to the maximum extent, the power consumption of the display panel is reduced, the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Drawings

FIG. 1 is a schematic diagram of a display panel in the prior art;

FIG. 2 is a timing diagram corresponding to FIG. 1;

fig. 3 is a schematic structural diagram of a first display panel according to an embodiment of the present invention;

FIG. 4 is a timing diagram corresponding to FIG. 3;

fig. 5 is a schematic structural diagram of a second display panel provided in the embodiment of the present invention;

fig. 6 is a schematic structural diagram of a third display panel provided in the embodiment of the present invention;

FIG. 7 is a timing diagram corresponding to FIGS. 5 and 6;

FIG. 8 is a diagram illustrating a cascade relationship between shift registers according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display device provided in an embodiment of the present invention.

Among them, 10, D1, D2, D3, D4-data lines, 20, G1, G2, G3, G4, G5, G6, G7, G8, G9, G10, G11, G12, G13, G14, G15, G16-gate lines, P0-pixels, P-sub-pixels, 40-touch signal lines, a 1-display regions, a 2-non-display regions, Z1, Z2-sub-regions, X-display panels.

Detailed Description

Embodiments of a display panel, a driving method thereof, and a display device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The inventor finds that, in a research, taking the structure of the display panel shown in fig. 1 as an example, the display panel includes sub-pixels, gate lines, and data lines arranged in an array, wherein two gate lines are disposed between any two adjacent rows of sub-pixels, one side of the first row of sub-pixels, which is far away from the last row of sub-pixels, and one side of the last row of sub-pixels, which is far away from the first row of sub-pixels, are both provided with one gate line, and two columns of sub-pixels are disposed between two adjacent data lines and are respectively electrically connected with the two columns of sub-pixels.

Referring to fig. 1, the display panel further includes: the shift register circuit comprises shift registers, a first clock signal line CK, a second clock signal line CKB and a starting signal line, wherein the shift registers are arranged in one-to-one correspondence with the grid lines, the first clock signal line CK and the second clock signal line CKB are electrically connected with the shift registers, the starting signal line is electrically connected with the first-stage shift register, the shift registers are connected in cascade, the first clock signal line CK can provide a first clock signal for the shift registers, the second clock signal line CKB can provide a second clock signal for the shift registers, and the starting signal line can provide a starting signal for the first-stage shift register.

A timing diagram corresponding to the structure shown in fig. 1 is shown in fig. 2, where fig. 2 shows a time when each gate electrode inputs a gate-on signal, and after a start signal is input and when a first clock signal is output from a first clock signal line CK, a first-stage shift register inputs a gate-on signal to a correspondingly connected gate line, and simultaneously the gate-on signal is input to a signal input terminal of a second-stage shift register as a start signal of the second-stage shift register.

When a second clock signal is provided by a second clock signal line, the second-stage shift register inputs a grid opening signal to the grid line correspondingly connected, meanwhile, on one hand, the second-stage shift register outputs the grid opening signal to the reset signal end of the first-stage shift register so that the first-stage shift register is reset to stop outputting the grid opening signal to the grid line correspondingly connected, and on the other hand, the second-stage shift register outputs the grid opening signal to the signal input end of the third-stage shift register to be used as a starting signal of the third-stage shift register.

Similarly, the working process from the third stage shift register to the penultimate shift register is similar to that described above, and repeated descriptions are omitted.

Only for the last stage shift register, it is only necessary to input a gate start signal to the gate line connected correspondingly and output the gate start signal to the reset signal terminal of the last stage shift register, so that the last stage shift register is reset to stop outputting the gate start signal to the gate line connected correspondingly.

That is, as the first clock signal periodically outputs the first clock signal and the second clock signal periodically outputs the second clock signal, the shift registers of the respective stages sequentially output the gate-on signals to the gate lines connected correspondingly, so that the gate lines are sequentially scanned.

Correspondingly, regarding the data line, as an example of the data line denoted by S1 in fig. 1, in order to make the polarities of the data signals input to any two adjacent sub-pixels in the row direction and the column direction opposite, the polarity of the data signal needs to be switched continuously when each gate line is scanned sequentially. As shown in fig. 2, the timing of the data line S1, where the position corresponding to R indicates the data signal input to the red sub-pixel R, and the position corresponding to G indicates the data signal input to the green sub-pixel G, is shown in fig. 2, where the timing when the red picture is displayed is shown, and thus the data signal is input only to the red sub-pixel R, and the sub-pixels of the other colors have no data signal input.

Referring to fig. 2, the data signal transmitted on the data line S1 needs to be switched between a high level signal, a low level signal, and a zero potential without stopping to ensure that the data signal is input to only the red sub-pixel R and that the polarities of the data signals input to two red sub-pixels R adjacent to each other in a column are opposite. Therefore, the switching times of the data signals are increased, which results in a large power consumption of the display panel.

To solve this problem, embodiments of the present invention provide a display panel to reduce power consumption of the display panel having a dual gate structure.

Specifically, an embodiment of the present invention provides a driving method of a display panel, wherein a structure of the display panel is described before describing the driving method, as shown in fig. 3, fig. 5 and fig. 6, where fig. 3 is a schematic structural diagram of a first display panel, fig. 5 is a schematic structural diagram of a second display panel, and fig. 6 is a schematic structural diagram of a third display panel.

Referring to fig. 3, 5 and 6, the display panel may include:

the pixels P0 are arranged in an array, the pixel P0 comprises at least three sub-pixels P with different colors, each column of sub-pixels consists of sub-pixels P with the same color, and the polarities of data signals input by any two adjacent sub-pixels P in the row direction and the column direction are opposite;

a plurality of data lines 10 arranged in the row direction and extending in the column direction, two columns of sub-pixels are arranged between any two adjacent data lines 10, and each data line 10 is electrically connected with the plurality of columns of sub-pixels; for example, as shown in fig. 3, each data line 10 is electrically connected to two columns of sub-pixels, and, for example, as shown in fig. 5 and 6, each data line 10 is electrically connected to four columns of sub-pixels.

A plurality of gate lines (e.g., G1 to G8 in fig. 3, and 20 or G1 to G16 in fig. 5 and 6) arranged in the column direction and extending in the row direction, two gate lines being disposed between any two adjacent rows of sub-pixels, one gate line being disposed on both a side of the first row of sub-pixels away from the last row of sub-pixels and a side of the last row of sub-pixels away from the first row of sub-pixels; all grid lines are divided into a plurality of grid line groups (the grid lines electrically connected with the sub-pixels with the same filling pattern are one grid line group, and the mark of the grid line group is not given in the figure), each grid line group comprises a plurality of grid lines, and at least one row of sub-pixels are arranged between the sub-pixels electrically connected with any two adjacent grid lines in each grid line group;

for example, as shown in fig. 3, the gate line group may include 2 gate lines, wherein the gate lines electrically connecting the sub-pixels having the same pattern filling in fig. 3 may be regarded as one gate line group, for example, taking two columns of sub-pixels electrically connected with the data line labeled D1 as an example, the gate lines electrically connecting the sub-pixels filled with sparse black dots are labeled G1 and G5, so the gate line G1 and the gate line G5 may be regarded as one gate line group; the gate lines electrically connected to the subpixels filled with the mesh pattern are labeled G3 and G7, so the gate line G3 and the gate line G7 may be regarded as one gate line group; the gate lines to which the subpixels filled with the transverse lines are electrically connected are labeled G4 and G8, so that the gate line G4 and the gate line G8 can be regarded as one gate line group; the gate lines to which the sub-pixels filled with the vertical lines are electrically connected are labeled G2 and G6, so the gate lines G2 and G6 may be treated as one gate line group.

Wherein, the first row of sub-pixels and the last row of sub-pixels can be understood as:

taking the structure shown in fig. 3 as an example, the first row of sub-pixels may be understood as the sub-pixel row farthest from the driving IC, and the last row of sub-pixels may be understood as the sub-pixel row closest to the driving IC.

Of course, the driving IC is not limited to the position of the lower frame of the display panel in fig. 3, and may also be the position of the upper frame of the display panel (not shown), where the first row of sub-pixels may be understood as the sub-pixel row closest to the driving IC, and the last row of sub-pixels may be understood as the sub-pixel row farthest from the driving IC. However, regardless of whether the driving IC is disposed in the upper frame or the lower frame, the first row of sub-pixels and the last row of sub-pixels are respectively rows of sub-pixels disposed at opposite edges of the display area along the column direction.

For another example, as shown in fig. 5, the gate line group may include 4 gate lines, wherein the gate lines electrically connected to the sub-pixels having the same pattern filling in fig. 5 may be regarded as one gate line group, for example, taking two columns of sub-pixels electrically connected to the data line labeled D2 as an example, the gate lines electrically connected to the sub-pixels filled with sparse black dots are labeled G1, G5, G9, and G13, so the gate line G1, the gate line G5, the gate line G9, and the gate line G13 may be regarded as one gate line group; the gate lines electrically connected to the subpixels filled with the mesh pattern are labeled G3, G7, G11, and G15, so that the gate line G3, the gate line G7, the gate line G11, and the gate line G15 can be regarded as one gate line group; the gate lines to which the subpixels filled with the transverse lines are electrically connected are labeled G4, G8, G12, and G16, so that the gate line G4, the gate line G8, the gate line G12, and the gate line G16 can be regarded as one gate line group; the gate lines to which the subpixels filled with the vertical lines are electrically connected are labeled G2, G6, G10, and G14, so that the gate line G2, the gate line G6, the gate line G10, and the gate line G14 can be regarded as one gate line group.

Of course, the above description is only to illustrate how many gate lines can be included in the gate line group, and which gate lines are included in the gate line group, but in specific implementation, the gate line group is not limited to the above-described fig. 3 and fig. 5, and other dividing manners may also be used, as long as the driving method that needs to be described below can be implemented, and the present invention is not limited herein.

At this time, referring to timing diagrams shown in fig. 4 and 7, where fig. 4 is a timing diagram corresponding to fig. 3 and fig. 7 is a timing diagram corresponding to fig. 5 and 6, the driving method may include:

each grid line group is sequentially input with a grid opening signal, each grid line in the grid line group is sequentially input with a grid opening signal, and the data lines are electrically connected with the data lines and each sub-pixel which is electrically connected with each grid line in the same grid line group and has the same color, and input with data signals of the same polarity.

In the embodiment of the invention, the driving method is improved, that is, the gate line groups are sequentially input with the gate start signal, and the gate lines in the gate line groups are sequentially input with the gate start signal, so that when the gate lines are scanned, the gate start signal is not sequentially input to the gate lines from top to bottom or from bottom to top as in the prior art, but the gate start signal is sequentially input to the gate lines according to the division of the gate line groups, thereby breaking the gate line scanning mode in the prior art.

Moreover, after the gate line scanning manner in the prior art is broken, the data line can input the data signal of the same polarity to each sub-pixel which is electrically connected with the data line and is electrically connected with each gate line in the same gate line group, and particularly when a monochrome picture is displayed, the data signal input by the data line to the sub-pixel of the same color which is electrically connected with the gate line in each gate line group does not need to be switched, the data signal can be kept unchanged, and the more gate lines included in the gate line group, the longer the data signal is kept unchanged, so that the switching times of the data signal can be effectively reduced, and the power consumption of the display panel can be reduced.

Specifically, as shown in table 1 below, the cases of data signals transmitted on three data lines labeled D2, D3, and D4 in fig. 5 are given in table 1, and G1-G16 represent 16 gate lines from top to bottom in fig. 5, where if G1, G5, G9, and G13 are regarded as a first gate line group, G3, G7, G11, and G15 are regarded as a second gate line group, G2, G6, G10, and G14 are regarded as a third gate line group, and G4, G8, G12, and G16 are regarded as a fourth gate line group, the four gate line groups are sequentially input with gate-on signals, and 4 gate lines in each gate line group are sequentially input with gate-on signals.

As shown in table 1, if three data lines need to input data signals to the red subpixels R connected correspondingly when displaying a red image, it can be seen that the data signals transmitted on each data line are data signals of the same polarity in each gate line group, and meanwhile, when two gate line groups driven continuously are scanned, the data signals transmitted on the data lines are of the same polarity (as shown by the bold B + in table 1), so that the switching times of the data signals can be greatly reduced, the power consumption of the display panel is greatly reduced, the power consumption of the display device is further reduced, and the service life of the display device is prolonged.

TABLE 1

In practical implementation, in the embodiment of the present invention, the number of the sub-pixel columns electrically connected to the data line may be set as:

referring to fig. 3, the data line 10 is electrically connected to two columns of sub-pixels, and the gate line group may include two gate lines;

alternatively, as shown in fig. 5 and 6, the data line 10 is electrically connected to four columns of sub-pixels, and the gate line group may include four gate lines.

The above description is given by way of example for the division of the gate line group, and specific reference may be made to the above description, and repeated descriptions are omitted.

To illustrate, the number of the gate lines included in the gate line group may be set according to actual needs.

For example, if the area requirement for the non-display area is small, more routing lines can be arranged in the non-display area, and the more the number of the gate lines included in the gate line group is, the more the routing lines among the shift registers in the non-display area are, and the more the space of the non-display area is, the more the number of the gate lines included in the gate line group is arranged, so that the non-display area is fully utilized, and the power consumption of the display is greatly reduced.

For another example, if the requirement for the area of the non-display area is high and the requirement for the structural complexity of the display panel is high, the space in the non-display area may be small, and sufficient space cannot be provided to set more routing lines, at this time, the number of gate lines included in the gate line group may be set to be small, so as to reduce the routing lines, thereby reducing the occupied area of the non-display area, and simultaneously, the routing arrangement is facilitated to be simplified, so as to simplify the structural complexity of the display panel, thereby facilitating the manufacturing of the display panel.

Therefore, the grid opening signals can be sequentially input into each grid line in the grid line group, and when the data lines can input data signals with the same polarity to each sub-pixel which is electrically connected with the data lines and is electrically connected with each grid line in the same grid line group, the switching times of the data signals are reduced, and the power consumption of the display panel is reduced; meanwhile, the electric connection condition of the data lines and the sub-pixel columns and the division of the gate line groups can be set according to actual needs, so that the design flexibility of the display panel is improved, and the requirements of various application scenes are met.

In practical implementation, in the embodiment of the present invention, the first phase difference between the gate-on signals input by every two adjacent gate lines in the same gate line group is the same.

For example, taking the timing diagram shown in fig. 7 as an example, T0 in the diagram may indicate the first phase difference, G1 to G16 indicated in the diagram indicate the time when the gate-on signal is inputted to each gate line, and as can be seen from the above description, the gate line G1, the gate line G5, the gate line G9, and the gate line G13 may be regarded as a gate line group. The time difference between the rising edge of the gate line G1 to which the gate-on signal is input and the rising edge of the gate line G5 to which the gate-on signal is input is the first phase difference T0, and the time difference between the rising edge of the gate line G5 to which the gate-on signal is input and the rising edge of the gate line G9 to which the gate-on signal is input is the first phase difference T0.

Therefore, when the grid line groups are ensured to input the grid opening signals in sequence, the grid lines can be ensured to input the grid opening signals regularly and sequentially, so that the charging time of each sub-pixel is effectively controlled, the driving process of the display panel is effectively controlled, the display panel can work normally and effectively, and disorder is avoided.

Optionally, in an embodiment of the present invention, the first phase difference may be 3 microseconds to 10 microseconds.

The setting magnitude of the first phase difference is related to a pulse width of a clock signal (described in the following), and may be set according to actual needs, as long as it is ensured that each gate line group sequentially inputs a gate start signal, and each gate line in the gate line group sequentially inputs a gate start signal, so as to reduce the switching times of data signals and reduce the power consumption of the display panel.

Alternatively, in the embodiment of the present invention, the first phase difference may be 5 microseconds.

Therefore, the charging time of each sub-pixel can be controlled, each sub-pixel can have sufficient charging time in each frame scanning time, and the display effect of the display panel can be improved.

Specifically, in the embodiment of the present invention, for different gate line groups, for two gate line groups that are continuously driven: and a second phase difference exists between the gate opening signal input by the last driven gate line in the last gate line group and the gate opening signal input by the first driven gate line in the next gate line group, and the first phase difference is the same as the second phase difference.

For example, taking the timing chart shown in fig. 3 as an example, G1 to G8 shown in the figure indicate the time when the gate-on signal is inputted to each gate line, and it can be seen from the above description that the gate line G1 and the gate line G5 can be regarded as one gate line group, and the gate line G3 and the gate line G7 can be regarded as one gate line group. In fig. 3, a gate line group including the gate line G1 and the gate line G5 and a gate line group including the gate line G3 and the gate line G7 are two gate line groups that are continuously driven, the gate line G5 is a last driven gate line in the gate line group, the gate line G3 is a first driven gate line in the gate line group, a time difference between a rising edge of the gate line G1 to which the gate on signal is input and a rising edge of the gate line G5 to which the gate on signal is input is a first phase difference, a time difference between the rising edge of the gate line G5 to which the gate on signal is input and a rising edge of the gate line G3 to which the gate on signal is input is a second phase difference, and the second phase difference and the first phase difference are both T0, that is, the second phase difference is the same as the first phase difference.

Therefore, the driving process of each grid line can be kept consistent, the driving complexity of the display panel can be simplified, the power consumption of the display panel is further reduced, meanwhile, the uniformity of the display panel can be improved, and therefore the display effect is improved.

In specific implementation, in order to enable each gate line group to sequentially input a gate start signal, and each gate line in the gate line group to sequentially input a gate start signal, it is necessary to control a working process of a shift register for outputting the gate start signal to the gate line. The shift register is usually electrically connected to a clock signal line, and a signal output from the shift register can be controlled by a clock signal provided through the clock signal line, so that the timing of the clock signal also needs to be set in order to control the operation of the shift register.

The driving method provided by the embodiment of the present invention is described below with reference to the setting condition of the shift register and the operation timing of the clock signal.

Specifically, in the embodiment of the present invention, as shown in fig. 3, 5, and 6, the display panel includes: a display region a1 and a non-display region a2 surrounding the display region a1, the pixels being located within the display region a 1;

provided within the non-display area a2 are: a plurality of shift register groups (the marks of the shift register groups are given in the figure), and a clock signal line group which is correspondingly and electrically connected with each shift register group, wherein each shift register group comprises a plurality of cascaded shift registers, and the shift registers are electrically connected with one end of a grid line; the clock signal line group includes a first clock signal line (e.g., CK 1-CK 8) and a second clock signal line (e.g., CKB 1-CKB 8).

For example, referring to fig. 3, there are shown 8 shift registers, each electrically connected to one gate line, wherein:

the shift registers labeled Y1 and Y5 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK1 and CKB1, cascaded between shift register Y1 and shift register Y5.

The shift registers labeled Y2 and Y6 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK2 and CKB2, cascaded between shift register Y2 and shift register Y6.

The shift registers labeled Y3 and Y7 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK3 and CKB3, cascaded between shift register Y3 and shift register Y7.

The shift registers labeled Y4 and Y8 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK4 and CKB4, cascaded between shift register Y4 and shift register Y8.

That is, 4 shift register groups are shown in fig. 3, and 4 clock signal line groups each including a first clock signal line (e.g., CK1, CK2, CK3, CK4) and a second clock signal line (e.g., CKB1, CKB2, CKB3, CKB 4).

For another example, referring to fig. 5, 16 shift registers are shown, each shift register being electrically connected to one gate line, wherein for 8 shift registers located at the right side in the figure:

the shift registers labeled Y1 and Y2 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK1 and CKB1, cascaded between shift register Y1 and shift register Y5.

The shift registers labeled Y5 and Y6 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK2 and CKB2, cascaded between shift register Y5 and shift register Y6.

The shift registers labeled Y9 and Y10 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK3 and CKB3, cascaded between shift register Y9 and shift register Y10.

The shift registers labeled Y13 and Y14 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK4 and CKB4, cascaded between shift register Y13 and shift register Y14.

For the 8 shift registers located on the left side of the figure:

the shift registers labeled Y3 and Y4 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK5 and CKB5, cascaded between shift register Y3 and shift register Y4.

The shift registers labeled Y7 and Y8 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK6 and CKB6, cascaded between shift register Y7 and shift register Y8.

The shift registers labeled Y11 and Y12 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK7 and CKB7, cascaded between shift register Y11 and shift register Y12.

The shift registers labeled Y15 and Y16 can be considered as a set of shift registers electrically connected to a set of clock signal lines including CK8 and CKB8, cascaded between shift register Y15 and shift register Y16.

That is, 8 shift register groups are shown in fig. 5, and 8 clock signal line groups each including a first clock signal line (e.g., CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8) and a second clock signal line (e.g., CKB1, CKB2, CKB3, CKB4, CKB5, CKB6, CKB7, CKB 8).

To explain, in the embodiment of the present invention, in combination with the schematic structural diagram of the connection relationship of the shift registers shown in fig. 8, the cascade connection between two shift registers may be understood as follows:

referring to fig. 8, if the previous shift register is denoted by Y1 and the next shift register is denoted by Y2, the signal output terminal OUT of the previous shift register Y1 inputs a gate-on signal to the signal input terminal IN of the next shift register Y2 as a start signal of the next shift register Y2, and the signal output terminal OUT of the next shift register Y2 inputs a gate-on signal to the RESET signal terminal RESET of the previous shift register Y1 as a RESET signal of the previous shift register Y1.

In order to ensure that the cascaded shift registers can normally and orderly operate, each shift register includes a first signal input terminal K1 and a second signal input terminal K2, the first signal input terminal K1 of the previous shift register Y1 is electrically connected to the first clock signal line CK1, the second signal input terminal K2 is electrically connected to the second clock signal line CKB1, the first signal input terminal K1 of the next shift register Y2 is electrically connected to the second clock signal line CKB1, and the second signal input terminal K2 is electrically connected to the first clock signal line CK1, as shown in fig. 8.

It should be noted that the differences between fig. 5 and fig. 6 are that the cascade relations of two adjacent shift registers in the same shift register group are adjusted, such as the cascade relation between the shift register Y5 and the shift register Y6, the cascade relation between the shift register Y13 and the shift register Y14, the cascade relation between the shift register Y7 and the shift register Y8, and the cascade relation between the shift register Y15 and the shift register Y16 in fig. 5 and fig. 6.

Moreover, the connection relationship between the sub-pixels in the sub-pixel rows and the gate lines on the two opposite sides is also adjusted, for example, taking the green sub-pixel G filled with sparse black dots in the sub-pixels in the third row as an example, in fig. 5, the green sub-pixel G is electrically connected to the gate line on the side close to the sub-pixel in the second row, and in fig. 6, the green sub-pixel G is electrically connected to the gate line on the side far from the sub-pixel in the second row. The connection relationship between the other sub-pixels and the gate lines to be adjusted is not described in detail herein, as long as when the gate start signal is sequentially input to each gate line group and the gate start signal is sequentially input to each gate line in the same gate line group, the sub-pixels electrically connected to the same data line and electrically connected to the gate lines in the same gate line group have the same color and input the data signal of the same polarity, so as to reduce the switching frequency of the data signal and reduce the power consumption of the display panel.

Therefore, the cascade shift registers can be ensured to input the grid opening signals to the grid lines which are correspondingly and electrically connected in sequence, and the cascade shift registers can work normally and orderly, and meanwhile, the cascade shift registers are beneficial to realizing that the grid opening signals are input to the grid line groups in sequence and the grid lines in the grid line groups are input to the grid opening signals in sequence.

Alternatively, referring to fig. 4 and 7, the driving method may further include:

a first phase difference exists between first clock signals provided by first clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group;

a first phase difference exists between second clock signals provided by second clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group.

Therefore, the shift register corresponding to every two adjacent grid lines in the same grid line group can output grid opening signals to the corresponding grid lines in sequence, so that when data signals with the same polarity are input to the sub-pixels which are electrically connected with the shift register and are electrically connected with the grid lines in the same grid line group and have the same color, the switching frequency of the data signals can be reduced to the greatest extent, and the power consumption of the display panel is effectively reduced.

two gate line groups driven consecutively: a first phase difference exists between a first clock signal provided by a first clock signal line electrically connected with a shift register correspondingly arranged on the last driven grid line in the last grid line group and a first clock signal provided by a first clock signal line electrically connected with a shift register correspondingly arranged on the first driven grid line in the next grid line group;

two gate line groups driven consecutively: and a first phase difference exists between a second clock signal provided by a second clock signal line electrically connected with the shift register correspondingly arranged to the last driven grid line in the last grid line group and a second clock signal provided by a second clock signal line electrically connected with the shift register correspondingly arranged to the first driven grid line in the next grid line group.

Therefore, the phase difference between the grid opening signal input by the last driven grid line in the last grid line group and the grid opening signal input by the first driven grid line in the next grid line group in the two continuously driven grid line groups is favorable to be the first phase difference, so that the driving processes of all the grid lines are kept consistent, the driving complexity of the display panel can be simplified, the power consumption of the display panel is further reduced, meanwhile, the uniformity of the display panel can be improved, and the display effect is improved.

Optionally, when the gate line group includes M gate lines, in an embodiment of the present invention, referring to fig. 4 and 7, the driving method may further include:

for two consecutive gate line groups of the odd-numbered drive or even-numbered drive: a third phase difference exists between the first clock signal provided by the first clock signal line electrically connected with the shift register correspondingly arranged to the last driven grid line in the last grid line group and the first clock signal provided by the first clock signal line electrically connected with the shift register correspondingly arranged to the first driven grid line in the next grid line group;

for two consecutive gate line groups of the odd-numbered drive or even-numbered drive: a third phase difference exists between a second clock signal provided by a second clock signal line electrically connected with the shift register correspondingly arranged on the last driven grid line in the last grid line group and a second clock signal provided by a second clock signal line electrically connected with the shift register correspondingly arranged on the first driven grid line in the next grid line group;

wherein the third phase difference is M times of the first phase difference.

Therefore, the same polarity of data signals input by the sub-pixels electrically connected with the grid lines in the two continuously driven grid line groups can be avoided, and the problems of image sticking and the like can be further avoided, so that the display effect is improved.

Alternatively, in the embodiment of the present invention, as shown in fig. 3, 5, and 6, the setting number of the shift register sets may be 2M.

For example, in fig. 3, each gate line group includes 2 gate lines, i.e., M is 2, and the number of shift register groups is 4, i.e., 2 times 2. For another example, in fig. 5 and 6, each gate line group includes 4 gate lines, i.e., M is 4, and the number of shift register groups is 8, i.e., 2 times 4.

Therefore, the scanning process of the grid lines in each grid line group can be effectively controlled through the arrangement of the shift register group, so that the switching times of data signals can be reduced, and the power consumption of the display panel can be reduced.

Optionally, in the embodiment of the present invention, the non-display area a2 includes two sub-areas (e.g., Z1 and Z2), and the two sub-areas are respectively located in the non-display area a2 to which the two ends of the gate line are directed;

each shift register group is arranged in the same subregion;

or, each shift register group is equally arranged in two subareas.

For example, as shown in fig. 3, the shift registers are disposed in the same sub-region Z2.

In this way, more space is left for another sub-region (e.g., Z1) to facilitate the arrangement of other structures in the sub-region Z1 to perform the display function of the display panel.

As another example, as shown in FIG. 5, 4 of the shift register sets are disposed in sub-region Z1, and the remaining 4 shift register sets are disposed in sub-region Z2.

Therefore, the problems that the number of the shift registers is large and short circuits are easily caused in one sub-region can be avoided, so that the shift registers can work normally and orderly, mutual interference is avoided, normal transmission of signals is guaranteed, and the reliability of the display panel is improved.

Of course, in the specific implementation process, the selection and the setting can be performed according to factors such as actual needs and application scenes, so that the flexibility of the design of the display panel can be improved.

Optionally, in order to enable the shift register to operate normally, in the embodiment of the present invention, a first start signal line STV1 and a second start signal line STV2 are further provided in the sub-region, as shown in fig. 3, 5 and 6, wherein the signal input terminal of the first stage shift register in each shift register group is electrically connected to the first start signal line or the second start signal line for receiving the start signal, so that the shift register can operate normally.

Specifically, regardless of the first start signal provided by the first start signal line or the second start signal provided by the second start signal line, as long as the shift register can work normally, and further, it is ensured that the gate lines in the gate line group input the gate start signal in sequence, and the start signal is input between the gate line groups in sequence.

It should be noted that, when the connection traces between the shift registers, the clock signal lines, the start signal line, and the connection traces between the shift registers and the gate lines, the clock signal lines, and the start signal line are arranged, taking the structure in the sub-region Z1 shown in fig. 5 as an example, in the sub-region Z1, a plurality of shift registers (e.g., Y1, Y2, Y5, Y6, Y9, Y10, Y13, and Y14), a plurality of first clock signal lines (e.g., CK1, CK2, CK3, CK4), a plurality of second clock signal lines (e.g., CKB1, CKB2, CKB3, and CKB4), and a first clock signal line (e.g., STV1), and a plurality of connection traces are arranged, and these lines requiring insulation may overlap with each other lines, so as to avoid short circuits between the lines requiring insulation, different layers of the lines requiring insulation may be arranged and overlap with each other lines.

For example, the extending directions of the first clock signal line, the second clock signal line and the first start signal line are all parallel to the column direction, the extending directions of the first connecting trace (as shown in the dotted line circle 1) between the shift register and the first clock signal line, the second clock signal line and the first start signal line are parallel to the row direction, at this time, when the extending direction of the data line is parallel to the column direction, and the extending direction of the gate line is parallel to the row direction, the first clock signal line, the second clock signal line and the first start signal line can all be arranged in the same layer as the data line, and the first connecting trace and the gate line between the shift register and the first clock signal line, the second clock signal line and the first start signal line are arranged in the same layer as the data line, so as to simplify the manufacturing process and reduce the manufacturing difficulty.

Meanwhile, in order to enable the shift register to be electrically connected with the corresponding first clock signal line, second clock signal line and first start signal line through the first connection trace, the first connection trace to be electrically connected with the first clock signal line, the second clock signal line and the first start signal line may be electrically connected through via holes.

For another example, the second connection trace that is cascaded among the shift registers and the third connection trace that is between the shift register and the gate line may overlap, as shown in the dotted line circle 2, although the second connection trace and the third connection trace overlap but need to be set to be insulated, so as to avoid affecting signal transmission, the second connection trace and the third connection trace may be set in different layers, wherein, because the third connection trace needs to be electrically connected with the gate line, and most of the line segments in the third connection trace extend along the row direction, the third connection trace may be set to be the same material as the gate line and set in the same layer, so that the third connection trace may be directly contacted and electrically connected with the gate line, thereby improving the reliability of electrical connection; for the second connection wire, it may be made of the same material as the data line and disposed on the same layer, or made of the same material as the pixel electrode and disposed on the same layer, or located on the same material as the other film layers and disposed on the same layer as the other electrode structures, and it is not limited herein as long as it is ensured that the second connection wire and the third connection wire are insulated.

That is to say, for two kinds of connection traces that need to be arranged in an insulating manner and overlap, the two kinds of connection traces may be arranged in different layers, but the layer in which each kind of connection trace is arranged may be arranged according to actual conditions and needs, and is not limited herein.

Next, the driving process of the display panel will be described by taking the structure shown in fig. 5 and the timing chart shown in fig. 7 as an example.

The case where the data lines D4 in fig. 5 are electrically connected and the data signals are transmitted to the sub-pixels, and the green screen is displayed will be described as an example.

As shown in fig. 5 and 7, the first start signal line STV1 inputs a first start signal to the shift register Y1, the shift register Y5, the shift register Y9, and the shift register Y13 electrically connected thereto, and when the second clock signal line CKB1 outputs an active second clock signal, the shift register Y1 outputs a gate-on signal to the gate line G1 connected thereto, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G1 is a green sub-pixel G with sparse black dot filling, and therefore, the data line D4 outputs a positive data signal to the green sub-pixel G because it is necessary to display a green picture.

After a time T0 after the rising edge of the second clock signal output from the second clock signal line CKB1, when the second clock signal line CKB2 outputs an active second clock signal, the shift register Y5 outputs a gate-on signal to the gate line G5 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G5 is a green sub-pixel G filled with sparse black dots, and since it is necessary to display a green screen at present, the data line D4 also outputs a positive data signal to the green sub-pixel G.

After T0 time after the rising edge of the second clock signal outputted from the second clock signal line CKB2, when the second clock signal line CKB3 outputs the valid second clock signal, the shift register Y9 outputs the gate-on signal to the gate line G9 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G9 is the green sub-pixel G filled with sparse black dots, and the data line D4 still outputs the positive data signal to the green sub-pixel G because the green screen needs to be displayed at present.

After a time T0 after the rising edge of the second clock signal output from the second clock signal line CKB3, when the second clock signal line CKB4 outputs an active second clock signal, the shift register Y13 outputs a gate-on signal to the gate line G13 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G13 is a green sub-pixel G filled with sparse black dots, and a green screen needs to be displayed at present, so the data line D4 keeps outputting a positive data signal to the green sub-pixel G.

When the gate-on signals are sequentially input to the first gate line group, the data signals transmitted through the data lines D4 always keep positive polarity, that is, the data signals transmitted through the data lines D4 do not need to be switched if the first gate line group is regarded as G1, G5, G9, and G13.

After the first start signal line STV1 outputs the first start signal for a certain time (which may be 2 times T0), the second start signal line STV2 inputs the second start signal into the shift register Y3, the shift register Y7, the shift register Y11, and the shift register Y15 electrically connected thereto.

After T0 time after the rising edge of the second clock signal outputted from the second clock signal line CKB4, when the second clock signal line CKB5 outputs the valid second clock signal, the shift register Y3 outputs a gate-on signal to the gate line G3 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G3 is a blue sub-pixel B filled with a grid pattern, and since it is currently necessary to display a green screen, no data signal is outputted from the data line D4.

Similarly, after T0 time after the rising edge of the second clock signal output from the second clock signal line CKB5, after T0 time after the rising edge of the second clock signal output from the second clock signal line CKB6, and after T0 time after the rising edge of the second clock signal output from the second clock signal line CKB7, the blue subpixels B filled with the grid patterns electrically connected to the data line D4 in fig. 5 are sequentially turned on, and thus no data signal is output from the data line D4 because it is currently necessary to display a green picture. That is, when G3, G7, G11, and G15 are regarded as the second gate line group, no data signal is output from any of the data lines D4 when the gate-on signals are sequentially input to the gate line group, and thus no data signal is switched.

After T0 time after the rising edge of the second clock signal outputted from the second clock signal line CKB8, when the first clock signal line CK1 outputs an active first clock signal, the shift register Y2 outputs a gate-on signal to the gate line G2 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G2 is a blue sub-pixel B filled with a vertical line, and therefore, since it is currently necessary to display a green screen, no data signal is outputted from the data line D4.

Similarly, after a time T0 after the rising edge of the first clock signal output from the first clock signal line CK1, a time T0 after the rising edge of the first clock signal output from the first clock signal line CK2, and a time T0 after the rising edge of the first clock signal output from the first clock signal line CK3, the blue subpixels B filled with the vertical lines electrically connected to the data line D4 in fig. 5 are sequentially turned on, and no data signal is output from the data line D4 because a green picture needs to be displayed at present. That is, when G2, G6, G10, and G14 are regarded as the third gate line group, no data signal is output from any of the data lines D4 when the gate-on signals are sequentially input to the gate line group, and thus no data signal is switched.

After a time T0 after the rising edge of the first clock signal outputted from the first clock signal line CK4, when the first clock signal line CK5 outputs an active first clock signal, the shift register Y4 outputs a gate-on signal to the gate line G4 connected correspondingly, and at this time, the sub-pixel electrically connected to the data line D4 and the gate line G4 is a red sub-pixel R filled with horizontal lines, and since it is currently necessary to display a green screen, no data signal is outputted from the data line D4.

Similarly, after a time T0 after the rising edge of the first clock signal output from the first clock signal line CK5, a time T0 after the rising edge of the first clock signal output from the first clock signal line CK6, and a time T0 after the rising edge of the first clock signal output from the first clock signal line CK7, the red subpixels R filled with the horizontal lines electrically connected to the data lines D4 in fig. 5 are sequentially turned on, and no data signal is output from the data lines D4 because a green picture needs to be displayed at present. That is, when G4, G8, G12, and G16 are regarded as the fourth gate line group, no data signal is output from any of the data lines D4 when the gate-on signals are sequentially input to the gate line group, and thus no data signal is switched.

Therefore, when a red image needs to be displayed at present, for the data line D4, the transmitted data signals only need to be switched once in the above driving process, and do not need to be switched continuously, so that the switching times of the data signals are reduced to the greatest extent by the driving method provided by the embodiment of the present invention, thereby effectively reducing the power consumption of the display panel, further reducing the power consumption of the display device, and prolonging the service life of the display device.

Optionally, in order to implement the touch function, in the embodiment of the present invention, a touch signal line 40 is further disposed in the display area a1, as shown in fig. 3 and 5, and the touch signal line 40 is located at a gap between two columns of sub-pixels and is located at a different gap from the data line 10.

Of course, in fig. 3, the touch signal line 40 may be located on the same film layer as the data line 10, or may be disposed on different layers, and may be disposed according to actual needs, so as to improve flexibility of design. In addition, in the structure shown in fig. 5, the touch signal line 40 needs to be disposed in a different layer from the data line 10 to avoid short circuit with other traces, so as to improve the reliability of the display panel.

Based on the same inventive concept, an embodiment of the present invention provides a display panel, as shown in fig. 3, 5 and 6, which may include:

Therefore, the sub-pixels which are electrically connected with the same data line and are electrically connected with the grid lines in the same grid line group and have the same color are enabled to sequentially input the data signals with the same polarity, so that the polarity switching times of the data signals are reduced to the maximum extent, the power consumption of the display panel is reduced, the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Alternatively, in the embodiment of the present invention, the setting number of the gate line groups may be an integer multiple of 4. For example, the number of the gate line groups is 4, 8, 12, 16, etc., which is not limited herein.

Therefore, the polarity switching frequency of the data signals is reduced, and the power consumption of the display panel is reduced.

In specific implementation, the embodiments of the display panel may refer to the embodiments of the display panel described above, and repeated descriptions are omitted.

Based on the same inventive concept, the embodiment of the present invention provides a display device, such as the schematic structural diagram of the display device shown in fig. 9, which may include a display panel X;

the display panel can be driven by the driving method provided by the embodiment of the invention. Alternatively, the display panel may be the display panel provided in the embodiment of the present invention.

In a specific implementation, the display device may be: any product or component with a display function, such as a mobile phone (as shown in fig. 9), a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A driving method of a display panel, the display panel comprising:

the driving method includes:

the data lines input data signals of the same polarity to the sub-pixels which are electrically connected with the data lines and are electrically connected with the gate lines in the same gate line group and have the same color;

first phase differences between grid opening signals input by every two adjacent grid lines in the same grid line group are the same;

the display panel includes: a display area and a non-display area surrounding the display area, the pixels being located within the display area;

the non-display area is internally provided with: the shift register comprises a plurality of shift register groups and clock signal line groups correspondingly and electrically connected with the shift register groups, wherein each shift register group comprises a plurality of cascaded shift registers, and the shift registers are electrically connected with one end of the grid lines; the clock signal line group comprises a first clock signal line and a second clock signal line;

the driving method further includes:

the first phase difference exists between first clock signals provided by first clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group;

the first phase difference exists between second clock signals provided by second clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group;

each grid line in the grid line group is correspondingly and electrically connected with the shift register at the same level in different shift register groups.

2. The driving method according to claim 1, wherein, of two of the gate line groups that are successively driven: a second phase difference exists between the gate start signal input by the last driven gate line in the last gate line group and the gate start signal input by the first driven gate line in the next gate line group, and the first phase difference is the same as the second phase difference.

3. The driving method according to claim 1, further comprising:

two of the gate line groups that are driven consecutively: a first clock signal provided by a first clock signal line electrically connected to the shift register and corresponding to the last gate line to be driven in the last gate line group exists, and a first phase difference exists between the first clock signal provided by a first clock signal line electrically connected to the shift register and corresponding to the first gate line to be driven in the next gate line group;

two of the gate line groups that are driven consecutively: the first phase difference exists between a second clock signal provided by a second clock signal line electrically connected with the shift register and correspondingly arranged to the last driven gate line in the last gate line group and a second clock signal provided by a second clock signal line electrically connected with the shift register and correspondingly arranged to the first driven gate line in the next gate line group.

4. The driving method of claim 1, wherein the gate line group includes M of the gate lines;

the driving method further includes:

for two consecutive gate line groups of the gate line groups of odd drive or even drive: a third phase difference exists between a first clock signal provided by a first clock signal line electrically connected with the shift register and correspondingly arranged to the last driven gate line in the last gate line group and a first clock signal provided by a first clock signal line electrically connected with the shift register and correspondingly arranged to the first driven gate line in the next gate line group;

for two consecutive gate line groups of the gate line groups of odd drive or even drive: the third phase difference exists between a second clock signal provided by a second clock signal line electrically connected with the shift register and correspondingly arranged to the last driven gate line in the last gate line group and a second clock signal provided by a second clock signal line electrically connected with the shift register and correspondingly arranged to the first driven gate line in the next gate line group;

wherein the third phase difference is M times the first phase difference.

5. The driving method according to claim 4, wherein the set number of the shift register groups is 2M.

6. The driving method according to claim 1, wherein the non-display region includes two sub-regions respectively located in the non-display regions to which both ends of the gate lines are directed;

each shift register group is arranged in the same subregion;

or, each shift register group is equally arranged in two sub-areas.

7. The driving method according to any one of claims 1 to 6, wherein the first phase difference is 3 microseconds to 10 microseconds.

8. The driving method according to any one of claims 1 to 5, wherein the data line is electrically connected to two columns of sub-pixels, and the gate line group includes two of the gate lines;

or, the data lines are electrically connected with four columns of sub-pixels, and the grid line group comprises four grid lines.

9. A display device, comprising a display panel;

the display panel is driven by the driving method according to any one of claims 1 to 8.

10. A display panel, comprising:

the grid lines are arranged along the column direction and extend along the row direction, two grid lines are arranged between any two adjacent rows of sub-pixels, and one side, away from the last row of sub-pixels, of the first row of sub-pixels and one side, away from the first row of sub-pixels, of the last row of sub-pixels are respectively provided with one grid line; all the grid lines are divided into a plurality of grid line groups, each grid line group comprises a plurality of grid lines, and at least one row of sub-pixels are arranged between the sub-pixels electrically connected with any two adjacent grid lines in the grid line groups; sequentially inputting a grid opening signal to each grid line group, and sequentially inputting a grid opening signal to each grid line in the grid line group so that the sub-pixels which are electrically connected with the same data line and are electrically connected with each grid line in the same grid line group have the same color and input the data signals with the same polarity;

the display panel further includes:

a display area and a non-display area surrounding the display area, the pixels being located within the display area;

each grid line is electrically connected with one shift register, and each grid line in the grid line group is correspondingly and electrically connected with the shift register in the same level in different shift register groups, so that the first phase difference exists between first clock signals provided by first clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group, and the first phase difference exists between second clock signals provided by second clock signal lines electrically connected with the shift registers corresponding to every two adjacent grid lines in the same grid line group.

11. The display panel according to claim 10, wherein the number of the gate line groups is set to an integral multiple of 4.