CN103268757B - A kind of grid of display panels drives module and display panels - Google Patents
A kind of grid of display panels drives module and display panels Download PDFInfo
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- CN103268757B CN103268757B CN201210224194.4A CN201210224194A CN103268757B CN 103268757 B CN103268757 B CN 103268757B CN 201210224194 A CN201210224194 A CN 201210224194A CN 103268757 B CN103268757 B CN 103268757B
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Abstract
The grid that the invention provides a kind of display panels drives module and display panels, described grid drives module to comprise master control amorphous gate driver circuit, controlled amorphous gate driver circuit and on-off circuit, the signal input part of described on-off circuit and signal output part arrange end respectively at the operating conditions of two controlled amorphous gate driver circuits and connect, and the control input end of described on-off circuit is connected with the output of described master control amorphous gate driver circuit. The electric charge that the grid of described display panels and display panels drives module to make full use of redundancy arranges end to the operating conditions of amorphous gate driver circuit to be charged and carries out precharge, amorphous gate driver circuit after precharge comes interim at subsequent clock pulse signal, can reduce to provide with clock pulse signal the difference of the voltage of charging, thereby save electric energy, further reduce grid and driven the overall power of module, and reduced the IC load of clock pulse signal output voltage.
Description
Technical field
The present invention relates to liquid crystal flat-panel Display Technique, relate in particular to a kind of display panels and grid thereof and driveModule.
Background technology
FPD (flat-panel display device) taking TFT-LCD (liquid crystal display panel of thin film transistor) as representativeTechnology started to develop rapidly and progressively move to maturity from the nineties in 20th century. Because TFT-LCD has high definitionClear, low-power consumption, frivolous, the advantage such as be easy to carry, be widely used in above-mentioned information to show in product,There are wide market prospects.
In the prior art, the drive unit of display panels generally includes following module: sequential controlDevice processed, grid drive module, source electrode driving device, common electric voltage, power module and reference voltage severalPart. Wherein, grid drives module for receiving the signal of time sequence control device, according to this signal cycle groundFor corresponding scan line output signal output, thereby open or close again and again scan line, to control liquidLCD panel is realized scanning process.
Along with display panels is higher to integrated level, definition better, response speed future development faster,Original common IC circuit as grid driving module becomes increasingly complex, the area that makes grid drive module to occupyIncreasing, the dwindling greatly of frame size of display floater limited, therefore can not be completeAdapt to grid and drive module, that arise at the historic moment is amorphous gate driver circuit (AmorphousSiliconGateDriver, ASGDriver), amorphous gate driver circuit can be with independently unit formation control one line scanningLine, amorphous gate driver circuit even can be according to process requirements Compiler scan program, and, amorphous gridDrive circuit can be jointly provides clock pulses by a supply lines or the supply lines that is divided into one of several groups of each freedomSignal, thereby the size of rotating different supply lines can make grid drive the entire area of module to be controlled at lessSize range in, simultaneously the response speed of amorphous gate driver circuit can effectively improve.
Fig. 1 is the structural representation of display panels in prior art, as shown in Figure 1, and in prior artIn, amorphous gate driver circuit 10 comprises a shift register circuit and two on-off circuits, wherein shift LDsDevice is D flip-flop commonly, and in shift register circuit, an output is as amorphous gate driver circuit 10Operating conditions arranges end, and as shown in Figure 1, in the time of a clock pulse signal CK input, operating conditions arranges endQ is just sent to its logic state the output Out of amorphous gate driver circuit 10, when operating conditions settingWhen end Q charges to high voltage, in the time of a clock pulse signal input, described amorphous gate driver circuit 10Output Out output HIGH voltage.
Fig. 2 is the structural representation of display panels in prior art, as shown in Figure 2, and LCDPlate 20 both sides are formed with some gate driver circuits, and this gate driver circuit is amorphous gate driver circuit 10,Each amorphous gate driver circuit 10 comprises: pulse signal input terminal CK, input Set is set, reset defeatedEnter to hold Reset and output Out, described pulse signal input terminal CK is for return pulse signal; Arrange defeatedEnter to hold Set for making amorphous gate driver circuit 10 in opening; Described replacement input Reset usesIn making amorphous gate driver circuit 10 in Reset Status; Described output Out is used for output signal output,Described amorphous gate driver circuit 10 also comprises that operating conditions arranges end Q, for its logic state is sent to non-The output Out of brilliant gate driver circuit 10. Some amorphous gate driver circuits 10 are by the first clock signalCKL1 and second clock signal CKL2 provide clock pulse signal, and it is strange that the first clock signal C KL1 controlsSeveral amorphous gate driver circuits 10, are connected in first, the 3rd, the amorphous gate driver circuit 10 such as the 5thPulse signal input terminal CK, second clock signal CKL2 controls even number amorphous gate driver circuit 10,For example be connected in second, the 4th, the pulse signal input terminal CK of the amorphous gate driver circuit 10 such as the 6th.What initial setting up signal STP1 was connected in the first amorphous gate driver circuit 10 arranges input Set, to controlThe unlatching of the first amorphous gate driver circuit 10, the output Out of last amorphous gate driver circuit 10 connectsWhat be connected to next amorphous gate driver circuit 10 arranges input Set, drives to control this next amorphous gridThe unlatching of circuit 10, and the output Out of a rear amorphous gate driver circuit 10 is connected in last amorphousThe replacement input Reset of gate driver circuit 10, to control the pass of this last amorphous gate driver circuit 10Close, wherein the operating conditions of each amorphous gate driver circuit 10 arranges end and does not drive electricity with other amorphous gridsRoad 10 connects.
Fig. 3 is the driving process sequential chart that in prior art, grid drives module, in conjunction with Fig. 1～Fig. 3, with liquidSome amorphous gate driver circuits 10 in LCD panel 20 left sides are example, the first clock signal C KL1 andThe cycle of second clock signal CKL2 is identical, and phase phasic difference 180 is spent, when initial signalization STP1 inputTime, the first amorphous gate driver circuit is opened, and its operating conditions arranges end Q11 and starts charging, when the first clockWhen signal CKL1 exports first pulse clock signal, Q11 output HIGH voltage, thereby the first amorphous gridDrive circuit output signal output G11; When this output signal G11 output, the second amorphous gate driver circuitOpen, its operating conditions arranges end Q12 and starts charging, and when second clock signal, CKL2 exports first pulseWhen clock signal, Q12 output HIGH voltage, thereby the second amorphous gate driver circuit output signal output G12;When this output signal G12 output, first amorphous gate driver circuit is closed, and its operating conditions arranges end Q11Start electric discharge, the 3rd amorphous gate driver circuit is opened, and its operating conditions arranges end Q13 and starts charging, when theWhen second pulse clock signal of one clock signal CKL1 output, Q13 output HIGH voltage, thus second non-Brilliant gate driver circuit output signal output G13, when output signal G13 output, the second amorphous grid drivesCircuit is closed, and its operating conditions arranges end Q12 and starts electric discharge, thereafter by that analogy, and TFT-LCD panel 20Some amorphous gate driver circuits 10 and the some amorphous gate driver circuits 10 in its right side in left side are controlled respectivelyThe scan line of display panels 20, the control of the amorphous gate driver circuit by left side and right side, realizesTo lining by line scan of scan line in display panels 20.
But, as shown in Figure 3, the output signal G11 of the first amorphous gate driver circuit stop output andThe output signal G12 of the second amorphous gate driver circuit starts in the time period M between output, the first amorphousThe operating conditions of gate driver circuit arranges end Q11 and does not start electric discharge, and the work of the 3rd amorphous gate driver circuitPose to arrange and hold Q13 also not start charging, the operating conditions of the first amorphous gate driver circuit arranges end Q11The electric charge of redundancy is directly discharged after this time period M, and the operating conditions of the 3rd amorphous gate driver circuit is establishedPutting end Q13 needs directly to utilize coupled clock pulse signal to charge, equally for the time periodN, the operating conditions of the second amorphous gate driver circuit arranges end Q12 and does not start electric discharge, and the 4th amorphous gridThe operating conditions of drive circuit arranges end Q14 and does not start charging, in the work of the second amorphous gate driver circuitState arranges the electric charge of end Q12 redundancy and directly discharges after this time period N, and the 4th amorphous grid drives electricityThe operating conditions on road arranges end Q14 needs directly to utilize coupled clock pulse signal to charge, fromAnd make in prior art, driving in module at grid has the electric charge of a lot of redundancies directly to be discharged, not effectivelyUtilize, thereby affect the overall power of grid driving module.
Summary of the invention
The grid that the object of this invention is to provide the display panels that a kind of power consumption is lower drives module, andThe display panels that drives module to be combined to form by this grid.
For addressing the above problem, the grid that the invention provides a kind of display panels drives module, described gridThe utmost point drives module to comprise master control amorphous gate driver circuit and controlled amorphous gate driver circuit; Also comprise switchCircuit, the signal input part of described on-off circuit and signal output part drive respectively at two controlled amorphous gridsThe operating conditions of circuit arranges end and connects, and the control input end of described on-off circuit and described master control amorphous grid driveThe output of moving circuit connects.
Further, in the time that master control amorphous gate driver circuit sends output signal, with described master control amorphous gridThe on-off circuit conducting that utmost point drive circuit connects, two controlled amorphous grid that are connected by described on-off circuitThe operating conditions of utmost point drive circuit arranges end conducting, makes the operating conditions setting of two controlled amorphous gate driver circuitsEnd transmits electric charge.
Further, in two controlled amorphous gate driver circuits that are connected with on-off circuit, partial redundance electricityLotus arranges end to controlled amorphous grid to be charged from the operating conditions of controlled amorphous gate driver circuit to be dischargedThe operating conditions of drive circuit arranges end.
Further, described on-off circuit is thin film transistor (TFT); The source electrode of described thin film transistor (TFT) and drain electrode pointWith the operating conditions of two described controlled amorphous gate driver circuits, end is not set and is connected, described thin film transistor (TFT)Grid is connected with the output of master control amorphous gate driver circuit.
The present invention also provides a kind of liquid crystal panel, comprise pixel cell group and with described pixel cell group in pixelThe scan line that unit connects, described liquid crystal panel also comprises some amorphous gate driver circuits and some switch electricityRoad, described amorphous gate driver circuit and described scan line connect one to one, and described amorphous grid drives electricityRoad is divided into the first circuit group and second circuit group, and A amorphous grid in wherein said the first circuit group drivesMoving circuit and A+2 amorphous gate driver circuit are as controlled amorphous gate driver circuit, second circuit groupIn A amorphous gate driver circuit as master control amorphous gate driver circuit and 2A-1 switch electricityRoad, composition drives module just like the grid described in any one in claim 1 to 4; And described secondA amorphous gate driver circuit in circuit group and A+2 amorphous gate driver circuit are as controlled non-In brilliant gate driver circuit, the first circuit group, A+1 amorphous gate driver circuit is as master control amorphous gridDrive circuit and 2A on-off circuit, composition is just like the grid described in any one in claim 1 to 4The utmost point drives module, and described A is positive integer.
Further, each amorphous gate driver circuit also comprises: pulse signal input terminal, and for receiving arteries and veinsRush signal; Input is set, for receiving start signal, so that amorphous gate driver circuit is in opening shapeState; Replacement input, for receiving reset signal, so that amorphous gate driver circuit is in closed condition;Wherein in the first circuit group and second circuit group in circuit group separately, first amorphous gate driver circuitInput access initial setting up signal is set, the replacement input of A+1 amorphous gate driver circuit andThe output electrical connection of A+2 amorphous gate driver circuit, A+1 amorphous gate driver circuit defeatedGoing out end is electrically connected with the input that arranges of A+2 amorphous gate driver circuit.
Further, in described the first circuit group, 2A-1 amorphous gate driver circuit accesses the first clock arteries and veinsRush signal, 2A amorphous gate driver circuit access second clock pulse signal in described the first circuit group,2A-1 amorphous gate driver circuit access the 3rd clock signal in described second circuit group, described the second electricity2A amorphous gate driver circuit access the 4th clock pulse signal of Lu Zuzhong.
Further, described the first clock pulse signal, second clock pulse signal, the 3rd clock pulses letterNumber identical with the cycle of the 4th clock pulse signal, and described the first clock pulse signal and second clock pulseThe single spin-echo of signal, the single spin-echo of described the 3rd clock pulse signal and the 4th clock pulse signal, instituteState after the 3rd clock pulse signal betides described the first clock pulse signal.
Further, described scan line is divided into first kind scan line and the Equations of The Second Kind scanning that alternate intervals is arrangedLine, in described the first circuit group, amorphous gate driver circuit is corresponding one by one with described first kind scan line, described inIn second circuit group, amorphous gate driver circuit is corresponding one by one with described Equations of The Second Kind scan line.
Further, described the first circuit group is arranged at a side of described pixel cell group, described second circuitGroup is arranged at the opposite side of described pixel cell group.
Further, described the first circuit group and described second circuit group are arranged at the same of described pixel cell groupOne side.
In sum, the grid of display panels of the present invention drives module, comprises that master control amorphous grid drivesCircuit and controlled amorphous gate driver circuit and on-off circuit, the signal input part of described on-off circuit and letterNumber output arranges end respectively at the operating conditions of two controlled amorphous gate driver circuits and connects, described switch electricityThe control input end on road is connected with the output of described master control amorphous gate driver circuit. By master control amorphous gridThe unlatching of utmost point drive circuit gauge tap circuit, opens on-off circuit, is connected by this on-off circuitThe operating conditions of two controlled amorphous gate driver circuits arranges end conducting, two operating conditions is arranged between end and transmitElectric charge, thus the operating conditions of controlled amorphous gate driver circuit to be discharged is arranged to the redundancy electric charge part of endThe operating conditions that passes to controlled amorphous gate driver circuit to be charged arranges end, to utilize the electric charge pair of redundancyThe operating conditions of controlled amorphous gate driver circuit to be charged arranges end and has carried out precharge, non-after prechargeBrilliant gate driver circuit comes interim at subsequent clock pulse signal, can reduce provides and fill with clock pulse signalThe difference of the voltage of electricity, thus electric energy saved, further reduce the overall power of grid driving module,And the IC that has reduced clock pulse signal output voltage loads.
The present invention also provides a kind of display panels, and this display floater is driven by some amorphous grid circuits whereinMoving the electric circuit constitute, amorphous grid circuit drive circuit drives module to form by some grids, has further reducedThe power consumption of whole display panels, the IC that has simultaneously reduced clock pulse signal output voltage loads, and makes liquidLCD panel work is more stable.
Brief description of the drawings
Fig. 1 is the structural representation of display panels in prior art.
Fig. 2 is the structural representation of display panels in prior art.
Fig. 3 is the driving process sequential chart of the amorphous gate driver circuit of display panels in prior art.
Fig. 4 is the structural representation that the grid in one embodiment of the invention drives module.
Fig. 5 is the structural representation of an amorphous gate driver circuit of display panels in one embodiment of the inventionFigure.
Fig. 6 is the structural representation of display panels in one embodiment of the invention.
When Fig. 7 is the driving process of amorphous gate driver circuit of display panels in one embodiment of the inventionOrder figure.
Fig. 8 is operating conditions setting in the amorphous gate driver circuit of display panels in one embodiment of the inventionThe emulation sequential chart of end output signal.
Fig. 9 is output output in the amorphous gate driver circuit of display panels in one embodiment of the inventionThe emulation sequential chart of signal.
Figure 10 is that the power of display panels and prior art display panels in one embodiment of the invention is imitativeTrue comparison diagram.
Detailed description of the invention
For making content of the present invention more clear understandable, below in conjunction with Figure of description, to content of the present inventionBe described further. Certainly the present invention is not limited to this specific embodiment, those skilled in the art instituteThe general replacement of knowing is also encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, in the time that example of the present invention is described in detail in detail, forBe convenient to explanation, schematic diagram does not amplify according to general ratio is local, should be using this as limitation of the invention.
Fig. 4 is the structural representation that the grid in one embodiment of the invention drives module. As shown in Figure 4, originallyInvention provides a kind of described grid to drive module to comprise master control amorphous gate driver circuit 13 and controlled amorphous gridDrive circuit 11,12; Also comprise on-off circuit T, signal input part and the signal of described on-off circuit T are defeatedGo out end respectively at the operating conditions of two controlled amorphous gate driver circuits 11,12 arrange end Q connect, described in openThe control input end of closing circuit T is connected with the output Out of described master control amorphous gate driver circuit 13, whenWhen master control amorphous gate driver circuit 13 sends output signal, with described master control amorphous gate driver circuit 13The on-off circuit conducting connecting, two controlled amorphous gate driver circuits that are connected by described on-off circuit11,12 operating conditions arranges end conducting, and the operating conditions of two controlled amorphous gate driver circuits 11,12 is establishedPut end and transmit electric charge, thereby the operating conditions of controlled amorphous gate driver circuit 11 to be discharged is arranged to the superfluous of endThe operating conditions that remaining electric charge part passes to controlled amorphous gate driver circuit 12 to be charged arranges end, to utilizeThe electric charge of redundancy arranges end to the operating conditions of controlled amorphous gate driver circuit 12 to be charged and has carried out preliminary fillingElectricity, the amorphous gate driver circuit 12 after precharge comes interim at subsequent clock pulse signal, can reduce withClock pulse signal provides the difference of the voltage of charging, has further reduced the overall power of grid driving module,And the IC that has reduced clock pulse signal output voltage loads.
Utilize above-mentioned grid to drive module, the present invention also provides a kind of liquid crystal panel, and described liquid crystal panel also wrapsDraw together some amorphous gate driver circuits and some on-off circuits, described amorphous gate driver circuit and described scanningLine connects one to one, and described amorphous gate driver circuit is divided into the first circuit group and second circuit group, establishes AFor arbitrary integer, particularly, A can from 1 to first circuit group or second circuit group amorphous grid driveAny integer (common the first circuit group equates with the number of second circuit group) between the number of circuit, itsDescribed in A amorphous gate driver circuit and A+2 amorphous gate driver circuit in the first circuit groupAs A amorphous gate driver circuit in controlled amorphous gate driver circuit, second circuit group as master controlAmorphous gate driver circuit and 2A-1 on-off circuit, the grid forming described in drives module; AndA amorphous gate driver circuit and A+2 amorphous gate driver circuit in described second circuit group are doneFor A+1 amorphous gate driver circuit in controlled amorphous gate driver circuit, the first circuit group is as master controlAmorphous gate driver circuit and 2A on-off circuit, composition one grid of the present invention drives module.
Fig. 5 is the structural representation of an amorphous gate driver circuit of display panels in one embodiment of the inventionFigure. As shown in Figure 5, in the present embodiment, each amorphous gate driver circuit also comprises: pulse signal is defeatedEnter to hold CK, for return pulse signal; Input Set is set, for receiving start signal, so that amorphousGate driver circuit is in opening; Replacement input Reset, for receiving reset signal, so that amorphousGate driver circuit is in closed condition; Output Out, for output signal output; Operating conditions arranges end Q,Described operating conditions arranges end Q, and described operating conditions arranges end Q for its logic state is sent to amorphous gridThe output Out of drive circuit 10. In addition, in Fig. 5, VGH is high level input, and VGL is low electricityFlat input, CKB is for accessing the pulse all the time signal anti-phase with pulse signal input terminal CK.
Wherein in the first circuit group and second circuit group in circuit group separately, first amorphous grid drivesThe input that arranges of circuit accesses initial setting up signal, the replacement input of A+1 amorphous gate driver circuitEnd is electrically connected with the output of A+2 amorphous gate driver circuit, A+1 amorphous gate driver circuitOutput be electrically connected with the input that arranges of A+2 amorphous gate driver circuit.
In the present embodiment, in described the first circuit group, 2A-1 amorphous gate driver circuit accesses at first o'clockClock signal, 2A amorphous gate driver circuit access second clock pulse letter in described the first circuit groupNumber, 2A-1 amorphous gate driver circuit access the 3rd clock signal in described second circuit group, described the2A amorphous gate driver circuit access the 4th clock pulse signal in two circuit groups.
Wherein, described the first clock pulse signal, second clock pulse signal, the 3rd clock pulse signal andThe cycle of the 4th clock pulse signal is identical, and described the first clock pulse signal and second clock pulse signalSingle spin-echo, the single spin-echo of described the 3rd clock pulse signal and the 4th clock pulse signal, describedThree clock pulse signals betide between described the first clock pulse signal and described second clock pulse signal andTime of origin is staggered.
Described scan line and described amorphous gate driver circuit connect one to one, and described scan line is divided into friendshipFor spaced first kind scan line and Equations of The Second Kind scan line, in described the first circuit group, amorphous grid drivesCircuit is corresponding one by one with described first kind scan line, amorphous gate driver circuit and institute in described second circuit groupState Equations of The Second Kind scan line corresponding one by one.
Preferably, described the first circuit group and second circuit group can be arranged at respectively the both sides of pixel cell group,The first circuit group is arranged at a side of described pixel cell group, and described second circuit group is arranged at described pixelThe opposite side of unit group, so that the area of the amorphous gate driver circuit of average liquid crystal panel both sides frame.In addition, described the first circuit group and described second circuit group are also arranged at the same side of described pixel cell group.
Fig. 6 is the structural representation of display panels in one embodiment of the invention. For clearer convenient descriptionThe grid of described display panels drives module, in conjunction with Fig. 6, below divides with display panels 20 both sidesThe first circuit group and second circuit group are not set, and the first circuit group and second circuit group respectively have eight amorphous gridsDrive circuit, and described on-off circuit is divided into two on-off circuit groups, and the first on-off circuit group has eight switchesCircuit T11～T18, it is example that second switch circuit group has eight on-off circuit T11～T18, describes this in detailThe grid of bright display panels drives module and is driven the knot of the display floater that module forms by this gridStructure, it will be clear that display floater of the present invention never only limits to structure, raw in actual techniqueIn product process, in the position of arranging of the first circuit group and second circuit group, the first circuit group and second circuit groupSwitch in the number of amorphous gate driver circuit and corresponding the first on-off circuit group and second switch circuit groupThe number of circuit is not defined, and all can specifically determine according to technological requirement.
In the present embodiment, described grid drives module to comprise some amorphous gate driver circuits 10 and switch electricityRoad group, in the present embodiment, described on-off circuit component is the first on-off circuit group T1 and second switch circuitGroup T2, the first on-off circuit group T1 is all odd number on-off circuits in described on-off circuit group, described inSecond switch circuit group T2 is all even number on-off circuits in described on-off circuit group, establishes A for just wholeNumber, 2A-1 on-off circuit is A on-off circuit in the first on-off circuit group T1, opens for 2AClosing circuit is A on-off circuit in second switch circuit group; Described amorphous gate driver circuit 10 with described inThe scan line of display panels 20 connects one to one. Each amorphous gate driver circuit 10 comprises: arteries and veinsRush signal input part CK, it is for return pulse signal; Input Set is set, and it opens letter for receivingNumber, so that amorphous gate driver circuit is in opening; Replacement input Reset, it is for receiving replacementSignal, so that amorphous gate driver circuit is in closed condition; Output Out, it is for output signal output;And operating conditions arrange end Q, operating conditions arrange end Q for its logic state is sent to amorphous grid driveThe output Out of circuit 10, in the time that operating conditions arranges end Q output HIGH voltage, its output Out can rootAccording to the control output HIGH voltage of clock pulse signal.
All amorphous gate driver circuits 10 are divided into the first circuit group and second circuit group, display panels 20Scan line be divided into first kind horizontal scanning line and Equations of The Second Kind horizontal scanning line, the first circuit group and first kind line scanningLine connects one to one, and second circuit group and Equations of The Second Kind horizontal scanning line connect one to one.
In preferred embodiment, the first circuit group and second circuit group are arranged at respectively described LCDThe left and right sides of plate 20, described first kind horizontal scanning line and Equations of The Second Kind horizontal scanning line interlaced alternative are arranged simultaneously.The first on-off circuit group and second switch circuit group are respectively in the left and right sides of display panels 20 equally, onState as structure preferably, be convenient to the both sides frame size of uniform distribution display panels 20, other are for example years oldOne circuit group and second circuit group are positioned at the same side, and first circuit group control the first half scan line, the second electricityThe structure of road group control later half scan line etc. is also within thought range of the present invention.
If A is positive integer, in the first circuit group and second circuit group, in circuit group separately, A non-The replacement input of brilliant gate driver circuit is electrically connected with the output of A+1 amorphous gate driver circuit,Be the replacement input Reset of first amorphous gate driver circuit and second amorphous gate driver circuitOutput Out electrical connection, the replacement input Reset of second amorphous gate driver circuit and the 3rd amorphousThe output Out electrical connection of gate driver circuit, by that analogy. Therefore at the first circuit group and second circuitIn group, in circuit group separately, the output signal control of the output of a rear amorphous gate driver circuit is lastClosing of amorphous gate driver circuit.
In the first circuit group and second circuit group in circuit group separately, first amorphous gate driver circuitInput Set access initial setting up signal STP is set, A+1 amorphous gate driver circuit thereafterOutput is electrically connected with the input that arranges of A+2 amorphous gate driver circuit; The first amorphous grid drivesMoving circuit input Set access initial setting up signal STP is set, first amorphous gate driver circuit defeatedGo out to hold Out to be electrically connected with the input Set that arranges of second amorphous gate driver circuit, second amorphous gridThe output Out of drive circuit is electrically connected with the input Set that arranges of the 3rd amorphous gate driver circuit, withThis analogizes. Therefore in the first circuit group and second circuit group in circuit group separately, previous amorphous gridThe unlatching of next amorphous gate driver circuit of output signal control of the output Out of drive circuit.
It is individual that in described the first circuit group, the operating conditions of A amorphous gate driver circuit arranges end Q and A+2The operating conditions of amorphous gate driver circuit arrange end Q respectively with A on-off circuit of the first on-off circuit groupSignal input part be connected with signal output part, the control of A on-off circuit of described the first on-off circuit groupInput processed is connected with the output Out of A amorphous gate driver circuit in second circuit group, described inA on-off circuit of the first on-off circuit group is by A amorphous gate driver circuit in second circuit groupOutput signal control opening and closing.
For example in the first circuit group, the operating conditions of first amorphous gate driver circuit arranges end Q11 and the first electricityThe operating conditions of the 3rd amorphous gate driver circuit of Lu Zuzhong arranges end Q13 by the of the first on-off circuit groupAn on-off circuit T11 is connected, and the control of first on-off circuit T11 of described the first on-off circuit group is defeatedEnter end and be connected with the output Out of first amorphous gate driver circuit in second circuit group, be i.e. the first switchFirst on-off circuit T11 of circuit group is by the output of first amorphous gate driver circuit in second circuit groupSignal G21 controls opening and closing; In the first circuit group, the operating conditions of second amorphous gate driver circuit is establishedThe operating conditions of putting the 4th amorphous gate driver circuit in end Q12 and the first circuit group arranges end Q14 and passes through theSecond on-off circuit T12 of one on-off circuit group is connected, second switch of described the first on-off circuit groupThe output Out of second amorphous gate driver circuit in the control input end of circuit T12 and second circuit groupConnect, second on-off circuit T12 of this first on-off circuit group is by second amorphous in second circuit groupThe output signal G22 of gate driver circuit controls opening and closing, thereafter the like.
It is individual that in described second circuit group, the operating conditions of A amorphous gate driver circuit arranges end Q and A+2The operating conditions of amorphous gate driver circuit arrange end Q respectively with A on-off circuit of second switch circuit groupSignal input part be connected with signal output part, the control of A on-off circuit of described second switch circuit groupInput processed is connected with the output of A+1 amorphous gate driver circuit in the first circuit group, and describedA on-off circuit of two on-off circuit groups is by A+1 amorphous gate driver circuit in the first circuit groupOutput signal control opening and closing.
For example in second circuit group, the operating conditions of first amorphous gate driver circuit arranges end Q21 and the second electricityThe operating conditions of the 3rd amorphous gate driver circuit of Lu Zuzhong arranges end Q23 by the of second switch circuit groupAn on-off circuit T21 is connected, and the control of first on-off circuit T21 of described second switch circuit group is defeatedEnter end and be connected with the output Out of second amorphous gate driver circuit in the first circuit group, be i.e. second switchFirst on-off circuit T21 of circuit group is by the output of second amorphous gate driver circuit in the first circuit groupSignal G12 controls opening and closing; In second circuit group, the operating conditions of second amorphous gate driver circuit is establishedThe operating conditions of putting the 4th amorphous gate driver circuit in end Q22 and second circuit group arranges end Q24 and passes through theSecond on-off circuit T22 of two on-off circuit groups is connected, second switch of described second switch circuit groupThe output Out of the 3rd amorphous gate driver circuit in the control input end of circuit T22 and the first circuit groupConnect, second of second switch circuit group on-off circuit T22 is by the 3rd amorphous grid in second circuit groupThe output signal G22 of utmost point drive circuit controls opening and closing, thereafter the like.
Hence one can see that, in display panels, except the first amorphous gate driver circuit in the first circuit group and theIn two circuit groups, outside a last amorphous gate driver circuit, each amorphous gate driver circuit can be done simultaneouslyBe that a grid drives the master control amorphous gate driver circuit in module, and drive as another amorphous gridControlled amorphous gate driver circuit in module, thus the output of each amorphous gate driver circuit can be controlledThe operating conditions of making another two amorphous gate driver circuits of corresponding connection arranges the transfer of the electric charge between end, andAnd, operating conditions that should each amorphous gate driver circuit is arranged to end and can accept other phases in the charging stageThe operating conditions of the amorphous gate driver circuit that should connect arranges the transfer of the electric charge of the redundancy of end, at discharge regimeThe electric charge of self redundancy can be transferred to the amorphous gate driver circuit of other corresponding connections, its each amorphousGate driver circuit is connected implementation as shown in Figure 6 with the concrete of other amorphous gate driver circuits, therebyIn the first circuit group, the first amorphous gate driver circuit, the operating conditions of each amorphous gate driver circuit is establishedPut end and first carry out precharge, the amorphous gate driver circuit work to be discharged of another corresponding connection of receiving unitPose the redundancy electric charge of end be set, come temporarily at the clock pulse signal of controlling amorphous gate driver circuit,The operating conditions that has reduced amorphous gate driver circuit arranges end and clock pulse signal provides between charging voltageDifference, thus electric energy saved, further reduce grid and driven the overall power of module, and while having reducedThe IC of clock signal output voltage loads, and then has reduced the power consumption of overall display panels.
Further, in the present embodiment, described on-off circuit T11～T18 and on-off circuit T21～T28For TFT, in described the first circuit group, the operating conditions of A amorphous gate driver circuit is establishedPut end and the operating conditions of A+2 amorphous gate driver circuit arrange end respectively with the of the first on-off circuit groupThe source electrode of A thin film transistor (TFT) is connected with drain electrode, A thin film transistor (TFT) of described the first on-off circuit groupGrid be electrically connected with the output of A amorphous gate driver circuit in second circuit group; I.e. the first circuitIn group, the operating conditions of first amorphous gate driver circuit arranges end Q11 and the 3rd amorphous gate driver circuitOperating conditions arrange end Q13 respectively with the source electrode of first thin film transistor (TFT) T11 of the first on-off circuit group andDrain electrode is connected, grid and the second circuit group of first thin film transistor (TFT) T11 of described the first on-off circuit groupIn the output Out of first amorphous gate driver circuit be electrical connected, of described the first on-off circuit groupThe unlatching of a thin film transistor (TFT) T11 is subject to the output of first amorphous gate driver circuit in second circuit groupThe output control of Out; In the first circuit group, the operating conditions of second amorphous gate driver circuit arranges end Q12With the operating conditions of the 4th amorphous gate driver circuit arrange end Q14 respectively with second of the first on-off circuit groupThe source electrode of individual thin film transistor (TFT) T12 is connected with drain electrode, second film crystal of described the first on-off circuit groupIn the grid of pipe T12 and second circuit group, the output Out of second amorphous gate driver circuit is electrical connected,The unlatching of second thin film transistor (TFT) T12 of described the first on-off circuit group be subject in second circuit group second non-The output signal G22 of the output Out of brilliant gate driver circuit controls, and the rest may be inferred thereafter.
In described second circuit group, that end is set is non-with A+2 for the operating conditions of A amorphous gate driver circuitThe operating conditions of brilliant gate driver circuit arranges end respectively with A thin film transistor (TFT) of second switch circuit groupSource electrode is connected with drain electrode, and the grid of A thin film transistor (TFT) of described second switch circuit group is by the first circuitThe output of A+1 amorphous gate driver circuit of group is electrical connected; Be that in second circuit group, first is non-The operating conditions of brilliant gate driver circuit arranges the 3rd amorphous gate driver circuit in end Q21 and second circuit groupOperating conditions arrange end Q23 respectively with the source electrode of first thin film transistor (TFT) T21 of second switch circuit group andDrain electrode is connected, the grid of first thin film transistor (TFT) T21 of described the first on-off circuit group and the first circuit groupIn the output Out of second amorphous gate driver circuit be electrical connected, of described second switch circuit groupThe unlatching of a thin film transistor (TFT) T21 is subject to the output of second amorphous gate driver circuit in the first circuit groupThe output signal G12 of Out controls; In second circuit group, the operating conditions of second amorphous gate driver circuit is establishedThe operating conditions of putting the 4th amorphous gate driver circuit in end Q22 and second circuit group arrange hold Q24 respectively withThe source electrode of second thin film transistor (TFT) T22 of second switch circuit group is connected with drain electrode, described the first switch electricityThe 3rd amorphous gate driver circuit in the grid of second thin film transistor (TFT) T22 of road group and the first circuit groupOutput Out be electrical connected, the unlatching of first thin film transistor (TFT) T22 of described second switch circuit groupControlled by the output signal G13 of the output Out of the 3rd amorphous gate driver circuit in the first circuit group;Thereafter, the rest may be inferred.
In described the first circuit group, odd number amorphous gate driver circuit receives the first clock pulse signalCKL1, the first clock signal C KL1 controls the odd number amorphous gate driver circuit of the first circuit group,In the first circuit group first, the 3rd, the pulse signal input terminal CK of the amorphous gate driver circuit such as the 5th;In described the first circuit group, even number amorphous gate driver circuit receives second clock pulse signal CKL2,In the first circuit group second, the 4th, the pulse signal input terminal CK of the amorphous gate driver circuit such as the 6th; InstituteState in second circuit group odd number amorphous gate driver circuit and receive the 3rd clock pulse signal CKR2, theIn two circuit groups first, the 3rd, the pulse signal input terminal CK of the amorphous gate driver circuit such as the 5th; DescribedIn the 4th class amorphous gate driver circuit, even number amorphous gate driver circuit receives the 4th clock pulse signalCKR2, in second circuit group second, the 4th, the pulse signal input of the amorphous gate driver circuit such as the 6thEnd CK.
When Fig. 7 is the driving process of amorphous gate driver circuit of display panels in one embodiment of the inventionOrder figure. As shown in Figure 7, described the first clock pulse signal CKL1, second clock pulse signal CKL2,The 3rd clock pulse signal CKR1 is identical with the frequency of the 4th clock pulse signal CKR2, described first o'clockThe single spin-echo of clock signal CKL1 and second clock pulse signal CKL2, described the 3rd clock pulsesThe single spin-echo of signal CKR1 and the 4th clock pulse signal CKR2, described the 3rd clock pulse signalCKR1 betides between described the first clock pulse signal CKL1 and described second clock pulse signal CKL2And time of origin is staggered. And odd number amorphous gate driver circuit and described in described the first circuit groupThe phase place of one clock pulse signal is identical, in described the first circuit group even number amorphous gate driver circuit withThe phase place of described second clock pulse signal is identical, and in described second circuit group, odd number amorphous grid drivesCircuit is identical with the phase place of described the 3rd clock pulse signal, even number amorphous grid in described second circuit groupUtmost point drive circuit is identical with the phase place of described the 4th clock pulse signal.
When a certain clock arteries and veins in first to fourth clock pulse signal CKL1, CKL2, CKR1 and CKR2While rushing signal generation, be connected with its clock pulse signal and send out in the amorphous gate driver circuit of openingGo out output signal, make the on-off circuit conducting of the output control that is subject to its amorphous gate driver circuit, pass throughThe operating conditions of two amorphous gate driver circuits that described on-off circuit is connected arranges end conducting, makes two operating conditionsEnd is set from high voltage to low-voltage transferring energy.
In conjunction with Fig. 7, first initial setting up signal STP1 opens, and in the first kind, first amorphous grid drivesThe operating conditions of circuit arranges end Q11 to start to charge, when first clock pulse signal CKL1 output arteries and veinsWhile rushing signal, in the first kind, the operating conditions of first amorphous gate driver circuit arranges end Q11 output HIGH voltage,The output signal G11 output HIGH voltage of first amorphous gate driver circuit in the first kind; Initially establish firstPut signal STP1 output pulse and stop rear second initial setting up signal STP2 and open, in Equations of The Second Kind firstThe operating conditions of amorphous gate driver circuit arranges end Q21 and starts charging, as the 3rd clock pulse signal CKR1When output pulse signal, in the first kind, the operating conditions of first amorphous gate driver circuit arranges end Q21 outputHigh voltage, the output signal G21 output HIGH voltage of first amorphous gate driver circuit in Equations of The Second Kind, simultaneouslyThis output signal G21 opens first on-off circuit T11 in the first on-off circuit group, in the first kindThe operating conditions of first amorphous gate driver circuit arranges the 3rd amorphous grid in end Q11 and the first kind and drivesThe operating conditions of circuit arranges end Q13 conducting, now the work of first amorphous gate driver circuit in the first kindPose and the voltage of end in Q11 is set is filled into the operating conditions of the 3rd amorphous gate driver circuit in the first kindArrange in end Q13, the operating conditions of both having realized the 3rd amorphous gate driver circuit arranges shifting to an earlier date of end Q13Charging, can arrange the operating conditions of first amorphous gate driver circuit in the first kind electricity of holding Q11 redundancyThe operating conditions that lotus is passed to the 3rd amorphous gate driver circuit in the first kind arranges in end Q13; Follow secondClock pulse signal CKL2 output pulse signal, second amorphous gate driver circuit in the described first kindOperating conditions arranges end Q12 output HIGH voltage, the output of second amorphous gate driver circuit letter in the first kindNumber Q12, this output signal Q12 opens first on-off circuit T21 in second switch circuit group, and theIn two classes, the operating conditions of first amorphous gate driver circuit arranges the 3rd amorphous grid in end Q21 and Equations of The Second KindThe operating conditions of utmost point drive circuit arranges end Q23 conducting, now, drives mould thereby further lowered gridThe overall power of group.
Fig. 8 is operating conditions setting in the amorphous gate driver circuit of display panels in one embodiment of the inventionThe emulation sequential chart of end output signal. Fig. 9 is the amorphous grid of display panels in one embodiment of the inventionThe emulation sequential chart of output output signal in drive circuit, for convenience of clear inventive concept, Fig. 9 of expressingEnter to have enumerated the first amorphous gate driver circuit to the six amorphous gate driver circuits in the first circuit group with Figure 10And in second circuit group, the operating conditions of the first amorphous gate driver circuit to the six amorphous gate driver circuits is establishedPut the emulation sequential chart of end Q11～Q16, Q21～Q26 and output output signal G11～G16, G21～G26,Certain each amorphous gate driver circuit is thereafter exported corresponding pulse signal according to same this sequential. In conjunction with figure4, Fig. 9 and Figure 10 can see, adopt the present invention's display panels as shown in Figure 4 at actual scanningProcess, output signal G11～G16, the G21～G26's of the output output of each amorphous gate driver circuitSequential chart meets sweep signal requirement, and signal problem, do not produce mutually signal and disturb, and amorphous grid drivesIt is electric to second amorphous grid driving thereafter successively that the operating conditions of moving circuit arranges end Q11～Q13, Q21～Q23The operating conditions on road arranges end Q13～Q16, Q23～Q26 and has carried out precharge, thereby the grid after precharge drivesMoving circuit comes interim at subsequent clock pulse signal, can reduce to provide with clock pulse signal the voltage of chargingDifference, thereby saved electric energy, further reduced grid and driven the overall power of module, and reducedThe IC load of clock pulse signal output voltage.
Figure 10 is that the power of display panels and prior art display panels in one embodiment of the invention is imitativeTrue comparison diagram. As 10 for to carry out to the display panels of the prior art as shown in Fig. 2 the entirety that emulation obtainsPower with the display panels in one embodiment of the invention in Fig. 4 is carried out to overall power that emulation obtainsComparison diagram, each display panels comprises 20 amorphous gate driver circuits, wherein power points 100 is for existingHave the simulation result of the overall power of the display panels of technology, power points 200 is one embodiment of the inventionIn the simulation architecture of overall power of display panels, the display panels of known the prior artOverall power is 162.7 μ W, and the overall power of display panels of the present invention is 156.5 μ W, therefore thisBright display panels is than prior art, and it effectively reduces the overall power of grid driving module.
Certainly, display panels of the present invention is not limited only to by first kind circuit group and Equations of The Second KindCircuit group composition, can also be made up of the circuit group being divided three classes or the circuit group etc. that is divided into four classes etc.; AndThe first circuit and second circuit group are not limited to have respectively two clock pulse signal controls, can also have respectively threeAmorphous gate driver circuit in each circuit group of clock pulse signal control of individual, four or six etc.,The annexation that input, replacement input are set between amorphous gate driver circuit also can be adjusted accordingly,Therefore change that can other structures, can be defeated successively with the amorphous gate driver circuit of realizing each circuit groupGoing out output signal drives the circuit group structure that scans of scan line all within thought range of the present invention.
Although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention, Ren HesuoBelong in technical field and have and conventionally know the knowledgeable, without departing from the spirit and scope of the present invention, a little when doingChange and retouching, therefore protection scope of the present invention is when being as the criterion depending on claims person of defining.
Claims (10)
1. the grid of display panels drives a module, it is characterized in that, described grid drives moduleComprise master control amorphous gate driver circuit and controlled amorphous gate driver circuit; Also comprise on-off circuit,
The signal input part of described on-off circuit and signal output part drive electricity with two controlled amorphous grids respectivelyThe operating conditions on road arranges end and connects, and the control input end of described on-off circuit and described master control amorphous grid driveThe output of circuit connects, and described operating conditions arranges end and drives for its logic state being sent to amorphous gridThe output of circuit; Wherein,
Described on-off circuit is thin film transistor (TFT); The source electrode of described thin film transistor (TFT) and drain electrode respectively with two institutesThe operating conditions of stating controlled amorphous gate driver circuit arranges end and connects, the grid of described thin film transistor (TFT) and master controlThe output of amorphous gate driver circuit connects.
2. the grid of display panels as claimed in claim 1 drives module, it is characterized in that, whenWhen master control amorphous gate driver circuit sends output signal, be connected with described master control amorphous gate driver circuitOn-off circuit conducting, the work of two controlled amorphous gate driver circuits that are connected by described on-off circuitState arranges end conducting, makes the operating conditions of two controlled amorphous gate driver circuits that end transmission electric charge is set.
3. the grid of display panels as claimed in claim 1 drives module, it is characterized in that, withIn two controlled amorphous gate driver circuits that on-off circuit is connected, partial redundance electric charge is to be discharged controlledThe operating conditions of amorphous gate driver circuit arranges the work of end to controlled amorphous gate driver circuit to be chargedState arranges end.
4. a liquid crystal panel, comprises pixel cell group and is connected with pixel cell in described pixel cell groupScan line, it is characterized in that, described liquid crystal panel also comprises some amorphous gate driver circuits and some openingClose circuit, described amorphous gate driver circuit and described scan line connect one to one, and described amorphous grid drivesMoving circuit is divided into the first circuit group and second circuit group, wherein
A amorphous gate driver circuit and A+2 amorphous grid in described the first circuit group drive electricityRoad as A amorphous gate driver circuit in controlled amorphous gate driver circuit, second circuit group as masterControl amorphous gate driver circuit and 2A-1 on-off circuit, composition is just like any in claims 1 to 3Grid described in one drives module; And
A amorphous gate driver circuit and A+2 amorphous grid in described second circuit group drive electricityRoad is as A+1 amorphous gate driver circuit conduct in controlled amorphous gate driver circuit, the first circuit groupMaster control amorphous gate driver circuit and 2A on-off circuit, composition is just like any in claims 1 to 3Grid described in one drives module, and described A is positive integer.
5. liquid crystal panel as claimed in claim 4, is characterized in that, each amorphous gate driver circuitAlso comprise: pulse signal input terminal, for return pulse signal; Input is set, opens letter for receivingNumber, so that amorphous gate driver circuit is in opening; Replacement input, for receiving reset signal,So that amorphous gate driver circuit is in closed condition; Wherein
In the first circuit group and second circuit group in circuit group separately, first amorphous gate driver circuitInput access initial setting up signal is set, the replacement input of A+1 amorphous gate driver circuit andThe output electrical connection of A+2 amorphous gate driver circuit, A+1 amorphous gate driver circuit defeatedGoing out end is electrically connected with the input that arranges of A+2 amorphous gate driver circuit.
6. liquid crystal panel as claimed in claim 4, is characterized in that, 2A-1 in described the first circuit groupIndividual amorphous gate driver circuit accesses the first clock pulse signal, 2A amorphous in described the first circuit groupGate driver circuit access second clock pulse signal, 2A-1 amorphous grid in described second circuit groupDrive circuit access the 3rd clock signal, in described second circuit group, 2A amorphous gate driver circuit connectsEnter the 4th clock pulse signal.
7. liquid crystal panel as claimed in claim 6, is characterized in that, described the first clock pulse signal,Second clock pulse signal, the 3rd clock pulse signal are identical with the cycle of the 4th clock pulse signal, and instituteState the single spin-echo of the first clock pulse signal and second clock pulse signal, described the 3rd clock pulse signalWith the single spin-echo of the 4th clock pulse signal, described the 3rd clock pulse signal betides described the first clockAfter pulse signal.
8. liquid crystal panel as claimed in claim 4, is characterized in that, described scan line is divided into alternatelySpaced first kind scan line and Equations of The Second Kind scan line, in described the first circuit group, amorphous grid drives electricityRoad is corresponding one by one with described first kind scan line, in described second circuit group amorphous gate driver circuit with described inEquations of The Second Kind scan line is corresponding one by one.
9. liquid crystal panel as claimed in claim 4, is characterized in that, described the first circuit group is arranged atOne side of described pixel cell group, described second circuit group is arranged at the opposite side of described pixel cell group.
10. liquid crystal panel as claimed in claim 4, is characterized in that, described the first circuit group with described inSecond circuit group is arranged at the same side of described pixel cell group.
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| CN103680388B (en) * | 2013-12-26 | 2015-11-11 | 深圳市华星光电技术有限公司 | For recoverable GOA circuit and the display device of flat pannel display |
| CN103730093B (en) * | 2013-12-26 | 2017-02-01 | 深圳市华星光电技术有限公司 | Array substrate drive circuit, array substrate and corresponding liquid crystal displayer |
| CN104332137B (en) | 2014-11-28 | 2016-11-16 | 京东方科技集团股份有限公司 | Gate driver circuit and display device |
| CN106960652B (en) * | 2017-04-21 | 2018-10-30 | 京东方科技集团股份有限公司 | Drive element of the grid, driving method, gate driving circuit and display device |
| CN109712550B (en) * | 2019-01-16 | 2022-03-15 | 上海思立微电子科技有限公司 | Grid driving circuit and area scanning method |
| CN110379390B (en) * | 2019-07-01 | 2022-01-04 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
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| KR20070076293A (en) * | 2006-01-18 | 2007-07-24 | 삼성전자주식회사 | Liquid crystal display and method of repairing the same |
| JP2009116214A (en) * | 2007-11-09 | 2009-05-28 | Epson Imaging Devices Corp | Liquid crystal panel and its manufacturing method |
| BRPI0822355A2 (en) * | 2008-03-19 | 2015-06-16 | Sharp Kk | Display panel excitation circuit, liquid crystal display device, shift register, liquid crystal panel, and display device excitation method. |
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| CN1145920C (en) * | 1995-03-06 | 2004-04-14 | 汤姆森多媒体公司 | Liquid crystal display driver with threshold voltage drift compensation |
| CN102224539A (en) * | 2008-12-10 | 2011-10-19 | 夏普株式会社 | Scanning signal line driving circuit, shift register, and method of driving shift register |
| CN101847377A (en) * | 2009-03-27 | 2010-09-29 | 北京京东方光电科技有限公司 | Gate drive device of liquid crystal display |
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