CN103268757A - Grid driving module of liquid crystal display panel and liquid crystal display panel - Google Patents
Grid driving module of liquid crystal display panel and liquid crystal display panel Download PDFInfo
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- CN103268757A CN103268757A CN2012102241944A CN201210224194A CN103268757A CN 103268757 A CN103268757 A CN 103268757A CN 2012102241944 A CN2012102241944 A CN 2012102241944A CN 201210224194 A CN201210224194 A CN 201210224194A CN 103268757 A CN103268757 A CN 103268757A
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Abstract
The invention provides a grid driving module of a liquid crystal display panel and the liquid crystal display panel, wherein the grid driving module comprises a main control amorphous grid driving circuit, controlled amorphous grid driving circuits and a switch circuit, a signal input end and a signal output end of the switch circuit are respectively connected with working state setting ends of the two controlled amorphous grid driving circuits, and a control input end of the switch circuit is connected with an output end of the main control amorphous grid driving circuit. The liquid crystal display panel and the gate drive module of the liquid crystal display panel fully utilize redundant charges to pre-charge the working state setting end of the amorphous gate drive circuit to be charged, and the pre-charged amorphous gate drive circuit can reduce the difference value of the charging voltage provided by the clock pulse signal when the subsequent clock pulse signal comes, so that the electric energy is saved, the overall power consumption of the gate drive module is further reduced, and the IC load of the output voltage of the clock pulse signal is reduced.
Description
Technical field
The present invention relates to the liquid crystal flat-panel display technique, relate in particular to a kind of display panels and grid thereof and drive module.
Background technology
With the TFT-LCD(liquid crystal display panel of thin film transistor) be the FPD(flat-panel display device of representative) technology begins to develop rapidly and progressively move to maturity from the nineties in 20th century.Because TFT-LCD has high-resolution, low-power consumption, frivolous, advantage such as be easy to carry, and has been widely used in above-mentioned information and has shown to have vast market prospect in the product.
In the prior art, the drive unit of display panels generally includes following module: time sequence control device, grid drive module, source electrode driving device, common electric voltage, power module and reference voltage several sections.Wherein, grid drives the signal that module is used for receiving time sequence control device, is the corresponding scanning line output signal output according to this signal cycle ground, thereby opens or closes sweep trace again and again, realizes scanning process with the control display panels.
Along with display panels is higher to integrated level, sharpness is better, response speed direction faster develops, original common IC circuit as grid driving module becomes increasingly complex, the area that grid driving module is occupied is increasing, the dwindling greatly of frame size of display panel limited, drive module so can not adapt to grid fully, that arise at the historic moment is amorphous gate driver circuit (Amorphous Silicon Gate Driver, ASG Driver), the amorphous gate driver circuit can form control one horizontal scanning line with unit independently, amorphous gate driver circuit even can compile scanning sequence according to process requirements, and, the amorphous gate driver circuit can be jointly by a supply lines or be divided into several groups of each supply lines of free one clock pulse signal is provided, thereby the size of rotating different supply lines can make entire area control that grid drives module in less range of size, and the response speed of amorphous gate driver circuit can effectively improve simultaneously.
Fig. 1 is the structural representation of display panels in the prior art, as shown in Figure 1, in the prior art, amorphous gate driver circuit 10 comprises a shift register circuit and two on-off circuits, shift register D flip-flop commonly wherein, an output terminal arranges end as the operating conditions of amorphous gate driver circuit 10 in the shift register circuit, as shown in Figure 1, when a clock pulse signal CK input, operating conditions arranges the output terminal Out that end Q just is sent to its logic state amorphous gate driver circuit 10, namely end Q is set when charging to high voltage when operating conditions, when a clock pulse signal input, the output terminal Out output HIGH voltage of described amorphous gate driver circuit 10.
Fig. 2 is the structural representation of display panels in the prior art, as shown in Figure 2, display panels 20 both sides are formed with some gate driver circuits, this gate driver circuit is amorphous gate driver circuit 10, each amorphous gate driver circuit 10 comprises: pulse signal input terminal CK, input end Set, replacement input end Reset and output terminal Out are set, described pulse signal input terminal CK is used for the received pulse signal; Input end Set is set to be used for making amorphous gate driver circuit 10 be in opening; Described replacement input end Reset is used for making amorphous gate driver circuit 10 be in Reset Status; Described output terminal Out is used for output signal output, and described amorphous gate driver circuit 10 comprises that also operating conditions arranges end Q, is used for its logic state is sent to the output terminal Out of amorphous gate driver circuit 10.Some amorphous gate driver circuits 10 provide clock pulse signal by the first clock signal C KL1 and second clock signal CKL2, the first clock signal C KL1 controls odd number amorphous gate driver circuit 10, be connected in the pulse signal input terminal CK of amorphous gate driver circuit 10 such as the first, the 3rd, the 5th, second clock signal CKL2 controls even number amorphous gate driver circuit 10, for example is connected in the pulse signal input terminal CK of amorphous gate driver circuit 10 such as the second, the 4th, the 6th.What initial setting up signal STP1 was connected in the first amorphous gate driver circuit 10 arranges input end Set, to control the unlatching of the first amorphous gate driver circuit 10, what the output terminal Out of last amorphous gate driver circuit 10 was connected in next amorphous gate driver circuit 10 arranges input end Set, to control the unlatching of this next amorphous gate driver circuit 10, and the output terminal Out of back one amorphous gate driver circuit 10 is connected in the replacement input end Reset of last amorphous gate driver circuit 10, to control closing of this last amorphous gate driver circuit 10, wherein the operating conditions of each amorphous gate driver circuit 10 arranges end not to be connected with other amorphous gate driver circuits 10.
Fig. 3 is the driving process sequential chart that grid drives module in the prior art, in conjunction with Fig. 1 ~ Fig. 3, some amorphous gate driver circuits 10 with display panels 20 left sides are example, the first clock signal C KL1 is identical with the cycle of second clock signal CKL2, phase phasic difference 180 degree, when initial signalization STP1 imports, the first amorphous gate driver circuit is opened, its operating conditions arranges end Q11 and begins charging, when the first clock signal C KL1 exports first pulse clock signal, Q11 output HIGH voltage, thereby the first amorphous gate driver circuit output signal output G11; During this output signal G11 output, the second amorphous gate driver circuit is opened, and its operating conditions arranges end Q12 and begins charging, when second clock signal CKL2 exports first pulse clock signal, Q12 output HIGH voltage, thereby the second amorphous gate driver circuit output signal output G12; During this output signal G12 output, first amorphous gate driver circuit is closed, its operating conditions arranges end Q11 and begins discharge, the 3rd amorphous gate driver circuit is opened, its operating conditions arranges end Q13 and begins charging, when second pulse clock signal of first clock signal C KL1 output, the Q13 output HIGH voltage, thereby the second amorphous gate driver circuit output signal output G13, during output signal G13 output, the second amorphous gate driver circuit is closed, its operating conditions arranges end Q12 and begins discharge, thereafter by that analogy, and the sweep trace that some amorphous gate driver circuits 10 in TFT-LCD panel 20 left sides and the some amorphous gate driver circuits 10 in its right side are controlled display panels 20 respectively, the control of the amorphous gate driver circuit by left side and right side realizes lining by line scan to sweep trace in the display panels 20.
Yet, as shown in Figure 3, the output signal G11 of the first amorphous gate driver circuit stop to export and the output signal G12 of the second amorphous gate driver circuit time period M between beginning to export in, the operating conditions of the first amorphous gate driver circuit arranges end Q11 and does not begin discharge, and the operating conditions of the 3rd amorphous gate driver circuit arrange the end Q13 also do not begin the charging, then the operating conditions of the first amorphous gate driver circuit arranges electric charge directly discharge after this time period M of end Q11 redundancy, the operating conditions of the 3rd amorphous gate driver circuit arranges end Q13 then needs directly to utilize coupled clock pulse signal to charge, equally for time period N, the operating conditions of the second amorphous gate driver circuit arranges end Q12 and does not begin discharge, and the operating conditions of the 4th amorphous gate driver circuit arrange the end Q14 do not begin the charging, electric charge directly discharge after this time period N of end Q12 redundancy then is set at the operating conditions of the second amorphous gate driver circuit, the operating conditions of the 4th amorphous gate driver circuit arranges end Q14 then needs directly to utilize coupled clock pulse signal to charge, thereby make in the prior art, in grid driving module, there is the electric charge of a lot of redundancies directly to be discharged, effectively do not utilize, thereby influence the overall power that grid drives module.
Summary of the invention
The grid that the purpose of this invention is to provide the lower display panels of a kind of power consumption drives module, and drives the display panels that module is combined to form by this grid.
For addressing the above problem, the grid that the invention provides a kind of display panels drives module, and described grid drives module and comprises master control amorphous gate driver circuit and controlled amorphous gate driver circuit; Also comprise on-off circuit, the signal input part of described on-off circuit and signal output part arrange the end connection respectively at the operating conditions of two controlled amorphous gate driver circuits, and the control input end of described on-off circuit is connected with the output terminal of described master control amorphous gate driver circuit.
Further, when master control amorphous gate driver circuit sends output signal, the on-off circuit conducting that is connected with described master control amorphous gate driver circuit, then the operating conditions by two continuous controlled amorphous gate driver circuits of described on-off circuit arranges the end conducting, makes the operating conditions of two controlled amorphous gate driver circuits that end transmission electric charge is set.
Further, in two controlled amorphous grid circuits that link to each other with on-off circuit, from the operating conditions of controlled amorphous grid circuit to be discharged end is set and to the operating conditions of controlled amorphous grid circuit to be charged end is set.
Further, described on-off circuit is thin film transistor (TFT); The source electrode of described thin film transistor (TFT) and drain electrode arrange end with the operating conditions of two described controlled amorphous gate driver circuits respectively and are connected, and the grid of described thin film transistor (TFT) is connected with the output terminal that master control amorphous grid drives electricity.
The present invention also provides a kind of liquid crystal panel, comprise pixel cell group and the sweep trace that is connected with pixel cell in the described pixel cell group, described liquid crystal panel also comprises some amorphous gate driver circuits and some on-off circuits, described amorphous gate driver circuit and described sweep trace connect one to one, described amorphous gate driver circuit is divided into first circuit bank and second circuit group, A amorphous gate driver circuit in wherein said first circuit bank and A+2 amorphous gate driver circuit are as controlled amorphous gate driver circuit, A amorphous gate driver circuit formed just like any described grid driving module in the claim 1 to 4 as master control amorphous gate driver circuit and 2A-1 on-off circuit in the second circuit group; And A amorphous gate driver circuit in the described second circuit group and A+2 amorphous gate driver circuit as A+1 amorphous gate driver circuit in controlled amorphous gate driver circuit, first circuit bank as master control amorphous gate driver circuit and 2A on-off circuit, composition drives module just like any described grid in the claim 1 to 4, and described A is positive integer.
Further, each amorphous gate driver circuit also comprises: pulse signal input terminal is used for the received pulse signal; Input end is set, is used for receiving start signal, so that the amorphous gate driver circuit is in opening; The replacement input end, be used for to receive reset signal, so that the amorphous gate driver circuit is in closed condition; Wherein in first circuit bank and second circuit group in separately the circuit bank, the input end that arranges of first amorphous gate driver circuit inserts the initial setting up signal, the replacement input end of A+1 amorphous gate driver circuit is electrically connected with the output terminal of A+2 amorphous gate driver circuit, and the output terminal of A+1 amorphous gate driver circuit is electrically connected with the input end that arranges of A+2 amorphous gate driver circuit.
Further, 2A-1 amorphous gate driver circuit inserts first clock pulse signal in described first circuit bank, 2A amorphous gate driver circuit inserts the second clock pulse signal in described first circuit bank, 2A-1 amorphous gate driver circuit inserts the 3rd clock signal in the described second circuit group, and 2A amorphous gate driver circuit inserts the 4th clock pulse signal in the described second circuit group.
Further, described first clock pulse signal, second clock pulse signal, the 3rd clock pulse signal are identical with the cycle of the 4th clock pulse signal, and the phase place of described first clock pulse signal and second clock pulse signal is opposite, the phase place of described the 3rd clock pulse signal and the 4th clock pulse signal is opposite, and described the 3rd clock pulse signal betides after described first clock pulse signal.
Further, described sweep trace is divided into first kind sweep trace and the second class sweep trace that alternate intervals is arranged, the amorphous gate driver circuit is corresponding one by one with described first kind sweep trace in described first circuit bank, and the amorphous gate driver circuit is corresponding one by one with described second sweep trace in the described second circuit group.
Further, described first circuit bank is arranged at a side of described pixel cell group, and described second circuit group is arranged at the opposite side of described pixel cell group.
Further, described first circuit bank and described second circuit group are arranged at the same side of described pixel cell group.
In sum, the grid of display panels of the present invention drives module, comprise master control amorphous gate driver circuit and controlled amorphous gate driver circuit and on-off circuit, the signal input part of described on-off circuit and signal output part arrange the end connection respectively at the operating conditions of two controlled amorphous gate driver circuits, and the control input end of described on-off circuit is connected with the output terminal of described master control amorphous gate driver circuit.Unlatching by master control amorphous gate driver circuit gauge tap circuit, on-off circuit is opened, then the operating conditions by two continuous controlled amorphous gate driver circuits of this on-off circuit arranges the end conducting, two operating conditions are arranged transmit electric charge between the end, thereby the operating conditions of controlled amorphous gate driver circuit that will be to be discharged arranges the operating conditions that the redundant electric charge of end partly passes to controlled amorphous gate driver circuit to be charged end is set, carried out precharge to utilize redundant electric charge that the operating conditions of controlled amorphous gate driver circuit to be charged is arranged end, amorphous gate driver circuit after the precharge comes interim at the subsequent clock pulse signal, can reduce to provide with clock pulse signal the difference of the voltage of charging, thereby saved electric energy, further reduce grid and driven the overall power of module, and reduced the IC load of clock pulse signal output voltage.
The present invention also provides a kind of display panels, this display panel is made up of some amorphous grid circuit driving circuits wherein, amorphous grid circuit driving circuit drives module by some grids and forms, further reduced the power consumption of whole liquid crystal display panel, reduced the IC load of clock pulse signal output voltage simultaneously, made display panels work more stable.
Description of drawings
Fig. 1 is the structural representation of display panels in the prior art.
Fig. 2 is the structural representation of display panels in the prior art.
Fig. 3 is the driving process sequential chart of the amorphous gate driver circuit of display panels in the prior art.
Fig. 4 is the structural representation that the grid in one embodiment of the invention drives module.
Fig. 5 is the structural representation of an amorphous gate driver circuit of display panels in one embodiment of the invention.
Fig. 6 is the structural representation of display panels in one embodiment of the invention.
Fig. 7 is the driving process sequential chart of the amorphous gate driver circuit of display panels in one embodiment of the invention.
Fig. 8 arranges the emulation sequential chart of end output signal for operating conditions in the amorphous gate driver circuit of display panels in one embodiment of the invention.
Fig. 9 is the emulation sequential chart of output terminal output signal in the amorphous gate driver circuit of display panels in one embodiment of the invention.
Figure 10 is the power emulation comparison diagram of display panels and prior art display panels in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes synoptic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, synoptic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 4 is the structural representation that the grid in one embodiment of the invention drives module.As shown in Figure 4, the invention provides a kind of described grid driving module and comprise master control amorphous gate driver circuit 13 and controlled amorphous gate driver circuit 11,12; Also comprise on-off circuit T, the signal input part of described on-off circuit T and signal output part are respectively at two controlled amorphous gate driver circuits 11,12 operating conditions arranges end Q and connects, the control input end of described on-off circuit T is connected with the output terminal Out of described master control amorphous gate driver circuit 13, when master control amorphous gate driver circuit 13 sends output signal, the on-off circuit conducting that is connected with described master control amorphous gate driver circuit 13, then by two continuous controlled amorphous gate driver circuits 11 of described on-off circuit, 12 operating conditions arranges the end conducting, make two controlled amorphous gate driver circuits 11,12 operating conditions arranges end and transmits electric charge, thereby the operating conditions of controlled amorphous gate driver circuit 11 that will be to be discharged arranges the operating conditions that the redundant electric charge of end partly passes to controlled amorphous gate driver circuit 12 to be charged end is set, carried out precharge to utilize redundant electric charge that the operating conditions of controlled amorphous gate driver circuit 12 to be charged is arranged end, amorphous gate driver circuit 12 after the precharge comes interim at the subsequent clock pulse signal, can reduce to provide with clock pulse signal the difference of the voltage of charging, further reduce grid and driven the overall power of module, and reduced the IC load of clock pulse signal output voltage.
Utilize above-mentioned grid to drive module, the present invention also provides a kind of liquid crystal panel, described liquid crystal panel also comprises some amorphous gate driver circuits and some on-off circuits, described amorphous gate driver circuit and described sweep trace connect one to one, described amorphous gate driver circuit is divided into first circuit bank and second circuit group, if A is arbitrary integer, particularly, A can from 1 to first circuit bank or the second circuit group any integer (common first circuit bank equates with the number of second circuit group) the number of amorphous gate driver circuit, A amorphous gate driver circuit in wherein said first circuit bank and A+2 amorphous gate driver circuit are as controlled amorphous gate driver circuit, A amorphous gate driver circuit formed a described grid and driven module as master control amorphous gate driver circuit and 2A-1 on-off circuit in the second circuit group; And A amorphous gate driver circuit in the described second circuit group and A+2 amorphous gate driver circuit, are formed a grid of the present invention and are driven module as master control amorphous gate driver circuit and 2A on-off circuit as A+1 amorphous gate driver circuit in controlled amorphous gate driver circuit, first circuit bank.
Fig. 5 is the structural representation of an amorphous gate driver circuit of display panels in one embodiment of the invention.As shown in Figure 5, in the present embodiment, each amorphous gate driver circuit also comprises: pulse signal input terminal CK is used for the received pulse signal; Input end Set is set, is used for receiving start signal, so that the amorphous gate driver circuit is in opening; Replacement input end Reset, be used for to receive reset signal, so that the amorphous gate driver circuit is in closed condition; Output terminal Out is used for output signal output; Operating conditions arranges end Q, and described operating conditions arranges end Q, and described operating conditions arranges the output terminal Out that end Q is used for its logic state is sent to amorphous gate driver circuit 10.In addition, VGH is the high level input end among Fig. 5, and VGL is the low level input end, and CKB be used for to insert and the anti-phase pulse of pulse signal input terminal CK signal all the time.
Wherein in first circuit bank and second circuit group in separately the circuit bank, the input end that arranges of first amorphous gate driver circuit inserts the initial setting up signal, the replacement input end of A+1 amorphous gate driver circuit is electrically connected with the output terminal of A+2 amorphous gate driver circuit, and the output terminal of A+1 amorphous gate driver circuit is electrically connected with the input end that arranges of A+2 amorphous gate driver circuit.
In the present embodiment, 2A-1 amorphous gate driver circuit inserts first clock pulse signal in described first circuit bank, 2A amorphous gate driver circuit inserts the second clock pulse signal in described first circuit bank, 2A-1 amorphous gate driver circuit inserts the 3rd clock signal in the described second circuit group, and 2A amorphous gate driver circuit inserts the 4th clock pulse signal in the described second circuit group.
Wherein, described first clock pulse signal, second clock pulse signal, the 3rd clock pulse signal are identical with the cycle of the 4th clock pulse signal, and the phase place of described first clock pulse signal and second clock pulse signal is opposite, the phase place of described the 3rd clock pulse signal and the 4th clock pulse signal is opposite, and described the 3rd clock pulse signal betides between described first clock pulse signal and the described second clock pulse signal and time of origin interlaces.
Described sweep trace and described amorphous gate driver circuit connect one to one, described sweep trace is divided into first kind sweep trace and the second class sweep trace that alternate intervals is arranged, the amorphous gate driver circuit is corresponding one by one with described first kind sweep trace in described first circuit bank, and the amorphous gate driver circuit is corresponding one by one with described second sweep trace in the described second circuit group.
Preferable, described first circuit bank and second circuit group can be arranged at the both sides of pixel cell group respectively, namely first circuit bank is arranged at a side of described pixel cell group, described second circuit group is arranged at the opposite side of described pixel cell group, so that the area of the amorphous gate driver circuit of average liquid crystal panel both sides frame.In addition, described first circuit bank and described second circuit group also are arranged at the same side of described pixel cell group.
Fig. 6 is the structural representation of display panels in one embodiment of the invention.For the clearer convenient grid of describing described display panels drives module, in conjunction with Fig. 6, below with display panels 20 both sides first circuit bank and second circuit group are set respectively, first circuit bank and second circuit group respectively have eight amorphous gate driver circuits, and described on-off circuit is divided into two on-off circuit groups, the first on-off circuit group has eight on-off circuit T11 ~ T18, it is example that the second switch circuit bank has eight on-off circuit T11 ~ T18, the structure that the grid that describes display panels of the present invention in detail drives module and driven the display panel that module forms by this grid, will be clear that, display panel of the present invention never only limits to structure, in the art production process of reality, the position of arranging of first circuit bank and second circuit group, the number of amorphous gate driver circuit in first circuit bank and the second circuit group, and the number of on-off circuit is not defined in the corresponding first on-off circuit group and the second switch circuit bank, all can specifically determine according to technological requirement.
In the present embodiment, described grid drives module and comprises some amorphous gate driver circuits 10 and on-off circuit group, in the present embodiment, described on-off circuit component is the first on-off circuit group T1 and second switch circuit bank T2, the first on-off circuit group T1 is all odd number on-off circuits in the described on-off circuit group, described second switch circuit bank T2 is all even number on-off circuits in the described on-off circuit group, namely establishing A is positive integer, 2A-1 on-off circuit is A on-off circuit among the first on-off circuit group T1, and 2A on-off circuit is A on-off circuit in the second switch circuit bank; Described amorphous gate driver circuit 10 connects one to one with the sweep trace of described display panels 20.Each amorphous gate driver circuit 10 comprises: pulse signal input terminal CK, and it is used for the received pulse signal; Input end Set is set, and it is used for receiving start signal, so that the amorphous gate driver circuit is in opening; Replacement input end Reset, it be used for to receive reset signal, so that the amorphous gate driver circuit is in closed condition; Output terminal Out, it is used for output signal output; And operating conditions arranges end Q, operating conditions arranges the output terminal Out that end Q is used for its logic state is sent to amorphous gate driver circuit 10, when operating conditions arranged end Q output HIGH voltage, its output terminal Out can be according to the control output HIGH voltage of clock pulse signal.
All amorphous gate driver circuits 10 are divided into first circuit bank and second circuit group, the sweep trace of display panels 20 is divided into first kind horizontal scanning line and the second class horizontal scanning line, first circuit bank and first kind horizontal scanning line connect one to one, and second circuit group and the second class horizontal scanning line connect one to one.
In preferred embodiment, first circuit bank and second circuit group are arranged at the left and right sides of described display panels 20 respectively, and described first kind horizontal scanning line and the second class horizontal scanning line interlaced alternative are arranged simultaneously.The first on-off circuit group and second switch circuit bank are respectively in the left and right sides of display panels 20 equally, above-mentioned is preferable structure, be convenient to the both sides frame size of uniform distribution display panels 20, for example first circuit bank and second circuit group are positioned at the same side for other, and first circuit bank control the first half sweep trace, the structure of second circuit group control later half sweep trace etc. is also within thought range of the present invention.
If A is positive integer, in first circuit bank and second circuit group in separately the circuit bank, the replacement input end of A amorphous gate driver circuit is electrically connected with the output terminal of A+1 amorphous gate driver circuit, the replacement input end Reset that is first amorphous gate driver circuit is electrically connected with the output terminal Out of second amorphous gate driver circuit, the replacement input end Reset of second amorphous gate driver circuit is electrically connected with the output terminal Out of the 3rd amorphous gate driver circuit, by that analogy.Therefore in first circuit bank and second circuit group in separately the circuit bank, the output signal of the output terminal of a back amorphous gate driver circuit is controlled closing of last amorphous gate driver circuit.
In first circuit bank and second circuit group in separately the circuit bank, the input end Set that arranges of first amorphous gate driver circuit inserts initial setting up signal STP, and the output terminal of A+1 amorphous gate driver circuit is electrically connected with the input end that arranges of A+2 amorphous gate driver circuit thereafter; Namely the input end Set that arranges of the first amorphous gate driver circuit inserts initial setting up signal STP, the output terminal Out of first amorphous gate driver circuit is electrically connected with the input end Set that arranges of second amorphous gate driver circuit, the output terminal Out of second amorphous gate driver circuit is electrically connected with the input end Set that arranges of the 3rd amorphous gate driver circuit, by that analogy.Therefore in first circuit bank and second circuit group in separately the circuit bank, the output signal of the output terminal Out of previous amorphous gate driver circuit is controlled the unlatching of next amorphous gate driver circuit.
The operating conditions of A amorphous gate driver circuit arranges end Q and the operating conditions of A+2 amorphous gate driver circuit and arranges and hold Q to link to each other with signal output part with the signal input part of A on-off circuit of the first on-off circuit group respectively in described first circuit bank, the control input end of A on-off circuit of the described first on-off circuit group is connected with the output terminal Out of A amorphous gate driver circuit in the second circuit group, and namely A on-off circuit of the described first on-off circuit group is by the output signal control opening and closing of A amorphous gate driver circuit in the second circuit group.
For example the operating conditions that the operating conditions of first amorphous gate driver circuit arranges the 3rd amorphous gate driver circuit in end Q11 and first circuit bank in first circuit bank arranges first on-off circuit T11 of end Q13 by the first on-off circuit group and links to each other, the control input end of first on-off circuit T11 of the described first on-off circuit group is connected with the output terminal Out of first amorphous gate driver circuit in the second circuit group, and namely first on-off circuit T11 of the first on-off circuit group is by the output signal G21 control opening and closing of first amorphous gate driver circuit in the second circuit group; The operating conditions that the operating conditions of second amorphous gate driver circuit arranges the 4th amorphous gate driver circuit in end Q12 and first circuit bank in first circuit bank arranges second the on-off circuit T12 of end Q14 by the first on-off circuit group and links to each other, the control input end of second on-off circuit T12 of the described first on-off circuit group is connected with the output terminal Out of second amorphous gate driver circuit in the second circuit group, namely second on-off circuit T12 of this first on-off circuit group controls opening and closing by the output signal G22 of second amorphous gate driver circuit in the second circuit group, thereafter and the like.
The operating conditions of A amorphous gate driver circuit arranges end Q and the operating conditions of A+2 amorphous gate driver circuit and arranges and hold Q to link to each other with signal output part with the signal input part of A on-off circuit of second switch circuit bank respectively in the described second circuit group, the control input end of A on-off circuit of described second switch circuit bank is connected with the output terminal of A+1 amorphous gate driver circuit in first circuit bank, and namely A on-off circuit of described second switch circuit bank is by the output signal control opening and closing of A+1 amorphous gate driver circuit in first circuit bank.
For example the operating conditions that the operating conditions of first amorphous gate driver circuit arranges the 3rd amorphous gate driver circuit in end Q21 and the second circuit group in the second circuit group arranges first on-off circuit T21 of end Q23 by the second switch circuit bank and links to each other, the control input end of first on-off circuit T21 of described second switch circuit bank is connected with the output terminal Out of second amorphous gate driver circuit in first circuit bank, and namely first on-off circuit T21 of second switch circuit bank is by the output signal G12 control opening and closing of second amorphous gate driver circuit in first circuit bank; The operating conditions that the operating conditions of second amorphous gate driver circuit arranges the 4th amorphous gate driver circuit in end Q22 and the second circuit group in the second circuit group arranges second the on-off circuit T22 of end Q24 by the second switch circuit bank and links to each other, the control input end of second on-off circuit T22 of described second switch circuit bank is connected with the output terminal Out of the 3rd amorphous gate driver circuit in first circuit bank, be that second on-off circuit T22 of second switch circuit bank is by the output signal G22 of the 3rd amorphous gate driver circuit in second circuit group control opening and closing, thereafter.
Hence one can see that, in the display panels, in first circuit bank in the first amorphous gate driver circuit and the second circuit group the last amorphous gate driver circuit, each amorphous gate driver circuit can be simultaneously as the master control amorphous gate driver circuit in the grid driving module, and as the controlled amorphous gate driver circuit in another amorphous grid driving module, thereby the output terminal of each amorphous gate driver circuit can be controlled the transfer that the operating conditions of two amorphous gate driver circuits in addition of corresponding connection arranges the electric charge between the end, and, operating conditions that should each amorphous gate driver circuit is arranged the transfer of electric charge that operating conditions that end can accept the amorphous gate driver circuit of other corresponding connections in the charging stage arranges the redundancy of end, the electric charge of self redundancy can be transferred to the amorphous gate driver circuit of other corresponding connections at discharge regime, its each amorphous gate driver circuit is connected implementation as shown in Figure 6 with the concrete of other amorphous gate driver circuits, thereby in first circuit bank the first amorphous gate driver circuit, the operating conditions of each amorphous gate driver circuit arranges end and at first carries out precharge, the amorphous gate driver circuit operating conditions to be discharged of another corresponding connection of receiving unit arranges the redundant electric charge of end, then the clock pulse signal at control amorphous gate driver circuit comes interim, the operating conditions that has reduced the amorphous gate driver circuit arranges end and clock pulse signal difference between the charging voltage is provided, thereby saved electric energy, further reduced the overall power of grid driving module, and reduced the IC load of clock pulse signal output voltage, and then reduced the power consumption of whole display panels.
Further, in the present embodiment, described on-off circuit T11 ~ T18 and on-off circuit T21 ~ T28 are Thin Film Transistor (TFT), the operating conditions of A amorphous gate driver circuit arranges end and the operating conditions of A+2 amorphous gate driver circuit and end is set links to each other with drain electrode with the source electrode of A thin film transistor (TFT) of the first on-off circuit group respectively in described first circuit bank, and the grid of A thin film transistor (TFT) of the described first on-off circuit group is electrically connected with the output terminal of A amorphous gate driver circuit in the second circuit group; Namely the operating conditions of first amorphous gate driver circuit arranges end Q11 and the operating conditions of the 3rd amorphous gate driver circuit and end Q13 is set respectively with the source electrode of first thin film transistor (TFT) T11 of the first on-off circuit group with drain and link to each other in first circuit bank, the output terminal Out of first amorphous gate driver circuit is electrical connected in the grid of first thin film transistor (TFT) T11 of the described first on-off circuit group and the second circuit group, and the unlatching of first thin film transistor (TFT) T11 of the described first on-off circuit group is controlled by the output of the output terminal Out of first amorphous gate driver circuit in the second circuit group; The operating conditions of second amorphous gate driver circuit arranges end Q12 and the operating conditions of the 4th amorphous gate driver circuit and end Q14 is set respectively with the source electrode of second thin film transistor (TFT) T12 of the first on-off circuit group with drain and link to each other in first circuit bank, the output terminal Out of second amorphous gate driver circuit is electrical connected in the grid of second thin film transistor (TFT) T12 of the described first on-off circuit group and the second circuit group, the unlatching of second thin film transistor (TFT) T12 of the described first on-off circuit group is controlled by the output signal G22 of the output terminal Out of second amorphous gate driver circuit in the second circuit group, and the rest may be inferred thereafter.
The operating conditions of A amorphous gate driver circuit arranges end and the operating conditions of A+2 amorphous gate driver circuit and end is set links to each other with drain electrode with the source electrode of A thin film transistor (TFT) of second switch circuit bank respectively in the described second circuit group, and the grid of A thin film transistor (TFT) of described second switch circuit bank is electrical connected by the output terminal of A+1 amorphous gate driver circuit of first circuit bank; Be that operating conditions that the operating conditions of first amorphous gate driver circuit in the second circuit group arranges the 3rd amorphous gate driver circuit in end Q21 and the second circuit group arranges end Q23 respectively with the source electrode of first thin film transistor (TFT) T21 of second switch circuit bank with drain and link to each other, the output terminal Out of second amorphous gate driver circuit is electrical connected in the grid of first thin film transistor (TFT) T21 of the described first on-off circuit group and first circuit bank, and the unlatching of first thin film transistor (TFT) T21 of described second switch circuit bank is controlled by the output signal G12 of the output terminal Out of second amorphous gate driver circuit in first circuit bank; The operating conditions that the operating conditions of second amorphous gate driver circuit arranges the 4th amorphous gate driver circuit in end Q22 and the second circuit group in the second circuit group arranges end Q24 respectively with the source electrode of second thin film transistor (TFT) T22 of second switch circuit bank with drain and link to each other, the output terminal Out of the 3rd amorphous gate driver circuit is electrical connected in the grid of second thin film transistor (TFT) T22 of the described first on-off circuit group and first circuit bank, and the unlatching of first thin film transistor (TFT) T22 of described second switch circuit bank is controlled by the output signal G13 of the output terminal Out of the 3rd amorphous gate driver circuit in first circuit bank; Thereafter, the rest may be inferred.
Odd number amorphous gate driver circuit receives the first clock pulse signal CKL1 in described first circuit bank, namely the first clock signal C KL1 controls the odd number amorphous gate driver circuit of first circuit bank, i.e. the pulse signal input terminal CK of amorphous gate driver circuit such as the first, the 3rd, the 5th in first circuit bank; Even number amorphous gate driver circuit receives second clock pulse signal CKL2 in described first circuit bank, i.e. the pulse signal input terminal CK of amorphous gate driver circuit such as the second, the 4th, the 6th in first circuit bank; Odd number amorphous gate driver circuit receives the 3rd clock pulse signal CKR2 in the described second circuit group, i.e. the pulse signal input terminal CK of amorphous gate driver circuit such as the first, the 3rd, the 5th in the second circuit group; Even number amorphous gate driver circuit receives the 4th clock pulse signal CKR2 in described the 4th class amorphous gate driver circuit, i.e. the pulse signal input terminal CK of amorphous gate driver circuit such as the second, the 4th, the 6th in the second circuit group.
Fig. 7 is the driving process sequential chart of the amorphous gate driver circuit of display panels in one embodiment of the invention.As shown in Figure 7, the described first clock pulse signal CKL1, second clock pulse signal CKL2, the 3rd clock pulse signal CKR1 are identical with the frequency of the 4th clock pulse signal CKR2, the phase place of the described first clock pulse signal CKL1 and second clock pulse signal CKL2 is opposite, the phase place of described the 3rd clock pulse signal CKR1 and the 4th clock pulse signal CKR2 is opposite, and described the 3rd clock pulse signal CKR1 betides between the described first clock pulse signal CKL1 and the described second clock pulse signal CKL2 and time of origin interlaces.And odd number amorphous gate driver circuit is identical with the phase place of described first clock pulse signal in described first circuit bank, even number amorphous gate driver circuit is identical with the phase place of described second clock pulse signal in described first circuit bank, odd number amorphous gate driver circuit is identical with the phase place of described the 3rd clock pulse signal in the described second circuit group, and even number amorphous gate driver circuit is identical with the phase place of described the 4th clock pulse signal in the described second circuit group.
When a certain clock pulse signal takes place among first to fourth clock pulse signal CKL1, CKL2, CKR1 and the CKR2, the amorphous gate driver circuit that links to each other with its clock pulse signal and be in opening sends output signal, make the on-off circuit conducting of the output terminal control that is subjected to its amorphous gate driver circuit, then the operating conditions by two continuous amorphous gate driver circuits of described on-off circuit arranges the end conducting, makes two operating conditions that end is set and transmits energy from high voltage to low-voltage.
In conjunction with Fig. 7, first initial setting up signal STP1 opens, the operating conditions of first amorphous gate driver circuit arranges and holds Q11 to begin to charge in the first kind, when first clock pulse signal CKL1 output pulse signal, the operating conditions of first amorphous gate driver circuit arranges end Q11 output HIGH voltage, the output signal G11 output HIGH voltage of first amorphous gate driver circuit in the first kind in the first kind; Stopping back second initial setting up signal STP2 in first initial setting up signal STP1 output pulse opens, the operating conditions of first amorphous gate driver circuit arranges and holds Q21 to begin charging in second class, when the 3rd clock pulse signal CKR1 output pulse signal, the operating conditions of first amorphous gate driver circuit arranges end Q21 output HIGH voltage in the first kind, the output signal G21 output HIGH voltage of first amorphous gate driver circuit in second class, this output signal G21 namely opens first on-off circuit T11 in the first on-off circuit group simultaneously, then the operating conditions of first amorphous gate driver circuit arranges the operating conditions of holding the 3rd amorphous gate driver circuit in Q11 and the first kind end Q13 conducting is set in the first kind, this moment then in the first kind operating conditions of first amorphous gate driver circuit the operating conditions that voltage among the end Q11 namely fills into the 3rd amorphous gate driver circuit in the first kind be set arrange among the end Q13, the operating conditions of both having realized the 3rd amorphous gate driver circuit arranges the charging in advance of end Q13, and the charge transfer that the operating conditions of first amorphous gate driver circuit in the first kind can be arranged end Q11 redundancy operating conditions of the 3rd amorphous gate driver circuit to the first kind arranges among the end Q13; Follow second clock pulse signal CKL2 output pulse signal, the operating conditions of second amorphous gate driver circuit arranges end Q12 output HIGH voltage in the described first kind, the output signal Q12 of second amorphous gate driver circuit in the first kind then, this output signal Q12 opens first on-off circuit T21 in the second switch circuit bank, then the operating conditions of first amorphous gate driver circuit arranges the operating conditions of holding the 3rd amorphous gate driver circuit in Q21 and second class end Q23 conducting is set in second class, this moment then, thus the overall power that grid drives module further lowered.
Fig. 8 arranges the emulation sequential chart of end output signal for operating conditions in the amorphous gate driver circuit of display panels in one embodiment of the invention.Fig. 9 is the emulation sequential chart of output terminal output signal in the amorphous gate driver circuit of display panels in one embodiment of the invention, be the convenient clear inventive concept of expressing, the operating conditions that Fig. 9 and Figure 10 have advanced to enumerate the first amorphous gate driver circuit to the, six amorphous gate driver circuits in the first amorphous gate driver circuit to the, six amorphous gate driver circuits in first circuit bank and the second circuit group arranges end Q11 ~ Q16, Q21 ~ Q26 and output terminal output signal G11 ~ G16, the emulation sequential chart of G21 ~ G26, each amorphous gate driver circuit is thereafter exported corresponding pulse signal according to same this sequential certainly.In conjunction with Fig. 4, Fig. 9 and Figure 10 can see, adopt the present invention's display panels as shown in Figure 4 in the actual scanning process, output signal G11 ~ the G16 of the output terminal output of each amorphous gate driver circuit, the sequential chart of G21 ~ G26 meets the sweep signal requirement, and signal problem, not producing signal mutually disturbs, and the operating conditions of amorphous gate driver circuit arranges end Q11 ~ Q13, Q21 ~ Q23 gives thereafter successively, and the operating conditions of second amorphous gate driver circuit arranges end Q13 ~ Q16, Q23 ~ Q26 has carried out precharge, it is interim that thereby the gate driver circuit after the precharge comes at the subsequent clock pulse signal, can reduce to provide with clock pulse signal the difference of the voltage of charging, thereby saved electric energy, further reduce grid and driven the overall power of module, and reduced the IC load of clock pulse signal output voltage.
Figure 10 is the power emulation comparison diagram of display panels and prior art display panels in one embodiment of the invention.As 10 for the display panels of prior art shown in Figure 2 being carried out overall power that emulation obtains and the comparison diagram that the display panels in one embodiment of the invention among Fig. 4 is carried out the overall power that emulation obtains, each display panels comprises 20 amorphous gate driver circuits, wherein power points 100 is the simulation result of overall power of the display panels of prior art, power points 200 is the simulation architecture of the overall power of the display panels in one embodiment of the invention, the overall power of the display panels of the prior art is 162.7 μ W as can be known, the overall power of display panels of the present invention is 156.5 μ W, so display panels of the present invention is than prior art, it effectively reduces the overall power that grid drives module.
Certainly, display panels of the present invention is not limited only to be made up of first kind circuit bank and the second class circuit bank, can also be made up of the circuit bank that is divided three classes or the circuit bank that is divided into four classes etc. etc.; And first circuit and second circuit group are not limited to have respectively two clock pulse signal controls, can also there be three, four or six s' etc. clock pulse signal to control amorphous gate driver circuit in each circuit bank respectively, then the annexation that input end, replacement input end are set between the amorphous gate driver circuit also can be adjusted accordingly, therefore change that can other structures, the circuit bank structure that scans with the amorphous gate driver circuit of realizing each circuit bank output signal output driven sweep line successively is all within thought range of the present invention.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. the grid of a display panels drives module, it is characterized in that, described grid drives module and comprises master control amorphous gate driver circuit and controlled amorphous gate driver circuit; Also comprise on-off circuit,
The signal input part of described on-off circuit and signal output part arrange end with the operating conditions of two controlled amorphous gate driver circuits respectively and are connected, and the control input end of described on-off circuit is connected with the output terminal of described master control amorphous gate driver circuit.
2. the grid of display panels as claimed in claim 1 drives module, it is characterized in that, when master control amorphous gate driver circuit sends output signal, the on-off circuit conducting that is connected with described master control amorphous gate driver circuit, then the operating conditions by two continuous controlled amorphous gate driver circuits of described on-off circuit arranges the end conducting, makes the operating conditions of two controlled amorphous gate driver circuits that end transmission electric charge is set.
3. the grid of display panels as claimed in claim 1 drives module, it is characterized in that, in two controlled amorphous grid circuits that link to each other with on-off circuit, from the operating conditions of controlled amorphous grid circuit to be discharged end is set and to the operating conditions of controlled amorphous grid circuit to be charged end is set.
4. the grid as any described display panels in the claim 1 to 3 drives module, it is characterized in that described on-off circuit is thin film transistor (TFT); The source electrode of described thin film transistor (TFT) and drain electrode arrange end with the operating conditions of two described controlled amorphous gate driver circuits respectively and are connected, and the grid of described thin film transistor (TFT) is connected with the output terminal that master control amorphous grid drives electricity.
5. liquid crystal panel, comprise pixel cell group and the sweep trace that is connected with pixel cell in the described pixel cell group, it is characterized in that, described liquid crystal panel also comprises some amorphous gate driver circuits and some on-off circuits, described amorphous gate driver circuit and described sweep trace connect one to one, described amorphous gate driver circuit is divided into first circuit bank and second circuit group, wherein
A amorphous gate driver circuit in described first circuit bank and A+2 amorphous gate driver circuit, are formed just like any described grid in the claim 1 to 4 and are driven module as master control amorphous gate driver circuit and 2A-1 on-off circuit as A amorphous gate driver circuit in controlled amorphous gate driver circuit, the second circuit group; And
A amorphous gate driver circuit in the described second circuit group and A+2 amorphous gate driver circuit as A+1 amorphous gate driver circuit in controlled amorphous gate driver circuit, first circuit bank as master control amorphous gate driver circuit and 2A on-off circuit, composition drives module just like any described grid in the claim 1 to 4, and described A is positive integer.
6. liquid crystal panel as claimed in claim 5 is characterized in that, each amorphous gate driver circuit also comprises: pulse signal input terminal is used for the received pulse signal; Input end is set, is used for receiving start signal, so that the amorphous gate driver circuit is in opening; The replacement input end, be used for to receive reset signal, so that the amorphous gate driver circuit is in closed condition; Wherein
In first circuit bank and second circuit group in separately the circuit bank, the input end that arranges of first amorphous gate driver circuit inserts the initial setting up signal, the replacement input end of A+1 amorphous gate driver circuit is electrically connected with the output terminal of A+2 amorphous gate driver circuit, and the output terminal of A+1 amorphous gate driver circuit is electrically connected with the input end that arranges of A+2 amorphous gate driver circuit.
7. liquid crystal panel as claimed in claim 5, it is characterized in that, 2A-1 amorphous gate driver circuit inserts first clock pulse signal in described first circuit bank, 2A amorphous gate driver circuit inserts the second clock pulse signal in described first circuit bank, 2A-1 amorphous gate driver circuit inserts the 3rd clock signal in the described second circuit group, and 2A amorphous gate driver circuit inserts the 4th clock pulse signal in the described second circuit group.
8. display panels as claimed in claim 7, it is characterized in that, described first clock pulse signal, second clock pulse signal, the 3rd clock pulse signal are identical with the cycle of the 4th clock pulse signal, and the phase place of described first clock pulse signal and second clock pulse signal is opposite, the phase place of described the 3rd clock pulse signal and the 4th clock pulse signal is opposite, and described the 3rd clock pulse signal betides after described first clock pulse signal.
9. liquid crystal panel as claimed in claim 5, it is characterized in that, described sweep trace is divided into first kind sweep trace and the second class sweep trace that alternate intervals is arranged, the amorphous gate driver circuit is corresponding one by one with described first kind sweep trace in described first circuit bank, and the amorphous gate driver circuit is corresponding one by one with described second sweep trace in the described second circuit group.
10. as any described liquid crystal panel in the claim 5 to 9, it is characterized in that described first circuit bank is arranged at a side of described pixel cell group, described second circuit group is arranged at the opposite side of described pixel cell group.
11., it is characterized in that described first circuit bank and described second circuit group are arranged at the same side of described pixel cell group as any described liquid crystal panel in the claim 5 to 9.
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