CN109712550A - A kind of gate driving circuit and sector scanning method - Google Patents
A kind of gate driving circuit and sector scanning method Download PDFInfo
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- CN109712550A CN109712550A CN201910041768.6A CN201910041768A CN109712550A CN 109712550 A CN109712550 A CN 109712550A CN 201910041768 A CN201910041768 A CN 201910041768A CN 109712550 A CN109712550 A CN 109712550A
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Abstract
It includes N+1 grades of shift register cells that the purpose of the application, which is to provide a kind of gate driving circuit and sector scanning method, area of grid circuit,；Each shift register cell includes primary transistor, the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor, reset transistor and lower trombone slide；The grid of the first transistor is used to receive the output signal of next stage shift register cell feedback to control the control signal of grid；The drain electrode of source electrode and the first transistor of primary transistor, the drain electrode of second transistor, the grid of third transistor and lower trombone slide grid be intersected in bootstrap point；The drain electrode of the reset transistor connects input signal, and grid is controlled by reset signal, the source electrode of the reset transistor, the grid of the second transistor, the drain electrode of the lower trombone slide and the 5th transistor grid be intersected in level drop-down control node.It is overlapping to avoid gate output signal from occurring, and chip area can be reduced.
Description
Technical field
This application involves fingerprint identification technology field more particularly to a kind of gate driving circuit and sector scanning methods.
Background technique
Amorphous silicon gate driving (Amorphous Silicon Gate Driver, ASG) technology, which refers to, utilizes A-SiTFT
(Amorphous Silicon Thin Film Transistor, amorphous silicon film transistor) constitutes shift-register circuit,
High pressure or low voltage gate signal are exported to drive or turn off thin film transistor (TFT) (TFT).Shift-register circuit includes N+1 in total
A shift register cell (can abbreviation SR), each a SR i.e. ASG unit, the N is positive integer.Due to each ASG circuit
It can be formed by the A-SiTFT in display panel, and the cost of A-SiTFT is low, therefore ASG can be used in fingerprint recognition replacing
Gate IC makees driving circuit, saves area.
Currently, common ASG circuit is as shown in Figure 1, but due to the variation with temperature and time, the threshold value meeting of TFT pipe
Change drift, so need first to reset bootstrap point Q and output signal Gn in all ASG modules before each upper electric drive
It is reused after dragging down, two reset transistors will lead to chip area increase；And existing clock signal timing will lead to the grid of ASG
Output signal is overlapping, influences each other.For Fig. 2 using 9T2C structure, but in this configuration, resetting operation can not be to Q
Point carries out initial state reset, belongs to hanging floating state, may subsequent give be drawn high process to P after pumping signal and be liquidated
It influences.
Summary of the invention
The purpose of the application is to provide a kind of gate driving circuit and sector scanning method, solves grid in the prior art
Internal node has hanging shape when output signal generation in pole overlaps, existing reset mode causes chip area big and reset state
State, may on it is subsequent give after pumping signal on bootstrap point draw high process liquidate influence the problem of.
According to the one aspect of the application, a kind of gate driving circuit is provided, which includes N+1 grades of shiftings
Bit register unit, wherein N is positive integer；
Each shift register cell includes primary transistor, the first transistor, second transistor, third transistor, the 4th
Transistor, the 5th transistor, reset transistor and lower trombone slide；
The grid of primary transistor is for receiving pumping signal；
The grid of the first transistor is used to receive the output signal of next stage shift register cell feedback to control grid
Control signal；
The drain electrode of source electrode and the first transistor of primary transistor, the drain electrode of second transistor, third transistor grid
And the grid of lower trombone slide is intersected in bootstrap point；
The output of the source electrode of third transistor, the drain electrode of the 4th transistor and the drain electrode of the 5th transistor and shift register
Signal connection；
For receiving input signal, grid is controlled by reset signal for the drain electrode of the reset transistor, the source electrode of the reset transistor,
The grid of the grid of the second transistor, the drain electrode of the lower trombone slide and the 5th transistor is intersected in level drop-down control
Node；
The drain electrode of third transistor receives the first clock signal, and the grid of the 4th transistor receives second clock signal, the
One clock signal is opposite each other with second clock signal and does not overlap further, the drain electrode connection first of the primary transistor
The source electrode of level signal, the first transistor connects second electrical level signal, the electricity of the first level signal and second electrical level signal
Position is opposite.
Further, each shift register cell includes first capacitor and the second capacitor, the two-plate of the first capacitor
It is separately connected the output signal of bootstrap point and shift register, the two-plate of second capacitor is separately connected the first clock signal
Control node is pulled down with the level.
Further, the source electrode of the second transistor connects low level signal, the source electrode of the 4th transistor and institute
The source electrode connection low level signal of the 5th transistor is stated, the source electrode of the lower trombone slide connects low level signal.
Further, the first clock signal and second clock signal and idol that the shift register cell of odd level is connected
The first clock signal and second clock signal that the shift register cell of several levels is connected are opposite each other and do not overlap.
Further, the shift register cell of the output signal of the shift register cell of upper level as next stage
Pumping signal, the output signal of the shift register cell of next stage is as first crystal in the shift register cell of upper level
The control signal of the grid of pipe.
Further, the drain electrode of the reset transistor connects input signal, and the input signal is in the first of clock signal
Quarter is raised, and is pulled low at the second moment.
According to the application another aspect, a kind of sector scanning side using the aforementioned gate driving circuit is provided
Method, this method comprises:
Specified region unit is selected from multiple blocks being made of gate driving circuit based on the fingerprint triggering information detected,
Wherein, in the specified region unit each piece include N+1 grades of shift register cells；
High level is set by the pumping signal of the shift register cell in the specified region, the displacement in rest block
The pumping signal of register cell keeps receiving low level.
Compared with prior art, the area of grid circuit of the application includes N+1 grades of shift register cells；Each shift LD
Device unit include primary transistor, the first transistor, second transistor, third transistor, the 4th transistor, the 5th transistor,
Reset transistor and lower trombone slide point；The grid of primary transistor is for receiving pumping signal；Under the grid of the first transistor is for receiving
The output signal of level-one shift register cell feedback is to control grid control signal；The source electrode and first crystal of primary transistor
The drain electrode of pipe, the drain electrode of second transistor, the grid of third transistor and lower trombone slide grid be intersected in bootstrap point；Third is brilliant
The connection of the output signal of the source electrode of body pipe, the drain electrode of the 4th transistor and the drain electrode of the 5th transistor and shift register；It is described
The drain electrode of reset transistor connects input signal, grid is controlled by reset signal, the source electrode of the reset transistor, the second transistor
The grid of grid, the drain electrode of the lower trombone slide and the 5th transistor is intersected in level drop-down control node；Third crystal
The drain electrode of pipe receives the first clock signal, and the grid of the 4th transistor receives second clock signal, the first clock signal and second
Clock signal is opposite each other and does not overlap.It is overlapping to avoid gate output signal from occurring, and chip area can be reduced, and make
New reset mode is provided with a reset transistor, avoids level drop-down control node when carrying out initial state reset in hanging shape
State, may on it is subsequent give after pumping signal on bootstrap point draw high process liquidate influence the problem of.
Further, gate driving circuit described herein can operate in sector scanning, by based on detecting
Fingerprint triggering information selects specified region unit from multiple blocks being made of gate driving circuit, wherein the specified region unit
In each piece include N+1 grades of shift registers；It sets the pumping signal of the shift register cell in the specified region to
High level, the pumping signal of the shift register cell in rest block keep receiving low level.To realize sector scanning, save
Power consumption and time.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, the application's is other
Feature, objects and advantages will become more apparent upon:
Fig. 1 shows a kind of ASG structural schematic diagram in the prior art；
Fig. 2 shows the ASG structural schematic diagrams of the 9T2C structure used in the prior art；
Fig. 3 shows a kind of grid electrode drive circuit structure schematic diagram provided according to the one aspect of the application；
Fig. 4 shows the block schematic illustration for the gate driving circuit that multi-stage shift register forms in one embodiment of the application；
Fig. 5 shows improved ASG timing diagram in one embodiment of the application；
Fig. 6 shows the schematic diagram that sector scanning is realized using ASG.
The same or similar appended drawing reference represents the same or similar component in attached drawing.
Specific embodiment
The application is described in further detail with reference to the accompanying drawing.
Fig. 3 shows a kind of grid electrode drive circuit structure schematic diagram provided according to the one aspect of the application, which drives
Dynamic circuit includes N+1 grades of shift register cells, wherein N is positive integer；Each shift register cell includes primary transistor
T0, the first transistor T1, second transistor T2, third transistor T3, the 4th transistor T4, the 5th transistor T5, reset transistor T6
And lower trombone slide T7；The grid of primary transistor T0 is for receiving pumping signal；The grid of the first transistor T1 is next for receiving
The output signal of grade shift register cell feedback is to control the control signal of grid；The source electrode of primary transistor T0 and the first crystalline substance
The drain electrode of body pipe T1, the drain electrode of second transistor T2, the grid of third transistor T3 and lower trombone slide T7 grid be intersected in from
Lift point；The source electrode of third transistor T3, the drain electrode of the 4th transistor T4 and the drain electrode of the 5th transistor T5 and shift register
Output signal connection；The drain electrode of third transistor T3 receives the first clock signal (CKB), and the grid of the 4th transistor T4 receives the
Two clock signals (CK), the first clock signal CKB is opposite each other with second clock signal CK and does not overlap；The leakage of the reset transistor
For receiving input signal, grid is controlled by reset signal for pole.Here, the initial transistor used, the first transistor are to the 5th
Transistor, reset transistor, lower trombone slide are TFT, and TFT uses Nmos pipe die formula, and high level end is the drain terminal of TFT, low level end
For source.It include T0, T1 ... T5 and T6, T7, the source of primary transistor T0 for each shift register ASG unit
Drain electrode, the grid of third transistor T3 and the grid of lower trombone slide T7 of pole and second transistor T2 are intersected in bootstrap point PU.Institute
State the source electrode of reset transistor T6, the grid of the second transistor T2, the drain electrode of the lower trombone slide T7 and the 5th transistor T5
Grid be intersected in level drop-down control node PD.The drain electrode of the primary transistor T0 is for receiving the first level signal
The source electrode of DIR1, the first transistor T1 are for receiving second electrical level signal DIR2, the electricity of the first level signal DIR1 and second
The current potential of ordinary mail DIR2 is opposite.Here, the first level signal DIR1 can be low level signal or high level signal, work as DIR1
When for low level signal, DIR2 is high level signal, and when DIR1 is high level signal, DIR2 is low level signal.To keep away
Exempt from gate output signal to occur to overlap, and chip area can be reduced, and provide new reset mode using a reset transistor, keeps away
Level drop-down control node is exempted from when carrying out initial state reset in vacant state, may give after pumping signal to subsequent to oneself
It lifts point and draws high process and liquidate the problem of influencing.
With continued reference to Fig. 3, each shift register cell includes first capacitor C1 and the second capacitor C2, the first capacitor C1
Two-plate be separately connected the output signal Gn of bootstrap point PU and shift register, the two-plate of the second capacitor C2 connects respectively
Meet the first clock signal CKB and level drop-down control node PD.Here, it is certainly that capacitor C1 two-plate, which is separately connected PU and Gn,
Act effect, capacitor C2 two-plate are separately connected CKB and PD, can draw high PD when CKB is drawn high as a capacitive coupling.
In one embodiment of the application, for ASG unit, the drain electrode of DIR1 connection T0, grid connects pumping signal STP,
Source electrode is PU；The drain electrode of T1 is PU, and next stage output signal Gn+1 feeds back the grid control signal as T1, source electrode connection
DIR2；T2 drain electrode is PU, and grid PD, source electrode is low level (VGL)；T3 drain electrode is CKB, and grid is controlled by PU, and source electrode is defeated
Signal Gn out；T4 drain electrode is Gn, grid subject clock signal CK control, source electrode VGL；T5 drain electrode is Gn, and grid is by PD control, source
Extremely VGL；T6 is initial state reset transistor, is drained as input signal VGX, and grid is controlled by reset signal (reset), source electrode PD；
T7 is lower trombone slide, is drained as PD, grid PU, source electrode VGL.
In one embodiment of the application, the first clock signal that the shift register cell of odd level is connected and when second
Clock signal is opposite each other with the first clock signal and second clock signal that the shift register cell of even level is connected and not
It is overlapping.The block schematic illustration of the gate driving circuit of multi-stage shift register composition as shown in Figure 4, the shift LD of upper level
Pumping signal of the output signal of device unit as the shift register cell of next stage, the shift register cell of next stage
Control signal of the output signal as the grid of the first transistor in the shift register cell of upper level.Here, first order ASG
STP port input whole system pumping signal STP, CK input system clock CK, CKB output system clock CKB, Gn output
First order output signal G1, Gn+1 connection second level output signal G2；The STP port input first order output letter of second level ASG
It number motivates, CK input system clock CKB, CKB output system clock CK, Gn export the first order output signal G2, Gn+1 connection
Third level output signal G3；And so on, and the clock signal CK and CKB of odd level and even level are opposite, odd level CK
Port connects CK, and the port CKB connects CKB；The port even level CK connects CKB, and the port CKB connects CK.In addition all grades of ends reset
Mouth all inputs RESET signal, and the port VGX all inputs VGX signal.Effective ASG unit has N number of in total, last additional level-one ASG
Unit is dummy, and STP inputs Gn signal, Gn+1 input system STP signal, and the output of Gn+1 is invalid output.In general, DIR1
Connect high level VGH, DIR2 connection low level VGL；If desired gate output signal is reversely generated, DIR1 can be connected to low electricity
Flat VGL, DIR2 connection high level VGH can since STP is connected to the grid of the T0 and dummy grades of afterbody of T1 of the first order
To complete slave dummy grades of shift register output of the similar grade from the first order to dummy to the reversed output process of the first order.
In one embodiment of the application, the drain electrode of the reset transistor T6 connects input signal, and the input signal is in clock
First moment of signal is raised, and is pulled low at the second moment.The source electrode of the second transistor T2 connects low level signal, institute
It states the source electrode of the 4th transistor T4 and the source electrode of the 5th transistor T5 connect low level signal, the source electrode of the lower trombone slide T7
Connect low level signal.Improved ASG timing diagram as shown in Figure 5, Reset is raised when initial state, T6 conducting, the level of VGX
PD point can be transferred to；At the t1 moment, VGX starts to be raised, and PD is also raised at this time, and PD level, which is drawn high, causes T2 and T5 to lead
It is logical, PU and Gn are connected with VGL, complete to reset PU and Gn；T2 moment VGX is pulled low, and state is drawn high in Reset holding, at this time
PD is pulled low, and t3 moment reset is pulled low, and completes to reset overall process.T4 moment input high level STP excitation, PU is drawn high, this
When T3 pipe be connected, while T7 grid is set to high level, and PD is pulled down to VGL, keeps PU high level that PD can be made not drag down T2
And T5, to will not have an impact to PU and Gn；The end-of-pulsing of t5 moment STP, but C1 capacitor is able to maintain the height electricity of PU
It is flat to make T3 constant conduction；T6 moment CKB is raised, and output Gn is raised, and due to capacitance characteristic, PU is raised (bootstrapping), PU by C1
It is drawn high again and T3 is enabled to be applied higher grid voltage, draw high Gn quickly.Between the t6-t7 moment, G1 output is given to the
On second level STP, the PU of second level ASG is drawn high by the T0 of the second level, and high level can be kept by C1 after G1 is pulled low
Current potential.T7 moment, CKB are pulled low, and Gn is in low level；Using dislocation clock, t8 moment CK is raised, and there are three effects at this time
Fruit: 1) T4 is switched in first order ASG, and G1 is pulled low；2) G2 that draws high feeds back to first order ASG simultaneously, by T1 by PU
It drags down；3) clock signal because of odd level and even level is reversed, and the T3 pipe drain terminal in the ASG of the second level is given height at this time
Level, G2 are drawn high, and complete the shift LD effect of subject clock signal control.The pulse width of clock signal, t6-t7, t8-t9,
T10-t11 can be adjusted but be consistent by actual read-out circuit required time.T9 moment CK is pulled low；T10 moment CKB is by again
It draws high, in first order ASG, as CKB is raised, by C2 capacitor, PD level point, which is coupled, to be raised, and T2, T5 are connected PU
VGL is pulled low to Gn；Overlapping thereafter through CK and CKB is drawn high, and guarantees that Gn is in low level always.GN has been generated when N grades
Signal is transmitted to dummy grades, i.e. Gn+1 grades of ASG, and the end pumping signal STP input high level, dummy grades of PU are raised, and work as CKB
After the input high level clock of port, Gn is raised, and feeds back to n-th grade；But the mode due to can not drag down PU can allow
Dummy grades of output end Gn have always the output signal with the clock signal synchronization of the port CKB input, feed back to upper level Gn help
This level-one Gn can be always maintained at pull-down state after being pulled low.
It ensure that dislocation gate output signal by the setting for the clock that misplaces, it is not overlapping to guarantee that grid is successively opened, no
It can influence each other.In addition, only using a transistor in initial state reseting procedure, reduce chip area, while can be to PD
Carrying out the initial state moment drags down, rather than vacant state, guarantee to it is subsequent give pumping signal after process is drawn high not to bootstrap point
It is influenced in the presence of liquidating.
According to the application another aspect, a kind of sector scanning side using the aforementioned gate driving circuit is provided
Method, this method comprises: step S11, based on the fingerprint triggering information detected from multiple blocks being made of gate driving circuit
Select specified region unit, wherein each piece includes N+1 grades of shift registers in the specified region unit；Step S12, will be described
The pumping signal of shift register cell in specified region is set as high level, the pumping signal of remaining shift register cell
It keeps receiving low level.Here, detecting as shown in fig. 6, the aforementioned gate driving circuit can apply in sector scanning
To fingerprint to choose the ASG unit of specified range, such as piece this region from the 3rd piece to the 6th is chosen, each piece includes N+1
Grade shift register, the ASG unit in specified region for detecting fingerprint give the STP signal of high level, STP after reset
Output gate drive level is drawn high, the ASG unit in other blocks keeps silent, and STP is connected to low level and does not trigger.To realize area
Domain scanning, saves power consumption and time.In one preferred embodiment of the application, for example detection zone is first divided into some ASG blocks, serial number
1,2,3 ... 100, when the range detection for detecting serial number 3,4,5 has arrived fingerprint, then serial number 3,4,5 corresponding pieces are specified model
The ASG unit enclosed, gives 3,4,5 pieces of serial number corresponding ASG unit high level excitations, and the ASG in corresponding piece of other serial numbers is mono-
Member keeps silent.It, can also be with it should be noted that the ASG unit in the specified range selected in above-described embodiment is only for example
For the corresponding ASG unit of serial number 2,3,4 or the corresponding ASG unit of other serial numbers.
Obviously, those skilled in the art can carry out various modification and variations without departing from the essence of the application to the application
Mind and range.In this way, if these modifications and variations of the application belong to the range of the claim of this application and its equivalent technologies
Within, then the application is also intended to include these modifications and variations.
It is obvious to a person skilled in the art that the application is not limited to the details of above-mentioned exemplary embodiment, Er Qie
In the case where without departing substantially from spirit herein or essential characteristic, the application can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and scope of the present application is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included in the application.Any reference signs in the claims should not be construed as limiting the involved claims.This
Outside, it is clear that one word of " comprising " does not exclude other units or steps, and odd number is not excluded for plural number.
Claims (8)
1. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes N+1 grades of shift register cells,
In, N is positive integer；
Each shift register cell include primary transistor, the first transistor, second transistor, third transistor, reset transistor and
Lower trombone slide；
The grid of primary transistor is for receiving pumping signal；
The grid of the first transistor is used to receive the output signal of next stage shift register cell feedback to control grid control
Signal；
The drain electrode of source electrode and the first transistor of primary transistor, the drain electrode of second transistor, third transistor grid and
The grid of lower trombone slide is intersected in bootstrap point；
The drain electrode of the reset transistor connects input signal, and grid is controlled by reset signal, the source electrode of the reset transistor, described second
The grid of the grid of transistor, the drain electrode of the lower trombone slide and the 5th transistor is intersected in level drop-down control node；
The source electrode of third transistor, the drain electrode of the 4th transistor and the drain electrode of the 5th transistor and shift register output signal
Connection；
The drain electrode of third transistor receives the first clock signal, and the grid of the 4th transistor receives second clock signal, when first
Clock signal is opposite each other with second clock signal and does not overlap.
2. gate driving circuit according to claim 1, which is characterized in that the drain electrode connection first of the primary transistor
The source electrode of level signal, the first transistor connects second electrical level signal, the electricity of the first level signal and second electrical level signal
Position is opposite.
3. gate driving circuit according to claim 1, which is characterized in that each shift register cell includes first capacitor
With the second capacitor, the two-plate of the first capacitor is separately connected the output signal of bootstrap point and shift register, and described second
The two-plate of capacitor is separately connected the first clock signal and level drop-down control node.
4. gate driving circuit according to claim 1, which is characterized in that the source electrode of the second transistor connects low electricity
Ordinary mail number, the source electrode of the 4th transistor connect low level signal with the source electrode of the 5th transistor, the lower trombone slide
Source electrode connects low level signal.
5. gate driving circuit according to claim 1, which is characterized in that the shift register cell of odd level is connected
The first clock signal and second clock signal and even level the first clock signal and for being connected of shift register cell
Two clock signals are opposite each other and do not overlap.
6. gate driving circuit according to claim 1, which is characterized in that the output of the shift register cell of upper level
Pumping signal of the signal as the shift register cell of next stage, the output signal conduct of the shift register cell of next stage
The control signal of the grid of the first transistor in the shift register cell of upper level.
7. gate driving circuit according to claim 1, which is characterized in that the drain electrode connection input letter of the reset transistor
Number, the input signal is raised at the first moment of clock signal, is pulled low at the second moment.
8. a kind of sector scanning method using gate driving circuit described in any one of any one of claims 1 to 77, feature exist
In, which comprises
Specified region unit is selected from multiple blocks being made of gate driving circuit based on the fingerprint triggering information detected,
In, each piece includes N+1 grades of shift registers in the specified region unit；
High level, remaining shift register cell are set by the pumping signal of the shift register cell in the specified region
Pumping signal keep receive low level.
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