CN110174804B

CN110174804B - Array substrate, display panel, driving method of display panel and display device

Info

Publication number: CN110174804B
Application number: CN201910569698.1A
Authority: CN
Inventors: 孙丽娜; 简守甫
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2019-06-27
Filing date: 2019-06-27
Publication date: 2022-03-01
Anticipated expiration: 2039-06-27
Also published as: CN110174804A

Abstract

The invention discloses an array substrate, a display panel, a driving method of the display panel and a display device, relates to the technical field of display and is used for reducing the power consumption of the display device. In the embodiment of the present invention, for an array substrate having a dual-gate structure and two columns of sub-pixels adjacent to each other in a row direction to form a sub-pixel column group, where a data line is located between two columns of sub-pixels in the sub-pixel column group and is electrically connected to the two columns of sub-pixels, for each row of sub-pixels in the sub-pixel column group: at least part of two adjacent rows of sub-pixels are different in connection sequence with the grid line; therefore, in each row of sub-pixels in the sub-pixel column group, the sequence of the scanning signals input by each sub-pixel in at least part of two adjacent rows of sub-pixels is different, and the switching times of the data signals transmitted on the data line when the scanning signals are sequentially input by each grid line can be reduced, so that the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Description

Array substrate, display panel, driving method of display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a display panel, a driving method of the display panel and a display device.

Background

The liquid crystal display is a non-self-luminous device, needs to be provided with a backlight module, and realizes a display function by utilizing a backlight source provided by the backlight module. In order to increase the screen ratio of the display, the display panel may be designed to have a dual gate structure, wherein each data line may be electrically connected to two columns of sub-pixels adjacent to each other on the left and right, and in each row of sub-pixels in two columns of sub-pixels electrically connected to the same data line, the sub-pixel on the left side of the data line may input a scan signal before the sub-pixel on the right side of the data line, or the sub-pixel on the right side of the data line may input a scan signal before the sub-pixel on the left side of the data line, that is, the two sub-pixels in each row of sub-pixels electrically connected to the same data line input a scan signal in the same order.

If the polarities of the data signals input by the two rows of sub-pixels electrically connected with the same data line are the same, and the two adjacent rows of sub-pixels have different colors, when the scanning signals are sequentially input to the corresponding electrically connected sub-pixels by each gate line, the data signals transmitted on the data line need to be switched once.

For example, as shown in fig. 1, a timing chart of a data signal transmitted on one of the data lines when a red screen is displayed is shown, in the figure, R denotes a red sub-pixel electrically connected to the data line, G denotes a green sub-pixel electrically connected to the data line, and the red sub-pixel R and the green sub-pixel G are arranged in the order in which a scan signal is sequentially input. In fig. 1, since a red frame needs to be displayed, the data line needs to input a data signal to the red sub-pixel R, and no data signal is input to the green sub-pixel G, so that the data line switches to a zero potential after outputting a data signal to one red sub-pixel R, so that no data signal is input to the green sub-pixel G, and then switches to a data signal from the zero potential, so that a data signal is input to the red sub-pixel R. Therefore, the data signals transmitted on the data lines need to be frequently switched, which causes the power consumption of the display panel to increase.

Therefore, how to reduce the power consumption of the display panel with the dual-gate structure is an urgent technical problem to be solved by the embodiments of the present invention.

Disclosure of Invention

The embodiment of the invention provides an array substrate, a display panel, a driving method thereof and a display device, which are used for reducing the power consumption of the display panel with a double-gate structure.

In a first aspect, an embodiment of the present invention provides an array substrate, including:

sub-pixels arranged in an array;

the data lines are arranged along the row direction and extend along the column direction, two columns of sub-pixels adjacent to each other in the row direction form a sub-pixel column group, the data lines are positioned between two columns of sub-pixels in the sub-pixel column group and are electrically connected with the two columns of sub-pixels, and the polarities of data signals received by the sub-pixels in the sub-pixel column group are the same;

the grid lines are arranged along the column direction and extend along the row direction, two grid lines are arranged between any two adjacent rows of sub-pixels, one side, away from the last row of sub-pixels, of the first row of sub-pixels and one side, away from the first row of sub-pixels, of the last row of sub-pixels are respectively provided with one grid line, and two sub-pixels, electrically connected with the same data line, in each row of sub-pixels are respectively and electrically connected with different grid lines; for each row of subpixels in the subpixel column group: at least part of two adjacent rows of sub-pixels are different from the grid line in connection sequence; in the column direction, a row of the sub-pixels includes a first side and a second side opposite to each other, wherein the connection order is: and two sub-pixels in the same row in the sub-pixel column group are electrically connected with the grid line on the first side and the grid line on the second side in sequence.

In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate provided in the embodiment of the present invention.

In a third aspect, an embodiment of the present invention provides a display device, including the display panel provided in the embodiment of the present invention.

In a fourth aspect, an embodiment of the present invention provides a driving method for a display panel, where the display panel is as described in the foregoing display panel provided in the embodiment of the present invention, and the driving method includes:

for each row of subpixels in the subpixel column group: the scanning signals input by each sub-pixel in at least part of two adjacent rows of sub-pixels are in different orders;

wherein, the sequence of the input scanning signals is as follows: and two sub-pixels positioned in the same row in the sub-pixel column group input scanning signals through the electrically connected grid lines in sequence.

The invention has the following beneficial effects:

the embodiment of the invention provides an array substrate, a display panel, a driving method thereof and a display device, aiming at each row of sub-pixels in a sub-pixel column group, the array substrate comprises: at least part of two adjacent rows of sub-pixels are different in connection sequence with the grid line; in the column direction, a row of sub-pixels comprises a first side and a second side opposite to each other, wherein the connection order is: and two sub-pixels positioned in the same row in the sub-pixel column group are electrically connected with the grid line on the first side and the grid line on the second side in sequence. Therefore, in each row of sub-pixels in the sub-pixel column group, the sequence of the scanning signals input by each sub-pixel in at least part of two adjacent rows of sub-pixels is different, and the switching times of the data signals transmitted on the data line when the scanning signals are sequentially input by each grid line can be reduced, so that the power consumption of the display device is reduced, and the service life of the display device is prolonged.

Drawings

FIG. 1 is a timing diagram of data signals transmitted on one data line when displaying a red color frame in the prior art;

fig. 2 is a schematic structural diagram of a first array substrate according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second array substrate according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of a third array substrate provided in an embodiment of the invention;

fig. 5 is a schematic structural diagram of a fourth array substrate provided in an embodiment of the present invention;

FIG. 6 is a diagram illustrating the data lines in FIG. 3 showing the switching of data signals when displaying a monochrome picture;

fig. 7 is a schematic structural diagram of a liquid crystal display panel provided in an embodiment of the invention;

fig. 8 is a schematic structural diagram of a display device provided in an embodiment of the present invention.

The touch panel comprises 10-grid lines, g11, g21, g31, g41, g51, g 61-first grid lines, g12, g22, g32, g42, g52, g 62-second grid lines, 20, S1, S2, S3-data lines, 30-sub-pixel column groups, 40a and 40 b-sub-pixel row groups, 50-touch signal lines, 101-array substrates, 102-opposite substrates, 103-liquid crystals, 104-packaging substrates, X-display panels, P, P1, P2, P3, P4, P5 and P6-sub-pixels, TFT-transistors, A1-display regions and A2-fan-out regions.

Detailed Description

Embodiments of an array substrate, a display panel, a driving method thereof, and a display device according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the invention provides an array substrate, as shown in fig. 2 to 5, where fig. 2 is a schematic structural diagram of a first array substrate, fig. 3 is a schematic structural diagram of a second array substrate, fig. 4 is a schematic structural diagram of a third array substrate, and fig. 5 is a schematic structural diagram of a fourth array substrate. In fig. 2 to 5, the straight line arrows on the right side indicate that the scanning order of the gate lines is to input the scanning signals sequentially from top to bottom, and it is to be noted that the scanning order of the gate lines may also be to input the scanning signals sequentially from bottom to top, which is not shown in the drawings, and is not limited herein.

Referring to fig. 2 to 5, the array substrate may include:

subpixels P arranged in an array;

a plurality of data lines (20 in fig. 2, 4 and 5, and S1, S2 and S3 in fig. 3) arranged in a row direction and extending in a column direction, two columns of sub-pixels adjacent to each other in the row direction forming a sub-pixel column group 30, the data lines 20 being located between two columns of sub-pixels in the sub-pixel column group 30 and electrically connected to the two columns of sub-pixels, and the polarities of data signals received by the sub-pixels P in the sub-pixel column group 30 being the same;

a plurality of gate lines 10 arranged along the column direction and extending along the row direction, two gate lines 10 are arranged between any two adjacent rows of sub-pixels, one side of the first row of sub-pixels far away from the last row of sub-pixels and one side of the last row of sub-pixels far away from the first row of sub-pixels are both provided with one gate line 10, and two sub-pixels electrically connected with the same data line 20 in each row of sub-pixels are respectively and electrically connected with different gate lines 10; for each row of subpixels in subpixel column group 30: at least part of two adjacent rows of sub-pixels are connected with the grid line 10 in different orders; in the column direction, a row of sub-pixels comprises a first side and a second side opposite to each other, wherein the connection order is: two sub-pixels P located in the same row in the sub-pixel column group 30 are electrically connected to the gate line on the first side and the gate line on the second side in sequence.

For convenience of description, first, a first gate line and a second gate line are defined, and referring to fig. 2 to 5, in which a display region a1 and a fan-out region a2 are shown, a subpixel P is located in the display region a1, and one end of a data line is electrically connected to a trace disposed in the fan-out region a 2. The first gate line may be understood as a gate line located at a side of the sub-pixel away from the fan-out region a2 (i.e., a gate line located above each sub-pixel as shown in fig. 2 to 5), and the second gate line may be understood as a gate line located at a side of the sub-pixel close to the fan-out region a2 (i.e., a gate line located below each sub-pixel as shown in fig. 2 to 5).

The connection sequence will be described below by taking the structure shown in fig. 3 as an example.

Referring to fig. 3, 6 sub-pixels, labeled P1, P2, P3, P4, P5 and P6, are electrically connected to the same data line 20, wherein the sub-pixel P1 and the sub-pixel P2 are located in the first row, the gate line located on the side of the sub-pixel of the first row far from the fan-out region a2 (i.e., the gate line located above the sub-pixel of the first row shown in fig. 3) is referred to as a first gate line (denoted by g 11), and the gate line located on the side of the sub-pixel of the first row near the fan-out region a2 (i.e., the gate line located below the sub-pixel of the first row shown in fig. 3) is referred to as a second gate line (denoted by g 12). At this time: for the sub-pixel P1 and the sub-pixel P2 in the first row, the connection sequence to the gate line is: the first grid line g11 and the second grid line g12 are electrically connected in sequence;

the subpixel P3 and subpixel P4 are in the second row, and the gate line on the side of the second row of subpixels away from fan-out area a2 (i.e., the gate line on the second row of subpixels shown in fig. 3) is referred to as the first gate line (denoted by g 21), and the gate line on the side of the second row of subpixels near fan-out area a2 (i.e., the gate line on the second row of subpixels shown in fig. 3) is referred to as the second gate line (denoted by g 22). At this time: for the sub-pixel P3 and the sub-pixel P4 in the second row, the connection sequence to the gate line is: the first gate line g21 is electrically connected with the second gate line g22 in sequence;

the sub-pixel P5 and the sub-pixel P6 are located in the third row, the gate line located on the side of the sub-pixel in the third row far from the fan-out region a2 (i.e., the gate line located above the sub-pixel in the third row shown in fig. 3) is referred to as a first gate line (denoted by g 31), and the gate line located on the side of the sub-pixel in the third row near the fan-out region a2 (i.e., the gate line located below the sub-pixel in the third row shown in fig. 3) is referred to as a second gate line (denoted by g 32), at this time: for the sub-pixel P5 and the sub-pixel P6 in the third row, the connection sequence to the gate line is: and are electrically connected to the first gate line g31 and the second gate line g32, respectively, in turn.

Therefore, the connection order of the two sub-pixels in the first row and the two sub-pixels in the second row to the gate line is different, and the connection order of the two sub-pixels in the second row and the two sub-pixels in the third row to the gate line is also different.

That is, in the case of sub-pixels for each row in a sub-pixel column group: when the connection sequence of at least part of the two adjacent rows of sub-pixels is different from the gate line 10, it is possible to avoid the following phenomenon in two rows of sub-pixels electrically connected to the same data line 20: the sub-pixel positioned on the left side inputs a scan signal before the sub-pixel positioned on the right side (for the moment, referred to as a positive Z scan mode) or the sub-pixel positioned on the right side inputs a scan signal before the sub-pixel positioned on the left side (for the moment, referred to as a negative Z scan mode), which breaks the positive Z scan mode and the negative Z scan mode, so that the following may occur for two adjacent rows of sub-pixels connected to the gate line 10 in a different order:

in the previous row of sub-pixels, the sub-pixels on the left side input the scanning signals first, and the sub-pixels on the right side input the scanning signals later, while in the next row of sub-pixels, the sub-pixels on the right side input the scanning signals first, and the sub-pixels on the left side input the scanning signals later.

Or, in the sub-pixels in the previous row, the sub-pixels on the right side input the scanning signals first, and the sub-pixels on the left side input the scanning signals later, while in the sub-pixels in the next row, the sub-pixels on the left side input the scanning signals first, and the sub-pixels on the right side input the scanning signals later.

So, to two adjacent row of sub-pixels in sub-pixel column group 30, make the number of times of switching of the data signal of transmission on the data line 20 reduce to twice from the cubic when positive Z scanning mode or anti-Z scanning mode, if there are a plurality of such two adjacent row of sub-pixels different with grid line 10 connection order in the array substrate, make the number of times of switching of the data signal of transmission on the data line 20 significantly reduce, and then can greatly reduced display panel's consumption, thereby greatly reduced display device's consumption, the length of time of use of extension display device.

In practical implementation, in the embodiment of the present invention, for each row of sub-pixels, two sub-pixels P electrically connected to the same data line 20 have different colors, and each sub-pixel P in the same column of sub-pixels has the same color, as shown in fig. 2 to 5.

Based on the design, through the arrangement of the connection sequence of the sub-pixels and the gate lines in the sub-pixel column group in the embodiment of the invention, when the scan signals are sequentially input to the gate lines, the sub-pixels with the same color can be sequentially and continuously turned on, that is, the sub-pixels with the same color sequentially and continuously input the data signals, instead of the situation that all the sub-pixels with the same color need to be turned on at intervals and input the data signals at intervals in the positive Z scanning and the negative Z scanning in the prior art, the switching times of the data signals are reduced, the power consumption of the array substrate is reduced, the power consumption of the display device is greatly reduced, and the service life of the display device is prolonged.

In particular implementation, to implement the following for each row of subpixels in the subpixel column group 30: in the embodiment of the present invention, the connection order of at least some adjacent two rows of sub-pixels and the gate line 10 is different, and the following two situations may exist for the arrangement of the connection order of each row of sub-pixels and the gate line 10:

in the first case:

for each row of subpixels in subpixel column group 30: the connection sequence of some adjacent two rows of sub-pixels and the grid line 10 is different.

For ease of illustration, the concept of subpixel row groups is introduced herein, i.e., subpixel row group 30 comprises a plurality of subpixel row groups, including at least three rows of subpixels;

wherein, aiming at each row of sub-pixels in the sub-pixel row group: the connection sequence of part of two adjacent rows of sub-pixels and the gate line 10 is different, and only the connection sequence of two adjacent rows of sub-pixels and the gate line 10 is the same.

For example, as shown in fig. 2, the dashed box 40 represents a sub-pixel row group, which includes three consecutive rows of sub-pixels, wherein, for the first row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, and is denoted by g11, and the gate line on the side of the first row of sub-pixels near the fan-out area a2 is the second gate line, and is denoted by g12, at this time: the connection sequence of the two sub-pixels in the first row and the grid line is as follows: are electrically connected with the first grid line g11 and the second grid line g12 in sequence;

for the second row of sub-pixels, the gate line at the side of the second row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g21, and the gate line at the side of the second row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g22, at this time: the connection sequence of the two sub-pixels in the second row and the grid line is as follows: are electrically connected with the second grid line g22 and the first grid line g21 in sequence;

for the third row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g31, and the gate line on the side of the third row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g32, at this time: the connection sequence of the two sub-pixels in the third row and the grid line is as follows: and is electrically connected to the second gate line g32 and the first gate line g31 in turn.

Therefore, in fig. 2, the connection order of the sub-pixels in the second and third rows to the gate lines is the same, and the connection order of the sub-pixels in the first and second rows to the gate lines is different.

In this way, when the scanning signals are sequentially input to the gate lines of each row, the turn-on sequence of each subpixel in the subpixel row group is shown by a broken line with an arrow in fig. 2, that is, there may be a case where subpixels of the same color in the subpixel row group are sequentially turned on, and data signals may be sequentially input through the data lines, instead of the case where all subpixels of the same color need to be turned on at intervals and input data signals at intervals as occurs in the prior art during the positive Z scanning and the negative Z scanning, so by setting the connection sequence of the subpixels of each row in the subpixel row group and the gate lines, the number of times of switching the data signals transmitted on the data lines 20 may be reduced, and thus the power consumption of the display panel may be reduced.

For another example, as shown in fig. 3, the dashed box 40a represents a sub-pixel row group, which includes four consecutive rows of sub-pixels, wherein, for the sub-pixels in the first row, the gate line on the side of the sub-pixels in the first row away from the fan-out area a2 is the first gate line and is denoted by g11, and the gate line on the side of the sub-pixels in the first row close to the fan-out area a2 is the second gate line and is denoted by g12, at this time: the connection sequence of the two sub-pixels in the first row and the grid line is as follows: are electrically connected with the first grid line g11 and the second grid line g12 in turn;

for the third row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g31, and the gate line on the side of the third row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g32, at this time: the connection sequence of the two sub-pixels in the third row and the grid line is as follows: are electrically connected with the first grid line g31 and the second grid line g32 in sequence;

for the fourth row of sub-pixels, the gate line on the side of the first row of sub-pixels far away from the fan-out area a2 is the first gate line, denoted by g41, and the gate line on the side of the fourth row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g42, at this time: the connection sequence of the two sub-pixels in the fourth row and the grid line is as follows: and is electrically connected to the first gate line g41 and the second gate line g42 in turn.

Therefore, in fig. 3, the sub-pixels in the first and second rows are connected to the gate line 10 in a different order, the sub-pixels in the second and third rows are connected to the gate line 10 in a different order, and the sub-pixels in the third and fourth rows are connected to the gate line 10 in the same order.

Thus, when the scan signals are sequentially inputted to the gate lines of each row, the turn-on sequence of each sub-pixel in the sub-pixel row group is shown by the broken line with an arrow in fig. 3. That is, there may be sub-pixels of the same color in the sub-pixel row group that are sequentially turned on, and data signals may be sequentially input through the data lines, instead of the situation that all sub-pixels of the same color need to be turned on at intervals and input data signals at intervals as occurs in the prior art in the forward Z scanning and the reverse Z scanning, so by setting the connection sequence of the sub-pixels and the gate lines in each row in the sub-pixel row group, the number of times of switching of the data signals transmitted on the data lines 20 may be reduced, and thus the power consumption of the display panel may be reduced.

Of course, when the number of sub-pixel rows included in the sub-pixel row group is large, the connection sequence of a plurality of sub-pixels in two adjacent rows and the gate line 10 may be set as required.

For example, as shown in fig. 4, the dashed box 40 represents a sub-pixel row group, which includes 6 consecutive rows of sub-pixels, wherein, for the first row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, and is denoted by g11, and the gate line on the side of the first row of sub-pixels near the fan-out area a2 is the second gate line, and is denoted by g12, at this time: the connection sequence of the two sub-pixels in the first row and the grid line is as follows: are electrically connected with the first grid line g11 and the second grid line g12 in sequence;

for the second row of sub-pixels, the gate line at the side of the second row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g21, and the gate line at the side of the second row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g22, at this time: the connection sequence of the two sub-pixels in the second row and the grid line is as follows: the first grid line g21 is electrically connected with the second grid line g22 in sequence;

for the third row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g31, and the gate line on the side of the third row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g32, at this time: the connection sequence of the two sub-pixels in the third row and the grid line is as follows: are electrically connected with the second grid line g32 and the first grid line g31 in sequence;

for the fourth row of sub-pixels, the gate line on the side of the first row of sub-pixels far away from the fan-out area a2 is the first gate line, denoted by g41, and the gate line on the side of the fourth row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g42, at this time: the connection sequence of the two sub-pixels in the fourth row and the grid line is as follows: are electrically connected with the first grid line g41 and the second grid line g42 in sequence;

for the sub-pixels in the fifth row, the gate line on the side of the sub-pixels in the first row far from the fan-out area a2 is the first gate line, and is denoted by g51, and the gate line on the side of the sub-pixels in the fifth row near the fan-out area a2 is the second gate line, and is denoted by g52, at this time: the connection sequence of the two sub-pixels in the fifth row and the grid line is as follows: are electrically connected with the first grid line g51 and the second grid line g52 in sequence;

for the sixth row of sub-pixels, the gate line on the side of the first row of sub-pixels far from the fan-out area a2 is the first gate line, denoted by g61, and the gate line on the side of the sixth row of sub-pixels near the fan-out area a2 is the second gate line, denoted by g62, at this time: the connection sequence of the two sub-pixels in the sixth row and the grid line is as follows: and is electrically connected to the second gate line g62 and the first gate line g61 in turn.

Therefore, in fig. 4, the connection order of the subpixels in the first and second rows to the gate line 10 is different, the connection order of the subpixels in the second and third rows to the gate line 10 is the same, the connection order of the subpixels in the third and fourth rows to the gate line 10 is different, the connection order of the subpixels in the fourth and fifth rows to the gate line 10 is the same, and the connection order of the subpixels in the fifth and sixth rows to the gate line 10 is different. That is, in the sub-pixel row group 40 shown in fig. 4, the connection order of two adjacent rows of sub-pixels to the gate line 10 is the same.

Thus, when the scan signals are sequentially input to the gate lines in each row, the turn-on sequence of each sub-pixel in the sub-pixel row group is shown by the broken line with an arrow in fig. 4. That is, there may be sub-pixels of the same color in the sub-pixel row group that are sequentially turned on, and data signals may be sequentially input through the data lines, instead of the situation that all sub-pixels of the same color need to be turned on at intervals and input data signals at intervals as occurs in the prior art in the forward Z scanning and the reverse Z scanning, so by setting the connection sequence of the sub-pixels and the gate lines in each row in the sub-pixel row group, the number of times of switching of the data signals transmitted on the data lines 20 may be reduced, and thus the power consumption of the display panel may be reduced.

In addition, it can be selected according to actual needs which adjacent rows of sub-pixels have the same connection sequence with the gate line 10 and which adjacent rows of sub-pixels have different connection sequences with the gate line 10, thereby improving the flexibility of design to meet the requirements of various application scenarios.

Specifically, two adjacent rows of sub-pixels in the same connection order as the gate lines 10 are located at the end of the sub-pixel row group (e.g., 40 in fig. 2, 40a and 40b in fig. 3); as shown in fig. 2 and 3.

Of course, two adjacent rows of sub-pixels in the same connection sequence as the gate line 10 may also be located in the middle of the sub-pixel row group 40 (as shown in fig. 4), and may be arranged according to actual needs in specific implementation, which is not limited herein.

Optionally, in the embodiment of the present invention, the sub-pixel row group may include 2N rows of sub-pixels, where N is an integer greater than 1.

The value of N may be 2, and at this time, the sub-pixel row group includes 4 rows of sub-pixels, as shown in fig. 3. Alternatively, the value of N may also be 3, and at this time, the sub-pixel row group includes 6 rows of sub-pixels, as shown in fig. 4.

That is, N may be any integer greater than 1, and it is within the scope of the present invention as long as the switching times of the data signals transmitted on the data lines 20 can be reduced.

Optionally, in the embodiment of the present invention, the connection sequence between the sub-pixels in different sub-pixel row groups in the sub-pixel column group 30 and the gate line 10 is the same, and two adjacent sub-pixel row groups in the sub-pixel column group 30 share one row of sub-pixels.

For example, taking the structure shown in fig. 3 as an example, a row of sub-pixels is shared between the sub-pixel row group labeled 40a and the sub-pixel row group labeled 40 b.

Therefore, the switching times of the data signals transmitted on the data lines 20 can be controlled and calculated favorably, inaccurate calculation caused by omission is avoided, and therefore the power consumption of the display panel can be effectively controlled, and the display panel can be effectively and accurately controlled.

Specifically, with the configuration shown in fig. 3, a timing chart of data signals transmitted on the data lines denoted by S1, S2, S3 in fig. 3 when displaying a monochrome screen is obtained, where a position in the data signal corresponding to R represents a data signal input into the red sub-pixel, a position in the data signal corresponding to G represents a data signal input into the green sub-pixel, and a position in the data signal corresponding to B represents a data signal input into the blue sub-pixel. Wherein the data signal may include a high level signal (denoted by V1) and a low level signal (denoted by V3); the zero potential (indicated by V2) is indicated in the figure when no data signal is output on the data line.

For example, the timing shown in fig. 6 is explained by taking the display of a red screen as an example.

Similarly, the display of the green frame may be considered as the case where the data signal is input to all the green sub-pixels and no data signal is input to the sub-pixels of other colors, and the display of the blue frame may be considered as the case where the data signal is input to all the blue sub-pixels and no data signal is input to the sub-pixels of other colors.

When a red screen is displayed, since a red subpixel is included in a subpixel column electrically connected to the data line S1 and the data line S2, a data signal is input only to the electrically connected red subpixel through the data line S1 and the data line S2. From the results shown in fig. 6, it can be seen that when switching between the high level signal V1 or the low level signal V3 and the zero potential V2, it is not necessary to switch to the zero potential V2 directly after outputting a high level signal V1 or a low level signal V3, and similarly, it is not necessary to switch to the high level signal V1 or the low level signal V3 directly after outputting a zero potential V2, so that the number of times of switching of the data signals is effectively reduced, and the power consumption of the display panel is effectively reduced.

Similarly, when displaying a green screen, since a green sub-pixel is included in a sub-pixel column electrically connected to the data line S1 and the data line S3, a data signal is input only to the electrically connected green sub-pixel through the data line S1 and the data line S3. As shown in fig. 6, at this time, when switching between the high level signal V1 or the low level signal V3 and the zero potential V2, it is not necessary to switch to the zero potential V2 every time a high level signal V1 or a low level signal V3 is output, so that the number of times of switching of the data signals is effectively reduced, and the power consumption of the display panel is effectively reduced.

Similarly, when a blue screen is displayed, since a blue sub-pixel is included in a sub-pixel column electrically connected to the data line S2 and the data line S3, a data signal is input only to the electrically connected blue sub-pixel through the data line S2 and the data line S3. At this time, when switching between the high level signal V1 or the low level signal V3 and the zero potential V2, it is not necessary to switch to the zero potential V2 every time a high level signal V1 or a low level signal V3 is output, so that the number of times of switching of the data signals is effectively reduced, and the power consumption of the display panel is effectively reduced.

Moreover, a power consumption comparison result when different images are displayed is shown in table 1, where power consumption 1 represents power consumption generated by the display when a positive Z scanning mode in the prior art is adopted, power consumption 2 represents power consumption generated by the display when a setting mode of a connection sequence of each row of subpixels in a subpixel column group and a gate line provided by an embodiment of the present invention is utilized, and power consumption 1-power consumption 2 represent the magnitude of power consumption reduced by the display through the setting mode of the connection sequence of each row of subpixels in the subpixel column group and the gate line provided by the embodiment of the present invention.

Obviously, the power consumption is effectively reduced through the arrangement mode of the connection sequence of each row of sub-pixels and the grid line in the sub-pixel column group, so that the service life of the display can be prolonged, and the user experience is improved.

TABLE 1

In the second case:

for each row of subpixels in subpixel column group 30: the connection sequence of any two adjacent rows of sub-pixels and the grid line 10 is different.

That is, in the embodiment of the present invention, for each row of subpixels in the subpixel column group 30: the connection sequence of the interlaced sub-pixels and the gate lines 10 is the same, and the connection sequence of the sub-pixels and the gate lines 10 of the adjacent rows is opposite.

For example, as shown in fig. 5, the figure shows 7 rows of sub-pixels and 3 sub-pixel column groups 30, and taking the left-most sub-pixel column group 30 as an example, the connection sequence of two sub-pixels in the first row, the third row, the fifth row and the seventh row to the gate line is: the first grid line and the second grid line are electrically connected in sequence; the connection sequence of the two sub-pixels in the second row, the fourth row and the sixth row to the grid line is as follows: and the second grid line and the first grid line are electrically connected in sequence. Here, the first gate line may be understood as a gate line located at a side of the sub-pixel far from the fan-out region a2, and the second gate line may be understood as a gate line located at a side of the sub-pixel near the fan-out region a 2.

In this way, compared with the forward Z scanning mode and the backward Z scanning mode, the number of times of switching the data signals transmitted on the data lines 20 can be reduced by about 1/2 times, that is, the number of times of switching the data signals transmitted on the data lines 20 is greatly reduced, so that the power consumption of the display panel can be greatly reduced.

Of course, in this case, the scanning manner of each row of sub-pixels is not limited to that shown in fig. 5, as long as it is possible to realize, for each row of sub-pixels in the sub-pixel column group 30: the scanning mode in which the connection sequence of the interlaced sub-pixels and the gate lines 10 is the same and the connection sequence of the sub-pixels and the gate lines 10 in the adjacent rows is opposite belongs to the protection scope of the embodiment of the present invention.

Based on this, in both the first case and the second case, the number of times of switching the data signal transmitted on the data line 20 can be reduced by setting the connection sequence between each row of sub-pixels in the sub-pixel column group 30 and the gate line 10, so that the power consumption of the array substrate can be reduced, and the power consumption of the display panel can be further reduced.

Alternatively, the above two cases describe the connection sequence of the sub-pixels and the gate lines 10 in each row in one sub-pixel column group 30, and for different sub-pixel column groups 30, in the embodiment of the present invention, the connection sequence of the sub-pixels and the gate lines 10 in different sub-pixel column groups 30 may be set to be the same, as shown in fig. 2 to fig. 5.

Therefore, the driving modes of different sub-pixel column groups 30 can be kept consistent, the complexity of the driving process of the display panel can be simplified, the display uniformity of the display panel can be guaranteed, the problem of nonuniform display caused by inconsistent driving modes of different areas is avoided, and the display effect is improved.

In practical implementation, since the data line 20 is located between and electrically connected to two columns of sub-pixels in the sub-pixel column group 30, and the polarities of the data signals received by the sub-pixels in the sub-pixel column group 30 are the same, in order to improve the display effect, in the embodiment of the present invention, the polarities of the data signals received by the sub-pixels in the adjacent sub-pixel column group 30 are opposite.

For example, taking the example shown in fig. 3, 6 columns of sub-pixels and 3 data lines 20 are shown, the left first column and second column of sub-pixels in the figure are electrically connected to the left first data line 20 in the figure, and the positive polarity data signals are input to the sub-pixels in the first column and second column through the data lines 20; the left third column and the fourth column of the sub-pixels are electrically connected with the left second data line 20, and the data signals with negative polarity are input to the sub-pixels in the third column and the fourth column through the data line 20; the subpixels in the fifth and sixth columns on the left in the figure are electrically connected to the third data line 20 on the left in the figure, and data signals of positive polarity are input to the subpixels in the fifth and sixth columns through the data line 20.

Therefore, the problem of image sticking caused by the fact that the polarities of the data signals received by the sub-pixels of each column are the same can be avoided, and the effect of the display panel can be improved.

It should be noted that, although the above mentioned is the case where the polarities of the data signals received by the sub-pixels in the sub-pixel column group 30 are the same, when the polarities of the data signals received by the sub-pixels in two adjacent columns in the sub-pixel column group 30 are different, the number of times of switching the polarities of the data signals transmitted on the data lines 20 can be reduced by arranging the connection order of the sub-pixels in each row in the sub-pixel column group 30 and the gate lines 10, thereby reducing the power consumption of the display panel.

To illustrate, in the embodiment of the present invention, the array substrate further includes a plurality of transistor TFTs, wherein the sub-pixels are electrically connected to the gate lines 10 and the data lines 20 through the transistor TFTs, respectively.

For example, in the structure shown in fig. 5, the gate electrode of the transistor TFT is electrically connected to the gate line 10, the source electrode of the transistor TFT is electrically connected to the data line 20, the drain electrode of the transistor TFT is electrically connected to the subpixel P, and the data line 20 inputs a data signal to the subpixel under the control of the transistor TFT.

In this manner, the data signals input to the sub-pixels can be controlled by the transistors TFT, thereby realizing display of different pictures.

In the embodiment of the invention, the array substrate may further include a touch signal line 50, and the touch signal line 50 is disposed between the adjacent sub-pixel column groups 30.

For example, as shown in fig. 5, a bold solid line 50 represents a touch signal line, and two touch signal lines 50 are shown in the figure, respectively located at: the sub-pixel column group 30 composed of the first and second columns of sub-pixels from the left in the figure and the sub-pixel column group 30 composed of the third and fourth columns of sub-pixels from the left in the figure, and the sub-pixel column group 30 composed of the third and fourth columns of sub-pixels from the left in the figure and the sub-pixel column group 30 composed of the fifth and sixth columns of sub-pixels from the left in the figure.

Therefore, on one hand, the display panel has a touch function, the thickness of the display panel can be favorably prevented from being increased, and the light and thin design is realized. On the other hand, the distance between the touch signal line 50 and the data line 20 can be increased, and the problem that signals cannot be normally transmitted due to short circuit caused by the small distance between the touch signal line 50 and the data line 20 is avoided, so that the array substrate can normally work, and the display panel can normally display.

Specifically, when the touch signal line 50 is disposed, the touch signal line 50 and the data line 20 may be disposed in the same material and layer, which is not shown. Therefore, the manufacturing process of the array substrate can be simplified, and the manufacturing difficulty of the array substrate is reduced.

Of course, the touch signal line 50 may also be disposed on other film layers, and the specific location of the touch signal line 50 is not limited herein as long as the touch function can be achieved.

Based on the same inventive concept, an embodiment of the present invention provides a display panel, such as the structural schematic diagram of the liquid crystal display panel shown in fig. 7, including the array substrate provided in the embodiment of the present invention.

In a specific implementation, the display panel may be a liquid crystal display panel, and as shown in fig. 7, the display panel X includes, in addition to the array substrate 101, further: the liquid crystal display device comprises an opposite substrate 102 opposite to an array substrate 101 and a liquid crystal 103 between the array substrate 101 and the opposite substrate 102, wherein pixel electrodes (not shown in fig. 7) are arranged in the array substrate 101, a common electrode (not shown in fig. 7) can be arranged on the array substrate 101, the common electrode can also be arranged on the opposite substrate 102, and the liquid crystal 103 can be driven to deflect through an electric field formed by voltages applied by the pixel electrodes and the common electrode, so that a display function is realized.

Based on the same inventive concept, an embodiment of the present invention provides a driving method of a display panel, where the driving method of the display panel, like the display panel provided in the embodiment of the present invention, may include:

wherein, the sequence of the input scanning signals is as follows: and the two sub-pixels positioned in the same row in the sub-pixel column group input scanning signals through the electrically connected grid lines in sequence.

Taking the structure shown in fig. 3 as an example, the order of inputting the scan signals through the electrically connected gate lines may be understood as:

taking the 4 rows of sub-pixels shown in the dashed-line box 40a as an example, along the direction indicated by the broken line with an arrow in fig. 3, the order of inputting the scan signals to the two sub-pixels in the first row is from left to right, the order of inputting the scan signals to the two sub-pixels in the second row is from right to left, the order of inputting the scan signals to the two sub-pixels in the third row is from left to right, and the order of inputting the scan signals to the two sub-pixels in the fourth row is still from left to right.

To explain this, in fig. 2, 4 and 5, the directions indicated by the arrows indicated by the broken lines in the figures are also the order in which the scanning signals are input to the sub-pixels, so as to indicate that the number of times of switching the data signals can be reduced when scanning is performed according to the arrows indicated by the broken lines in the figures.

Therefore, the switching times of the data signals transmitted on the data lines when the scanning signals are sequentially input to the grid lines can be reduced, so that the power consumption of the display device is reduced, and the service life of the display device is prolonged.

In a specific implementation, when the subpixel column group includes a plurality of subpixel row groups, and the subpixel row group includes four rows of subpixels, in an embodiment of the present invention, the driving method may specifically include:

for a group of subpixel rows in a subpixel column group:

the scanning signals input by each sub-pixel in the first row of sub-pixels, the third row of sub-pixels and the fourth row of sub-pixels are in the same order, and the scanning signals input by each sub-pixel in the second row of sub-pixels and each sub-pixel in the first row of sub-pixels are in different orders;

or, the scanning signals input by the sub-pixels in the first row of sub-pixels, the second row of sub-pixels and the fourth row of sub-pixels are in the same order, and the scanning signals input by the sub-pixels in the third row of sub-pixels and the sub-pixels in the fourth row of sub-pixels are in different orders.

For example, taking the structure shown in fig. 3 as an example, the subpixel row group 40a includes 4 rows of subpixels, and along the direction indicated by the broken line with an arrow in fig. 3, the order of inputting the scan signals to the two subpixels in the first row is from left to right, the order of inputting the scan signals to the two subpixels in the second row is from right to left, the order of inputting the scan signals to the two subpixels in the third row is from left to right, and the order of inputting the scan signals to the two subpixels in the fourth row is still from left to right.

Therefore, the order of the scanning signals input by each sub-pixel in the first row of sub-pixels, the third row of sub-pixels and the fourth row of sub-pixels is the same, and all the scanning signals are from left to right; the sequence of the scanning signals input by the sub-pixels in the second row of sub-pixels is different from that of the scanning signals input by the sub-pixels in the first row of sub-pixels.

Therefore, the switching times of data signals transmitted on the data lines can be reduced, the power consumption of the display panel is reduced, the sequence of scanning signals input by each row of sub-pixels in the sub-pixel row group can be set according to actual needs, and therefore the design flexibility is improved, and the display panel is suitable for the needs of various application scenes.

Of course, the above description only illustrates that the sub-pixel row group includes 4 rows of sub-pixels, and if the number of sub-pixel rows included in the sub-pixel row group is 3, 6, or 8, etc., the display panel can still be driven by the above driving method, so as to reduce the number of times of switching the data signals transmitted on the data lines and reduce the power consumption of the display panel.

Based on the same inventive concept, an embodiment of the present invention provides a display apparatus, such as the structural schematic diagram of the display apparatus shown in fig. 8, including the display panel X provided in the embodiment of the present invention.

In a specific implementation, the display device may be: any product or component with a display function, such as a mobile phone (as shown in fig. 8), a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. An array substrate, comprising:

sub-pixels arranged in an array;

the grid lines are arranged along the column direction and extend along the row direction, two grid lines are arranged between any two adjacent rows of sub-pixels, one side, away from the last row of sub-pixels, of the first row of sub-pixels and one side, away from the first row of sub-pixels, of the last row of sub-pixels are respectively provided with one grid line, and two sub-pixels, electrically connected with the same data line, in each row of sub-pixels are respectively and electrically connected with different grid lines; for each row of subpixels in the subpixel column group: at least part of two adjacent rows of sub-pixels are different from the grid line in connection sequence; in the column direction, a row of the sub-pixels includes a first side and a second side opposite to each other, wherein the connection order is: two sub-pixels in the same row in the sub-pixel column group are electrically connected with the grid line on the first side and the grid line on the second side in sequence; scanning signals are sequentially input to all the grid lines; and the connection sequence of the sub-pixels and the grid lines in different sub-pixel column groups is the same.

2. The array substrate of claim 1, wherein the subpixel column group comprises a plurality of subpixel row groups, the subpixel row group comprising at least three rows of subpixels;

for each row of subpixels in the subpixel row group: and the connection sequence of part of two adjacent rows of sub-pixels and the grid line is different, and only the connection sequence of two adjacent rows of sub-pixels and the grid line is the same.

3. The array substrate of claim 2, wherein two adjacent rows of sub-pixels in the same connection order as the gate lines are located at ends of the sub-pixel row group.

4. The array substrate of claim 3, wherein the subpixel row group comprises 2N rows of subpixels, N being an integer greater than 1.

5. The array substrate of claim 4, wherein N is 2.

6. The array substrate of claim 4, wherein the connection sequence of the subpixels in different subpixel row groups in the subpixel column group and the gate line is the same, and two adjacent subpixel row groups in the subpixel column group share one row of subpixels.

7. The array substrate of claim 1, wherein for each row of subpixels in the subpixel column group: the connection sequence of the interlaced sub-pixels and the grid lines is the same, and the connection sequence of the adjacent sub-pixels and the grid lines is opposite.

8. The array substrate of claim 1, wherein the polarities of the data signals received by the subpixels in adjacent subpixel column groups are opposite.

9. The array substrate of claim 1, wherein for each row of subpixels, two subpixels electrically connected with the same data line have different colors.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device characterized by comprising the display panel according to claim 10.

12. A driving method of a display panel according to claim 10, the driving method comprising:

wherein, the sequence of the input scanning signals is as follows: inputting the sequence of scanning signals by two sub-pixels positioned in the same row in the sub-pixel column group through electrically connected grid lines; scanning signals are sequentially input to all the grid lines; the sequence of the scanning signals input by the sub-pixels in different sub-pixel column groups is the same.

13. The driving method according to claim 12, wherein the subpixel column group includes a plurality of subpixel row groups, and when the subpixel row group includes four rows of subpixels, the driving method specifically includes:

for the group of subpixel rows in the group of subpixel rows:

the scanning signals input by each sub-pixel in the first row of sub-pixels, the third row of sub-pixels and the fourth row of sub-pixels are in the same order, and the scanning signals input by each sub-pixel in the second row of sub-pixels and the first row of sub-pixels are in different orders;

or, the scanning signals input by each sub-pixel in the first row of sub-pixels, the second row of sub-pixels and the fourth row of sub-pixels are in the same order, and the scanning signals input by each sub-pixel in the third row of sub-pixels and the fourth row of sub-pixels are in different orders.