CN108735139B

CN108735139B - Array substrate, driving method thereof, display panel and display device

Info

Publication number: CN108735139B
Application number: CN201810516767.8A
Authority: CN
Inventors: 王宝强; 徐姗姗
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2018-05-25
Filing date: 2018-05-25
Publication date: 2021-08-10
Anticipated expiration: 2038-05-25
Also published as: CN108735139A

Abstract

The invention discloses an array substrate, a driving method of the array substrate, a display panel and a display device, relates to the technical field of display, and aims to solve the problems of short charging time and insufficient charging rate of a traditional display product. In the array substrate, the charging circuit positioned in the 2N +1 th row is used for controlling and conducting connection between the corresponding row data line and the corresponding pixel electrode when the grid driving signal output by the grid line of the 2N +1 th row and the first charging control signal output by the first control line are both effective levels; the charging circuit positioned in the 2 Nth row is used for controlling and conducting connection between the corresponding row data line and the corresponding pixel electrode when the grid driving signal output by the grid line of the 2 Nth row and the second charging control signal output by the second control line are both effective levels; when the second charging control signal is at an active level, the first charging control signal is at an inactive level. The array substrate provided by the invention is used for displaying.

Description

Array substrate, driving method thereof, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a driving method of the array substrate, a display panel and a display device.

Background

With the continuous development of display technology, the variety of display products is more and more abundant, and the requirements for the display image quality of the display products are also higher and higher. The resolution ratio is an important parameter for measuring the quality of the display image of the display product, and is widely concerned by people. The display product with higher resolution can achieve better display effect, but the higher the resolution is, the shorter the time for charging the pixel unit is when the display product displays, and further the problem of insufficient charging rate is easy to occur.

In addition, when the existing display product displays, because the gate driving signal for controlling the writing of the data signal is not an ideal square wave signal, the signal has time delay during rising and falling, and in order to avoid the phenomenon of mis-charging in the process of charging the pixel unit, the data signal is correspondingly delayed for a period of time and then becomes an effective level, thereby further reducing the charging time. Therefore, the conventional display product has the problems of short charging time and insufficient charging rate.

Disclosure of Invention

The invention aims to provide an array substrate, a driving method thereof, a display panel and a display device, which are used for solving the problems of short charging time and insufficient charging rate of the traditional display product.

In order to achieve the above purpose, the invention provides the following technical scheme:

the first aspect of the invention provides an array substrate, which comprises a plurality of rows of grid lines, a plurality of columns of data lines, and a plurality of pixel units formed by crossing the plurality of rows of grid lines and the plurality of columns of data lines, wherein each pixel unit comprises a pixel electrode, and the array substrate further comprises a first control line and a second control line; the pixel unit also comprises a charging circuit, and the charging circuit corresponds to the pixel electrodes one by one; wherein the content of the first and second substances,

the charging circuits in the 2N +1 th row are respectively connected with the 2N +1 th row of gate lines, the corresponding column of data lines, the corresponding pixel electrodes and the first control line, and are used for controlling and conducting connection between the corresponding column of data lines and the corresponding pixel electrodes when the gate driving signals output by the 2N +1 th row of gate lines and the first charging control signals output by the first control line are both effective levels;

the charging circuits in the 2N row are respectively connected with the 2N row of grid lines, the corresponding column of data lines, the corresponding pixel electrodes and the second control lines, and are used for controlling and conducting connection between the corresponding column of data lines and the corresponding pixel electrodes when the grid driving signals output by the 2N row of grid lines and the second charging control signals output by the second control lines are both effective levels, wherein N is an integer;

when the second charging control signal is at an active level, the first charging control signal is at an inactive level.

Further, when the data lines in the corresponding columns output data voltages corresponding to the pixel units in the 2N +1 th row, the gate driving signals output by the first charging control signal and the gate lines in the 2N +1 th row are both active levels; when the data voltage corresponding to the 2N-th row of pixel units is output by the corresponding row of data lines, the second charging control signal and the gate driving signal output by the 2N-th row of gate lines are both effective levels.

Further, the charging circuit includes: a data write sub-circuit, a charge control sub-circuit, and a first node, wherein,

the data writing sub-circuit is respectively connected with the corresponding row grid line, the corresponding pixel electrode and the first node; the pixel electrode is used for controlling connection between the corresponding pixel electrode and the first node to be switched on or off under the control of the corresponding row of grid lines;

the charging control subcircuits positioned in the 2N +1 th row are respectively connected with the first control line, the corresponding column data line and the first node; the first control line is used for controlling connection between the corresponding column data line and the first node to be switched on or off;

the charging control subcircuits positioned in the 2N-th row are respectively connected with the second control line, the corresponding column data line and the first node; for controlling to switch on or off the connection between the respective column data line and the first node under the control of the second control line.

Furthermore, the data writing sub-circuit includes a first switch tube, a gate of the first switch tube is connected to the corresponding row gate line, a first pole of the first switch tube is connected to the corresponding pixel electrode, and a second pole of the first switch tube is connected to the first node.

Furthermore, the charge control sub-circuit in the 2N +1 th row includes a second switch tube, a gate of the second switch tube is connected to the first control line, a first pole of the second switch tube is connected to the first node, and a second pole of the second switch tube is connected to the corresponding column data line.

Furthermore, the charge control sub-circuit in the 2N-th row includes a third switching tube, a gate of the third switching tube is connected to the second control line, a first pole of the third switching tube is connected to the first node, and a second pole of the third switching tube is connected to the corresponding column data line.

Based on the technical solution of the array substrate, a second aspect of the present invention is a driving method of an array substrate, for driving the array substrate, the driving method including:

in a first charging period, both a gate driving signal output by the gate line of the 2N +1 th row and a first charging control signal output by the first control line are effective levels, and the charging circuit positioned in the 2N +1 th row controls and conducts connection between the corresponding row data line and the corresponding pixel electrode;

in a second charging period, both the gate driving signal output by the gate line in the 2 nth row and the second charging control signal output by the second control line are at an effective level, the charging circuit in the 2 nth row controls and conducts the connection between the corresponding row of data lines and the corresponding pixel electrode, and N is an integer.

Further, when the charging circuit includes: when the data is written into the sub-circuit, the charge control sub-circuit and the first node, the driving method specifically includes:

in the first charging period, the data writing sub-circuit in the 2N +1 th row controls to conduct the connection between the corresponding pixel electrode and the first node under the control of the gate line in the 2N +1 th row;

the charging control subcircuit positioned in the 2N +1 th row controls and conducts connection between the corresponding column data line and the first node under the control of the first control line;

in the second charging period, the data writing sub-circuit in the 2N row controls and conducts the connection between the corresponding pixel electrode and the first node under the control of the grid line in the 2N row;

and the charging control subcircuit positioned in the 2N-th row controls and conducts the connection between the corresponding column data line and the first node under the control of the second control line.

Based on the above technical solution of the array substrate, a third aspect of the present invention provides a display panel, including the above array substrate.

Based on the technical solution of the display panel, a fourth aspect of the present invention provides a display device, including the display panel.

In the technical scheme provided by the invention, the array substrate comprises a first control line, a second control line and a plurality of pixel units formed by crossing a plurality of rows of grid lines and a plurality of columns of data lines, and each pixel unit comprises a pixel electrode and a charging circuit, and when a grid driving signal output by the grid line of the 2N +1 row and a first charging control signal output by the first control line are both effective levels, the connection between the corresponding column of data lines and the corresponding pixel electrode of the 2N +1 row is controlled and conducted; the charging circuit in the 2N row can control and conduct connection between the corresponding column data line and the pixel electrode corresponding to the 2N row when the grid driving signal output by the grid line in the 2N row and the second charging control signal output by the second control line are both effective levels; when the second charging control signal is at an active level, the first charging control signal is at an inactive level; therefore, when the charging circuit in the 2N +1 th row controls to turn on the connection between the corresponding column data line and the corresponding pixel electrode in the 2N +1 th row, the charging circuit in the 2N +2 nd row and the charging circuit in the 2N +2 nd row can turn off the connection between the corresponding column data line and the corresponding pixel electrode in the 2N row and the 2N +2 nd row.

Therefore, in the technical scheme provided by the invention, when the pixel electrodes corresponding to the pixel units in the 2N +1 th row are charged, the pixel electrodes corresponding to the pixel units in the adjacent 2N th row and 2N +2 th row are not charged, and the phenomenon of wrong charging in the process of charging the pixel units is well avoided.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic diagram of a basic structure of an array substrate according to an embodiment of the present invention;

fig. 2 is a schematic view of another basic structure of an array substrate according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a data line delay inputting data voltages in the prior art;

FIG. 4 is a schematic diagram of the data line inputting data voltages in a non-delayed state according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another embodiment of an array substrate according to the present invention;

fig. 7 is a timing diagram illustrating a control process of the array substrate according to an embodiment of the invention;

FIG. 8 is a schematic diagram of a pixel unit in the prior art;

fig. 9 is a schematic structural diagram of a pixel unit according to an embodiment of the invention.

Reference numerals:

1-pixel cell, 10-pixel electrode,

2-charging circuit, 21-data writing sub-circuit,

22-charge control sub-circuit, a-first node,

a Gate-Gate line, a Data-Data line,

m1-first control line, M2-second control line,

t1-the first switch tube, T2-the second switch tube,

t3-third switch tube.

Detailed Description

In order to further explain the array substrate and the driving method thereof, the display panel, and the display device provided by the embodiments of the invention, the following description is made in detail with reference to the accompanying drawings.

Referring to fig. 1 and 5, an array substrate according to an embodiment of the present invention includes a plurality of rows of Gate lines Gate, a plurality of columns of Data lines Data, and a plurality of pixel units 1 formed by crossing the plurality of rows of Gate lines Gate and the plurality of columns of Data lines Data, where each pixel unit 1 includes a pixel electrode 10, and the array substrate further includes a first control line M1 and a second control line M2; the pixel unit 1 further comprises a charging circuit 2, and the charging circuit 2 corresponds to the pixel electrodes 10 one by one; the charging circuit 2 in the 2N +1 th row is respectively connected to the Gate line Gate2N +1 in the 2N +1 th row, the corresponding column Data line Data, the corresponding pixel electrode 10 and the first control line M1, and is configured to control and conduct connection between the corresponding column Data line Data and the corresponding pixel electrode 10 when the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row and the first charging control signal output by the first control line M1 are both active levels; the charging circuit 2 in the 2 nth row is respectively connected to the Gate line Gate in the 2 nth row, the corresponding column Data line Data, the corresponding pixel electrode 10, and the second control line M2, and is configured to control and conduct connection between the corresponding column Data line Data and the corresponding pixel electrode 10 when the Gate driving signal output by the Gate line Gate2N in the 2 nth row and the second charging control signal output by the second control line M2 are both active levels, where N is an integer; when the second charging control signal is at an active level, the first charging control signal is at an inactive level.

Specifically, when the array substrate works, a plurality of rows of Gate lines Gate are scanned one by one, and in the process of scanning each row of Gate lines Gate, a plurality of rows of Data lines Data input Data voltages into the corresponding pixel electrodes 10. In more detail, in the first charging period, that is, when a Data voltage is written into the pixel electrode 10 corresponding to the pixel unit 1 in the 2N +1 th row, the Gate line Gate2N +1 in the 2N +1 th row outputs a Gate driving signal, the first control line M1 outputs a first charging control signal, and the Gate driving signal and the first charging control signal output by the Gate line Gate2N +1 in the 2N +1 th row are both at an active level, under the control of the Gate driving signal and the first charging control signal output by the Gate line Gate2N +1 in the 2N +1 th row, the charging circuit 2 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10, so as to write the Data voltage into the pixel electrode 10 corresponding to the 2N +1 th row; meanwhile, in the first charging period, the second charging control signal output from the second control line M2 is at an inactive level. In the second charging period, that is, when the Data voltage is written into the pixel electrode 10 corresponding to the pixel unit 1 in the 2N row, the Gate line Gate2N in the 2N row outputs a Gate driving signal, the second control line M2 outputs a second charging control signal, and the Gate driving signal and the second charging control signal output by the Gate line Gate2N in the 2N row are both at an active level, and under the control of the Gate driving signal and the second charging control signal output by the Gate line Gate2N in the 2N row, the charging circuit 2 in the 2N row controls to turn on the connection between the Data line Data in the corresponding column and the corresponding pixel electrode 10, so as to write the Data voltage into the pixel electrode 10 corresponding to the 2N row; meanwhile, in the second charging period, the first charging control signal output by the first control line M1 is at an inactive level.

More specifically, as shown in fig. 7, a timing diagram corresponding to four rows of Gate lines Gate1-Gate4 is shown in fig. 7, and it can be seen from the figure that when the first row Gate line Gate1 and the third row Gate line Gate3 are at an active level, the first charging control signal output by the first control line M1 is at an active level, and when the first charging control signal output by the first control line M1 is at an active level, the second charging control signal output by the second control line M2 is at an inactive level.

According to the specific structure and the working process of the array substrate, the array substrate provided by the embodiment of the invention includes a first control line M1, a second control line M2, and a plurality of pixel units 1 formed by intersecting a plurality of rows of Gate lines Gate and a plurality of columns of Data lines Data, and each pixel unit 1 includes a pixel electrode 10 and a charging circuit 2, and when the charging circuit 2 located in the 2N +1 th row is capable of outputting a Gate driving signal on the 2N +1 th row of Gate lines Gate2N +1 and a first charging control signal output by the first control line M1 are both active levels, the connection between the corresponding column of Data lines Data and the pixel electrode 10 corresponding to the 2N +1 th row is controlled to be conducted; the charging circuit 2 in the 2 nth row is capable of controlling and turning on the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2 nth row when the Gate driving signal output by the Gate line Gate2N in the 2 nth row and the second charging control signal output by the second control line M2 are both active levels; when the second charging control signal is at an active level, the first charging control signal is at an inactive level; therefore, when the charging circuit 2 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N +1 th row, the charging circuit 2 in the 2N th row and the charging circuit 2 in the 2N +2 nd row can disconnect the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N th row and the 2N +2 nd row. Likewise, when the charging circuit 2 in the 2N-th row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N-th row, the charging circuit 2 in the 2N + 1-th row and the charging circuit 2 in the 2N-1-th row can turn off the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N + 1-th row and the 2N-1-th row.

As can be seen, in the array substrate provided in the embodiment of the present invention, when the pixel electrode 10 corresponding to the pixel unit 1 in the 2N +1 th row is charged, the pixel electrode 10 corresponding to the pixel unit 1 in the adjacent 2N th row and 2N +2 th row is not charged; when the pixel electrode 10 corresponding to the pixel unit 1 in the 2N-th row is charged, the pixel electrode 10 corresponding to the pixel unit 1 in the adjacent 2N-1-th row and 2N + 1-th row is not charged; therefore, when the pixel unit 1 in the array substrate provided by the embodiment of the invention is charged, a Data signal input by the column Data line Data does not need to be delayed, sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved.

Further, when the Data voltage corresponding to the pixel unit 1 in the 2N +1 th row is output by the corresponding column Data line Data, both the first charging control signal and the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row are active levels; when the Data voltage corresponding to the pixel unit 1 in the 2N row is output by the corresponding column Data line Data, both the second charging control signal and the Gate driving signal output by the Gate line Gate2N in the 2N row are active levels.

Specifically, when the first charging control signal output by the first control line M1 and the Gate driving signal output by the Gate line Gate2N +1 of the 2N +1 th row are both at an active level, the charging circuit 2 in the 2N +1 th row can control and conduct the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2N +1 th row, so when the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 of the 2N +1 th row, the first charging control signal and the Gate driving signal output by the Gate line Gate2N +1 of the 2N +1 th row are both at an active level, and when the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 of the 2N +1 th row, the charging circuit 2 in the 2N +1 th row can control and conduct the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2N +1 th row, so that the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 of the 2N +1 th row In the second row, the array substrate is always in a state of charging the pixel unit 1 in the 2N +1 th row. Similarly, when the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 in the 2N th row, the second charging control signal and the Gate driving signal output by the Gate line Gate2N in the 2N th row are both set to be active levels, so that when the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 in the 2N th row, the charging circuit 2 in the 2N th row can control and conduct the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2N th row, and thus the array substrate is always in the state of charging the pixel unit 1 in the 2N th row in the process that the corresponding column Data line Data outputs the Data voltage corresponding to the pixel unit 1 in the 2N th row.

As can be seen, in the array substrate provided in the above embodiment, in the whole process of outputting the Data voltage by the corresponding column Data line Data, the corresponding charging circuit 2 can control the corresponding column Data line Data and the corresponding pixel electrode 10 to be always in the conducting state, so as to maximally prolong the time for charging the pixel unit 1.

In more detail, as shown in fig. 3, B1 represents an ideal waveform of the Gate driving signal output by the Gate line Gate, and B2 represents an actual waveform of the Gate driving signal output by the Gate line Gate, in the prior art, in order to avoid a phenomenon of mis-charging during the process of charging the pixel unit, the Data line Data is delayed for a period of time C1 and then outputs the Data voltage, so that the charging time is reduced, as shown in fig. 3, C2 represents the charging time.

In the array substrate according to the embodiment of the invention, as shown in fig. 4, taking the active levels of the charging control signal (including the first charging control signal and the second charging control signal) and the Gate driving signal output by the Gate line Gate as high levels as an example, it can be seen from fig. 4 that during the period when the Data voltage is output by the corresponding column Data line Data, i.e., during the 1H period shown in the figure, the corresponding charging control signal and the Gate driving signal are both high levels, so that the charging time for the pixel unit 1 is a complete 1H period (including C1+ C2), and the charging rate is effectively improved. In addition, as shown in fig. 7, in the array substrate provided by the embodiment of the invention, the charging time for each row of pixel units 1 is a complete 1H time period.

Further, the structure of the charging circuit 2 is various, and a specific structure of the charging circuit 2 is given as an example, and the operation process thereof will be described in detail.

As shown in fig. 2, the charging circuit 2 includes: a data writing sub-circuit 21, a charging control sub-circuit 22 and a first node a, wherein the data writing sub-circuit 21 is respectively connected with the corresponding row Gate line Gate, the corresponding pixel electrode 10 and the first node a; the pixel electrode 10 is used for controlling to be connected or disconnected with the first node a under the control of the corresponding row of Gate lines Gate; the charge control sub-circuit 22 in the 2N +1 th row is connected to the first control line M1, the corresponding column Data line Data, and the first node a, respectively; for controlling to turn on or off the connection between the corresponding column Data line Data and the first node a under the control of the first control line M1; the charge control sub-circuit 22 in the 2 nth row is connected to the second control line M2, the corresponding column Data line Data, and the first node a, respectively; for controlling to turn on or off the connection between the corresponding column Data line Data and the first node a under the control of the second control line M2.

The working process of the charging circuit 2 with the above structure is as follows:

in the first charging period, the Gate line Gate2N +1 in the 2N +1 th row outputs a Gate driving signal, the first control line M1 outputs a first charging control signal, and the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row and the first charging control signal are both active levels, under the control of the first charging control signal, the charging control sub-circuit 22 in the 2N +1 th row controls and turns on the connection between the corresponding column Data line Data and the corresponding first node a, so as to write the Data voltage input by the corresponding column Data line Data into the corresponding first node a; under the control of the Gate driving signal output from the Gate line Gate2N +1 of the 2N +1 th row, the data writing sub-circuit 21 in the 2N +1 th row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a, so as to further write the data voltage written into the first node a into the corresponding pixel electrode 10, thereby realizing the charging of the pixel unit 1 in the 2N +1 th row.

In the second charging period, the Gate line Gate2N in the 2 nth row outputs a Gate driving signal, the second control line M2 outputs a second charging control signal, and the Gate driving signal and the second charging control signal output by the Gate line Gate2N in the 2 nth row are both active levels, under the control of the second charging control signal, the charging control sub-circuit 22 in the 2 nth row controls to turn on the connection between the corresponding column Data line Data and the corresponding first node a, so as to write the Data voltage input by the corresponding column Data line Data into the corresponding first node a; under the control of the Gate driving signal output from the Gate line Gate2N in the 2 nth row, the data writing sub-circuit 21 in the 2 nth row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a, so as to further write the data voltage written into the first node a into the corresponding pixel electrode 10, thereby realizing the charging of the pixel unit 1 in the 2 nth row.

As can be seen from the specific structure and operation process of the charging circuit 2, in the array substrate provided in the above embodiment, the charging circuit 2 includes the Data writing sub-circuit 21, the charging control sub-circuit 22 and the first node a, when the first charging control signal output by the first control line M1 is at an active level, the charging control sub-circuit 22 located in the 2N +1 th row is in an active state, and when the Gate driving signal output by the Gate line Gate2N +1 of the 2N +1 th row is at an active level, the Data writing sub-circuit 21 located in the 2N +1 th row is in an active state, so that the Data voltage input by the corresponding column Data line Data can be written into the pixel unit 1 corresponding to the 2N +1 th row; similarly, when the second charging control signal output by the second control line M2 is at an active level, the charging control sub-circuit 22 in the 2N-th row is in an operating state, and when the Gate driving signal output by the Gate line Gate2N in the 2N-th row is at an active level, the Data writing sub-circuit 21 in the 2N-th row is in an operating state, so that the Data voltage input by the corresponding column Data line Data can be written into the pixel unit 1 corresponding to the 2N-th row.

It can be seen that when writing data voltage into the pixel unit 1 corresponding to the 2N +1 th row, it is required to satisfy that the charge control sub-circuit 22 located in the 2N +1 th row and the data write sub-circuit 21 located in the 2N +1 th row are both in a working state; when writing data voltage into the pixel unit 1 corresponding to the 2N-th row, it needs to be satisfied that the charge control sub-circuit 22 located in the 2N-th row and the data write sub-circuit 21 located in the 2N-th row are both in a working state; when the second charging control signal is at an active level, the first charging control signal is at an inactive level; therefore, in the same period of time, writing of the data voltage to only the pixel cells 1 corresponding to the 2N +1 th row or writing of the data voltage to only the pixel cells 1 corresponding to the 2N th row can be realized without the occurrence of erroneous writing of the data voltage to the pixel cells 1 of the other rows. Therefore, when the pixel unit 1 in the array substrate provided by the embodiment of the invention is charged, the Data signal input by the column Data line Data does not need to be delayed, so that sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved.

Further, as shown in fig. 5 to 7, the data writing sub-circuit 21, the charge control sub-circuit 22 located in the 2N +1 th row, and the charge control sub-circuit 22 located in the 2N th row each have various structures, for example: the data writing sub-circuit 21 includes a first switch T1, a Gate of the first switch T1 is connected to the corresponding row Gate line Gate, a first pole of the first switch T1 is connected to the corresponding pixel electrode 10, and a second pole of the first switch T1 is connected to the first node a. The charge control sub-circuit 22 in the 2N +1 th row includes a second switch transistor T2, a gate of the second switch transistor T2 is connected to the first control line M1, a first pole of the second switch transistor T2 is connected to the first node a, and a second pole of the second switch transistor T2 is connected to the corresponding column Data line Data. The charge control sub-circuit 22 in the 2N row includes a third switch transistor T3, a gate of the third switch transistor T3 is connected to the second control line M2, a first pole of the third switch transistor T3 is connected to the first node a, and a second pole of the third switch transistor T3 is connected to the corresponding column Data line Data.

Specifically, when the data writing sub-circuit 21 is in an operating state, the first switching tube T1 can be turned on under the control of the corresponding row Gate line Gate, so as to connect the corresponding pixel electrode 10 with the corresponding first node a; when the charge control sub-circuit 22 in the 2N +1 th row is in an operating state, the second switch tube T2 can be turned on under the control of the first control line M1, so as to connect the corresponding column Data line Data to the corresponding first node a; when the charge control sub-circuit 22 in the 2N row is in an operating state, the third switching tube T3 can be turned on under the control of the second control line M2, so as to connect the corresponding column Data line Data to the corresponding first node a.

In more detail, as shown in fig. 8 and 9, fig. 8 is a schematic diagram of a structure in the prior art, and fig. 9 is a schematic diagram of a structure in the embodiment of the present invention, it can be seen that, in the prior art, a Data voltage inputted from a Data line Data is written into a Pixel only under the control of a first switching transistor T1, whereas in the embodiment of the present invention, a Data voltage inputted from a Data line Data needs to be written into a Pixel simultaneously under the common control of a second switching transistor T2, a third switching transistor T3, and a first switching transistor T1. Vcom in fig. 8 and 9 represents a common electrode terminal, and Cst and Ctc represent storage capacitances.

It should be noted that each of the above-mentioned switching transistors may be a thin film transistor, a field effect transistor or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of each switching tube except for the gate, one of the two poles is referred to as a first pole, and the other pole is referred to as a second pole. In practical operation, the first pole may be a drain, and the second pole may be a source; alternatively, the first pole may be a source and the second pole may be a drain.

In addition, as shown in fig. 5, a schematic structural diagram when the array substrate includes five rows of Gate lines Gate1-Gate5 and three columns of Data lines Data1-Data3 is given, and as shown in fig. 6, a schematic connection diagram of the first switch tube T1, the second switch tube T2 and the third switch tube T3 in one column of pixel units included in the array substrate is given.

It should be noted that, compared to the prior art, the array substrate provided in the above embodiment adds the first control line M1, the second control line M2, the second switch tube T2 and the third switch tube T3, when these added portions are fabricated, the second switch tube T2 and the third switch tube T3 may be fabricated at the same time when the first switch tube T1 is fabricated, and when the SD metal layer in the switch tube is fabricated, the first control line M1 and the second control line M2 may be formed at the same time through one patterning process, and the first control line M1 and the second control line M2 may be connected to the gates of the second switch tube T2 and the third switch tube T3 respectively by providing vias. Therefore, when the array substrate provided by the above embodiments is manufactured, an additional Mask process is not required. In addition, the first charge control signal output by the first control line M1 and the second charge control signal output by the second control line M2 may be both provided by an external printed circuit board.

In addition, the array substrate provided in the above embodiments only adds the first control line M1, the second control line M2, the second switch tube T2 and the third switch tube T3, compared with the prior art, and can be applied to all GOA products.

A second aspect of the present invention provides a driving method of an array substrate, for driving the array substrate provided in the foregoing embodiment, the driving method including:

in the first charging period, the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row and the first charging control signal output by the first control line M1 are both at an active level, and the charging circuit 2 in the 2N +1 th row controls and turns on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10;

specifically, in the first charging period, that is, when a Data voltage is written into the pixel electrode 10 corresponding to the pixel unit 1 in the 2N +1 th row, the Gate line Gate2N +1 in the 2N +1 th row outputs a Gate driving signal, the first control line M1 outputs a first charging control signal, and the Gate driving signal and the first charging control signal output by the Gate line Gate2N +1 in the 2N +1 th row are both at an active level, and under the control of the Gate driving signal and the first charging control signal output by the Gate line Gate2N +1 in the 2N +1 th row, the charging circuit 2 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line and the corresponding pixel electrode 10, so as to write the Data voltage into the pixel electrode 10 corresponding to the 2N +1 th row; meanwhile, in the first charging period, the second charging control signal output from the second control line M2 is at an inactive level.

In the second charging period, the Gate driving signal output by the Gate line Gate2N in the 2 nth row and the second charging control signal output by the second control line M2 are both active levels, the charging circuit 2 in the 2 nth row controls and turns on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10, where N is an integer.

Specifically, in the second charging period, that is, when a Data voltage is written into the pixel electrode 10 corresponding to the pixel unit 1 in the 2N row, the Gate line Gate2N in the 2N row outputs a Gate driving signal, the second control line M2 outputs a second charging control signal, and the Gate driving signal output by the Gate line Gate2N in the 2N row and the second charging control signal are both at an active level, under the control of the Gate driving signal output by the Gate line Gate2N in the 2N row and the second charging control signal, the charging circuit 2 in the 2N row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10, so as to write the Data voltage into the pixel electrode 10 corresponding to the 2N row; meanwhile, in the second charging period, the first charging control signal output by the first control line M1 is at an inactive level.

According to the specific overdrive process of the driving method, in the driving method of the array substrate provided in the embodiment of the invention, when the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row and the first charging control signal output by the first control line M1 are both at the valid level, the charging circuit 2 in the 2N +1 th row can control to turn on the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2N +1 th row; the charging circuit 2 in the 2 nth row is capable of controlling and turning on the connection between the corresponding column Data line Data and the pixel electrode 10 corresponding to the 2 nth row when the Gate driving signal output by the Gate line Gate2N in the 2 nth row and the second charging control signal output by the second control line M2 are both active levels; when the second charging control signal is at an active level, the first charging control signal is at an inactive level; therefore, when the charging circuit 2 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N +1 th row, the charging circuit 2 in the 2N th row and the charging circuit 2 in the 2N +2 nd row can disconnect the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N th row and the 2N +2 nd row. Likewise, when the charging circuit 2 in the 2N-th row controls to turn on the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N-th row, the charging circuit 2 in the 2N + 1-th row and the charging circuit 2 in the 2N-1-th row can turn off the connection between the corresponding column Data line Data and the corresponding pixel electrode 10 in the 2N + 1-th row and the 2N-1-th row.

It can be seen that in the driving method of the array substrate provided in the embodiment of the present invention, when the pixel electrode 10 corresponding to the pixel unit 1 in the 2N +1 th row is charged, the pixel electrode 10 corresponding to the pixel unit 1 in the adjacent 2N-th row and the 2N +2 nd row is not charged, and when the pixel electrode 10 corresponding to the pixel unit 1 in the 2N-th row is charged, the pixel electrode 10 corresponding to the pixel unit 1 in the adjacent 2N-1 th row and the 2N +1 th row is not charged; therefore, when the pixel unit 1 in the array substrate provided by the embodiment of the invention is charged, a Data signal input by the column Data line Data does not need to be delayed, sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved.

Further, when the charging circuit 2 includes: when the data is written into the sub-circuit 21, the charge control sub-circuit 22, and the first node a, the driving method provided by the above embodiment specifically includes:

in the first charging period, the data writing sub-circuit 21 in the 2N +1 th row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a under the control of the Gate line Gate2N +1 in the 2N +1 th row; the charge control sub-circuit 22 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line Data and the first node a under the control of the first control line M1;

specifically, in the first charging period, the Gate line Gate2N +1 in the 2N +1 th row outputs a Gate driving signal, the first control line M1 outputs a first charging control signal, and the Gate driving signal output by the Gate line Gate2N +1 in the 2N +1 th row and the first charging control signal are both at an active level, under the control of the first charging control signal, the charging control sub-circuit 22 in the 2N +1 th row controls to turn on the connection between the corresponding column Data line Data and the corresponding first node a, so as to write the Data voltage input by the corresponding column Data line Data into the corresponding first node a; under the control of the Gate driving signal output from the Gate line Gate2N +1 of the 2N +1 th row, the data writing sub-circuit 21 in the 2N +1 th row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a, so as to further write the data voltage written into the first node a into the corresponding pixel electrode 10, thereby realizing the charging of the pixel unit 1 in the 2N +1 th row.

In the second charging period, the data writing sub-circuit 21 in the 2 nth row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a under the control of the Gate line Gate2N in the 2 nth row; the charge control sub-circuit 22 in the 2N-th row controls to turn on the connection between the corresponding column Data line Data and the first node a under the control of the second control line M2.

Specifically, in the second charging period, the Gate line Gate2N in the 2 nth row outputs a Gate driving signal, the second control line M2 outputs a second charging control signal, and the Gate driving signal output by the Gate line Gate2N in the 2 nth row and the second charging control signal are both at an active level, under the control of the second charging control signal, the charging control sub-circuit 22 in the 2 nth row controls to turn on the connection between the corresponding column Data line Data and the corresponding first node a, so as to write the Data voltage input by the corresponding column Data line Data into the corresponding first node a; under the control of the Gate driving signal output from the Gate line Gate2N in the 2 nth row, the data writing sub-circuit 21 in the 2 nth row controls to turn on the connection between the corresponding pixel electrode 10 and the first node a, so as to further write the data voltage written into the first node a into the corresponding pixel electrode 10, thereby realizing the charging of the pixel unit 1 in the 2 nth row.

According to the driving method corresponding to the charging circuit 2 with the specific structure, in the driving method of the array substrate provided in the embodiment, when the first charging control signal output by the first control line M1 is at the active level, the charging control sub-circuit 22 located in the 2N +1 th row is in the active state, and when the Gate driving signal output by the Gate line Gate2N +1 of the 2N +1 th row is at the active level, the Data writing sub-circuit 21 located in the 2N +1 th row is in the active state, so that the Data voltage input by the corresponding column Data line Data can be written into the pixel unit 1 corresponding to the 2N +1 th row; similarly, when the second charging control signal output by the second control line M2 is at an active level, the charging control sub-circuit 22 in the 2N-th row is in an operating state, and when the Gate driving signal output by the Gate line Gate2N in the 2N-th row is at an active level, the Data writing sub-circuit 21 in the 2N-th row is in an operating state, so that the Data voltage input by the corresponding column Data line Data can be written into the pixel unit 1 corresponding to the 2N-th row.

It can be seen that when writing data voltage into the pixel unit 1 corresponding to the 2N +1 th row, it is required to satisfy that the charge control sub-circuit 22 located in the 2N +1 th row and the data write sub-circuit 21 located in the 2N +1 th row are both in a working state; when writing data voltage into the pixel unit 1 corresponding to the 2N-th row, it needs to be satisfied that the charge control sub-circuit 22 located in the 2N-th row and the data write sub-circuit 21 located in the 2N-th row are both in a working state; when the second charging control signal is at an active level, the first charging control signal is at an inactive level; therefore, in the same period of time, writing of the data voltage to only the pixel cells 1 corresponding to the 2N +1 th row or writing of the data voltage to only the pixel cells 1 corresponding to the 2N th row can be realized without the occurrence of erroneous writing of the data voltage to the pixel cells 1 of the other rows. Therefore, when the driving method of the array substrate provided by the embodiment of the invention is adopted to charge the pixel unit 1, the Data signal input by the column Data line Data does not need to be delayed, so that sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved.

The embodiment of the invention also provides a display panel which comprises the array substrate provided by the embodiment.

Because the array substrate provided by the embodiment does not charge the pixel electrodes 10 corresponding to the pixel units 1 in the adjacent 2N-th row and 2N +2 nd row when charging the pixel electrodes 10 corresponding to the pixel units 1 in the 2N +1 th row, the phenomenon of wrong charging in the process of charging the pixel units 1 is avoided, and thus, when charging the pixel units 1 in the array substrate provided by the embodiment, the Data signals input by the column Data lines Data do not need to be delayed, sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved. Therefore, the display panel provided by the embodiment of the invention has the same effects when the display panel comprises the array substrate provided by the embodiment, and details are not repeated herein.

The embodiment of the invention also provides a display device which comprises the display panel provided by the embodiment.

Because the display panel provided by the embodiment can avoid the phenomenon of wrong charging in the process of charging the pixel unit 1, when the pixel unit 1 in the display panel is charged, a Data signal input by a column Data line Data does not need to be delayed, sufficient charging time is ensured, and the problems of less charging time and insufficient charging rate of the traditional display product are well solved. Therefore, the display device provided by the embodiment of the invention has the same effects as the display panel provided by the embodiment, and details are not repeated here.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. An array substrate comprises a plurality of rows of grid lines, a plurality of columns of data lines and a plurality of pixel units formed by crossing the plurality of rows of grid lines and the plurality of columns of data lines, wherein each pixel unit comprises a pixel electrode; the pixel unit also comprises a charging circuit, and the charging circuit corresponds to the pixel electrodes one by one; wherein the content of the first and second substances,

when the second charging control signal is at an active level, the first charging control signal is at an inactive level;

the charging circuit includes: a data write sub-circuit, a charge control sub-circuit, and a first node, wherein,

2. The array substrate of claim 1, wherein the first charge control signal and the gate driving signal output by the gate line in the 2N +1 th row are both active levels when the corresponding column data line outputs the data voltage corresponding to the pixel unit in the 2N +1 th row; when the data voltage corresponding to the 2N-th row of pixel units is output by the corresponding row of data lines, the second charging control signal and the gate driving signal output by the 2N-th row of gate lines are both effective levels.

3. The array substrate of claim 1,

the data writing sub-circuit comprises a first switch tube, the grid electrode of the first switch tube is connected with the corresponding row grid line, the first pole of the first switch tube is connected with the corresponding pixel electrode, and the second pole of the first switch tube is connected with the first node.

4. The array substrate of claim 1,

the charging control sub-circuit positioned on the 2N +1 th row comprises a second switch tube, the grid electrode of the second switch tube is connected with the first control line, the first pole of the second switch tube is connected with the first node, and the second pole of the second switch tube is connected with the corresponding column data line.

5. The array substrate of claim 1,

the charging control sub-circuit positioned on the 2N row comprises a third switching tube, the grid electrode of the third switching tube is connected with the second control line, the first pole of the third switching tube is connected with the first node, and the second pole of the third switching tube is connected with the corresponding row data line.

6. A driving method of an array substrate, for driving the array substrate according to any one of claims 1 to 5, the driving method comprising:

in a second charging period, both the gate driving signal output by the gate line in the 2 nth row and the second charging control signal output by the second control line are at effective levels, the charging circuit in the 2 nth row controls and conducts the connection between the corresponding row of data lines and the corresponding pixel electrode, and N is an integer;

when the charging circuit comprises: when the data is written into the sub-circuit, the charge control sub-circuit and the first node, the driving method specifically includes:

7. A display panel comprising the array substrate according to any one of claims 1 to 5.

8. A display device characterized by comprising the display panel according to claim 7.