CN110689848B

CN110689848B - Display device and driving method

Info

Publication number: CN110689848B
Application number: CN201911256185.1A
Authority: CN
Inventors: 李新国; 许晨; 王漪
Original assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY; BOE Technology Group Co Ltd
Current assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY; BOE Technology Group Co Ltd
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-04-14
Anticipated expiration: 2039-12-10
Also published as: CN110689848A

Abstract

The invention provides a display device and a driving method. The display device is provided with a display area, a driving circuit area and a transition area positioned between the display area and the driving circuit area; in the first direction, the width of the transition region is smaller than that of the driving circuit region, and the width of the transition region is smaller than that of the display region; the display device also comprises a plurality of pixel circuits arranged in an array in the display area; the pixel circuit comprises a first light-emitting element and a pixel driving circuit which are electrically connected with each other, wherein the pixel driving circuit is used for providing driving current for the first light-emitting element; the first light emitting element includes a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode; the first electrodes included in different ones of the first light emitting elements are spaced apart from each other. The invention arranges the transition area between the display area and the driving circuit area, and the virtual light-emitting element can be arranged in the transition area to improve the uniformity of light-emitting display.

Description

Display device and driving method

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display device and a driving method.

Background

At present, display technologies are widely applied to displays of televisions, mobile phones and public information, display panels for displaying pictures are also various, and rich and colorful pictures can be displayed, however, both thin film transistor liquid crystal display panels and organic electroluminescence display panels need to be controlled by a driving integrated circuit, and the driving integrated circuit controls the display panels to realize the functions of line-by-line scanning and frame-by-frame refreshing, so that image data input to the display panels can be refreshed in real time, and dynamic display is realized. In the prior art, a display device has a display area and a driving area, but the phenomenon of uneven film formation of an organic light emitting thin film occurs at the boundary between the display area and the driving area.

Disclosure of Invention

The invention mainly aims to provide a display device, a driving method, a light-emitting control circuit and the display device, which solve the problem that the existing display device causes uneven film formation of an organic light-emitting thin film at the boundary of a display area and a driving area.

In order to achieve the above object, the present invention provides a display device having a display area, a driving circuit area, and a transition area between the display area and the driving circuit area;

in the first direction, the width of the transition region is smaller than that of the driving circuit region, and the width of the transition region is smaller than that of the display region;

the display device also comprises a plurality of pixel circuits arranged in an array in the display area; the pixel circuit comprises a first light-emitting element and a pixel driving circuit which are electrically connected with each other, wherein the pixel driving circuit is used for providing a driving current for the first light-emitting element;

the first light-emitting element includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode; the area of the second electrode is larger than that of the first electrode;

the first electrodes included in different ones of the first light emitting elements are spaced apart from each other.

In practice, the display device of the present invention further includes a display substrate, wherein the pixel circuit is disposed on the display substrate;

the area of the orthographic projection of the pixel driving circuit on the display substrate is different from the area of the orthographic projection of the first electrode on the display substrate.

In practice, the display device of the present invention further comprises a light emitting control circuit disposed in the driving circuit region;

the light-emitting control circuit comprises a plurality of stages of shift register units;

and the output end of the shift register unit passes through the transition region and is electrically connected with the corresponding row of pixel driving circuits in the display region so as to provide a light-emitting control signal for the corresponding row of pixel driving circuits.

In practice, the display device of the present invention further comprises a second light emitting element disposed in the transition region; the structure of the second light-emitting element is the same as that of the first light-emitting element; the second light-emitting element includes a light-emitting layer;

the second light emitting element includes a light emitting layer having the same area as that of the first light emitting element.

In practice, the shift register unit comprises an input terminal, a first node control circuit, a first storage capacitor circuit, a first clock access control circuit, a second node control circuit, a third node control circuit, an output circuit and a light-emitting control signal output terminal, wherein,

the first node control circuit is used for controlling the first node to be electrically connected with the input end under the control of a first clock signal and controlling the first node to be electrically connected with a first voltage end under the control of the potential of a third node and a second clock signal;

a first end of the first storage capacitor circuit is electrically connected with the first node;

the first clock access control circuit is used for controlling the second end of the first storage capacitor circuit to be electrically connected with the second clock signal end under the control of the potential of the first node;

the third node control circuit is used for controlling the electric connection between a third node and a second voltage end under the control of a first clock signal, controlling the electric connection between the third node and the first clock signal end under the control of the electric potential of the first node, and controlling the electric potential of the third node;

the second node control circuit is used for controlling the potential of the second node under the control of the potential of the third node and a second clock signal and controlling the electrical connection between the second node and the first voltage end under the control of the potential of the first node;

the output circuit is used for controlling generation and outputting a light-emitting control signal through a light-emitting control signal output end under the control of the electric potential of the first node and the electric potential of the second node.

In practice, the output circuit is used for providing the light-emitting control signal to a control electrode of a light-emitting control transistor in the pixel circuit so as to control the light-emitting control transistor to be turned off in a first stage;

the first phase lasts longer than the period of the first clock signal, and the first phase lasts longer than the period of the second clock signal.

In practice, the first clock signal and the second clock signal have a first time period with opposite phases and a second time period with the same phase;

the second time period is adjacent to the first time period;

in the second period, both the potential of the first clock signal and the potential of the second clock signal are at the first level.

In practice, the first clock access control circuit comprises a first clock access control transistor;

the control electrode of the first clock access control transistor is electrically connected with the first node, the first electrode of the first clock access control transistor is electrically connected with the second end of the first storage capacitor circuit, and the second electrode of the first clock access control transistor is electrically connected with the second clock signal end.

In implementation, the third node control circuit comprises a first control circuit and a second storage capacitor circuit;

the first control circuit is used for controlling the electric connection between a third node and a second voltage end under the control of a first clock signal and controlling the electric connection between the third node and the first clock signal end under the control of the electric potential of the first node;

the first end of the second storage capacitor circuit is electrically connected with the third node, and the second end of the second storage capacitor circuit is electrically connected with the second clock signal end.

In implementation, the display device of the invention further comprises a second clock access control circuit;

the second end of the second storage capacitor circuit is electrically connected with the second clock signal end through the second clock access control circuit; the second clock access control circuit is used for controlling the second end of the second storage capacitor circuit to be electrically connected with the second clock signal end under the control of the potential of a third node.

In implementation, the second clock access control circuit comprises a second clock access control transistor;

the control electrode of the second clock access control transistor is electrically connected with the third node, the first electrode of the second clock access control transistor is electrically connected with the second clock signal end, and the second electrode of the second clock access control transistor is electrically connected with the second end of the second storage capacitor circuit.

the first end of the second storage capacitor circuit is electrically connected with the third node, and the second end of the second storage capacitor circuit is electrically connected with the control node.

In practice, the first control circuit includes a first control transistor and a second control transistor;

a control electrode of the first control transistor is electrically connected with the first node, a first electrode of the first control transistor is electrically connected with the third node, and a second electrode of the first control transistor is electrically connected with a first clock signal end;

the control electrode of the second control transistor is electrically connected with the first clock signal end, the first electrode of the second control transistor is electrically connected with the second voltage end, and the second electrode of the second control transistor is electrically connected with the third node.

In practice, the first control transistor is a double-gate transistor.

In practice, the second node control circuit includes a second control circuit, a third control circuit, a fourth control circuit and a third storage capacitor circuit;

the second control circuit is used for enabling the control node to be electrically connected with the second voltage end under the control of the potential of the third node;

the third control circuit is used for controlling the electrical connection between the control node and the second node under the control of a second clock signal;

the fourth control circuit is used for controlling the second node to be electrically connected with the first voltage end under the control of the potential of the first node;

the first end of the third storage capacitor circuit is electrically connected with the second node, and the second end of the third storage capacitor circuit is electrically connected with the first voltage end.

In practice, the second control circuit includes a third control transistor, the third control circuit includes a fourth control transistor, and the fourth control circuit includes a fifth control transistor;

a control electrode of the third control transistor is electrically connected with the third node, a first electrode of the third control transistor is electrically connected with the second voltage end, and a second electrode of the third control transistor is electrically connected with the control node;

a control electrode of the fourth control transistor is electrically connected with a second clock signal end, a first electrode of the fourth control transistor is electrically connected with the control node, and a second electrode of the fourth control transistor is electrically connected with the second node;

a control electrode of the fifth control transistor is electrically connected to the first node, a first electrode of the fifth control transistor is electrically connected to the second node, and a second electrode of the fifth control transistor is electrically connected to the first voltage terminal.

the second control circuit is used for electrically connecting the control node and the second clock signal end under the control of the potential of the third node;

a control electrode of the third control transistor is electrically connected with the third node, a first electrode of the third control transistor is electrically connected with the second clock signal end, and a second electrode of the third control transistor is electrically connected with the control node;

In practice, the first node control circuit includes a sixth control transistor, a seventh control transistor, and an eighth control transistor;

a control electrode of the sixth control transistor is electrically connected with a first clock signal end, a first electrode of the sixth control transistor is electrically connected with an input end, and a second electrode of the sixth control transistor is electrically connected with the first node;

a control electrode of the seventh control transistor is electrically connected with a second electrode of the eighth control transistor, a first electrode of the seventh control transistor is electrically connected with a first voltage end, and a second electrode of the seventh control transistor is electrically connected with the first node;

and the control electrode of the eighth control transistor is electrically connected with the third node, and the first electrode of the eighth control transistor is electrically connected with the second clock signal end.

a control electrode of the seventh control transistor is electrically connected with a second clock signal end, a first electrode of the seventh control transistor is electrically connected with a second electrode of the eighth control transistor, and the second electrode of the seventh control transistor is electrically connected with the first node;

and a control electrode of the eighth control transistor is electrically connected with the third node, and a first electrode of the eighth control transistor is electrically connected with the first voltage end.

In practice, the output circuit includes a first output transistor and a second output transistor;

the control electrode of the first output transistor is electrically connected with the second node, the first electrode of the first output transistor is electrically connected with a first voltage end, and the second electrode of the first output transistor is electrically connected with a light-emitting control signal output end;

the control electrode of the second output transistor is electrically connected with the first node, the first electrode of the second output transistor is electrically connected with the light-emitting control signal output end, and the second electrode of the second output transistor is electrically connected with a second voltage end.

The invention also provides a driving method applied to the display device, and the driving method comprises the following steps:

the first node control circuit controls the first node to be electrically connected with the input end under the control of a first clock signal, and controls the first node to be electrically connected with a first voltage end under the control of the potential of a third node and a second clock signal so as to control the potential of the first node;

when the first node control circuit controls the electric potential of the first node to be at a first level, the first clock access control circuit controls the second end of the first storage capacitor circuit to be disconnected from the second clock signal end under the control of the electric potential of the first node;

when the first node control circuit controls the electric potential of the first node to be at the second level, the first clock access control circuit controls the second end of the first storage capacitor circuit to be electrically connected with the second clock signal end under the control of the electric potential of the first node.

In implementation, the third node control circuit comprises a first control circuit and a second storage capacitor circuit; the shift register unit also comprises a second clock access control circuit; the driving method further includes:

the third node control circuit controls the third node to be electrically connected with the second voltage end under the control of a first clock signal, controls the third node to be electrically connected with the first clock signal end under the control of the potential of the first node, and controls the potential of the third node;

when the third node control circuit controls the potential of the third node to be a first level, the second clock access control circuit controls the second end of the second storage capacitor circuit to be disconnected from the second clock signal end under the control of the potential of the third node;

when the third node control circuit controls the electric potential of the third node to be at the second level, the second clock access control circuit controls the second end of the second storage capacitor circuit to be electrically connected with the second clock signal end under the control of the electric potential of the third node.

When the LED lamp is implemented, the light-emitting control period comprises an input stage, a first output stage, a second output stage, a third output stage, a first reset stage and a second reset stage which are sequentially arranged; the driving method includes:

in the input stage, a first level is input at the input end, the first node control circuit controls the potential of a first node to be the first level, the output circuit controls the light-emitting control signal output end and the second voltage end to be disconnected, and the first clock access control circuit controls the second end of the first storage capacitor circuit and the second clock signal end to be disconnected; the third node control circuit controls the potential of the third node to be a second voltage, and the second node control circuit controls the second node to be in a floating state;

in the first output stage, the input end inputs a first level, and the third node control circuit controls the potential of the third node to be a second level; the first node control circuit controls the potential of the first node to be a first voltage according to a second clock signal and the potential of a third node; the second node control circuit controls the potential of the second node to be a second voltage under the control of a second clock signal; the first clock access control circuit controls the second end of the first storage capacitor circuit to be disconnected with the second clock signal end under the control of the potential of the first node; the output circuit controls the light-emitting control signal output end to be electrically connected with the first voltage end under the control of the potential of the second node;

in the second output stage, the input end inputs a first level, and the first node control circuit controls the potential of the first node to be the first level; the first clock access control circuit controls the second end of the first storage capacitor circuit to be disconnected with the second clock signal end under the control of the potential of the first node; the third node control circuit controls the potential of the third node to be a second voltage; the second node control circuit controls the second node to be in a floating state; the output circuit controls the light-emitting control signal output end to be electrically connected with the first voltage end under the control of the potential of the second node;

in a third output stage, a second level is input into the input end, and the third node control circuit controls the potential of the third node to be a second voltage; the first node control circuit controls and maintains the electric potential of the first node as a first voltage, and the second node control circuit controls and maintains the electric potential of the second node as a second voltage; the first clock access control circuit controls the second end of the first storage capacitor circuit to be disconnected with the second clock signal end under the control of the potential of the first node; the output circuit controls the light-emitting control signal output end to be electrically connected with the first voltage end under the control of the potential of the second node;

in a first reset stage, a second level is input to the input end, and the first node control circuit controls the potential of the first node to be the second level; the first clock access control circuit controls the second end of the first storage capacitor circuit to be electrically connected with the second clock signal end under the control of the potential of the first node; the third node control circuit controls the potential of the third node to be a second voltage under the control of the first clock signal; the second node control circuit controls the potential of the second node to be a first voltage; the output circuit controls the light-emitting control signal output end to be electrically connected with the second voltage end under the control of the potential of the first node;

in a second reset stage, a second level is input at the input end, the first node control circuit controls and maintains the potential of the first node as the second level, and the third node control circuit controls the potential of the third node as the first level; the second node control circuit controls the potential of the second node to be a first voltage; the first clock access control circuit controls the second end of the first storage capacitor circuit to be electrically connected with the second clock signal end under the control of the potential of the first node; the third node control circuit controls the potential of the third node to be a first level to reset the potential of the third node.

Compared with the prior art, the display device and the driving method provided by the invention have the advantages that the transition area is arranged between the display area and the driving circuit area, the width of the transition area is set to be smaller, and the virtual light-emitting element can be arranged in the transition area, so that the uniformity of light-emitting display is improved.

Drawings

FIG. 1 is a schematic diagram of a display device having a display area, a transition area and a driving circuit area according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of one embodiment of a pixel circuit;

fig. 3 is a schematic diagram of a layout implementation of transistors and storage capacitors in a pixel circuit included in a display device according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a layout implementation of an anode, a transistor and a storage capacitor in a pixel circuit included in a display device according to an embodiment of the present invention;

FIG. 5 is a block diagram of a shift register unit in a display device according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating the operation of a shift register unit in a display device according to an embodiment of the present invention;

FIG. 7 is a block diagram of a shift register unit in a display device according to another embodiment of the present invention;

FIG. 8 is a block diagram of a shift register unit in a display device according to still another embodiment of the present invention;

fig. 9 is a structural diagram of a shift register unit in a display device according to still another embodiment of the present invention;

fig. 10 is a structural diagram of a shift register unit in a display device according to still another embodiment of the present invention;

FIG. 11 is a block diagram of a shift register unit in a display device according to another embodiment of the present invention;

fig. 12 is a structural diagram of a shift register unit in a display device according to still another embodiment of the present invention;

fig. 13 is a structural diagram of a shift register unit in a display device according to still another embodiment of the present invention;

FIG. 14 is a circuit diagram of a first embodiment of a shift register unit in a display device according to the present invention;

FIG. 15 is a timing diagram illustrating operation of a shift register unit in a display device according to an embodiment of the present invention;

FIG. 16 is a circuit diagram of a second embodiment of a shift register unit in a display device according to the present invention;

FIG. 17 is a circuit diagram of a third embodiment of a shift register unit in a display device according to the present invention;

FIG. 18 is a circuit diagram of a fourth embodiment of a shift register unit in a display device according to the present invention;

FIG. 19 is a circuit diagram of a fifth embodiment of a shift register unit in a display device according to the present invention;

FIG. 20 is a circuit diagram of a shift register unit according to a sixth embodiment of the present invention;

fig. 21 is a structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The display device provided by the embodiment of the invention is provided with a display area, a driving circuit area and a transition area positioned between the display area and the driving circuit area;

The display device provided by the embodiment of the invention is provided with the transition area between the display area and the driving circuit area, the width of the transition area is set to be smaller, and the virtual light-emitting element can be arranged in the transition area so as to improve the uniformity of light-emitting display.

In an embodiment of the present invention, the display device may include a plurality of rows of gate lines, a plurality of rows of light-emitting control lines, and a plurality of columns of data lines, where the plurality of rows of gate lines and the plurality of columns of data lines enclose a plurality of rows and a plurality of columns of pixel regions, and the pixel circuits may be disposed in the pixel regions, but not limited thereto.

In the embodiment of the present invention, the first direction may be a direction substantially parallel to the gate line, but is not limited thereto. And the light emission control line may be substantially parallel to the gate line.

The first direction substantially parallel to the gate line may be: an included angle between a straight line of the first direction and the gate line is greater than or equal to 0 degree and less than or equal to 20 degrees, but not limited thereto. The included angle between the straight line of the first direction and the grid line can be as follows: and the straight line of the first direction intersects with the grid line to form an acute angle.

The light emitting control line substantially parallel to the gate line may be: the included angle between the light-emitting control line and the gate line is greater than or equal to 0 degree and less than or equal to 20 degrees, but not limited thereto. The included angle between the light-emitting control line and the gate line may be: and the light-emitting control line and the grid line intersect to form an acute angle.

In the embodiment of the present invention, the first electrodes may have a certain pattern, and the first electrodes included in different first light emitting elements may be spaced from each other.

In the embodiment of the present invention, the first electrode may be an anode, and the second electrode may be a cathode, but not limited thereto.

In the embodiment of the present invention, the display device may include a first light emitting element having a plurality of colors, for example, the first light emitting element may be a red light emitting element, a green light emitting element, or a blue light emitting element; alternatively, the first light emitting element may be a red light emitting element, a green light emitting element, a blue light emitting element, or a white light emitting element, but not limited thereto.

Specifically, the display device according to the embodiment of the present invention may further include a display substrate, wherein the pixel circuit is disposed on the display substrate;

Specifically, the display device according to the embodiment of the present invention may further include a light emitting control circuit disposed in the driving circuit region;

In a specific implementation, the display device of the present invention may further include a second light emitting element disposed in the transition region; the structure of the second light-emitting element is the same as that of the first light-emitting element; the second light-emitting element includes a light-emitting layer;

the second light emitting element includes a light emitting layer having the same area as that of the first light emitting element to improve display unevenness of the first light emitting element.

In a specific embodiment, the first light-emitting element and the second light-emitting element are formed by depositing a light-emitting material through the mask opening. When the display device performs a display operation, the first light emitting element emits light, and the second light emitting element does not emit light.

When a display panel is manufactured, if the second light-emitting elements are not manufactured at the same time as the first light-emitting elements but the first light-emitting elements are manufactured in a plurality of rows and a plurality of columns only in the display region, the film thickness and the performance of the light-emitting layer of the first light-emitting element are greatly different from those of the light-emitting layer of the first light-emitting element in the middle of the display region at the extreme edge of the display region, and display uniformity is affected. Based on this, in the embodiment of the invention, the second light emitting element is manufactured in the transition region, the structure of the second light emitting element is the same as that of the first light emitting element, and the area of the light emitting layer of the second light emitting element is the same as that of the light emitting layer of the first light emitting element, that is, the first light emitting element and the second light emitting element are manufactured simultaneously through one process, and the second light emitting element is controlled not to emit light when the display device performs the display operation, so that the difference between the film thickness and the performance of the first light emitting element arranged at the edge of the display region and the film thickness and the performance of the other first light emitting elements in the display region is not large, and the display uniformity of the first light emitting element is improved. And because the second light-emitting element does not emit light when the display device performs a display operation, even if the film thickness and performance of the second light-emitting element are greatly different from those of the first light-emitting element, the display uniformity is not affected.

In an embodiment of the present invention, the second light emitting element may be a dummy light emitting element.

As shown in fig. 1, the display device according to the embodiment of the invention has a display area AA, a first driving circuit area AD1, a second driving circuit area AD2, a first transition area AG1 between the display area AA and the first driving circuit area AD1, and a second transition area AG2 between the display area AA and the second driving circuit area AD 2;

a plurality of rows and columns of pixel driving circuits are arranged in the display area AA, and the display device comprises a plurality of rows of light-emitting control lines and a plurality of columns of data lines;

in the transverse direction, the width d1 of the first transition area AG1 is smaller than the width d2 of the first driving circuit area AD1, the width d1 of the first transition area AG1 is smaller than the width d0 of the display area AA, the width d3 of the second transition area AG2 is smaller than the width d4 of the second driving circuit area AD2, and the width d3 of the second transition area AG2 is smaller than the width d0 of the display area AA;

in the display area AA, a pixel circuit of an nth row and an mth column is marked with Pnm, a light-emitting control line of the nth row is marked with EMn, a data line of the mth column is marked with Dm, De1n in a first transition area AG1 is an nth left virtual light-emitting element, De2n in a second transition area AG2 is an nth right virtual light-emitting element, and m and n are positive integers;

in the first driving circuit area AD1, a first light emission control circuit is denoted by reference numeral S1, and a second light emission control circuit is denoted by reference numeral S2;

the first light emitting control circuit S1 provides corresponding light emitting control signals for a plurality of rows of light emitting control lines from the left side, and the second light emitting control circuit S2 provides corresponding light emitting control signals for a plurality of rows of light emitting control lines from the right side;

in fig. 1, a first stage shift register unit denoted by ESZ1 and included at S1, a second stage shift register unit denoted by ESZ2 and included at S1, an N-1 stage shift register unit denoted by ESZN-1 and included at S1, and an N stage shift register unit denoted by ESZN and included at S1; n is an integer greater than 1;

in fig. 1, a first stage shift register unit denoted by ESR1 and included at S2, a second stage shift register unit denoted by ESR2 and included at S2, an N-1 stage shift register unit denoted by ESRN-1 and included at S2, and an N stage shift register unit denoted by ESRN and included at S1.

In fig. 1, in the display area AA, a pixel circuit is shown in a box, and in the first transition area AG1 and the second transition area AG2, a dummy light emitting element is shown by oblique lines.

In an embodiment of the present invention, the display device may be an organic electroluminescent display device including an organic electroluminescent display panel, and in a pixel circuit of the organic electroluminescent display panel, the first light emitting element may be an organic light emitting element, and the driving transistor is connected to the organic light emitting element and outputs a driving current to the organic light emitting element under control of a data signal, a gate driving signal, a light emission control signal, and the like, so as to drive the organic light emitting element to emit light.

Specifically, the organic light emitting element may be, for example, an organic light emitting diode, but is not limited thereto.

In a specific implementation, the organic electroluminescent display panel may include a plurality of rows of gate lines, a plurality of columns of data lines, voltage lines, light emitting control lines, and a plurality of pixel circuits arranged in an array; each pixel circuit includes a pixel driving circuit and a first light emitting element; the pixel driving circuit can be electrically connected with a corresponding row grid line, a corresponding column data line, a corresponding row light-emitting control line and a voltage line respectively, and the organic light-emitting element is controlled to emit light according to the data voltage on the corresponding column data line under the control of the gate driving signal on the corresponding row grid line and the light-emitting control signal on the corresponding row light-emitting control line.

As shown in fig. 2, an embodiment of the pixel circuit may include a first light emitting element E1, a driving transistor M1, a data writing transistor M2, a compensation transistor M3, a first light emitting control transistor M4, a second light emitting control transistor M5, a first reset transistor M6, a second reset transistor M7, and a storage capacitor Cst; in fig. 2, a power voltage line is denoted by ELVDD, a low voltage line is denoted by ELVSS, and an initial voltage line is denoted by Vint; in the embodiment shown in fig. 2, the voltage lines include the power voltage line ELVDD, the low voltage line ELVSS, and the initial voltage line Vint;

in fig. 2, a gate line labeled Gn is an nth row, a reset line labeled Resetn +1 is an n +1 th row, and a data line labeled Dm is an mth column;

the first light-emitting element E1 is an organic light-emitting diode;

a first pole of the driving transistor M1 is electrically connected to the power voltage line ELVDD through the first light emission controlling transistor M4; a second pole of the driving transistor M1 is electrically connected to the anode of the first light emitting element E1 through the second light emission controlling transistor M5;

a control electrode of the first light emission controlling transistor M4 and a control electrode of the second light emission controlling transistor M5 are electrically connected to an nth row light emission control line EMn;

a control electrode of M2 is electrically connected with an nth row grid line Gn, a first electrode of M2 is electrically connected with an mth column data line Dm, and a second electrode of M2 is electrically connected with a first electrode of M1;

a control electrode of M3 is electrically connected with the nth row gate line Gn, a first electrode of M3 is electrically connected with the control electrode of M1, and a second electrode of M3 is electrically connected with the second electrode of M1;

a first terminal of Cst is electrically connected to the power voltage line ELVDD, and a second terminal of Cst is electrically connected to the control electrode of M1;

a control electrode of M6 is electrically connected to an nth row reset line Resetn, a first electrode of M6 is electrically connected to a control electrode of M1, and a second electrode of M6 is electrically connected to an initial voltage line Vint;

a control pole of M7 is electrically connected to a reset line Resetn +1 of the n +1 th row, a first pole of M7 is electrically connected to an anode of E1, and a second pole of M7 is electrically connected to an initial voltage line Vint; the cathode of E1 is electrically connected to the low voltage line ELVSS.

In the embodiment shown in fig. 2, each transistor may be a p-type thin film transistor, but not limited thereto.

The embodiment of the pixel circuit as shown in figure 2 is in operation,

m4 and M5 turn on or off under the control of a light emission control signal provided by EMn;

m2 controls the writing of the data voltage on Dm to the first pole of M1 under the control of the gate drive signal provided by Gn, M3 controls the compensation of the threshold voltage of M1 under the control of the gate drive signal provided by Gn;

m6 controls the writing of the initial voltage provided by Vint to the gate of M1 under the control of the first reset signal provided by Resetn;

m7 controls the writing of the initial voltage provided by Vint to the anode of E1 under the control of the second reset signal provided by Resetn + 1.

In a specific implementation, the first reset signal and the second reset signal may be the same, or the first reset signal and the second reset signal may be different;

specifically, the first reset signal may be a gate driving signal of an adjacent previous stage, and the second reset signal may be the gate driving signal, but not limited thereto.

The embodiment of the pixel circuit shown in fig. 2 is only one specific implementation of the pixel circuit, and in the specific implementation, the structure of the pixel circuit may also be other circuit structures, for example, the pixel circuit structure may further include a stabilization capacitor, a first end of the stabilization capacitor is electrically connected to the data line, and a second end of the stabilization capacitor is electrically connected to the power voltage line.

The embodiment of the pixel circuit shown in fig. 2 may be an nth row and an mth column of pixel circuits, with m and n both being positive integers. In fig. 2, the mth column pixel driving circuit of the nth row includes M1, M2, M3, M4, M5, M6, M7, and Cst.

Fig. 3 is a schematic diagram of a layout implementation of a transistor and a storage capacitor in a display substrate according to an embodiment of the present invention, where fig. 3 is composed of an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer from bottom to top. In fig. 3, a reference numeral Dm is an m-th column data line, a reference numeral Dm +1 is an m + 1-th column data line, a reference numeral ELVDD is a power supply voltage line, a reference numeral Vint is an initial voltage line, a reference numeral Resetn is an nth row reset line, a reference numeral Resetn +1 is an n + 1-th row reset line, a reference numeral EMn is an nth row light emitting control line, a reference numeral EMn +1 is an n + 1-th row light emitting control line, a reference numeral Gn is an nth row gate line, and a reference numeral Gn +1 is an n + 1-th row gate line.

In fig. 3, a channel region of an active layer pattern of M6 is denoted by reference numeral 16g, a source region of an active layer pattern of M6 is denoted by reference numeral 16s, a drain region of an active layer pattern of M6 is denoted by reference numeral 16d, a channel region of an active layer pattern of M3 is denoted by reference numeral 13g, a channel region of an active layer pattern of M1 is denoted by reference numeral 11g, a drain region of an active layer pattern of M1 is denoted by reference numeral 11d, and a source region of an active layer pattern of M1 is denoted by reference numeral 11 s; a channel region of the active layer pattern of M2, 12g, a source region of the active layer pattern of M2, 14g, M4, 14s, M4, 15g, M5, 15d, M5, 17g, M7, 17s, M7, Csa, and the first plate of the storage capacitor Cst.

Fig. 4 is a diagram in which An anode An m of the first light emitting element included in the nth row and mth column pixel circuit and An anode An +1m of the first light emitting element included in the (n + 1) th row and mth column pixel circuit are added to fig. 3.

As can be seen from fig. 4, the area occupied by Anm is not equal to the area occupied by the mth row and mth column pixel driving circuits; anm may not be completely disposed in the mth column pixel area of the nth row, and the mth column pixel area of the nth row may be an area surrounded by Resetn, Resetn +1, Dm, and Dm +1, but is not limited thereto.

In the related art, with the development of the flat panel display technology, technicians in the related art begin to use the edge of the display panel to build a light emitting control GOA (Gate On Array, a driving Circuit disposed On the Array substrate), which includes a plurality of cascaded shift register units, and output light emitting control signals to corresponding light emitting control lines through each shift register unit, so as to implement the function of a light emitting control IC (Integrated Circuit). However, in the conventional light-emitting control circuit, the output light-emitting control signal of the shift register unit is unstable in the output stage and the reset stage, and the potential of the node in the shift register unit is easily interfered by other signals, thereby affecting the display effect of the display panel. Therefore, the shift register unit in the display device according to the embodiment of the invention enables the light emitting control signal to be output stably by accessing the first clock to the control circuit, and ensures the display effect of the display panel.

The shift register unit in the display device according to the embodiment of the present invention is configured to generate a light emission control signal, and includes an input terminal, a first node control circuit, a first storage capacitor circuit, a first clock access control circuit, a second node control circuit, a third node control circuit, an output circuit, and a light emission control signal output terminal,

In a specific implementation, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal, but not limited thereto.

The shift register unit in the display device of the embodiment of the invention adopts the first clock to access the control circuit, so that the light-emitting control signal is stably output, and the display effect of the display panel is ensured.

In a specific implementation, the output circuit may be further electrically connected to a first voltage terminal and a second voltage terminal, and the output circuit is configured to control whether the light-emitting control signal output terminal is electrically connected to the second voltage terminal under the control of the potential of the first node, and control whether the light-emitting control signal output terminal is electrically connected to the first voltage terminal under the control of the potential of the second node.

When the shift register unit in the display device according to the embodiment of the present invention is in operation,

when the electric potential of the first node is at a first level, the first clock access control circuit controls the second end of the first storage capacitor circuit to be disconnected from the second clock signal end, so that the electric potential of the second end of the first storage capacitor circuit is not influenced by the second clock signal, the output circuit is ensured to be controlled to be disconnected between the light-emitting control signal output end and the second voltage end under the control of the electric potential of the first node, the light-emitting control signal output end is ensured to output a light-emitting control signal, and the output stability of the light-emitting control signal is improved;

when the electric potential of the first node is at the second level, the first clock access control circuit controls the second end of the first storage capacitor circuit to be electrically connected with the second clock signal end, so that the electric potential of the second end of the first storage capacitor circuit changes along with the change of the second clock signal, the output capacity of the output circuit is enhanced, the output circuit can ensure that the light-emitting control signal output end is electrically connected with the second voltage end under the control of the electric potential of the first node, the light-emitting control signal output end can be reset, and the output stability of the light-emitting control signal is improved.

In a specific implementation, the first level may be a high level, and the second level may be a low level, but not limited thereto.

In specific implementation, the output circuit is configured to provide the light emission control signal to a control electrode of a light emission control transistor in a pixel circuit to control the light emission control transistor to turn off in a first phase;

In the embodiment of the present invention, the first stage may include a first output stage, a second output stage, and a third output stage, but is not limited thereto.

In practical operation, the output circuit may be configured to provide the emission control signal to a control electrode of an emission control transistor in the pixel circuit to control the emission control transistor to be turned on in the second stage; the second phase may include, for example, but not limited to, a first pre-phase, a second pre-phase, an input phase, a first reset phase, a second reset phase, and a reset-hold phase.

In specific implementation, the first clock signal and the second clock signal have a first time period with opposite phases and a second time period with the same phase;

the second time period is adjacent to the first time period;

In the embodiment of the present invention, the first clock signal and the second clock signal having the first time period with opposite phases and the second time period with the same phase may refer to:

in the first time period, when the electric potential of the first clock signal is at a first level, the electric potential of the second clock signal is at a second level, and when the electric potential of the first clock signal is at the second level, the electric potential of the second clock signal is at the first level; in the second time period, when the potential of the first clock signal is at the first level, the potential of the second clock signal is at the first level; but not limited thereto.

In the embodiment of the present invention, the second time period may be set before the first time period, and the second time period may also be set after the first time period.

In a specific implementation, the duration of the first time period may be greater than the duration of the second time period, but is not limited thereto.

The shift register unit in the display device according to the embodiment of the present invention is configured to generate a light-emitting control signal, and as shown in fig. 5, the shift register unit includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit 14, a second node control circuit 15, an output circuit 16, and a light-emitting control signal output terminal OUT, where,

the first node control circuit 11 is electrically connected to the first clock signal terminal, the first node N1, the input terminal STV, the third node N3, the second clock signal terminal and the first voltage terminal, respectively, and is configured to control the first node N1 to be electrically connected to the input terminal STV under the control of the first clock signal CK, and control the first node N1 to be electrically connected to the first voltage terminal under the control of the potential of the third node N3 and the second clock signal CB; the first clock signal terminal is used for providing a first clock signal CK, the second clock signal terminal is used for providing a second clock signal CB, and the first voltage terminal is used for providing a first voltage V1;

a first terminal of the first storage capacitor circuit 12 is electrically connected to the first node N1;

the first clock access control circuit 13 is electrically connected to a first node N1, the second terminal of the first storage capacitor circuit 12 and a second clock signal terminal, respectively, and is configured to control the second terminal of the first storage capacitor circuit 12 and the second clock signal terminal to be electrically connected under the control of the potential of the first node N1;

the third node control circuit 14 is electrically connected to the first clock signal terminal, the third node N3, the second voltage terminal and the first node N1, respectively, and is configured to control an electrical connection between the third node N3 and the second voltage terminal under the control of the first clock signal CK, and to control an electrical connection between the third node N3 and the first clock signal terminal under the control of the potential of the first node N1, and to control the potential of the third node N3; the second voltage end is used for inputting a second voltage V2;

the second node control circuit 15 is electrically connected to the third node N3, the second clock signal terminal, the second node N2, the first node N1 and the first voltage terminal, respectively, and is configured to control the potential of the second node N2 under the control of the potential of the third node N3 and the second clock signal CB, and to control the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1;

the output circuit 16 is electrically connected to the first node N1, the second node N2, the light-emitting control signal output terminal OUT, the first voltage terminal and the second voltage terminal, respectively, and is configured to control the light-emitting control signal output terminal OUT and the second voltage terminal under the control of the potential of the first node N1, and to control the light-emitting control signal output terminal OUT and the first voltage terminal under the control of the potential of the second node.

In a specific implementation, the input terminal STV may be a start signal, or may be an adjacent previous stage lighting control signal, but is not limited thereto.

In particular implementations, the first storage capacitor circuit may include a first storage capacitor;

the first end of the first storage capacitor is the first end of the first storage capacitor circuit, and the second end of the first storage capacitor is the second end of the first storage capacitor circuit.

In particular implementations, the output circuit may include a first output transistor and a second output transistor;

the control electrode of the first output transistor is electrically connected with the second node, the first electrode of the first output transistor is electrically connected with the first voltage end, and the second electrode of the first output transistor is electrically connected with the light-emitting control signal output end;

the control electrode of the second output transistor is electrically connected with the first node, the first electrode of the second output transistor is electrically connected with the light-emitting control signal output end, and the second electrode of the second output transistor is electrically connected with the second voltage end.

In operation of the shift register cell embodiment of the present invention as shown in fig. 5, when the second output transistor included in the output circuit 16 and having its gate electrically connected to the first node N1 is a p-type transistor,

when the potential of N1 is at a low level, the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be electrically connected to the second clock signal terminal, and at this time, the potential of CB jumps from a high level to a low level, so that the potential of N1 (i.e., the potential of the first terminal of the first storage capacitor circuit 12) can be made lower, thereby enhancing the output capability of the second output transistor;

when the potential of the N1 is at a high level, the second output transistor is turned off, and the first clock access control circuit 13 controls the second end of the first storage capacitor circuit 12 and the second clock signal end to be disconnected, so that the change of the second clock signal CB does not affect the potential of the N1, the high potential of the N1 is ensured, the second output transistor is ensured to be not turned on, and the stability of outputting the light emitting control signal is improved.

In the embodiment of the present invention, the first voltage is a high voltage, the second voltage is a low voltage, the first level is a high level, and the second level is a low level; but not limited thereto. In actual operation, the first voltage may be a low voltage, the second voltage may be a high voltage, the first level may be a low level, and the second level may be a high level.

When the embodiment of the shift register unit shown in fig. 5 of the present invention is in operation, as shown in fig. 6, the light emission control period includes a first pre-stage t01, a second pre-stage t02, an input stage t1, a first output stage t21, a second output stage t22, a third output stage t23, a first reset stage t3, a second reset stage t4, and a reset holding stage t5, which are sequentially arranged; a preliminary interval phase t00 is provided between the first preliminary phase t01 and the second preliminary phase t 02; a first separation phase t10 is provided between the input phase t1 and the first output phase t 21; a second interval phase t20 is provided between the first output phase t21 and the second output phase t 22; a third interval phase t30 is provided between the second output phase t22 and the third output phase t 23; a fourth interval phase t40 is provided between the third output phase t23 and the first reset phase t 3; a fifth interval phase t50 is provided between the first reset phase t3 and the second reset phase t 4;

in the first pre-stage t01, the potential of the first clock signal CK is at the second level, the potential of the second clock signal CB is at the first level, the input terminal STV inputs the second level, the first node control circuit 11 controls the electrical connection between the first node N1 and the input terminal STV to control the potential of N1 to be at the second level, and the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal to make the potential of the second node N2 be at the first voltage; the output circuit 16 controls the electrical connection between the light emission control signal output terminal OUT and the second voltage terminal under the control of the potential of the first node N1, and the output circuit 16 controls the disconnection between the light emission control signal output terminal OUT and the first voltage terminal under the control of the potential of the second node N2, so that the potential of the light emission control signal is the second voltage; the first clock access control circuit 13 controls the second end of the first storage capacitor circuit 12 to be electrically connected with the second clock signal end under the control of the potential of N1;

during the pre-interval period t00, the potential of the first clock signal CK and the potential of the second clock signal CB are both at the first level, the first node control circuit 11 controls to maintain the potential of N1 at the second level, and the third node control circuit 14 controls the third node N3 to switch in the CK under the control of the potential of the first node N1, so as to control the potential of N3 at the first level; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, so as to control the potential of the second node N2 to be maintained at the first voltage; the first clock access control circuit 13 controls the second end of the first storage capacitor circuit 12 to be electrically connected with the second clock signal end under the control of the potential of N1;

in the second pre-stage t02, the potential of the first clock signal CK is at the first level, the potential of the second clock signal CB jumps from the first level to the second level, the first node control circuit 11 maintains the potential of N1 at the second level, and the second node control circuit 15 controls to maintain the potential of N2 at the first level; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be electrically connected to the second clock signal terminal under the control of the potential of N1, and due to a capacitor bootstrap effect, the potential of N1 is further lowered, so that the output circuit 16 can control the light-emitting control signal output terminal OUT to be electrically connected to the second voltage terminal under the control of the potential of the first node N1, so as to control OUT to output the second voltage;

in the input stage t1, the potential of the first clock signal CK is at the second level, the potential of the second clock signal CB is at the first level, the input terminal STV inputs the first level, the first node control circuit 11 controls the electrical connection between the first node N1 and the input terminal STV to control the potential of N1 to be at the first level, the output circuit 16 controls the disconnection between the light-emitting control signal output terminal OUT and the second voltage terminal, and the first clock access control circuit 13 controls the disconnection between the second terminal of the first storage capacitor circuit 12 and the second clock signal terminal, so that the potential of the first terminal of the first storage capacitor circuit 12 (i.e. the potential of the first node N1) is not affected by CB; the third node control circuit 14 controls the third node N3 to be electrically connected to the second voltage terminal under the control of the first clock signal CK, so as to control the potential of the N3 to be the second voltage, the second node control circuit 15 controls the second node N2 to be in a floating state under the control of the potential of the third node N3 and the second clock signal CB, so as to maintain the potential of the N2 at the first level, and the output circuit 16 controls OUT to still output the second voltage;

in the first interval period t10, the potential of the first clock signal CK jumps to the first level, the potential of the second clock signal CB is the first level, the first node control circuit 11 controls to maintain the potential of the first node N1 at the first level, and the third node control circuit 14 controls to maintain the potential of the third node N3 at the second voltage;

in the first output stage t21, the potential of the first clock signal CK is maintained at the first level, the potential of the second clock signal CB jumps from the first level to the second level, the STV inputs the first level, and the third node control circuit 14 controls the potential of the third node N3 to be the second level; the first node control circuit 11 controls the potential of the first node N1 to be a first voltage according to the second clock signal CB and the potential of the third node N3; the second node control circuit 15 controls the potential of the second node N2 to be a second voltage under the control of the second clock signal CB; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be disconnected from the second clock signal terminal under the control of the potential of N1, so that the potential of the first node N1 is not affected by CB, and the potential of N1 can be maintained at the first voltage; the output circuit 16 controls the electrical connection between the light-emitting control signal output terminal OUT and the first voltage terminal under the control of the potential of the second node N2, thereby controlling OUT to output the first voltage;

in the second interval period t20, the potential of the second clock signal CB jumps from the second level to the first level, the potential of the first clock signal CK is at the first level, STV is inputted at the first level, the first node control circuit 11 controls to maintain the potential of the first node N1 at the first voltage, and the second node control circuit 15 controls to maintain the potential of the second node N2 at the second voltage;

in the second output stage t22, the potential of the first clock signal CK jumps from the first level to the second level, the potential of the second clock signal CB is maintained at the first level, the STV is input at the first level, and the first node control circuit 11 controls the potential of the first node N1 to be at the first level; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be disconnected from the second clock signal terminal under the control of the potential of N1, so that the potential of N1 is not influenced by CB, and the potential of N1 can be maintained at the first level; the third node control circuit 14 controls the third node N3 to be electrically connected to the second voltage terminal under the control of the first clock signal CK, so as to control the potential of the third node N3 to be the second voltage; the second node control circuit 15 controls the second node N2 to be in a floating state so that the potential of the second node N2 is maintained at a second voltage; the output circuit 16 controls the electrical connection between the light-emitting control signal output terminal OUT and the first voltage terminal under the control of the potential of the second node N2, thereby controlling OUT to output the first voltage;

in the third interval period t30, the potential of the first clock signal CK jumps from the second level to the first level, the potential of the second clock signal CB is maintained at the first level, the STV is inputted at the first level, the first node control circuit 11 controls to maintain the potential of the first node N1 at the first voltage, and the second node control circuit 15 controls to maintain the potential of the second node N2 at the second voltage;

in the third output stage t23, the STV inputs the second level, the potential of the first clock signal CK is the first level, the potential of the second clock signal CB jumps from the first level to the second level, and the third node control circuit 14 controls the potential of the third node N3 to be the second voltage; the first node control circuit 11 controls to maintain the potential of the first node N1 at a first voltage, and the second node control circuit 15 controls to maintain the potential of the second node N2 at a second voltage; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be disconnected from the second clock signal terminal under the control of the potential of N1, so that the potential of N1 is not influenced by CB, and the potential of N1 can be maintained at the first level; the output circuit 16 controls the electrical connection between the light-emitting control signal output terminal OUT and the first voltage terminal under the control of the potential of the second node N2, thereby controlling OUT to output the first voltage;

in the fourth interval period t40, the electric potential of CB jumps from the second level to the first level, the electric potential of CK is the first level, STV inputs the second level, the first node control circuit 11 controls to maintain the electric potential of the first node N1 as the first voltage, and the second node control circuit 15 controls to maintain the electric potential of the second node N2 as the second voltage;

in the first reset phase t3, the potential of CB is at the first level, the potential of CK jumps from the first level to the second level, STV inputs the second level, and the first node control circuit 11 controls the electrical connection between the first node N1 and the input terminal STV under the control of the first clock signal CK to control the potential of the first node N1 to be at the second level; the first clock access control circuit 13 controls the second end of the first storage capacitor circuit 12 to be electrically connected with the second clock signal end under the control of the potential of the first node N1; the third node control circuit 14 controls the third node N3 to be electrically connected to the second voltage terminal under the control of the first clock signal CK, so as to control the potential of the third node N3 to be the second voltage; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, thereby controlling the potential of the second node N2 to be the first voltage; the output circuit 16 controls the electrical connection between the light-emitting control signal output terminal OUT and the second voltage terminal under the control of the potential of the first node N1;

in the fifth interval period t50, the potential of the first clock signal CK jumps from the second level to the first level, and the potential of the second clock signal CB is at the first level; the first node control circuit 11 controls the first node N1 to be in a floating state, thereby controlling the potential of the first node N1 to be maintained at the second level; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, thereby controlling the potential of the second node N2 to be the first voltage;

in the second reset phase t4, the potential of the first clock signal CK is at the first level, the potential of the second clock signal CB jumps from the first level to the second level, the first node control circuit 11 controls to maintain the potential of the first node N1 at the second level, and the third node control circuit 14 controls the third node N3 to access the CK under the control of the potential of the first node N1 to control the potential of the third node N3 at the first level; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, thereby controlling the potential of the second node N2 to be the first voltage; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be electrically connected to the second clock signal terminal under the control of the potential of the first node N1, and further pulls down the potential of the first node N1 under the capacitor bootstrap action, so as to improve the output capability of the second output transistor included in the output circuit 16, and further pulls down the potential of the emission control signal output by the emission control signal output terminal OUT; meanwhile, the third node control circuit 14 controls the third node N3 to be connected to CK under the control of the potential of the first node N1, so as to control the potential of N3 to be a first level, and reset N3;

in the reset hold phase t5, STV inputs the second level, the potential interval of the first clock signal CK is the second level, the first level, the potential interval of the second clock signal CB is the first level, the second level;

in the reset holding period t5, when the potential of CK is at the second level and the potential of CB is at the first level, the first node control circuit 11 controls the potential of the first node N1 to be at the second level under the control of CK; the third node control circuit 14 controls the third node N3 to be electrically connected to the second voltage terminal under the control of the first clock signal CK, and controls the third node N3 to be connected to CK under the control of the potential of the first node N1, thereby controlling the potential of the N3 to be at the second level; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, thereby controlling the potential of the second node N2 to be the first voltage; the output circuit 16 controls the electrical connection between the light-emitting control signal output terminal OUT and the second voltage terminal under the control of the potential of the first node N1;

in the reset and hold period t5, when the potential of CK is at the first level and the potential of CB jumps from the first level to the second level, the first node control circuit 11 controls to maintain the potential of the first node N1 at the second level, and the third node control circuit 14 controls the third node N3 to access CK under the control of the potential of the first node N1 to control the potential of the third node N3 at the first level; the second node control circuit 15 controls the electrical connection between the second node N2 and the first voltage terminal under the control of the potential of the first node N1, thereby controlling the potential of the second node N2 to be the first voltage; the first clock access control circuit 13 controls the second terminal of the first storage capacitor circuit 12 to be electrically connected to the second clock signal terminal under the control of the potential of the first node N1, further pulls down the potential of the first node N1 under the capacitor bootstrap action to improve the output capability of the second output transistor included in the output circuit 16, and the output circuit 16 controls the light-emitting control signal output terminal OUT to be electrically connected to the second voltage terminal under the control of the potential of the first node N1.

In fig. 6, t21 may be the first period of time, t10 and t20 may be the second period of time, t10 is set before t21, t20 is set after t 21;

at t21, the potential of CK is at the first level, the potential of CB is at the second level;

at t10, the potential of CK and the potential of CB are both at the first level;

at t20, the potential of CK and the potential of CB are both at the first level;

t21 lasts longer than t10 and t21 lasts longer than t 20.

Specifically, the first clock access control circuit may include a first clock access control transistor;

As shown in fig. 7, on the basis of the embodiment of the shift register unit shown in fig. 5, the first clock access control circuit 13 may include a first clock access control transistor T13;

the gate of the first clock access control transistor T13 is electrically connected to the first node N1, the source of the first clock access control transistor T13 is electrically connected to the second terminal of the first storage capacitor circuit 12, and the drain of the first clock access control transistor T13 is connected to a second clock signal CB.

In the embodiment shown in fig. 7, T13 is a p-type tft, but not limited thereto.

In operation of the embodiment of the shift register cell of the present invention as shown in figure 7,

when the potential of the N1 is at a low level, the T13 is turned on to control the second terminal of the first storage capacitor circuit 12 to be connected to the CB, and when the potential of the CB jumps from a high level to a low level, the potential of the N1 is pulled lower, so that the output capability of the second output transistor included in the output circuit can be enhanced;

when the potential of the N1 is at a high level, the T13 is turned off to control the second terminal of the first storage capacitor circuit 12 to be disconnected from the second clock signal terminal, so that the potential of the N1 is not affected by CB, and the second output transistor can be guaranteed to be turned off, thereby preventing erroneous output.

According to a specific embodiment, the third node control circuit may include a first control circuit and a second storage capacitor circuit;

In a specific implementation, the second storage capacitor circuit may include a second storage capacitor, a first end of the second storage capacitor is a first end of the second storage capacitor circuit, and a second end of the second storage capacitor is a second end of the second storage capacitor circuit.

As shown in fig. 8, on the basis of the embodiment of the shift register unit shown in fig. 5, the third node control circuit may include a first control circuit 141 and a second storage capacitor circuit 142;

the first control circuit 141 is electrically connected to the third node N3, the first node N1, the low voltage terminal, and the first clock signal terminal, respectively, and is configured to control the third node N3 to be electrically connected to the low voltage terminal under the control of the first clock signal CK, and control the third node N3 to be electrically connected to the first clock signal terminal under the control of the potential of the first node N1; the low voltage end is used for inputting low voltage VGL;

a first end of the second storage capacitor circuit 142 is electrically connected to the third node N3, and a second end of the second storage capacitor circuit 142 is electrically connected to a second clock signal end; the second clock signal terminal is used for inputting a second clock signal CB.

In the embodiment shown in fig. 8, the second voltage is the low voltage VGL, but not limited thereto.

In the embodiment of the shift register unit shown in fig. 8, when the shift register unit operates, the first control circuit 141 controls the potential of the third node N3 under the control of the first clock signal CK and the potential of the first node N1, the first terminal of the second storage capacitor circuit 142 is electrically connected to the third node N3, and the second terminal of the second storage capacitor circuit 142 is connected to the second clock signal CB, so that the potential of the third node N3 can be controlled according to the potential of the second clock signal CB.

Preferably, the shift register unit in the display device according to the embodiment of the present invention may further include a second clock access control circuit;

As shown in fig. 9, on the basis of the embodiment of the shift register unit shown in fig. 8, the shift register unit in the display device according to the embodiment of the present invention may further include a second clock access control circuit 17;

a second end of the second storage capacitor circuit 142 is electrically connected to the second clock signal end through the second clock access control circuit 17; the second clock signal terminal is used for inputting a second clock signal CB;

the second clock access control circuit 17 is electrically connected to a third node N3, the second end of the second storage capacitor circuit 142, and the second clock signal end, respectively, and is configured to control the second end of the second storage capacitor circuit 142 and the second clock signal end to be electrically connected under the control of the potential of the third node N3.

In operation of the embodiment of the shift register cell of the present invention as shown in figure 9,

when the potential of the N3 is at the first level, the second clock signal access control circuit 17 controls the second terminal of the second storage capacitor circuit 142 to be disconnected from the second clock signal terminal, so that the potential of the third node N3 is not affected by CB;

when the potential of the N3 is at the second level, the second clock signal access control circuit 17 controls the electrical connection between the second terminal of the second storage capacitor circuit 142 and the second clock signal terminal, so that when the potential of the CB jumps from the first level to the second level, the potential of the third node N3 can change accordingly.

Specifically, the second clock access control circuit may include a second clock access control transistor;

As shown in fig. 10, on the basis of the embodiment of the shift register cell shown in fig. 9, the second clock access control circuit 17 may include a second clock access control transistor T14;

the gate of the second clock access control transistor T14 is electrically connected to the third node N3, the source of the second clock access control transistor T14 is electrically connected to the second clock signal terminal, and the drain of the second clock access control transistor T14 is electrically connected to the second terminal of the second storage capacitor circuit 142.

In the embodiment of the shift register unit shown in fig. 10, T14 is a p-type thin film transistor, but not limited thereto.

In operation of the embodiment of the shift register cell of the present invention shown in figure 10,

when the potential of the N3 is at a low level, the T14 is turned on to control the second terminal of the second storage capacitor circuit 142 to be connected to the CB, so that when the potential of the CB jumps from a high level to a low level, the potential of the N3 can be further pulled down, thereby improving the driving capability of the N3;

when the potential of N3 is at a high level, T14 turns off to control the disconnection between the second terminal of the second storage capacitor circuit 142 and the second clock signal terminal, so that the potential of N3 is not affected by CB.

According to another specific embodiment, the third node control circuit may include a first control circuit and a second storage capacitor circuit;

As shown in fig. 11, on the basis of the embodiment of the shift register unit shown in fig. 5, the third node control circuit may include a first control circuit 141 and a second storage capacitor circuit 142;

the first control circuit 141 is electrically connected to the first clock signal terminal, the third node N3, the low voltage terminal and the first node N1, respectively, and is configured to control the third node N3 to be electrically connected to the low voltage terminal under the control of the first clock signal CK, and to control the third node N3 to be electrically connected to the first clock signal terminal under the control of the potential of the first node N1; the first clock signal end is used for inputting a first clock signal CK, and the low voltage end is used for inputting low voltage VGL;

a first terminal of the second storage capacitor circuit 142 is electrically connected to the third node N3, and a second terminal of the second storage capacitor circuit 142 is electrically connected to the control node NC.

In the embodiment of the shift register unit shown in fig. 11, when the first control circuit 141 controls the potential of the third node N3 under the control of the first clock signal CK and the potential of the first node N1, the first terminal of the second storage capacitor circuit 142 is electrically connected to the third node N3, and the second terminal of the second storage capacitor circuit 142 is connected to the control node NC, so that the potential of the third node N3 can be controlled according to the potential of the control node NC.

In the embodiment of the shift register unit shown in fig. 11, the control node NC may be an internal node in the second node control circuit (in fig. 11, NC is electrically connected to the second node control circuit 15), but not limited thereto.

Specifically, the first control circuit may include a first control transistor and a second control transistor;

Preferably, the first control transistor may be a double gate transistor to prevent a potential of the third node from being lowered due to leakage of the first control transistor.

According to a specific embodiment, the second node control circuit may include a second control circuit, a third control circuit, a fourth control circuit, and a third storage capacitor circuit;

In a specific implementation, the third storage capacitor circuit may include a third storage capacitor, where a first end of the third storage capacitor is a first end of the third storage capacitor circuit, and a second end of the third storage capacitor is a second end of the third storage capacitor circuit.

As shown in fig. 12, on the basis of the embodiment of the shift register unit shown in fig. 5, the second node control circuit may include a second control circuit 152, a third control circuit 153, a fourth control circuit 154, and a third storage capacitor circuit 150;

the second control circuit 152 is electrically connected to the third node N3, the control node NC and the low voltage terminal, respectively, and is configured to electrically connect the control node NC and the low voltage terminal under the control of the potential of the third node N3; the low voltage end is used for inputting low voltage VGL;

the third control circuit 153 is electrically connected to the second clock signal terminal, the control node NC and the second node N2, respectively, and is configured to control the control node NC and the second node N2 to be electrically connected to each other under the control of a second clock signal CB;

the fourth control circuit 154 is electrically connected to the first node N1, the second node N2 and the high voltage terminal, respectively, for controlling the electrical connection between the second node N2 and the high voltage terminal under the control of the potential of the first node N1; the high voltage end is used for inputting high voltage VGH;

a first terminal of the third storage capacitor circuit 150 is electrically connected to the second node N2, and a second terminal of the third storage capacitor circuit 150 is electrically connected to the high voltage terminal.

When the embodiment of the shift register unit shown in fig. 12 of the present invention is in operation, the second control circuit 152 controls whether NC is connected to VGL under the control of the potential of N3; the third control circuit 153 controls whether NC is electrically connected to N2 under the control of CB; the fourth control circuit 154 controls whether N2 is connected to VGH or not under the control of the potential of N1; the third storage capacitor circuit 150 is used for maintaining the potential of the second node N2.

Specifically, the second control circuit may include a third control transistor, the third control circuit may include a fourth control transistor, and the fourth control circuit may include a fifth control transistor;

According to another specific embodiment, the second node control circuit may include a second control circuit, a third control circuit, a fourth control circuit, and a third storage capacitor circuit;

As shown in fig. 13, on the basis of the embodiment of the shift register unit shown in fig. 5, the second node control circuit may include a second control circuit 152, a third control circuit 153, a fourth control circuit 154, and a third storage capacitor circuit 150;

the second control circuit 152 is electrically connected to the third node N3, the control node NC and the second clock signal terminal, respectively, and is configured to electrically connect the control node NC and the second clock signal terminal under the control of the potential of the third node N3; the second clock signal terminal is used for inputting a second clock signal CB;

the third control circuit 153 is electrically connected to the second clock signal terminal, the control node NC and the second node N2, respectively, and is configured to control the control node NC to be electrically connected to the second node N2 under the control of a second clock signal CB;

When the embodiment of the shift register unit shown in fig. 13 of the present invention operates, the second control circuit 152 controls whether the control node NC is connected to the CB under the control of the potential of the third node N3; the third control circuit 153 controls whether the control node NC is electrically connected to the second node N2 under the control of a second clock signal CB, and the fourth control circuit 154 controls whether the second node N2 is connected to a high voltage VGH under the control of the potential of the first node N1; the third storage capacitor circuit 150 is used for maintaining the potential of the second node N2.

According to a specific embodiment, the first node control circuit may include a sixth control transistor, a seventh control transistor, and an eighth control transistor;

According to another specific embodiment, the first node control circuit may include a sixth control transistor, a seventh control transistor, and an eighth control transistor;

Specifically, the output circuit may include a first output transistor and a second output transistor;

The following describes a shift register unit in a display device according to the present invention with specific embodiments.

As shown in fig. 14, the first embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, and a light-emitting control signal output terminal OUT, wherein,

the first reservoir capacitor circuit 12 comprises a first reservoir capacitor C1;

the output circuit 16 includes a first output transistor T9 and a second output transistor T10;

a first end of the first storage capacitor C1 is electrically connected with a first node N1;

a gate of the first output transistor T9 is electrically connected to the second node N2, a source of the first output transistor T9 is electrically connected to the high voltage terminal, and a drain of the first output transistor T9 is electrically connected to the emission control signal output terminal OUT; the high voltage end is used for inputting high voltage VGH;

a gate of the second output transistor T10 is electrically connected to the first node N1, a source of the second output transistor T10 is electrically connected to the emission control signal output terminal OUT, and a drain of the second output transistor T10 is electrically connected to the low voltage terminal; the low voltage end is used for inputting low voltage VGL;

the first clock access control circuit 13 comprises a first clock access control transistor T13;

the gate of the first clock access control transistor T13 is electrically connected to the first node N1, the source of the first clock access control transistor T13 is electrically connected to the second end of the first storage capacitor C1, and the drain of the first clock access control transistor T13 is connected to a second clock signal CB;

the third node control circuit includes a first control circuit 141 and a second storage capacitor circuit 142;

the first control circuit 141 includes a first control transistor T2 and a second control transistor T3;

a gate of the first control transistor T2 is electrically connected to the first node N1, a source of the first control transistor T2 is electrically connected to the third node N3, and a drain of the first control transistor T2 is electrically connected to a first clock signal terminal; the first clock signal end is used for inputting a first clock signal CK;

a gate of the second control transistor T3 is electrically connected to the first clock signal terminal, a source of the second control transistor T3 is electrically connected to the low voltage terminal, and a drain of the second control transistor T3 is electrically connected to the third node N3; the low voltage end is used for inputting low voltage VGL;

the second storage capacitor circuit 142 includes a second storage capacitor C2;

a first terminal of the second storage capacitor C2 is electrically connected to the third node N3, and a second terminal of the second storage capacitor C2 is electrically connected to a second clock signal terminal; the second clock signal terminal is used for inputting a second clock signal CB;

the second node control circuit includes a second control circuit 152, a third control circuit 153, a fourth control circuit 154, and a third storage capacitor circuit 150;

the second control circuit 152 includes a third control transistor T6, the third control circuit 153 includes a fourth control transistor T7, and the fourth control circuit 154 may include a fifth control transistor T8;

a gate of the third control transistor T6 is electrically connected to the third node N3, a source of the third control transistor T6 is electrically connected to the low voltage terminal, and a drain of the third control transistor T6 is electrically connected to a control node NC;

a gate of the fourth control transistor T7 is electrically connected to a second clock signal terminal, a source of the fourth control transistor T7 is electrically connected to the control node NC, and a drain of the fourth control transistor T7 is electrically connected to the second node N2;

a gate of the fifth control transistor T8 is electrically connected to the first node N1, a source of the fifth control transistor T8 is electrically connected to the second node N2, and a drain of the fifth control transistor T8 is electrically connected to a high voltage terminal;

the third reservoir capacitor circuit 150 includes a third reservoir capacitor C3;

a first terminal of C3 is electrically connected to the second node N2, and a second terminal of C3 is electrically connected to the high voltage terminal;

the first node control circuit 11 includes a sixth control transistor T1, a seventh control transistor T4, and an eighth control transistor T5;

a gate of the sixth control transistor T1 is electrically connected to the first clock signal terminal, a source of the sixth control transistor T1 is electrically connected to the input terminal STV, and a drain of the sixth control transistor T1 is electrically connected to the first node N1;

a gate of the seventh control transistor T4 is electrically connected to the drain of the eighth control transistor T5, a source of the seventh control transistor T4 is electrically connected to the high voltage terminal, and a drain of the seventh control transistor T4 is electrically connected to the first node N1;

the gate of the eighth control transistor T5 is electrically connected to the third node N3, and the source of the eighth control transistor T5 is electrically connected to the second clock signal terminal; the second clock signal terminal is used for inputting a second clock signal CB.

In the first embodiment of the shift register unit in the display device according to the present invention, all the transistors are p-type thin film transistors, but not limited thereto.

As shown in fig. 15, when the first embodiment of the shift register unit in the display device according to the present invention operates, the light emitting control period includes a first pre-stage t01, a second pre-stage t02, an input stage t1, a first output stage t21, a second output stage t22, a third output stage t23, a first reset stage t3, a second reset stage t4, and a reset and hold stage t5, which are sequentially arranged; a preliminary interval phase t00 is provided between the first preliminary phase t01 and the second preliminary phase t 02; a first interval phase t10 is arranged between the input phase t1 and the first output phase t 21; a second interval phase t20 is provided between the first output phase t21 and the second output phase t 22; a third interval phase t30 is provided between the second output phase t22 and the third output phase t 23; a fourth interval phase t40 is provided between the third output phase t23 and the first reset phase t 3; a fifth interval phase t50 is provided between the first reset phase t3 and the second reset phase t 4;

in the first pre-stage T01, the potential of CK is low, the potential of CB is high, STV input is low, T1, T2, T3 and T8 are turned on, the potential of N1 is low, the potential of N3 is low, and the potential of N2 is high; the T13 is opened to control the second end of the C1 to access the CB; t10 is turned on and T9 is turned off, so that OUT outputs a low voltage;

in the pre-interval period T00, the STV inputs a low level, the potential of CK and the potential of CB are both high level, the potential of N1 is maintained at low level, and T2 is turned on to control N3 to be switched in CK, so as to control the potential of N3 to be high level; t8 is turned on to control the potential of N2 to be maintained at a high voltage; the T13 is opened to control the second end of the C1 to access the CB; t10 is turned on and T9 is turned off, so that OUT outputs a low voltage;

in the second pre-stage T02, STV inputs low level, CK is high level, CB jumps from high level to low level, N1 maintains low level, T8 is turned on to control and maintain N2 high level; the T13 is opened to control the second end of the C1 to be connected to the CB, and due to a capacitor bootstrap effect, the potential of the N1 is further pulled low, the output capability of the T10 is improved, the T10 can be ensured to be opened, and the OUT can be controlled to output low voltage;

in the input stage T1, the potential of CK is low, the potential of CB is high, STV inputs high, T1 and T3 are turned on, so that the potential of N1 is high, the potential of N3 is low, T10 is turned off, T13 is turned off, so that the second end of C1 is disconnected from the second clock signal end, so that the potential of the first end of C1 (i.e., the potential of the first node N1) is not affected by CB; t7 and T8 are turned off to control N2 to be in a floating state, so that the potential of N2 is maintained to be high level, and the output circuit 16 controls OUT to still output low voltage;

in the first interval period T10, the potential of CK jumps to a high level, the potential of CB is at a high level, T1 and T3 are turned off, the potential of N1 is maintained at a high level, and the potential of N3 is maintained at a low voltage;

in the first output stage T21, the potential of CK is maintained at a high level, the potential of CB jumps from the high level to a low level, STV inputs the high level, and since the potential of the second terminal of C2 decreases, the potential of the first terminal of C2 also decreases correspondingly, so that the potential of N3 is further pulled low (lower than VGL) to improve the output capability of T6; t4 and T5 are opened, and N1 is connected to VGH, so that the potential of N1 is high voltage; the method comprises the following steps that T6 is turned on, the potential of NC is low, T7 is turned on, N2 is connected to VGL, and therefore the potential of N2 is low; t9 is turned on, T10 is turned off, and OUT outputs high voltage VGH; and T13 is turned off to disconnect the second terminal of C1 from the second clock signal terminal, so that the potential of N1 is not affected by CB and the potential of N1 can be maintained at a high voltage;

in the second interval period T20, the potential of the CB jumps from low level to high level, the potential of the CK is high level, the STV input is high level, T1 and T3 are turned off, the potential of N1 is maintained at high voltage, and the potential of N2 is maintained at low voltage;

in the second output stage T22, the potential of CK jumps from high level to low level, the potential of CB is maintained at high level, the STV input is high level, T1 and T3 are opened, and the potential of N1 is high level; the T13 is turned off to control the disconnection between the second terminal of the C1 and the second clock signal terminal, so that the potential of N1 is not affected by CB, thereby enabling the potential of N1 to be maintained at a high level; the N3 is electrically connected with the low-voltage end to control the potential of the N3 to be low voltage; t7 is turned off, and N2 is in a floating state, so that the potential of N2 is maintained at a low voltage; t9 is turned on, T10 is turned off, and OUT outputs high voltage;

in the third interval period t30, the potential of CK jumps from low level to high level, the potential of CB is maintained at high level, STV input is high level, the potential of N1 is maintained at high voltage, and the potential of N2 is maintained at low voltage;

in a third output stage T23, STV inputs low level, the potential of CK is high level, the potential of CB jumps from high level to low level, the potential of N3 becomes low accordingly, the output capability of T6 is enhanced, T6 is turned on so that the potential of NC is low voltage, and T7 is turned on so that the potential of N2 is low voltage; the T5 is turned on, the T4 is turned on, so that the potential of the N1 is high voltage, the T13 is turned off, the disconnection between the second end of the C1 and the second clock signal end is controlled, the potential of the N1 is not influenced by CB, and the T10 is ensured to be turned off; t9 is opened, and OUT is controlled to output high voltage;

in the fourth interval period T40, the potential of CB jumps from low level to high level, the potential of CK is high level, STV input is low level, T1 and T3 are turned off, the potential of N1 is maintained as high voltage, and the potential of N2 is maintained as low voltage;

in the first reset phase T3, the electric potential of CB is high level, the electric potential of CK jumps from high level to low level, the STV inputs low level, T1 and T3 are opened to control the electric connection between N1 and STV, to control the electric potential of N1 to low level, and T13 is opened; the potential of N3 is low voltage, and T8 is turned on to control the potential of N2 to be high voltage; t9 is turned off, and T10 is turned on to control the light emission control signal outputted from OUT to be pulled low, so that the light emission control signal can control the corresponding light emission control transistor to be turned on;

in the fifth interval period t50, the potential of CK jumps from low level to high level, and the potential of CB is high level; t1 and T3 are turned off, and N1 is in a floating state, so that the potential of N1 is controlled to be maintained at a low level; t8 is turned on to control the potential of N2 to be high voltage;

in the second reset phase T4, the potential of CK is high level, the potential of CB jumps from high level to low level, the STV input is low level, the potential of N1 is maintained at low level, T8 is opened to control the potential of N2 to be high level; the T13 is turned on, the second end of the C1 is connected to the CB, the potential of the N1 is further pulled down to improve the output capability of the T10, and the potential of the light-emitting control signal output by the light-emitting control signal output end OUT is further pulled down; t2 is turned on to control N3 to access CK, and the potential of N3 is controlled to be high level to reset N3;

in the reset hold phase t5, STV inputs low level, the potential interval of CK is low level and high level, and the potential interval of CB is high level and low level;

in the reset holding period T5, when the potential of CK is at a low level and the potential of CB is at a high level, T1 is turned on to control the potential of N1 to be at a low level; t2 and T3 are turned on to control the potential of N3 to a low level; t8 is turned on to control the potential of N2 to be high voltage; t9 is turned off, and T10 is turned on to control OUT to output low voltage;

in the reset holding phase T5, when the potential of CK is at high level and the potential of CB jumps from high level to low level, T1 and T3 are turned off, the potential of N1 is maintained at low level, and T2 is turned on to control N3 to be switched in CK, so that the potential of N3 is at high level; t8 is turned on to control the potential of N2 to be high voltage; the T13 is turned on to control the electrical connection between the second terminal of the C1 and the second clock signal terminal, and under the capacitor bootstrap action, the potential of N1 is further pulled down to improve the output capability of T10, T9 is turned off, and T10 is turned on to control OUT to output a low voltage.

As shown in fig. 16, the second embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, and a light-emitting control signal output terminal OUT, wherein,

the gate of the seventh control transistor T4 is electrically connected to the second clock signal terminal, the source of the seventh control transistor T4 is electrically connected to the drain of the eighth control transistor T5, and the drain of the seventh control transistor T4 is electrically connected to the first node N1;

the gate of the eighth control transistor T5 is electrically connected to the third node N3, and the source of the eighth control transistor T5 is electrically connected to the high voltage terminal.

In the second embodiment of the shift register unit in the display device according to the present invention, all the transistors are p-type thin film transistors, but not limited thereto.

As shown in fig. 15, when the second embodiment of the shift register unit in the display device according to the present invention operates, the light emitting control period includes a first pre-stage t01, a second pre-stage t02, an input stage t1, a first output stage t21, a second output stage t22, a third output stage t23, a first reset stage t3, a second reset stage t4, and a reset and hold stage t5, which are sequentially arranged; a preliminary interval phase t00 is provided between the first preliminary phase t01 and the second preliminary phase t 02; a first separation phase t10 is provided between the input phase t1 and the first output phase t 21; a second interval phase t20 is provided between the first output phase t21 and the second output phase t 22; a third interval phase t30 is provided between the second output phase t22 and the third output phase t 23; a fourth interval phase t40 is provided between the third output phase t23 and the first reset phase t 3; a fifth interval phase t50 is provided between the first reset phase t3 and the second reset phase t 4;

in the first interval period T10, the potential of CK jumps to a high level, the potential of CB is at a first level, T1 and T3 are turned off, the potential of N1 is maintained at a high level, and the potential of N3 is maintained at a low voltage;

As shown in fig. 17, a third embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, and a light-emitting control signal output terminal OUT, wherein,

a first end of the second storage capacitor C2 is electrically connected with the third node N3, and a second end of the second storage capacitor C2 is electrically connected with a control node NC;

a gate of the third control transistor T6 is electrically connected to the third node N3, a source of the third control transistor T6 is electrically connected to the second clock signal terminal, and a drain of the third control transistor T6 is electrically connected to a control node NC; the second clock signal terminal is used for inputting a second clock signal CB;

In the third embodiment of the shift register unit in the display device according to the present invention, all the transistors are p-type thin film transistors, but not limited thereto.

As shown in fig. 15, when the third embodiment of the shift register unit in the display device according to the present invention operates, the light emitting control period includes a first pre-stage t01, a second pre-stage t02, an input stage t1, a first output stage t21, a second output stage t22, a third output stage t23, a first reset stage t3, a second reset stage t4, and a reset and hold stage t5, which are sequentially arranged; a preliminary interval phase t00 is provided between the first preliminary phase t01 and the second preliminary phase t 02; a first separation phase t10 is provided between the input phase t1 and the first output phase t 21; a second interval phase t20 is provided between the first output phase t21 and the second output phase t 22; a third interval phase t30 is provided between the second output phase t22 and the third output phase t 23; a fourth interval phase t40 is provided between the third output phase t23 and the first reset phase t 3; a fifth interval phase t50 is provided between the first reset phase t3 and the second reset phase t 4;

in the first output stage T21, the potential of CK is maintained at a high level, the potential of CB jumps from the high level to a low level, STV inputs the high level, the potential of N3 is maintained at a low voltage, T6 is turned on, so that the second end of C2 is connected to CB, and as the potential of the second end of C2 decreases, the potential of the first end of C2 also decreases correspondingly, so that the potential of N3 is further pulled low (lower than VGL), so as to further improve the output capability of T6, and make the potential of NC be low voltage; t4 and T5 are opened, and N1 is connected to VGH, so that the potential of N1 is high voltage; t7 is turned on, N2 is connected into VGL, so that the potential of N2 is low voltage; t9 is turned on, T10 is turned off, and OUT outputs high voltage VGH; and T13 is turned off to disconnect the second terminal of C1 from the second clock signal terminal, so that the potential of N1 is not affected by CB and the potential of N1 can be maintained at a high voltage;

in the third interval period t30, the potential of CK jumps from low level to high level, the potential of CB is maintained at high level, STV input is high level, the potential of N1 is maintained at high voltage, the potential of N2 is maintained at low voltage, and the potential of N3 is maintained at low voltage;

in a third output stage T23, STV inputs low level, CK is high level, CB jumps from high level to low level, T6 opens, so that the second end of C2 is connected to CB, since the potential of the second end of C2 becomes low, the potential of N3 also becomes low accordingly, the output capability of T6 is enhanced, NC is low voltage, T7 opens, so that N2 is low voltage; the T5 is turned on, the T4 is turned on, so that the potential of the N1 is high voltage, the T13 is turned off, the disconnection between the second end of the C1 and the second clock signal end is controlled, the potential of the N1 is not influenced by CB, and the T10 is ensured to be turned off; t9 is opened, and OUT is controlled to output high voltage;

As shown in fig. 18, a fourth embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and the fourth embodiment of the shift register unit includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, and a light-emitting control signal output terminal OUT, wherein,

a gate of the third control transistor T6 is electrically connected to the third node N3, a source of the third control transistor T6 is electrically connected to the second clock signal terminal, and a drain of the third control transistor T6 is electrically connected to the control node NC; the second clock signal terminal is used for inputting a second clock signal CB;

In the fourth embodiment of the shift register unit in the display device according to the present invention, all the transistors are p-type thin film transistors, but not limited thereto.

As shown in fig. 15, in the fourth embodiment of the shift register unit in the display device according to the present invention, when operating, the light emitting control period includes a first pre-stage t01, a second pre-stage t02, an input stage t1, a first output stage t21, a second output stage t22, a third output stage t23, a first reset stage t3, a second reset stage t4, and a reset and hold stage t 5; a preliminary interval phase t00 is provided between the first preliminary phase t01 and the second preliminary phase t 02; a first separation phase t10 is provided between the input phase t1 and the first output phase t 21; a second interval phase t20 is provided between the first output phase t21 and the second output phase t 22; a third interval phase t30 is provided between the second output phase t22 and the third output phase t 23; a fourth interval phase t40 is provided between the third output phase t23 and the first reset phase t 3; a fifth interval phase t50 is provided between the first reset phase t3 and the second reset phase t 4;

in a first output stage T21, the potential of CK is maintained at a high level, the potential of CB jumps from the high level to a low level, STV inputs the high level, the potential of N3 is maintained at a low level, T6 is turned on to control the second end of C2 to be connected to CB, and as the potential of the second end of C2 decreases, the potential of the first end of C2 also decreases correspondingly, so that the potential of N3 is further pulled low (lower than VGL) to improve the output capability of T6; t4 and T5 are opened, and N1 is connected to VGH, so that the potential of N1 is high voltage; the method comprises the following steps that T6 is turned on, the potential of NC is low, T7 is turned on, N2 is connected to VGL, and therefore the potential of N2 is low; t9 is turned on, T10 is turned off, and OUT outputs high voltage VGH; and T13 is turned off to disconnect the second terminal of C1 from the second clock signal terminal, so that the potential of N1 is not affected by CB and the potential of N1 can be maintained at a high voltage;

in a third output stage T23, STV inputs low level, the potential of CK is high level, the potential of CB jumps from high level to low level, T6 is opened, the second end of C2 is connected to CB, the potential of N3 becomes low correspondingly as the potential of CB becomes low, the output capability of T6 is enhanced, T6 is opened to make the potential of NC low voltage, T7 is opened to make the potential of N2 low voltage; the T5 is turned on, the T4 is turned on, so that the potential of the N1 is high voltage, the T13 is turned off, the disconnection between the second end of the C1 and the second clock signal end is controlled, the potential of the N1 is not influenced by CB, and the T10 is ensured to be turned off; t9 is opened, and OUT is controlled to output high voltage;

As shown in fig. 19, a fifth embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, a second clock access control circuit 17, and a light-emitting control signal output terminal OUT, wherein,

a first terminal of the second storage capacitor C2 is electrically connected with the third node N3;

the gate of the eighth control transistor T5 is electrically connected to the third node N3, and the source of the eighth control transistor T5 is electrically connected to the second clock signal terminal; the second clock signal terminal is used for inputting a second clock signal CB;

the second clock access control circuit 17 comprises a second clock access control transistor T14;

the gate of the second clock access control transistor T14 is electrically connected to the third node N3, the source of the second clock access control transistor T14 is electrically connected to the second clock signal terminal, and the drain of the second clock access control transistor T14 is electrically connected to the second terminal of the second storage capacitor C2.

In a fifth embodiment of the shift register unit in the display device according to the invention, all the transistors are p-type thin film transistors, but not limited thereto.

The fifth embodiment of the shift register unit in the display device according to the present invention is different from the first embodiment of the shift register unit in the display device according to the present invention in that: the fifth embodiment of the shift register unit in the display device according to the present invention adds a second clock access control transistor T14;

in operation of the fifth embodiment of the shift register unit in the display device according to the invention,

when the potential of the N3 is at a low level, the T14 is turned on, the second end of the C2 is connected with the second clock signal CB, and when the potential of the CB jumps from a high level to a low level, the potential of the N3 can be further pulled down, so that the output capacity of the T6 is improved;

when the potential of the N3 is in a high level, the T14 is turned off, and the second end of the C2 and the second clock signal end are disconnected, so that the potential of the N3 is not influenced by CB, and the T6 is controlled to be turned off.

As shown in fig. 20, a sixth embodiment of the shift register unit in the display device according to the present invention is used for generating a light-emitting control signal, and includes an input terminal STV, a first node control circuit 11, a first storage capacitor circuit 12, a first clock access control circuit 13, a third node control circuit, a second node control circuit, an output circuit 16, a second clock access control circuit 17, and a light-emitting control signal output terminal OUT, wherein,

the gate of the eighth control transistor T5 is electrically connected to the third node N3, and the source of the eighth control transistor T5 is electrically connected to the high voltage terminal;

In the sixth embodiment of the shift register unit in the display device according to the present invention, all the transistors are p-type thin film transistors, but not limited thereto.

The sixth embodiment of the shift register unit in the display device according to the present invention is different from the second embodiment of the shift register unit in the display device according to the present invention in that: the sixth embodiment of the shift register unit in the display device according to the present invention adds a second clock access control transistor T14;

in operation of the sixth embodiment of the shift register unit in the display device according to the invention,

In an embodiment of the shift register unit in the display device of the present invention, T2 may be a double-gate transistor to avoid the potential drop of N3 caused by the leakage of T2.

The shift register unit in the display device according to the embodiment of the present invention may be composed of a first gate metal layer, a second gate metal layer, and a source drain metal layer, or may be composed of a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer.

The driving method of the embodiment of the invention is applied to the display device, and the display device comprises a light-emitting control circuit arranged in the driving circuit area; the light-emitting control circuit comprises a plurality of stages of shift register units; the output end of the shift register unit penetrates through the transition region and is electrically connected with the corresponding row pixel driving circuit in the display region so as to provide a light-emitting control signal for the corresponding row pixel driving circuit; the shift register unit comprises an input end, a first node control circuit, a first storage capacitor circuit, a first clock access control circuit, a second node control circuit, a third node control circuit, an output circuit and a light-emitting control signal output end;

the driving method includes:

According to the driving method provided by the embodiment of the invention, the first clock is connected to the control circuit, so that the light-emitting control signal is stably output, and the display effect of the display panel is ensured.

Specifically, the third node control circuit may include a first control circuit and a second storage capacitor circuit; the shift register unit also comprises a second clock access control circuit; the driving method may further include:

when the third node control circuit controls the electric potential of the third node to be at the first level, the second clock access control circuit controls the second end of the second storage capacitor circuit to be electrically connected with the second clock signal end under the control of the electric potential of the third node.

In a preferred case, the shift register unit may include a second clock access control circuit, and the second clock access control circuit controls, under control of a potential of a third node, whether the second end of the second storage capacitor circuit is electrically connected to the second clock signal terminal, so as to well control a potential of the third node, and improve an output capability of a transistor whose gate is electrically connected to the third node.

In a specific implementation, the light emission control period may include an input stage, a first output stage, a second output stage, a third output stage, a first reset stage, and a second reset stage, which are sequentially arranged; the driving method includes:

in the input stage, a first level is input at the input end, the first node control circuit controls the potential of a first node to be the first level, the output circuit controls the light-emitting control signal output end and the second voltage end to be disconnected, and the first clock access control circuit controls the second end of the first storage capacitor circuit and the second clock signal end to be disconnected; the third node control circuit controls the potential of a third node to be a second voltage, and the second node control circuit controls the second node to be in a floating state;

The display device according to the embodiment of the present invention may include a light emission control circuit, and the light emission control circuit may include a plurality of stages of the shift register units;

the light-emitting control signal output end of the adjacent upper-stage shift register unit is electrically connected with the input end of the lower-stage shift register unit.

In implementation, the display device may further include a gate driving circuit and a plurality of rows of pixel circuits; the gate driving circuit comprises a plurality of stages of gate driving units;

each stage of the grid driving unit is electrically connected with one row of the pixel circuits and is used for providing corresponding grid driving signals for the row of the pixel circuits;

each stage of shift register unit included in the light-emitting control circuit is electrically connected with two rows of pixel circuits respectively and is used for providing corresponding light-emitting control signals for the two rows of pixel circuits.

In a specific implementation, each stage of the shift register unit included in the light emission control circuit may be electrically connected to two adjacent rows of pixel circuits, respectively, and is configured to provide a corresponding light emission control signal for the two adjacent rows of pixel circuits, but not limited thereto.

As shown in fig. 21, the display device according to the embodiment of the invention includes a plurality of rows of pixel circuits, a first light-emitting control circuit disposed on the left side of the display panel, a second light-emitting control circuit disposed on the right side of the display panel, a first gate driving circuit disposed on the left side of the display panel, and a second gate driving circuit disposed on the right side of the display panel;

in fig. 21, a shift register unit of the first stage denoted by ESZ1 included in the first light emission control circuit, a shift register unit of the nth stage denoted by ESZN included in the first light emission control circuit, a shift register unit of the first stage denoted by ESR1 included in the second light emission control circuit, and a shift register unit of the nth stage denoted by ESRN included in the second light emission control circuit; n is an integer greater than 1;

in fig. 21, a first stage gate driving unit denoted by GSZ1 and included in the first gate driving circuit, a second stage gate driving unit denoted by GSZ2 and included in the first gate driving circuit, a 2N-1 stage gate driving unit denoted by GSZ2N-1 and a 2N stage gate driving unit denoted by GSZ2N and included in the first gate driving circuit; a first stage gate driving unit denoted by GSR1 and included in the second gate driving circuit, a second stage gate driving unit denoted by GSR2 and included in the second gate driving circuit, a 2N-1 stage gate driving unit denoted by GSR2N-1 and a 2N stage gate driving unit denoted by GSR2N and included in the second gate driving circuit;

in fig. 21, Pixel1 is denoted by a first row of Pixel circuits, Pixel2 is denoted by a second row of Pixel circuits, Pixel2N-1 is denoted by a 2N-1 row of Pixel circuits, and Pixel2N is denoted by a 2N-th row of Pixel circuits.

As shown in fig. 21, the first light-emitting control circuit is disposed outside the first gate driving circuit, the second light-emitting control circuit is disposed outside the second gate driving circuit, each stage of shift register unit included in the first light-emitting control circuit provides light-emitting control signals for two rows of pixel circuits, respectively, so as to reduce the number of adopted light-emitting control circuits, and output lines of the shift register units in the first light-emitting control circuit pass through two adjacent stages of gate driving units in the first gate driving circuit and are provided to the corresponding rows of pixel circuits, thereby facilitating implementation of a narrow frame; and clock signals accessed by adjacent two stages of shift register units included in each light-emitting control circuit are mutually inverted.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display device is characterized by comprising a display area, a driving circuit area and a transition area positioned between the display area and the driving circuit area;

the first electrodes included in different first light-emitting elements are arranged at intervals from each other;

the display device further comprises a second element arranged in the transition area; the second element includes a second light emitting layer;

a shape of the second light emitting layer is the same as a shape of a light emitting layer of the first light emitting element having the same color as the second light emitting layer;

the area of the second light emitting layer is the same as the area of a light emitting layer of the first light emitting element having the same color as the second light emitting layer.

2. The display device of claim 1, further comprising a display substrate, the pixel circuit being disposed on the display substrate;

3. The display device according to claim 1, further comprising a light emission control circuit provided in the driving circuit region;

4. The display device according to claim 1, further comprising a second light-emitting element provided in the transition region; the structure of the second light-emitting element is the same as that of the first light-emitting element; the second light-emitting element includes a light-emitting layer;

5. The display device according to claim 3, wherein the shift register unit includes an input terminal, a first node control circuit, a first storage capacitor circuit, a first clock access control circuit, a second node control circuit, a third node control circuit, an output circuit, and a light emission control signal output terminal, wherein,

6. The display device according to claim 5, wherein the output circuit is configured to supply the emission control signal to a control electrode of an emission control transistor in the pixel circuit to control the emission control transistor to turn off in a first phase;

7. The display device according to claim 5, wherein the first clock signal and the second clock signal have a first period in which phases are opposite and a second period in which phases are the same;

the second time period is adjacent to the first time period;

8. The display device of claim 5, wherein the first clock access control circuit comprises a first clock access control transistor;

9. The display device according to claim 5, wherein the third node control circuit includes a first control circuit and a second storage capacitor circuit;

10. The display device of claim 9, further comprising a second clock access control circuit;

11. The display device of claim 10, wherein the second clock access control circuit comprises a second clock access control transistor;

12. The display device according to claim 5, wherein the third node control circuit includes a first control circuit and a second storage capacitor circuit;

13. The display device according to any one of claims 9 to 12, wherein the first control circuit includes a first control transistor and a second control transistor;

14. The display device according to claim 13, wherein the first control transistor is a double gate transistor.

15. The display device according to any one of claims 5 to 12, wherein the second node control circuit includes a second control circuit, a third control circuit, a fourth control circuit, and a third storage capacitor circuit;

16. The display device according to claim 15, wherein the second control circuit includes a third control transistor, wherein the third control circuit includes a fourth control transistor, wherein the fourth control circuit includes a fifth control transistor;

17. The display device according to any one of claims 5 to 12, wherein the second node control circuit includes a second control circuit, a third control circuit, a fourth control circuit, and a third storage capacitor circuit;

18. The display device according to claim 17, wherein the second control circuit includes a third control transistor, the third control circuit includes a fourth control transistor, and the fourth control circuit includes a fifth control transistor;

19. The display device according to any one of claims 5 to 12, wherein the first node control circuit includes a sixth control transistor, a seventh control transistor, and an eighth control transistor;

20. The display device according to any one of claims 5 to 12, wherein the first node control circuit includes a sixth control transistor, a seventh control transistor, and an eighth control transistor;

21. The display device according to any one of claims 5 to 12, wherein the output circuit includes a first output transistor and a second output transistor;

22. A driving method applied to the display device according to any one of claims 5 to 21, wherein the driving method comprises:

23. The driving method according to claim 22, wherein the third node control circuit includes a first control circuit and a second storage capacitor circuit; the shift register unit also comprises a second clock access control circuit; the driving method further includes:

24. The driving method according to claim 22, wherein the light emission control period includes an input phase, a first output phase, a second output phase, a third output phase, a first reset phase, and a second reset phase, which are sequentially arranged; the driving method includes: