CN112652271B - Shift register, display panel and display device - Google Patents
Shift register, display panel and display device Download PDFInfo
- Publication number
- CN112652271B CN112652271B CN202011437701.3A CN202011437701A CN112652271B CN 112652271 B CN112652271 B CN 112652271B CN 202011437701 A CN202011437701 A CN 202011437701A CN 112652271 B CN112652271 B CN 112652271B
- Authority
- CN
- China
- Prior art keywords
- transistor
- node
- electrically connected
- clock signal
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The application discloses a shift register, a display panel and a display device. The shift register comprises a first node control module, a second node control module, a pull-up module, an input module, a first output module and a second output module. According to the embodiment of the application, the on-off state of the N-type transistor can be controlled by the scanning signal output by the output signal end through the mutual matching of the first node control module, the second node control module, the pull-up module, the input module, the first output module and the second output module, so that the control of the N-type transistor in the pixel circuit is realized.
Description
Technical Field
The application relates to the technical field of display, in particular to a shift register, a display panel and a display device.
Background
In an Active Matrix Organic Light Emitting Diode (AMOLED) display panel, a pixel circuit is generally used to drive the Light Emitting Diode to emit Light. The pixel circuit includes a plurality of transistors, and in order to reduce the leakage current phenomenon of the transistors, an oxide transistor is used in the pixel circuit, and the oxide transistor is usually an N-type transistor, so a new shift register is required to control the on-off state of the N-type transistor.
Disclosure of Invention
The embodiment of the application provides a shift register, a display panel and a display device, which can control the on-off state of an N-type transistor.
In a first aspect, an embodiment of the present application provides a shift register, which includes a first node control module, a second node control module, a pull-up module, an input module, a first output module, and a second output module; the first node control module is used for writing a first clock signal into a first node under the control of the first clock signal provided by the first clock signal terminal and the potential of a second node; the second node control module is used for writing a second clock signal provided by a second clock signal end into a second node under the control of the potential of a third node, or writing a first voltage signal provided by a first voltage end into the second node under the control of the second clock signal; the pull-up module is used for writing a third clock signal provided by a third clock signal end into the first node under the control of the potential of the third node; the input module is used for writing an input signal provided by the input signal end into a third node under the control of a second clock signal and a third clock signal; the first output module is used for transmitting the third clock signal to the output signal end under the control of the electric potential of the first node; the second output module is used for transmitting the first voltage signal to the output signal end under the control of the electric potential of the third node.
In a possible implementation manner of the first aspect, the shift register further includes a pull-down module, where the pull-down module is electrically connected to the second node, the third node, the first clock signal terminal, and the second voltage terminal, and is configured to pull down a potential of the third node.
In one possible implementation of the first aspect, the pull-down module includes a first transistor, a second transistor, and a first capacitor;
the grid electrode of the first transistor is electrically connected with the third node, the first electrode of the first transistor is electrically connected with the fourth node, and the second electrode of the first transistor is electrically connected with the first clock signal end;
the grid electrode of the second transistor is electrically connected with the second node, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the second voltage end;
the first pole of the first capacitor is electrically connected with the fourth node, and the second pole of the first capacitor is electrically connected with the third node.
In one possible implementation of the first aspect, the first node control module includes a third transistor and a fourth transistor;
the grid electrode of the third transistor is electrically connected with the second node, the first electrode of the third transistor is electrically connected with the second electrode of the fourth transistor, and the second electrode of the third transistor is electrically connected with the first clock signal end;
the grid of the fourth transistor is electrically connected with the first clock signal end, and the first electrode of the fourth transistor is electrically connected with the first node.
In a possible implementation manner of the first aspect, the shift register further includes a second capacitor, a first pole of the second capacitor is electrically connected to the second node, and a second pole of the second capacitor is electrically connected to the first pole of the third transistor and the second pole of the fourth transistor.
In one possible implementation of the first aspect, the second node control module includes a fifth transistor and a sixth transistor;
the grid electrode of the fifth transistor is electrically connected with the second clock signal end, the first electrode of the fifth transistor is electrically connected with the first voltage end, and the second electrode of the fifth transistor is electrically connected with the second node;
the grid electrode of the sixth transistor is electrically connected with the third node, the first electrode of the sixth transistor is electrically connected with the second clock signal end, and the second electrode of the sixth transistor is electrically connected with the second node.
In a possible implementation manner of the first aspect, the shift register further includes a seventh transistor, the fifth transistor is electrically connected to the second node through the seventh transistor, a gate of the seventh transistor is electrically connected to the first voltage terminal, a first electrode of the seventh transistor is electrically connected to the second node, and a second electrode of the seventh transistor is electrically connected to the second electrode of the fifth transistor.
In a possible implementation manner of the first aspect, the shift register further includes an eighth transistor, the sixth transistor is electrically connected to the second node through the eighth transistor, a gate of the eighth transistor is electrically connected to the first voltage terminal, a first electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the second electrode of the sixth transistor.
In a possible implementation manner of the first aspect, the pull-up module includes a ninth transistor, a gate of the ninth transistor is electrically connected to the third node, a first pole of the ninth transistor is electrically connected to the first node, and a second pole of the ninth transistor is electrically connected to the third clock signal terminal.
In a possible implementation manner of the first aspect, the shift register further includes a tenth transistor, a gate of the ninth transistor is electrically connected to the third node through the tenth transistor, a gate of the tenth transistor is electrically connected to the first voltage terminal, a first electrode of the tenth transistor is electrically connected to a gate of the ninth transistor, and a second electrode of the tenth transistor is electrically connected to the third node.
In one possible implementation of the first aspect, the input module includes an eleventh transistor and a twelfth transistor;
a first electrode of the eleventh transistor is electrically connected to the input signal terminal, a second electrode of the eleventh transistor is electrically connected to a first electrode of the twelfth transistor, a second electrode of the twelfth transistor is electrically connected to the third node, a gate of one of the eleventh transistor and the twelfth transistor is electrically connected to the second clock signal terminal, and a gate of the other of the eleventh transistor and the twelfth transistor is electrically connected to the third clock signal terminal.
In a possible implementation manner of the first aspect, the first output module includes a thirteenth transistor, a gate of the thirteenth transistor is electrically connected to the first node, a first electrode of the thirteenth transistor is electrically connected to the third clock signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the output signal terminal;
the second output module comprises a fourteenth transistor, a grid electrode of the fourteenth transistor is electrically connected with the third node, a first electrode of the fourteenth transistor is electrically connected with the output signal end, and a second electrode of the fourteenth transistor is electrically connected with the first voltage end.
In a possible implementation manner of the first aspect, the shift register further includes a third capacitor, a first electrode of the third capacitor is electrically connected to the third clock signal terminal, and a second electrode of the third capacitor is electrically connected to the first node.
In a possible implementation manner of the first aspect, the shift register further includes a fifteenth transistor, the first node control module and the pull-up module are electrically connected to the first node through the fifteenth transistor, a gate of the fifteenth transistor is electrically connected to the first voltage terminal, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the first node control module and the pull-up module.
In a possible implementation manner of the first aspect, the shift register further includes a sixteenth transistor, the input module and the second node control module are electrically connected to the third node through the sixteenth transistor, a gate of the sixteenth transistor is electrically connected to the first voltage level terminal, a first electrode of the sixteenth transistor is electrically connected to the input module and the second node control module, and a second electrode of the sixteenth transistor is electrically connected to the third node.
In a second aspect, an embodiment of the present application provides a display panel, which includes a plurality of cascaded shift registers as in any one of the embodiments of the first aspect.
In a third aspect, embodiments of the present application provide a display device, including the display panel according to the second aspect.
In the embodiment of the application, through the mutual cooperation of the first node control module, the second node control module, the pull-up module, the input module, the first output module and the second output module, the on-off state of the N-type transistor can be controlled by the scanning signal output by the output signal end, so that the control of the N-type transistor in the pixel circuit is realized.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 shows a schematic structural diagram of a pixel circuit of an example in the related art;
FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present application;
FIG. 3 is a schematic diagram of timing signals provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of a shift register according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a shift register according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a shift register according to another embodiment of the present application;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a cascade structure of a shift register according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when an element is referred to as being "on" or "over" another layer, region or layer in describing its structure, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
Fig. 1 shows a schematic structural diagram of a pixel circuit of an example in the related art. As shown in fig. 1, the pixel circuit includes seven transistors M11-M17 and a capacitor C11. The transistor M11 is a driving transistor, and the transistor M13 and the transistor M14 are both electrically connected to the gate of the driving transistor M11. The oxide transistor has a characteristic of small leakage current, and in order to reduce the influence of the leakage current of the transistor M13 and the transistor M14 on the gate potential of the driving transistor M11, the transistor M13 and the transistor M14 may be oxide transistors. The oxide transistor is usually an N-type transistor, and the on level and the off level of the N-type transistor are high and low, respectively, so that a new shift register is required to control the on/off state of the N-type transistor.
In order to solve the above technical problems, embodiments of a shift register, a display panel and a display device are provided, and the following describes embodiments of the shift register, the display panel and the display device with reference to the accompanying drawings.
Fig. 2 shows a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 2, a shift register provided in the embodiment of the present application includes a first node control module 11, a second node control module 12, a pull-up module 13, an input module 14, a first output module 15, and a second output module 16.
The first node control module 11 is configured to write the first clock signal SCK1 into the first node N1 under the control of the potentials of the first clock signal SCK1 provided by the first clock signal terminal SCK1 and the second node N2. The second node control module 12 is configured to write the second clock signal SCK2 provided by the second clock signal terminal SCK2 into the second node N2 under the control of the potential of the third node N3, or write the first voltage signal provided by the first voltage terminal VGL into the second node N2 under the control of the second clock signal SCK 2. The pull-up module 13 is configured to write the third clock signal SCK2 provided from the third clock signal terminal SCK3 into the first node under the control of the potential of the third node N3. The input module 14 is configured to write the input signal SIN provided by the input signal terminal SIN into the third node N3 under the control of the second clock signal sck2 and the third clock signal sck 3. The first output module 15 is configured to transmit the third clock signal sck3 to the output signal terminal S _ out under the control of the potential of the first node N1. The second output module 16 is configured to transmit the first voltage signal provided by the first voltage terminal VGL to the output signal terminal S _ out under the control of the potential of the third node N3.
It is understood that the first node control module 11 is electrically connected to the first clock signal terminal SCK1, the first node N1 and the second node N2; the second node control module 12 is electrically connected to the second clock signal terminal SCK2, the first voltage terminal VGL, the second node N2 and the third node N3; the pull-up module 13 is electrically connected to the third node N3, the third clock signal terminal SCK3 and the first node N1; the input module 14 is electrically connected to the second clock signal terminal SCK2, the third clock signal terminal SCK3, the input signal terminal SIN and the third node N3; the first output module 15 is electrically connected to the first node N1, the third clock signal terminal SCK3 and the output signal terminal S _ out; the second output module 16 is electrically connected to the third node N3, the first voltage terminal VGL, and the output signal terminal S _ out.
The first node N1 represents a connection point between the first node control module 11, the pull-up module 13, and the first output module 15, the second node N2 represents a connection point between the first node control module 11 and the second node control module 12, and the third node N3 represents a connection point between the input module 14, the pull-up module, and the second output module 16.
In the embodiment of the present application, through the mutual cooperation among the first node control module 11, the second node control module 12, the pull-up module 13, the input module 14, the first output module 15, and the second output module 16, the scan signal output by the output signal terminal S _ out can be realized to control the on-off state of the N-type transistor, so as to realize the control of the N-type transistor in the pixel circuit.
FIG. 3 illustrates a timing signal diagram according to an embodiment of the present application. In this application, the first voltage terminal VGL is a fixed voltage terminal. The first voltage terminal VGL may be a low level dc power source terminal, and a first voltage signal (not shown in fig. 3) provided by the first voltage terminal VGL may always be a low level signal. In this application, the input signal SIN is provided by the input signal SIN, the first clock signal SCK1 provides the first clock signal SCK1, the second clock signal SCK2 provides the second clock signal SCK2, and the third clock signal SCK3 provides the third clock signal SCK 3. Illustratively, a first rising edge of the second clock signal sck2 precedes a first falling edge of the first clock signal sck1, and a first falling edge of the first clock signal sck1 precedes a first rising edge of the third clock signal sck3 during one frame period. The low-level duty ratio of the first clock signal sck1 and the second clock signal sck2 may be less than 50%.
The operation of the shift register according to the embodiment of the present application will be described in detail below with reference to the shift register structure in fig. 2 and the timing signals in fig. 3.
In the initial period t0, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are at a low level, the first clock signal sck1 is at a high level, the input signal sin at the low level is transmitted to the third node N3 through the input module 14, the second clock signal sck2 at the low level and the first voltage signal at the low level are transmitted to the second node N2 through the second node control module 12, the third clock signal sck3 is transmitted to the first node N1 through the pull-up module 13, the first output module 15 and the second output module 16 are both in a conductive state, and the output signal terminal S _ out outputs a low level.
In the first period t1, the second clock signal SCK2 and the third clock signal SCK3 are at a low level, the input signal sin and the first clock signal SCK1 are at a high level, the high-level input signal sin is transmitted to the third node N3 through the input module 14, the low-level first voltage signal is transmitted to the second node N2 through the second node control module 12, since the first clock signal SCK1 is at a high level and no signal is transmitted to the first node N1, the first node N1 maintains a low level, the first output module 15 is turned on, the second output module 16 is turned off, and the output signal terminal S _ outputs a low level out provided by the third clock signal terminal SCK 3.
In the second period t2, the second clock signal SCK2 and the third clock signal SCK3 are at a high level, the input signal sin and the first clock signal SCK1 are at a low level, the second node N2 is maintained at a low level, the third node N3 is maintained at a high level, the first clock signal SCK1 at a low level is transmitted to the first node N1 through the first node control module 11, the first output module 15 is turned on, the second output module 16 is turned off, and the output signal terminal S _ out outputs the high level provided by the third clock signal terminal SCK 3.
In the third period t3, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are at a low level, the first clock signal sck1 is at a high level, the input signal sin at the low level is transmitted to the third node N3 through the input module 14, the first voltage signal at the low level is transmitted to the second node N2 through the second node control module 12, the third clock signal sck3 at the low level is transmitted to the first node N1 through the pull-up module 13, the first output module 15 and the second output module 16 are both turned on, and the output signal terminal S _ out outputs the low level.
In the fourth period t4, the second clock signal sck2 and the third clock signal sck3 are at a high level, the input signal sin and the first clock signal sck1 are at a low level, the third node N3 is maintained at a low level, the second clock signal sck2 at the high level is transmitted to the second node N2 through the second node control module 12, the third clock signal sck3 at the high level is transmitted to the first node N1 through the pull-up module 13, so that the potential of the first node N1 is pulled up, the first output module 15 is turned off, the second output module 16 is turned on, and the output signal terminal S _ outputs the low level provided by the first level terminal VGL. At this stage, the pull-up module 13 pulls up the potential of the first node N1, so as to prevent the output signal terminal S _ out from outputting the high level provided by the third clock signal terminal SCK 3.
In the fifth period t5, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are at a low level, the first clock signal sck1 is at a high level, the input signal sin at the low level is transmitted to the third node N3 through the input module 14, the first voltage signal at the low level is transmitted to the second node N2 through the second node control module 12, the third clock signal sck3 at the low level is transmitted to the first node N1 through the pull-up module 13, the first output module 15 and the second output module 16 are both turned on, and the output signal terminal S _ out outputs the low level.
The sixth period t6 is the same as the fourth period t4, and the seventh period t7 is the same as the fifth period t5, which will not be described in detail herein.
Fig. 4 shows a schematic structural diagram of a shift register according to another embodiment of the present application. In some optional embodiments, as shown in fig. 4, the shift register provided in the embodiments of the present application may further include a pull-down module 17. The pull-down module 17 is electrically connected to the second node N2, the third node N3, the first clock signal terminal SCK1, and the second voltage terminal VGH, and is configured to pull down the potential of the third node N3. The pull-down module 17 can make the third node N3 reach an ultra-low level, so that the control output signal terminal S _ out can mostly keep outputting at a low level, and the shift register can better control the N-type transistor in the pixel circuit.
Fig. 5 shows a schematic structural diagram of a shift register according to another embodiment of the present application. As shown in fig. 5, the first node control module 11, the second node control module 12, the pull-up module 13, the input module 14, the first output module 15, the second output module 16, and the pull-down module 17 may be composed of components. The specific structures of the first node control module 11, the second node control module 12, the pull-up module 13, the input module 14, the first output module 15, the second output module 16, and the pull-down module 17 will be exemplified below.
In some alternative embodiments, the pull-down module 17 may include a first transistor T1, a second transistor T2, and a first capacitor C1.
A gate of the first transistor T1 is electrically connected to the third node N3, a first pole of the first transistor T1 is electrically connected to the fourth node N4, and a second pole of the first transistor T1 is electrically connected to the first clock signal terminal SCK 1; a gate of the second transistor T2 is electrically connected to the second node N2, a first pole of the second transistor T2 is electrically connected to the fourth node N4, and a second pole of the second transistor T2 is electrically connected to the second voltage terminal VGH; a first pole of the first capacitor C1 is electrically connected to the fourth node N4, and a second pole of the first capacitor C1 is electrically connected to the third node N3.
It is understood that the fourth node N4 is a connection point between the first transistor T1, the second transistor T2 and the first capacitor C1. In this application, the second voltage terminal VGH is a fixed voltage terminal. The second voltage terminal VGH may be a high level dc power terminal, and a second voltage signal (not shown in fig. 3) provided by the second voltage terminal VGH may be a high level signal all the time.
The first transistor T1 and the second transistor T2 may be P-type transistors or N-type transistors, and the types of the first transistor T1 and the second transistor T2 are not limited in the present application. The first transistor T1 and the second transistor T2 are both P-type transistors, and will be described as an example.
In the third stage T3, the second node N2 and the third node N3 are both at a low level, the first transistor T1 and the second transistor T2 are both turned on, and the high-level second voltage signal provided by the second voltage terminal VGH is transmitted to the first pole of the first capacitor C1 through the second transistor T2 to initialize the first pole of the first capacitor C1. In the fourth stage T4, the first transistor T1 is still turned on, the first clock signal SCK1 provides the first clock signal SCK1 to transition to low level, so as to pull down the potential of the first electrode of the first capacitor C1 in a short time, and due to the coupling effect of the first capacitor C1, the potential of the second electrode of the first capacitor C1 is also pulled down instantaneously, so as to further pull down the potential of the third node N3.
In some alternative embodiments, as shown in fig. 5, the first node control module 11 includes a third transistor T3 and a fourth transistor T4.
A gate of the third transistor T3 is electrically connected to the second node N2, a first pole of the third transistor T3 is electrically connected to a second pole of the fourth transistor T4, and a second pole of the third transistor T3 is electrically connected to the first clock signal terminal SCK 1. The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal SCK1, and the first pole of the fourth transistor T4 is electrically connected to the first node N1.
In some alternative embodiments, as shown in fig. 6, the shift register further includes a second capacitor C2, a first pole of the second capacitor C2 is electrically connected to the second node N2, and a second pole of the second capacitor C2 is electrically connected to a first pole of the third transistor T3 and a second pole of the fourth transistor T4.
The third transistor T3 and the fourth transistor T4 may be P-type transistors or N-type transistors, and the types of the third transistor T3 and the fourth transistor T4 are not limited in this application. The third transistor T3 and the fourth transistor T4 are both P-type transistors, and will be described as an example.
The second node N2 maintains a low level for the first period t 1; in the second period T2, the first clock signal terminal SCK1 provides the first clock signal SCK1 to transition to a low level, the fourth transistor T4 is turned on, the potential of the second node N2 is further pulled down due to the coupling effect of the second capacitor C2, the third transistor T3 is fully turned on, and the low level first clock signal SCK1 is transmitted to the first node N1 through the third transistor T3 and the fourth transistor T4, so that the first node N1 maintains a low level.
In some alternative embodiments, as shown in FIG. 5, the second node control module 12 includes a fifth transistor T5 and a sixth transistor T6. A gate of the fifth transistor T5 is electrically connected to the second clock signal terminal SCK2, a first pole of the fifth transistor T5 is electrically connected to the first voltage terminal VGL, and a second pole of the fifth transistor T5 is electrically connected to the second node N2. A gate of the sixth transistor T6 is electrically connected to the third node N3, a first pole of the sixth transistor T6 is electrically connected to the second clock signal terminal SCK2, and a second pole of the sixth transistor T6 is electrically connected to the second node N2.
In some alternative embodiments, as shown in fig. 6, the shift register further includes a seventh transistor T7, and the fifth transistor T5 is electrically connected to the second node through the seventh transistor T7. Specifically, the gate of the seventh transistor T7 is electrically connected to the first voltage terminal VGL, the first pole of the seventh transistor T7 is electrically connected to the second node N2, and the second pole of the seventh transistor T7 is electrically connected to the second pole of the fifth transistor T5.
In some optional embodiments, with continued reference to fig. 6, the shift register further includes an eighth transistor T6, and the sixth transistor T6 is electrically connected to the second node N2 through the eighth transistor T8. Specifically, the gate of the eighth transistor T8 is electrically connected to the first voltage terminal VGL, the first pole of the eighth transistor T8 is electrically connected to the second node N2, and the second pole of the eighth transistor T8 is electrically connected to the second pole of the sixth transistor T6.
Illustratively, the seventh transistor T7 and the eighth transistor T8 may be P-type transistors. The seventh transistor T7 and the eighth transistor T8 are always in a conductive state.
As described above, during the second period T2, the potential of the second node N2 is further pulled low due to the coupling effect of the second capacitor C2, and the seventh transistor T7 can prevent the second pole of the fifth transistor T5 from being stressed (stress), so as to prevent the fifth transistor T5 from being broken down; the eighth transistor T8 may prevent the second pole of the sixth transistor T6 from being stressed (stress) and prevent the sixth transistor T6 from being broken.
In some alternative embodiments, as shown in fig. 5, the pull-up module 13 includes a ninth transistor T9, a gate of the ninth transistor T9 is electrically connected to the third node N3, a first pole of the ninth transistor T9 is electrically connected to the first node N1, and a second pole of the ninth transistor T9 is electrically connected to the third clock signal terminal SCK 3. Taking the ninth transistor T9 as an example of a P-type transistor, during the fourth period T4, the third node N3 is maintained at a low level, the ninth transistor T9 is turned on, and the high-level third clock signal SCK3 provided by the third clock signal terminal SCK3 is transmitted to the first node N1 through the ninth transistor T9, so that the first node N1 becomes a high level. That is, in the fourth period T4, the ninth transistor T9 forms an inverter between the first node N1 and the third node N3, and prevents the output signal terminal S _ out from outputting the high-level third clock signal SCK3 provided from the third clock signal terminal SCK 3.
In some alternative embodiments, as shown in fig. 6, the shift register further includes a tenth transistor T10, and the gate of the ninth transistor T9 is electrically connected to the third node N3 through the tenth transistor T10. Specifically, a gate of the tenth transistor T10 is electrically connected to the first voltage terminal VGL, a first electrode of the tenth transistor T10 is electrically connected to a gate of the ninth transistor T9, and a second electrode of the tenth transistor T10 is electrically connected to the third node N3.
Illustratively, the tenth transistor T10 may be a P-type transistor. The tenth transistor T10 is always in a conductive state. As described above, during the fourth period T4, the potential of the third node N3 is further pulled low due to the coupling effect of the first capacitor C1, and the tenth transistor T10 can prevent the gate of the ninth transistor T9 from being stressed (stress) and prevent the ninth transistor T9 from being broken down.
In some alternative embodiments, as shown in fig. 5, the input block 14 includes an eleventh transistor T11 and a twelfth transistor T12. A first pole of the eleventh transistor T11 is electrically connected to the input signal terminal SIN, a second pole of the eleventh transistor T11 is electrically connected to a first pole of the twelfth transistor T12, a second pole of the twelfth transistor T12 is electrically connected to the third node N3, gates of one of the eleventh transistor T11 and the twelfth transistor T12 are electrically connected to the second clock signal terminal SCK2, and a gate of the other is electrically connected to the third clock signal terminal SCK 3. Fig. 5 exemplarily shows that the gate of the eleventh transistor T11 is electrically connected to the second clock signal terminal SCK2, and the gate of the twelfth transistor T12 is electrically connected to the third clock signal terminal SCK 3. Fig. 5 exemplarily shows that the gate of the eleventh transistor T11 is electrically connected to the third clock signal terminal SCK3, and the gate of the twelfth transistor T12 is electrically connected to the second clock signal terminal SCK 2.
In some alternative embodiments, as shown in fig. 5, the first output module 15 includes a thirteenth transistor T13, a gate of the thirteenth transistor T13 is electrically connected to the first node N1, a first pole of the thirteenth transistor T13 is electrically connected to the third clock signal terminal SCK3, and a second pole of the thirteenth transistor T13 is electrically connected to the output signal terminal S _ out. The second output module 16 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is electrically connected to the third node N3, a first pole of the fourteenth transistor T14 is electrically connected to the output signal terminal S _ out, and a second pole of the fourteenth transistor T14 is electrically connected to the first voltage terminal VGL.
In some alternative embodiments, as shown in fig. 6, the shift register further includes a third capacitor C3, a first pole of the third capacitor C3 is electrically connected to the third clock signal terminal SCK3, and a second pole of the third capacitor C3 is electrically connected to the first node N1. By providing the third capacitor C3, the potential of the first node N1 can be maintained better.
In some optional embodiments, as shown in fig. 6, the shift register further includes a fifteenth transistor T15, and the first node control module 11 and the pull-up module 13 are electrically connected to the first node N1 through the fifteenth transistor T15. A gate of the fifteenth transistor T15 is electrically connected to the first voltage terminal VGL, a first pole of the fifteenth transistor T15 is electrically connected to the first node N1, and a second pole of the fifteenth transistor T15 is electrically connected to the first node control module 11 and the pull-up module 13. Illustratively, the second pole of the fifteenth transistor T15 is electrically connected to the first pole of the fourth transistor T4 and the first pole of the ninth transistor T9.
Exemplarily, the fifteenth transistor T15 may be a P-type transistor. The fifteenth transistor T15 is always in a conductive state. In the third period T3, the third clock signal sck3 transitions to a low level, and due to the coupling effect of the third capacitor C3, the potential of the first node N1 is further pulled low, and the fifteenth transistor T15 can prevent the first pole of the ninth transistor T9 and the first pole of the fourth transistor T4 from being stressed (stress), so as to prevent the ninth transistor T9 and the fourth transistor T4 from being broken down.
In some optional embodiments, as shown in fig. 6, the shift register further includes a sixteenth transistor T16, the input module 14 and the second node control module 12 are electrically connected to the third node N3 through a sixteenth transistor T16, a gate of the sixteenth transistor T16 is electrically connected to the first voltage terminal VGL, a first pole of the sixteenth transistor T16 is electrically connected to the input module 14 and the second node control module 12, and a second pole of the sixteenth transistor T16 is electrically connected to the third node N3. Illustratively, a first pole of the sixteenth transistor T16 is electrically connected to both the gate of the sixth transistor T6 and the second pole of the twelfth transistor T12.
Illustratively, the sixteenth transistor T16 may be a P-type transistor. The sixteenth transistor T16 is always in a conductive state. As described above, during the fourth period T4, the potential of the third node N3 is further pulled low by the coupling effect of the first capacitor C1, and the sixteenth transistor T16 can prevent the gate of the sixth transistor T6 and the second pole of the twelfth transistor T12 from being stressed (stress), so as to prevent the sixth transistor T6 and the twelfth transistor T12 from being broken down.
Hereinafter, the operation of the shift register will be further described with reference to the timing diagram shown in fig. 3 and the circuit structure of the shift register shown in fig. 5, in which each transistor is a P-type transistor.
In the initial period T0, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are at a low level, the first clock signal sck1 is at a high level, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the input signal sin at the low level is transmitted to the third node N3 through the input module 14; the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, the second clock signal sck2 of a low level is transmitted to the second node N2 through the sixth transistor T6, the first voltage signal of a low level is transmitted to the second node N2 through the fifth transistor T5, the third clock signal sck3 is transmitted to the first node N1 through the ninth transistor T9, the thirteenth transistor T13 and the fourteenth transistor T14 are both in a pass state, and the output signal terminal S _ out outputs a low level.
In the first period T1, the second clock signal sck2 and the third clock signal sck3 are at a low level, the input signal sin and the first clock signal sck1 are at a high level, the eleventh transistor T11 and the twelfth transistor T12 are still in a conducting state, and the input signal sin at the high level is transmitted to the third node N3 through the input module 14; the fifth transistor T5 is still turned on, the sixth transistor T6 is turned off, the first voltage signal with a low level is transmitted to the second node N2 through the fifth transistor T5, since the first clock signal SCK1 is at a high level, no signal is transmitted to the first node N1, the first node N1 is maintained at a low level, the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and the output signal terminal S _ out outputs a low level provided by the third clock signal terminal SCK 3.
In the second period t2, the second clock signal sck2 and the third clock signal sck3 are at a high level, and the input signal sin and the first clock signal sck1 are at a low level; the eleventh transistor T11 and the twelfth transistor T12 are turned off, and the third node N3 maintains a high level; the fifth transistor T5 and the sixth transistor T6 are turned off, and the second node N2 maintains a low level; the third transistor T3 and the fourth transistor T4 are turned on, the first clock signal SCK1 of a low level is transmitted to the first node N1 through the third transistor T3 and the fourth transistor T4, the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and the output signal terminal S _ out outputs a high level provided from the third clock signal terminal SCK 3.
In the third period t3, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are low, and the first clock signal sck1 is high; the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the input signal sin of a low level is transmitted to the third node N3 through the eleventh transistor T11 and the twelfth transistor T12; the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, the second clock signal sck2 of a low level is transmitted to the second node N2 through the sixth transistor T6, the first voltage signal of a low level is transmitted to the second node N2 through the fifth transistor T5, the third clock signal sck3 of a low level is transmitted to the first node N1 through the ninth transistor T9, the thirteenth transistor T13 and the fourteenth transistor T14 are both turned on, and the output signal terminal S _ out outputs a low level.
In a fourth period t4, the second clock signal sck2 and the third clock signal sck3 are at high level, and the input signal sin and the first clock signal sck1 are at low level; the eleventh transistor T11 and the twelfth transistor T12 are turned off, and the third node N3 maintains a low level; the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the high level second clock signal sck2 is transmitted to the second node N2 through the sixth transistor T6; the ninth transistor T9 is turned on, the third clock signal sck3 of a high level is transmitted to the first node N1 through the ninth transistor T9, thereby pulling up the potential of the first node N1, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned on, and the output signal terminal S _ out outputs a low level provided by the first level terminal VGL.
In the fifth period t5, the input signal sin, the second clock signal sck2 and the third clock signal sck3 are low, and the first clock signal sck1 is high; the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the input signal sin of a low level is transmitted to the third node N3 through the eleventh transistor T11 and the twelfth transistor T12; the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, the second clock signal sck2 of a low level is transmitted to the second node N2 through the sixth transistor T6, the first voltage signal of a low level is transmitted to the second node N2 through the fifth transistor T5, the third clock signal sck3 of a low level is transmitted to the first node N1 through the ninth transistor T9, the thirteenth transistor T13 and the fourteenth transistor T14 are both turned on, and the output signal terminal S _ out outputs a low level.
The sixth period t6 is the same as the fourth period t4, and the seventh period t7 is the same as the fifth period t5, which will not be described in detail herein.
In addition, in the third stage T3, the second node N2 and the third node N3 are both low level, the first transistor T1 and the second transistor T2 are both turned on, and the high level second voltage signal provided by the second voltage terminal VGH is transmitted to the first pole of the first capacitor C1 through the second transistor T2 to initialize the first pole of the first capacitor C1. In the fourth stage T4, the first transistor T1 is still turned on, the first clock signal terminal SCK1 provides the first clock signal SCK1 to transition to low level, so as to pull down the first electrode of the first capacitor C1 in a short time, and due to the coupling effect of the first capacitor C1, the second electrode of the first capacitor C1 is also pulled down instantaneously, so as to further pull down the potential of the third node N3.
Fig. 7 shows a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 7, the display panel 100 includes a display area AA and a non-display area NA. The display area AA includes pixel circuits (not shown) and scan lines 20. The non-display area NA includes a gate driving circuit 10, and the gate driving circuit 10 includes a plurality of cascaded shift registers according to any one of the above embodiments. The display panel 100 may be dual gate driven, that is, a gate driving circuit is disposed on both sides of the display area AA.
The display panel provided in the embodiments of the present application has the beneficial effects of the shift register provided in any of the embodiments of the present application, and specific descriptions of the shift register in the embodiments may be specifically referred to, and this embodiment is not described herein again.
Fig. 8 is a schematic diagram illustrating a cascade structure of a shift register according to an embodiment of the present application. In some alternative embodiments, as shown in fig. 8, the gate driving circuit 10 includes N cascaded shift registers according to any one of the above embodiments, where N is a positive integer greater than 1. Except the last stage of shift register SR _ N, the output signal terminal of each stage of shift register is electrically connected with the input signal terminal SIN of the next stage of shift register.
For example, the display panel may be provided with four clock signal lines 31, 32, 33, and 34, wherein the clock signal line 31 is connected to the first clock signal terminal SCK1, the clock signal line 32 is connected to the second clock signal terminal SCK2, the clock signal line 33 is connected to the third clock signal terminal SCK3, and the clock signal line 34 is connected to the fourth clock signal terminal SCK 4. For example, transistors of the odd-numbered stage shift register, which need to be electrically connected to the first clock signal terminal SCK1, are connected to the clock signal line 31, transistors of the odd-numbered stage shift register, which need to be electrically connected to the second clock signal terminal SCK2, are connected to the clock signal line 32, and transistors of the odd-numbered stage shift register, which need to be electrically connected to the third clock signal terminal SCK3, are connected to the clock signal line 33. The transistors of the even-numbered stage shift register, which need to be electrically connected to the first clock signal terminal SCK1, are connected to the clock signal line 32, the transistors of the even-numbered stage shift register, which need to be electrically connected to the second clock signal terminal SCK2, are connected to the clock signal line 31, and the transistors of the even-numbered stage shift register, which need to be electrically connected to the third clock signal terminal SCK3, are connected to the clock signal line 34. The clock signal provided by the fourth clock signal terminal SCK4 may be the same as the clock signal provided by the third clock signal terminal SCK3, but the high levels of the two are shifted from each other.
In addition, the input signal terminal SIN of the first stage shift register SR _1 is electrically connected to the start signal terminal STV.
The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 9, fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 9 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 9 by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (15)
1. A shift register is characterized by comprising a first node control module, a second node control module, a pull-up module, an input module, a first output module and a second output module;
the first node control module is electrically connected with the first clock signal end, the first node and the second node and is used for writing the first clock signal into the first node under the control of the potentials of the first clock signal provided by the first clock signal end and the second node;
the second node control module is electrically connected with a second clock signal end, the second node, the third node and the first voltage end, and is used for writing a second clock signal provided by the second clock signal end into the second node under the control of the potential of the third node, or writing a first voltage signal provided by the first voltage end into the second node under the control of the second clock signal;
the pull-up module is electrically connected with a third clock signal end, the first node and the third node, and is used for writing a third clock signal provided by the third clock signal end into the first node under the control of the potential of the third node;
the input module is electrically connected with an input signal end, the second clock signal end, the third clock signal end and the third node, and is used for writing an input signal provided by the input signal end into the third node under the control of the second clock signal and the third clock signal;
the first output module is electrically connected with the first node, the third clock signal end and the output signal end and is used for transmitting the third clock signal to the output signal end under the control of the potential of the first node;
the second output module is electrically connected with the third node, the first voltage end and the output signal end and is used for transmitting the first voltage signal to the output signal end under the control of the potential of the third node;
wherein the first node control module includes a third transistor and a fourth transistor, and the input module includes an eleventh transistor and a twelfth transistor;
a gate of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to a second electrode of the fourth transistor, and the second electrode of the third transistor is electrically connected to the first clock signal terminal;
a gate of the fourth transistor is electrically connected to the first clock signal terminal, and a first electrode of the fourth transistor is electrically connected to the first node;
a first electrode of the eleventh transistor is electrically connected to the input signal terminal, a second electrode of the eleventh transistor is electrically connected to a first electrode of the twelfth transistor, a second electrode of the twelfth transistor is electrically connected to the third node, a gate of one of the eleventh transistor and the twelfth transistor is electrically connected to the second clock signal terminal, and a gate of the other of the eleventh transistor and the twelfth transistor is electrically connected to the third clock signal terminal.
2. The shift register according to claim 1, further comprising a pull-down module electrically connected to the second node, the third node, the first clock signal terminal, and a second voltage terminal, for pulling down a potential of the third node.
3. The shift register of claim 2, wherein the pull-down module comprises a first transistor, a second transistor, and a first capacitor;
a grid electrode of the first transistor is electrically connected with the third node, a first electrode of the first transistor is electrically connected with the fourth node, and a second electrode of the first transistor is electrically connected with the first clock signal end;
a gate of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the fourth node, and a second electrode of the second transistor is electrically connected to the second voltage terminal;
the first pole of the first capacitor is electrically connected with the fourth node, and the second pole of the first capacitor is electrically connected with the third node.
4. The shift register of claim 1, further comprising a second capacitor, a first pole of the second capacitor being electrically connected to the second node, a second pole of the second capacitor being electrically connected to the first pole of the third transistor and the second pole of the fourth transistor.
5. The shift register according to claim 1, wherein the second node control module includes a fifth transistor and a sixth transistor;
a gate of the fifth transistor is electrically connected to the second clock signal terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node;
a gate of the sixth transistor is electrically connected to the third node, a first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the second node.
6. The shift register according to claim 5, further comprising a seventh transistor, wherein the fifth transistor is electrically connected to the second node through the seventh transistor, a gate of the seventh transistor is electrically connected to the first voltage terminal, a first electrode of the seventh transistor is electrically connected to the second node, and a second electrode of the seventh transistor is electrically connected to a second electrode of the fifth transistor.
7. The shift register according to claim 5, further comprising an eighth transistor, wherein the sixth transistor is electrically connected to the second node through the eighth transistor, a gate of the eighth transistor is electrically connected to the first voltage terminal, a first electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to a second electrode of the sixth transistor.
8. The shift register according to claim 1, wherein the pull-up module includes a ninth transistor, a gate of the ninth transistor is electrically connected to the third node, a first electrode of the ninth transistor is electrically connected to the first node, and a second electrode of the ninth transistor is electrically connected to the third clock signal terminal.
9. The shift register according to claim 8, further comprising a tenth transistor, wherein a gate of the ninth transistor is electrically connected to the third node through the tenth transistor, a gate of the tenth transistor is electrically connected to the first voltage terminal, a first electrode of the tenth transistor is electrically connected to a gate of the ninth transistor, and a second electrode of the tenth transistor is electrically connected to the third node.
10. The shift register of claim 1, wherein the first output module includes a thirteenth transistor, a gate of the thirteenth transistor is electrically connected to the first node, a first electrode of the thirteenth transistor is electrically connected to the third clock signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the output signal terminal;
the second output module comprises a fourteenth transistor, a gate of the fourteenth transistor is electrically connected to the third node, a first electrode of the fourteenth transistor is electrically connected to the output signal terminal, and a second electrode of the fourteenth transistor is electrically connected to the first voltage terminal.
11. The shift register of claim 10, further comprising a third capacitor, wherein a first electrode of the third capacitor is electrically connected to the third clock signal terminal, and a second electrode of the third capacitor is electrically connected to the first node.
12. The shift register of claim 10, further comprising a fifteenth transistor, wherein the first node control module and the pull-up module are electrically connected to the first node through the fifteenth transistor, a gate of the fifteenth transistor is electrically connected to the first voltage terminal, a first electrode of the fifteenth transistor is electrically connected to the first node, and a second electrode of the fifteenth transistor is electrically connected to the first node control module and the pull-up module.
13. The shift register of claim 10, further comprising a sixteenth transistor, wherein the input module and the second node control module are electrically connected to the third node through the sixteenth transistor, a gate of the sixteenth transistor is electrically connected to the first voltage level terminal, a first electrode of the sixteenth transistor is electrically connected to the input module and the second node control module, and a second electrode of the sixteenth transistor is electrically connected to the third node.
14. A display panel comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 13.
15. A display device characterized by comprising the display panel according to claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011437701.3A CN112652271B (en) | 2020-12-11 | 2020-12-11 | Shift register, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011437701.3A CN112652271B (en) | 2020-12-11 | 2020-12-11 | Shift register, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112652271A CN112652271A (en) | 2021-04-13 |
| CN112652271B true CN112652271B (en) | 2022-03-15 |
Family
ID=75350832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011437701.3A Active CN112652271B (en) | 2020-12-11 | 2020-12-11 | Shift register, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112652271B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113362761B (en) * | 2021-06-25 | 2022-09-06 | 合肥维信诺科技有限公司 | Display driving circuit and display panel |
| WO2023000322A1 (en) * | 2021-07-23 | 2023-01-26 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113516949B (en) * | 2021-07-27 | 2022-04-26 | 武汉华星光电半导体显示技术有限公司 | Pixel control circuit and display panel |
| CN113506541B (en) * | 2021-07-27 | 2022-04-26 | 武汉华星光电半导体显示技术有限公司 | Pixel control circuit |
| CN113593476A (en) * | 2021-08-02 | 2021-11-02 | 武汉华星光电半导体显示技术有限公司 | Light-emitting control circuit and mobile terminal |
| CN113658553A (en) * | 2021-08-03 | 2021-11-16 | 武汉华星光电半导体显示技术有限公司 | Light-emitting control circuit and mobile terminal |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883067A (en) * | 2020-07-30 | 2020-11-03 | 云谷（固安）科技有限公司 | Scanning circuit and display panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104575430B (en) * | 2015-02-02 | 2017-05-31 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN104778928B (en) * | 2015-03-26 | 2017-04-05 | 京东方科技集团股份有限公司 | A kind of shift register, gate driver circuit, display floater and display device |
| CN105632560B (en) * | 2016-01-04 | 2019-08-02 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN109243358B (en) * | 2018-11-22 | 2021-11-12 | 合肥京东方光电科技有限公司 | Shifting register unit, grid driving circuit and display device |
-
2020
- 2020-12-11 CN CN202011437701.3A patent/CN112652271B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883067A (en) * | 2020-07-30 | 2020-11-03 | 云谷（固安）科技有限公司 | Scanning circuit and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112652271A (en) | 2021-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112652271B (en) | Shift register, display panel and display device | |
| US20200357352A1 (en) | Shift register, method for driving the same, gate driving circuit, and display device | |
| TWI433459B (en) | Bi-directional shift register | |
| CN101937718B (en) | Bidirectional shift register | |
| KR102275425B1 (en) | Shift register and its driving method, gate driving circuit, and display device | |
| CN111754923B (en) | GOA circuit and display panel | |
| CN101609719B (en) | Shift register of display device | |
| WO2019109446A1 (en) | Goa circuit unit, goa circuit, and display panel | |
| CN108766340A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN106652901B (en) | Drive circuit and display device using the same | |
| CN112419960B (en) | Shift register, display panel and display device | |
| CN110797070B (en) | Shift register and display panel | |
| CN111145680B (en) | Drive circuit and display panel | |
| CN101510443A (en) | Shift register capable of reducing coupling effect | |
| CN112634805B (en) | Shift register, display panel and display device | |
| CN101593561B (en) | Liquid crystal display | |
| CN111754925A (en) | GOA circuit and display panel | |
| CN112802424A (en) | Shift register, display panel and display device | |
| CN113192453A (en) | Display panel and display device | |
| CN110675793A (en) | Display driving circuit | |
| CN112102768A (en) | GOA circuit and display panel | |
| CN114512084B (en) | Shifting register unit and driving method thereof, grid driving circuit and display panel | |
| CN115331644A (en) | Gate drive circuit, drive method thereof and display device | |
| CN113436580A (en) | Grid driving circuit and display panel | |
| CN112365851A (en) | GOA circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |