CN114078549A - Shift register and driving method thereof, grid driving circuit and display device - Google Patents

Abstract

The invention discloses a shift register, a driving method thereof, a grid driving circuit and a display device. In an output stage, the pull-down compensation sub-circuit provides a signal of a second power supply end to a pull-down node of the pull-down sub-circuit under the control of the first input end so as to pull down the potential of the pull-down node of the pull-down sub-circuit; the output sub-circuit provides a signal of a third clock signal end to the first output end under the control of the first pull-up node, and provides a signal of the second clock signal end to the second output end under the control of the second pull-up node. The invention reduces the occupied wiring space, meets the requirement of a narrow frame, simultaneously ensures that the potential of the pull-down node of the pull-down sub-circuit maintains a sufficiently low potential in the output stage, and reduces the phenomenon of abnormal output of the GOA circuit.

Description

Shift register and driving method thereof, grid driving circuit and display device

Technical Field

The invention belongs to the technical field of display, and particularly relates to a shift register, a driving method thereof, a grid driving circuit and a display device.

Background

In recent years, flat panel displays, such as Thin Film transistor liquid Crystal Display (TFT-LCD) panels and Active Matrix Organic Light Emitting Diode (AMOLED) panels, have been widely used in electronic products such as televisions and mobile phones because of their advantages of Light weight, Thin thickness, and low power consumption.

With the development of display technology, high resolution and narrow frame display panels are becoming more and more developed, and therefore, a Gate Driver on Array (GOA) technology has emerged. The GOA technology integrates a gate driving circuit of a display panel directly on an array substrate to replace an external driving chip, and has the advantages of low cost, few processes, high productivity and the like, wherein the GOA circuit is usually realized by a shift register, and the shift register converts a clock signal into an on/off voltage to be respectively output to each gate line of the display panel.

In the current GOA circuit design, one shift register (i.e. one stage of the shift register) is connected to one gate line. However, the inventor of the present application finds that the conventional GOA design not only occupies a large wiring space and cannot meet the requirement of a narrow frame, but also cannot guarantee the potential of a pull-up node in a GOA circuit in an output stage when a noise reduction transistor in the GOA circuit has abnormal characteristics and leaks electricity, so that the potential of the pull-down node is affected, and abnormal output of the GOA circuit is caused.

Disclosure of Invention

The invention mainly aims to provide a shift register, a driving method thereof, a gate driving circuit and a display device, and aims to solve the problems that in the prior art, a GOA not only occupies a large wiring space in design and cannot meet the requirement of a narrow frame, but also output of the GOA circuit is abnormal due to leakage caused by abnormal characteristics of a noise reduction transistor in the GOA circuit.

In view of the above problems, the present invention provides a shift register, which includes a pull-down sub-circuit, a pull-down compensation sub-circuit, a pull-up sub-circuit and an output sub-circuit;

the first end of the pull-down sub-circuit is electrically connected with a first power supply end, the second end of the pull-down sub-circuit is electrically connected with a second power supply end, the pull-down node of the pull-down sub-circuit is electrically connected with the second end of the pull-down compensation sub-circuit, and the first control end of the pull-down sub-circuit is electrically connected with the pull-up control node of the pull-up sub-circuit;

the first end of the pull-down compensation sub-circuit is electrically connected with the second power supply end, and the control end of the pull-down compensation sub-circuit is electrically connected with the first scanning end;

a first pull-up node of the pull-up sub-circuit is electrically connected with a first control end of the output sub-circuit, a second pull-up node of the pull-up sub-circuit is electrically connected with a second control end of the output sub-circuit, and the first control end of the pull-up sub-circuit and the second control end of the pull-up sub-circuit are both electrically connected with the first power end;

the first end of the output sub-circuit is electrically connected with the third clock signal end, the second end of the output sub-circuit is electrically connected with the fourth clock signal end, the third end of the output sub-circuit is electrically connected with the first output end, and the fourth end of the output sub-circuit is electrically connected with the second output end;

the pull-down compensation sub-circuit is used for providing a signal of a second power supply end to a pull-down node of the pull-down sub-circuit under the control of the first input end in an output stage so as to pull down the potential of the pull-down node of the pull-down sub-circuit;

the output sub-circuit is configured to provide a signal of a third clock signal terminal to the first output terminal under the control of the first pull-up node and provide a signal of the second clock signal terminal to the second output terminal under the control of the second pull-up node in an output stage.

The invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers;

the first input end of the first-stage shift register is connected with the initial signal end, the second output end of the Nth-stage shift register is connected with the first input end of the (N + 1) th-stage shift register, and the first output end of the (N + 1) th-stage shift register is connected with the second input end of the Nth-stage shift register.

The present invention also provides a driving method of a shift register, which is applied to the shift register described above, and is characterized by including:

in an output phase, the pull-down compensation sub-circuit provides a signal of a second power supply end to a pull-down node of the pull-down sub-circuit under the control of the first input end, and the first control end of the pull-down sub-circuit provides the signal of the second power supply end to the pull-down node of the pull-down sub-circuit under the control of a pull-up control node of the pull-up sub-circuit, so that the potential of the pull-down node of the pull-down sub-circuit is pulled down; the output sub-circuit provides a signal of a third clock signal end to the first output end under the control of the first pull-up node, and provides a signal of the second clock signal end to the second output end under the control of the second pull-up node.

The invention also provides a display device comprising the gate driving circuit.

Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:

according to the shift register, the driving method thereof, the grid driving circuit and the display device, the two signals are output by the output sub-circuit to drive the two rows of grid lines, so that the number of the shift register is reduced, the occupied wiring space is reduced, the requirement of a narrow frame is met, and the cost is reduced. Meanwhile, by additionally arranging the pull-down compensation sub-circuit, in the output stage, under the control of the first input end, a signal of a second power end is provided for the pull-down node of the pull-down sub-circuit, so that the potential of the pull-down node of the pull-down sub-circuit is fully pulled down, and thus, the potential of the pull-down node of the pull-down sub-circuit is ensured to be maintained at a sufficiently low potential in the output stage, and the phenomenon of abnormal output of the GOA circuit is reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a shift register topology according to the related art;

FIG. 2 is a timing control diagram of FIG. 1;

FIG. 3 is a schematic diagram of the path current of T7 '-T6' in FIG. 1;

FIG. 4 is a diagram illustrating the effect of Vth shift of T1 '& T6' on shift register output in a related art shift register;

FIG. 5 is a diagram illustrating the effect of Ion reduction of T1 '& T6' on the shift register output in a related art shift register;

FIG. 6 is a diagram illustrating a shift register according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of an embodiment of a shift register shown in FIG. 7;

FIG. 9 is a timing diagram of the shift register of FIG. 8;

FIG. 10 is a schematic diagram of the current of a fifth transistor in the shift register of FIG. 8;

FIG. 11 is a diagram illustrating the effect of Vth shift of T1& T6 on shift register output according to the present invention;

FIG. 12 is a diagram illustrating the effect of Ion reduction of T1& T6 on the shift register output in the shift register of the present invention;

fig. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

Fig. 1 is a schematic diagram of a topology structure of a shift register in the related art, and as shown in fig. 1, the shift register is composed of 11T2C, which is an eleventh transistor T11 'having a first transistor T1', a first capacitor C1 'and a second capacitor C2'.

Fig. 2 is a timing control diagram of fig. 1, and as shown in fig. 2, the shift register shown in fig. 1 operates in 3 stages.

Stage one t 1': the STV signal (the last OUTPUT signal) is at high level, T1 'is turned on to charge C1', and the PUCN point and the pull-up node PU are raised to high level; the CKB signal is high level, T7 ' is turned on, the pull-down node PD is low level, the pull-up control node PUCN discharges the pull-down node PD through T6 ', and the pull-down node PD discharges the pull-up control node PUCN through T5 ', so that the pull-down node PD is not fully pulled down; the clock signal terminal CK is low, T3' is turned off, and the OUTPUT terminal OUTPUT is low.

At a second stage t2 ', the pull-down node PD is at a low level, the clock signal terminal CK is at a high level, the OUTPUT terminal OUTPUT becomes at a high level, and the level of the pull-up node PU continues to rise due to the bootstrap action of the first capacitor C1';

at the third stage T3 ', the CKB signal is at high level, the fourth transistor T4 ' is turned on, meanwhile, the clock signal terminal CK is at low level, the third transistor T3 ' is turned off, the OUTPUT terminal OUTPUT becomes at low level, and the GOA finishes the OUTPUT of the stage; the pull-down node PD is high, and the potential of the pull-up node PU is pulled down.

After the third stage, the pull-down node PD of the shift register keeps at the high level, and the potential of the pull-up node PU is pulled down, so that the OUTPUT terminal OUTPUT keeps at the low level until the stage is turned on in the next frame.

In the first stage, since the sixth transistor T6 'is turned on when the potential of the pull-up node PU rises to a high level, the CKB signal is at a high level, the seventh transistor T7' is turned on, and a path from the high level of CKB to the low level of VGL is formed between the seventh transistor T7 'and the sixth transistor T6', so that a large current is generated.

FIG. 3 is a schematic diagram of the path current of T7 '-T6' in FIG. 1. As shown in fig. 3, the simulation result shows that the path current of T7 '-T6' is higher than 100uA, the path on time is the same as the on time of the CKB signal, and the large current at this time accounts for the main power consumption of the shift register compared with the operating state of other processes.

When the shift register operates in a harsh environment for a long time, the TFT characteristics of T1 ' & T6 ' may shift, Vth increases and Ion decreases greatly, the PU dot level is not high enough at stage two, the pull-down node PD cannot be pulled down completely, and the OUTPUT of the OUTPUT terminal OUTPUT is abnormal due to the turn-on of T4 ', as shown in fig. 4 and 5.

FIG. 4 is a diagram illustrating the influence of Vth shift of T1 '& T6' on the shift register output, and FIG. 5 is a diagram illustrating the influence of Ion reduction of T1 '& T6' on the shift register output. As shown in fig. 4, Vth of T1 '& T6' is normal at 2.6V and abnormal at 2.7V. As shown in fig. 5, the output is normal when Ion of T1 '& T6' is 1E-4, and is not normal when Ion is 1E-5.

In addition, the bit register is connected with a grid line, so that the occupied wiring space is large, and the requirement of a narrow frame cannot be met.

Therefore, in order to solve the above technical problems, the present invention provides the following technical solutions:

fig. 6 is a schematic structural diagram of an embodiment of a shift register of the present invention, and as shown in fig. 6, the shift register of this embodiment may include a pull-down sub-circuit 10, a pull-down compensation sub-circuit 11, a pull-up sub-circuit 12, and an output sub-circuit 13.

The first end of the pull-down sub-circuit 10 is electrically connected to a first power source end VGH, the second end of the pull-down sub-circuit 10 is electrically connected to a second power source end VGL, the pull-down node PD of the pull-down sub-circuit 10 is electrically connected to the second end of the pull-down compensation sub-circuit 11, and the first control end of the pull-down sub-circuit 10 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12. The first terminal of the pull-down compensation sub-circuit 11 is electrically connected to the second power source terminal VGL, and the control terminal of the pull-down compensation sub-circuit 11 is electrically connected to the first scan terminal G1. The first pull-up node of the pull-up sub-circuit 12 is electrically connected to the first control end of the output sub-circuit 13, the second pull-up node of the pull-up sub-circuit 12 is electrically connected to the second control end of the output sub-circuit 13, and both the first control end of the pull-up sub-circuit 12 and the second control end of the pull-up sub-circuit 12 are electrically connected to the first power end VGH. The first terminal of the OUTPUT sub-circuit 13 is electrically connected to the third clock signal terminal CK3, the second terminal of the OUTPUT sub-circuit 13 is electrically connected to the fourth clock signal terminal CK4, the third terminal of the OUTPUT sub-circuit 13 is electrically connected to the first OUTPUT terminal OUTPUT1, and the fourth terminal of the OUTPUT sub-circuit 13 is electrically connected to the second OUTPUT terminal OUTPUT 2.

In a specific implementation process, the pull-up node is configured to pull up a potential of the first control terminal of the output sub-circuit 13 and a potential of the second control terminal of the output sub-circuit 13 under the control of the first power source terminal VGH in the input stage. The pull-down sub-circuit 10 is configured to pull down a potential of a pull-down node PD of the pull-down sub-circuit 10 under the control of a first pull-up node of the pull-up sub-circuit 12 and a second pull-up node of the pull-up sub-circuit 12 in an input stage. The pull-down compensation sub-circuit 11 is configured to provide a signal of the second power source terminal VGL to the pull-down node PD of the pull-down sub-circuit 10 under the control of the first INPUT terminal INPUT1 during the output stage, so as to pull down the potential of the pull-down node PD of the pull-down sub-circuit 10 sufficiently. The OUTPUT sub-circuit 13 is configured to provide the signal of the third clock signal terminal CK3 to the first OUTPUT terminal OUTPUT1 under the control of the first pull-up node, and provide the signal of the second clock signal terminal CK2 to the second OUTPUT terminal OUTPUT2 under the control of the second pull-up node during the OUTPUT stage.

In one specific implementation, since the pull-down compensation sub-circuit 11 provides the signal of the second power source terminal VGL to the pull-down node PD of the pull-down sub-circuit 10 under the control of the first INPUT terminal INPUT1 during the OUTPUT stage, so as to pull down the potential of the pull-down node PD of the pull-down sub-circuit 10 sufficiently, and ensure that the first OUTPUT terminal OUTPUT1 and the second OUTPUT terminal OUTPUT2 OUTPUT normally.

The shift register of this embodiment, through two signal drive two rows of grid lines of output sub-circuit 13 output, reduced shift register's quantity, not only reduced the wiring space that occupies, satisfied the requirement of narrow frame, still reduced the cost. Meanwhile, by additionally providing the pull-down compensation sub-circuit 11, in the INPUT stage, under the control of the first INPUT terminal INPUT1, a signal of the second power terminal VGL is provided to the pull-down node PD of the pull-down sub-circuit 10, so that the potential of the pull-down node PD of the pull-down sub-circuit 10 is sufficiently pulled down, and thus, in the output stage, the potential of the pull-down node PD of the pull-down sub-circuit 10 is ensured to be maintained at a sufficiently low potential, and the phenomenon of abnormal output of the GOA circuit is reduced.

Fig. 7 is a schematic structural diagram of another embodiment of the shift register of the present invention, and as shown in fig. 7, the shift register of this embodiment further includes a first input sub-circuit 14 and a first node control sub-circuit 15.

The first terminal of the first INPUT sub-circuit 14 is electrically connected to the second scan terminal CN, the second terminal of the first INPUT sub-circuit 14 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12, and the control terminal of the first INPUT sub-circuit 14 is electrically connected to the first INPUT terminal INPUT 1; the first end of the first node control sub-circuit 15 is electrically connected to the first clock signal end CK1, the second end of the first node control sub-circuit 15 is electrically connected to the second control end of the pull-down sub-circuit 10, and the control end of the first node control sub-circuit 15 is electrically connected to the second scan end CN. The second scan terminal CN maintains a high level signal during forward scanning. The INPUT signal of the first INPUT terminal INPUT1 of the first polar shift register is the signal of the initial signal terminal STV, and the signal of the second OUTPUT terminal OUTPUT2 of the nth stage shift register is the signal of the first INPUT terminal INPUT1 of the N +1 th stage shift register.

In one embodiment, the first INPUT sub-circuit 14 is configured to provide a signal of the first INPUT terminal INPUT1 to the pull-up control node PUCN of the pull-up sub-circuit 12 under the control of the second scan terminal CN. The first node control sub-circuit 15 is used for providing the clock signal of the first clock signal terminal CK1 to the second control terminal of the pull-down sub-circuit 10 under the control of the second scan terminal CN.

As shown in fig. 7, the shift register may further include a second input sub-circuit 16, a second node control sub-circuit 17. A first end of the second INPUT sub-circuit 16 is electrically connected to the third scan end CNB, a second end of the second INPUT sub-circuit 16 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12, and a control end of the second INPUT sub-circuit 16 is electrically connected to the second INPUT end INPUT 2. A first end of the second node control sub-circuit 17 is electrically connected to the second clock signal end CK2, a second end of the second node control sub-circuit 17 is electrically connected to the second control end of the pull-down sub-circuit 10, and a control end of the second node control sub-circuit 17 is electrically connected to the third scanning end CNB. The signal at the second OUTPUT terminal OUTPUT2 of the N +1 th stage shift register is the signal at the second INPUT terminal INPUT2 of the nth stage shift register.

The third scanning end CNB continuously provides a high level in the reverse scanning mode, and the phase of the signal input by the third scanning end CNB is opposite to that of the signal input by the second scanning end CN, that is, the second scanning end CN inputs a high level, the third scanning end CNB inputs a low level, or the second scanning end CN inputs a low level, and the third scanning end CNB inputs a high level. The second scanning end CN inputs a high level, the third scanning end CNB inputs a low level, and at the moment, the shift register is in a forward scanning working mode; the second scanning end CN inputs a low level, the third scanning end CNB inputs a high level, and at this time, the shift register is in a reverse scanning mode.

In one embodiment, the second INPUT sub-circuit 16 is configured to provide the signal of the first INPUT terminal INPUT1 to the pull-up control node PUCN of the pull-up sub-circuit 12 under the control of the third scan terminal CNB. The second node control sub-circuit 17 is used for providing the clock signal of the first clock signal terminal CK1 to the second control terminal of the pull-down sub-circuit 10 under the control of the third scan terminal CNB.

As shown in fig. 7, the shift register further includes a reset sub-circuit 18. A first end of the reset sub-circuit 18 and a second end of the reset sub-circuit 18 are both electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12; the third terminal of the reset sub-circuit 18 is electrically connected to the second power supply terminal VGL; the fourth end of the reset sub-circuit 18 is electrically connected to the first OUTPUT terminal OUTPUT 1; the fifth terminal of the reset sub-circuit 18 is electrically connected to the second OUTPUT terminal OUTPUT 2; a first control terminal of the reset sub-circuit 18 is electrically connected to the reset terminal REST; the second control terminal of the reset sub-circuit 18 is electrically connected to the pull-down node PD.

The reset sub-circuit 18 is configured to provide the signal of the second power source terminal VGL to the pull-up control node PUCN of the pull-up sub-circuit 12 under the control of the reset terminal REST, and provide the signal of the second power source terminal VGL to the pull-up control node PUCN of the pull-up sub-circuit 12, the first OUTPUT terminal OUTPUT1, and the second OUTPUT terminal OUTPUT2 under the control of the pull-down node PD.

Fig. 8 is a schematic diagram of a specific circuit structure of the shift register shown in fig. 7, and as shown in fig. 8, in the shift register of this embodiment, the first input sub-circuit 14 includes a first transistor T1, and the first node control sub-circuit 15 includes a fifth transistor T5.

A first pole of the first transistor T1 serves as a first terminal of the first input sub-circuit 14, a second pole of the first transistor T1 serves as a second terminal of the first input sub-circuit 14, and a control pole of the first transistor T1 serves as a control terminal of the first input sub-circuit 14.

A first pole of the fifth transistor T5 serves as a first terminal of the first node control sub-circuit 15, a second pole of the fifth transistor T5 serves as a second terminal of the first node control sub-circuit 15, and a control pole of the fifth transistor T5 serves as a control terminal of the first node control sub-circuit 15.

A first pole of the first transistor T1 is electrically connected to the second scan terminal CN, a second pole of the first transistor T1 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12, and a control pole of the first transistor T1 is electrically connected to the first INPUT terminal INPUT 1.

A first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK1, a second electrode of the fifth transistor T5 is electrically connected to the second control terminal of the pull-down sub-circuit 10, and a control electrode of the fifth transistor T5 is electrically connected to the second scan terminal CN.

The pull-down sub-circuit 10 includes an eighth transistor T8, a tenth transistor T10, and a second capacitor; the pull-down compensation sub-circuit 11 includes a fifteenth transistor T15; the pull-up sub-circuit 12 includes a ninth transistor T9, a fourteenth transistor T14, and a first capacitor C1; the output sub-circuit 13 includes a third transistor T3 and a twelfth transistor T12;

a first pole of the eighth transistor T8 is used as a first terminal of the pull-down sub-circuit 10; the second pole of the ninth transistor T9 and the first end of the second capacitor C2 are commonly used as the second end of the pull-down sub-circuit 10; the second pole of the eighth transistor T8, the first pole of the ninth transistor T9 and the second end of the second capacitor are commonly used as a pull-down node PD of the pull-down sub-circuit 10; the control electrode of the eighth transistor T8 serves as the first control terminal of the pull-down sub-circuit 10.

A first pole of the fifteenth transistor T15 is used as a first terminal of the pull-down compensation sub-circuit 11; the second pole of the fifteenth transistor T15 serves as the second terminal of the pull-down compensation sub-circuit 11, and the control pole of the fifteenth transistor T15 serves as the control terminal of the pull-down compensation sub-circuit 11.

A first pole of the ninth transistor T9 and a first pole of the fourteenth transistor T14 collectively serve as a pull-up control node PUCN of the pull-up sub-circuit 12; a second pole of the ninth transistor T9 is used as a first pull-up node of the pull-up sub-circuit 12, and a control pole of the ninth transistor T9 is used as a first control terminal of the pull-up sub-circuit 12; a second pole of the fourteenth transistor T14 is used as a second pull-up node of the pull-up sub-circuit 12; the gate of the fourteenth transistor T14 is used as the second control terminal of the pull-up sub-circuit 12.

A first pole of the third transistor T3 serves as a first terminal of the output sub-circuit 13; a second pole of the third transistor T3 is the third terminal of the output sub circuit 13; a control electrode of the third transistor T3 is used as a first control terminal of the output sub-circuit 13; a first pole of the twelfth transistor T12 serves as a second terminal of the output sub-circuit 13; a second pole of the twelfth transistor T12 serves as a fourth terminal of the output sub-circuit 13; the control electrode of the twelfth transistor T12 serves as the second control terminal of the output sub-circuit 13.

A first electrode of the eighth transistor T8 is electrically connected to the first power source terminal VGH; a second pole of the ninth transistor T9 and a first end of the second capacitor are electrically connected to the second power source terminal VGL in common; a second pole of the eighth transistor T8, a first pole of the ninth transistor T9, and a second end of the second capacitor are electrically connected in common to a second pole of the fifteenth transistor T15; a control electrode of the eighth transistor T8 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12.

A first electrode of the fifteenth transistor T15 is electrically connected to the second power source terminal VGL, and a control electrode of the fifteenth transistor T15 is electrically connected to the first scan terminal G1.

A second pole of the ninth transistor T9 is electrically connected to the control electrode of the third transistor T3, a second pole of the fourteenth transistor T14 is electrically connected to the control electrode of the twelfth transistor T12, and the control electrodes of the ninth transistor T9 and the fourteenth transistor T14 are electrically connected to the first power source terminal VGH.

A first pole of the third transistor T3 is electrically connected to the third clock signal terminal CK3, a first pole of the twelfth transistor T12 is electrically connected to the fourth clock signal terminal CK4, a second pole of the third transistor T3 is electrically connected to the first OUTPUT terminal OUTPUT1, and a second pole of the twelfth transistor T12 is electrically connected to the second OUTPUT terminal OUTPUT 2.

It should be noted that, the first INPUT terminal INPUT1 and the first scan terminal G1 are the same terminal or different terminals, in this embodiment, the first INPUT terminal INPUT1 and the first scan terminal G1 are the same terminal, and the fifteenth transistor T15 and the first transistor T1 at the same terminal of the first INPUT terminal INPUT1 and the first scan terminal G1 are different types of transistors, and the level signals required for the first INPUT terminal INPUT and the first scan terminal G1 to be turned on are opposite, for example, when the first transistor T1 is turned on by a high level signal, the fifteenth transistor T15 is turned off by a high level signal, and conversely, when the first transistor T1 is turned off by a high level signal, the fifteenth transistor T15 is turned on by a high level signal.

As shown in fig. 8, the second input sub-circuit 16 includes a second transistor T2, and the second node control sub-circuit 17 includes a sixth transistor T6.

A first pole of the second transistor T2 serves as a first terminal of the second input sub-circuit 16, a second pole of the second transistor T2 serves as a second terminal of the second input sub-circuit 16, and a control pole of the second transistor T2 serves as a control terminal of the second input sub-circuit 16.

A first pole of the sixth transistor T6 serves as the first terminal of the second node control sub-circuit 17, a second pole of the sixth transistor T6 serves as the second terminal of the second node control sub-circuit 17, and a control pole of the sixth transistor T6 serves as the control terminal of the second node control sub-circuit 17.

A first pole of the second transistor T2 is electrically connected to the third scan terminal CNB, a second pole of the second transistor T2 is electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12, and a control pole of the second transistor T2 is electrically connected to the second INPUT terminal INPUT 2.

A first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, a second electrode of the sixth transistor T6 is electrically connected to the second control terminal of the pull-down sub-circuit 10, and a control electrode of the sixth transistor T6 is electrically connected to the first scan terminal G1.

As shown in fig. 8, the reset sub-circuit 18 includes a fourth transistor T4, a seventh transistor T7, an eleventh transistor T11, and a thirteenth transistor T13.

A first pole of the eleventh transistor T11 serves as a first terminal of the reset sub-circuit 18; a first pole of the seventh transistor T7 serves as a second terminal of the reset sub-circuit 18.

The second pole of the fourth transistor T4, the second pole of the seventh transistor T7, the second pole of the eleventh transistor T11, and the second pole of the thirteenth transistor T13 are commonly used as the third terminal of the reset sub-circuit 18.

A first pole of the fourth transistor T4 is used as the fourth terminal of the reset sub-circuit 18, and a first pole of the thirteenth transistor T13 is used as the fifth terminal of the reset sub-circuit 18.

The control electrode of the seventh transistor T7 serves as the first control terminal of the reset sub-circuit 18.

A control electrode of the fourth transistor T4, a control electrode of the seventh transistor T7 and a control electrode of the thirteenth transistor T13 are commonly used as the second control terminal of the reset sub-circuit 18.

A first pole of the eleventh transistor T11 and a first pole of the seventh transistor T7 are electrically connected to the pull-up control node PUCN of the pull-up sub-circuit 12.

The second pole of the fourth transistor T4, the second pole of the seventh transistor T7, the second pole of the eleventh transistor T11, and the second pole of the thirteenth transistor T13 are electrically connected to the second power source terminal VGL in common.

A first pole of the fourth transistor T4 is electrically connected to the first OUTPUT terminal OUTPUT 1; a first pole of the thirteenth transistor T13 is electrically connected to the second OUTPUT terminal OUTPUT 2.

A control electrode of the seventh transistor T7 is electrically connected to the reset terminal REST.

A control electrode of the fourth transistor T4, a control electrode of the seventh transistor T7, and a control electrode of the thirteenth transistor T13 are electrically connected to the pull-down node PD in common.

Fig. 9 is a timing control diagram of the shift register shown in fig. 8, and as shown in fig. 9, this embodiment describes the technical solution of the present invention by taking a forward direction scan mode as an example. The shift register operates in 5 stages.

Input stage t 1: the signal of the first INPUT signal terminal INPUT1 (the signal of the first OUTPUT terminal OUTPUT1 of the previous stage) is at a high level, the first transistor T1 is turned on, and the pull-up control node PUCN is at a high level; the ninth transistor T9 and the fourteenth transistor T14 are turned on, and the first pull-up node PU1& the second pull-up node PU2 are raised to a high level, respectively charging the first capacitor C1 and the second capacitor C2; the eighth transistor T8 is turned on, and the pull-down node PD is pulled down to a low level by the pull-up control node PUCN; the third transistor T3 is turned on, the fourth transistor T4 is turned off, and the first OUTPUT terminal OUTPUT1 OUTPUTs a low level; the twelfth transistor T12T12 is turned on, the thirteenth transistor T13T13 is turned off, and the second OUTPUT terminal OUTPUT2 OUTPUTs a low level;

first output phase t 2: the clock signal of the third clock signal terminal CK3 is at a high level, and the first pull-up node PU1 is bootstrapped and boosted; the second pull-up node PU2 maintains the level of the stage input stage; the fifteenth transistor T15 is turned on to further pull down the potential of the pull-down node PD, so that the pull-down node PD maintains a low level; the first OUTPUT terminal OUTPUT1 OUTPUTs a high level; the clock signal CK4 of the fourth clock signal terminal CK4 is low, and the second OUTPUT terminal OUTPUT2 maintains low;

second output phase t 3: the clock signal CK3 of the third clock signal terminal CK3 is low, and the first pull-up node PU1 recovers the input stage level; the clock signal CK4 at the fourth clock signal terminal CK4 is high, and the second pull-up node PU2 is bootstrapped and boosted; the fifteenth transistor T15 is turned on to further pull down the potential of the pull-down node PD, so that the pull-down node PD maintains a low level; the first OUTPUT terminal OUTPUT1 returns to the low level; the second OUTPUT terminal OUTPUT2 OUTPUTs a high level;

first discharge phase t 4: the clock signal CK1 of the first clock signal end CK1 is at a high level, and the pull-down node PD is raised to a high level; the first pull-up node PU1, the second pull-up node PU2 is pulled low by the pull-down node PD; the first OUTPUT terminal OUTPUT1 and the second OUTPUT terminal OUTPUT2 are low.

Second discharge period t 5: the clock signal CK1 of the first clock signal terminal CK1 is at a low level, and the pull-down node PD is maintained at a high level; the first pull-up node PU1, the second pull-up node PU2, the first OUTPUT terminal OUTPUT1, and the second OUTPUT terminal OUTPUT2 are maintained at a low level.

After the second discharging period t5, the shift register of this stage receives a high signal again until the first INPUT terminal INPUT1 or the second INPUT terminal INPUT 2.

In this embodiment, the signal at the first INPUT terminal INPUT1 is a pulse signal, and is high only in the INPUT stage; the OUTPUT signal of the first OUTPUT terminal OUTPUT1 is a pulse signal and is high level only in the first OUTPUT stage; the OUTPUT signal of the second OUTPUT terminal OUTPUT2 is a pulse signal and is high only in the second OUTPUT stage.

In a specific implementation process, an initialization stage may further be included, in which the signal of the reset terminal REST is at a high level, the eleventh transistor T11 is turned on, the pull-up control node PUCN is pulled down, and since the first power source terminal VGH continuously provides the high level, the potentials of the first pull-up node PU1 and the second pull-up node PU2 are pulled down to the low level, so that noise is reduced. The reset terminal RESTR signal is a pulse signal and is high only in the initialization period.

In a specific implementation process, since the second pole of the fifth transistor is connected to the control of the tenth transistor, a path from the high level of the first clock signal terminal CK1 to the low level of the second power supply terminal VGL is no longer formed among the fifth transistor, the tenth transistor and the eighth transistor, and the current of the fifth transistor is relatively small.

Fig. 10 is a diagram illustrating a current of a fifth transistor in the shift register shown in fig. 8. The current of the fifth transistor is between-3 muA and +3 muA as shown in FIG. 10, and the current is very small.

FIG. 11 is a diagram illustrating the effect of Vth shift of T1& T6 on the output of the shift register, and FIG. 12 is a diagram illustrating the effect of Ion reduction of T1& T6 on the output of the shift register. As shown in FIG. 11, Vth at T1 '& T6' is output normally at 4V. As shown in fig. 12, when Ion of T1 '& T6' is 1E-5, the output is normal.

Fig. 13 is a schematic structural diagram of an embodiment of a gate driving circuit of the present invention, and as shown in fig. 13, the gate driving circuit of the present embodiment includes a plurality of cascaded shift registers of the above embodiments.

The first INPUT terminal INPUT1 of the first stage shift register is connected to the initial signal terminal, the second OUTPUT terminal OUTPUT2 of the nth stage shift register is connected to the first INPUT terminal INPUT1 of the (N + 1) th stage shift register, and the first OUTPUT terminal OUTPUT _2 of the (N + 1) th stage shift register is connected to the second INPUT terminal INPUT2 of the nth stage shift register.

The present invention further provides a driving method of a shift register, which is applied to the shift register of the above embodiment, and the driving method of the shift register may include:

in the output stage, the pull-down compensation sub-circuit 11 provides the signal of the second power source terminal VGL to the pull-down node PD of the pull-down sub-circuit 10 under the control of the first INPUT terminal INPUT1, and the first control terminal of the pull-down sub-circuit 10 provides the signal of the second power source terminal VGL to the pull-down node PD of the pull-down sub-circuit 10 under the control of the pull-up control node PUCN of the pull-up sub-circuit 12, so that the potential of the pull-down node PD of the pull-down sub-circuit 10 is pulled down; the OUTPUT sub-circuit 13 provides the signal of the third clock signal terminal CK3 to the first OUTPUT terminal OUTPUT1 under the control of the first pull-up node, and provides the signal of the second clock signal terminal CK2 to the second OUTPUT terminal OUTPUT2 under the control of the second pull-up node.

The method of the foregoing embodiment is used to implement the corresponding shift register in the foregoing embodiment, and specific implementation schemes thereof may refer to the shift register described in the foregoing embodiment and relevant descriptions in the shift register embodiment, and have beneficial effects of the corresponding method embodiment, which are not described herein again.

The invention also provides a display device which comprises the gate driving circuit of the embodiment.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (12)

1. A shift register is characterized by comprising a pull-down sub circuit, a pull-down compensation sub circuit, a pull-up sub circuit and an output sub circuit;

the first end of the pull-down sub-circuit is electrically connected with a first power supply end, the second end of the pull-down sub-circuit is electrically connected with a second power supply end, the pull-down node of the pull-down sub-circuit is electrically connected with the second end of the pull-down compensation sub-circuit, and the first control end of the pull-down sub-circuit is electrically connected with the pull-up control node of the pull-up sub-circuit;

the first end of the pull-down compensation sub-circuit is electrically connected with the second power supply end, and the control end of the pull-down compensation sub-circuit is electrically connected with the first scanning end;

a first pull-up node of the pull-up sub-circuit is electrically connected with a first control end of the output sub-circuit, a second pull-up node of the pull-up sub-circuit is electrically connected with a second control end of the output sub-circuit, and the first control end of the pull-up sub-circuit and the second control end of the pull-up sub-circuit are both electrically connected with the first power end;

the first end of the output sub-circuit is electrically connected with the third clock signal end, the second end of the output sub-circuit is electrically connected with the fourth clock signal end, the third end of the output sub-circuit is electrically connected with the first output end, and the fourth end of the output sub-circuit is electrically connected with the second output end;

the pull-down compensation sub-circuit is used for providing a signal of a second power supply end to a pull-down node of the pull-down sub-circuit under the control of the first input end in an output stage so as to pull down the potential of the pull-down node of the pull-down sub-circuit;

the output sub-circuit is configured to provide a signal of a third clock signal terminal to the first output terminal under the control of the first pull-up node and provide a signal of the second clock signal terminal to the second output terminal under the control of the second pull-up node in an output stage.

2. The shift register of claim 1, further comprising a first input sub-circuit, a first node control sub-circuit;

the first end of the first input sub-circuit is electrically connected with the second scanning end, the second end of the first input sub-circuit is electrically connected with the pull-up control node of the pull-up sub-circuit, and the control end of the first input sub-circuit is electrically connected with the first input end;

the first end of the first node control sub-circuit is electrically connected with the first clock signal end, the second end of the first node control sub-circuit is electrically connected with the second control end of the pull-down sub-circuit, and the control end of the first node control sub-circuit is electrically connected with the second scanning end.

3. The shift register of claim 2, wherein the first input sub-circuit comprises a first transistor, and the first node control sub-circuit comprises a fifth transistor;

a first pole of the first transistor is used as a first end of the first input sub-circuit, a second pole of the first transistor is used as a second end of the first input sub-circuit, and a control pole of the first transistor is used as a control end of the first input sub-circuit;

a first pole of the fifth transistor is used as a first end of the first node control sub-circuit, a second pole of the fifth transistor is used as a second end of the first node control sub-circuit, and a control pole of the fifth transistor is used as a control end of the first node control sub-circuit;

a first electrode of the first transistor is electrically connected with the second scanning end, a second electrode of the first transistor is electrically connected with a pull-up control node of the pull-up sub-circuit, and a control electrode of the first transistor is electrically connected with the first input end;

a first electrode of the fifth transistor is electrically connected to the first clock signal terminal, a second electrode of the fifth transistor is electrically connected to the second control terminal of the pull-down sub-circuit, and a control electrode of the fifth transistor is electrically connected to the second scan terminal.

4. A shift register according to claim 2 or 3, wherein the first input terminal is the same terminal as the first scan terminal.

5. The shift register of claim 1, further comprising a second input sub-circuit, a second node control sub-circuit;

the first end of the second input sub-circuit is electrically connected with the third scanning end, the second end of the second input sub-circuit is electrically connected with the pull-up control node of the pull-up sub-circuit, and the control end of the second input sub-circuit is electrically connected with the second input end;

the first end of the second node control sub-circuit is electrically connected with the second clock signal end, the second end of the second node control sub-circuit is electrically connected with the second control end of the pull-down sub-circuit, and the control end of the second node control sub-circuit is electrically connected with the third scanning end.

6. The shift register of claim 5, wherein the second input sub-circuit comprises a second transistor, and the second node control sub-circuit comprises a sixth transistor;

a first pole of the second transistor is used as a first end of the second input sub-circuit, a second pole of the second transistor is used as a second end of the second input sub-circuit, and a control pole of the second transistor is used as a control end of the second input sub-circuit;

a first pole of the sixth transistor serves as a first end of the second node control sub-circuit, a second pole of the sixth transistor serves as a second end of the second node control sub-circuit, and a control pole of the sixth transistor serves as a control end of the second node control sub-circuit;

a first electrode of the second transistor is electrically connected with the third scanning end, a second electrode of the second transistor is electrically connected with a pull-up control node of the pull-up sub-circuit, and a control electrode of the second transistor is electrically connected with the first input end;

the first electrode of the sixth transistor is electrically connected with the second clock signal end, the second electrode of the sixth transistor is electrically connected with the second control end of the pull-down sub-circuit, and the control electrode of the sixth transistor is electrically connected with the first scanning end.

7. The shift register of claim 1, further comprising a reset subcircuit;

the first end of the reset sub-circuit and the second end of the reset sub-circuit are both electrically connected with a pull-up control node of the pull-up sub-circuit; the third end of the reset sub-circuit is electrically connected with the second power supply end; the fourth end of the reset sub-circuit is electrically connected with the first output end; a fifth end of the reset sub-circuit is electrically connected with the second output end; the first control end of the reset sub-circuit is electrically connected with the reset end; the second control end of the reset sub-circuit is electrically connected with the pull-down node;

the reset sub-circuit is configured to provide the signal of the second power source terminal to a pull-up control node of the pull-up sub-circuit under the control of the reset terminal, and provide the signal of the second power source terminal to the pull-up control node, the first output terminal, and the second output terminal of the pull-up sub-circuit under the control of the pull-down node.

8. The shift register according to claim 7, wherein the reset sub-circuit includes a fourth transistor, a seventh transistor, an eleventh transistor, and a thirteenth transistor;

a first pole of the eleventh transistor serves as a first end of the reset sub-circuit; a first pole of the seventh transistor serves as a second end of the reset sub-circuit;

a second pole of the fourth transistor, a second pole of the seventh transistor, a second pole of the eleventh transistor, and a second pole of the thirteenth transistor collectively serve as a third terminal of the reset sub-circuit;

a first pole of the fourth transistor is used as a fourth end of the reset sub-circuit, and a first pole of the thirteenth transistor is used as a fifth end of the reset sub-circuit;

a control electrode of the seventh transistor is used as a first control end of the reset sub-circuit;

a control electrode of the fourth transistor, a control electrode of the seventh transistor and a control electrode of the thirteenth transistor are used as a second control end of the reset sub-circuit together;

a first pole of the eleventh transistor and a first pole of the seventh transistor are both electrically connected to a pull-up control node of the pull-up sub-circuit;

a second pole of the fourth transistor, a second pole of the seventh transistor, a second pole of the eleventh transistor, and a second pole of the thirteenth transistor are electrically connected to the second power supply terminal in common;

a first pole of the fourth transistor is electrically connected with the first output end; a first pole of the thirteenth transistor is electrically connected with the second output end;

a control electrode of the seventh transistor is electrically connected with the reset terminal;

a control electrode of the fourth transistor, a control electrode of the seventh transistor, and a control electrode of the thirteenth transistor are commonly electrically connected to the pull-down node.

9. The shift register according to claim 1, wherein the pull-down sub-circuit comprises an eighth transistor, a tenth transistor, and a second capacitor; the pull-down compensation sub-circuit comprises a fifteenth transistor; the pull-up sub-circuit comprises a ninth transistor, a fourteenth transistor and a first capacitor; the output sub-circuit comprises a third transistor and a twelfth transistor;

a first pole of the eighth transistor is used as a first end of the pull-down sub-circuit; a second pole of the ninth transistor and a first end of the second capacitor are used as a second end of the pull-down sub-circuit together; a second pole of the eighth transistor, a first pole of the ninth transistor and a second end of the second capacitor are used as pull-down nodes of the pull-down sub-circuit together; a control electrode of the eighth transistor is used as a first control end of the pull-down sub-circuit;

a first pole of the fifteenth transistor serves as a first end of the pull-down compensation sub-circuit; a second pole of the fifteenth transistor serves as a second end of the pull-down compensation sub-circuit, and a control pole of the fifteenth transistor serves as a control end of the pull-down compensation sub-circuit;

a first pole of the ninth transistor and a first pole of the fourteenth transistor are used as a pull-up control node of the pull-up sub-circuit together; a second pole of the ninth transistor is used as a first pull-up node of the pull-up sub-circuit, and a control pole of the ninth transistor is used as a first control end of the pull-up sub-circuit; a second pole of the fourteenth transistor serves as a second pull-up node of the pull-up sub-circuit; a control electrode of the fourteenth transistor is used as a second control end of the pull-up sub-circuit;

a first pole of the third transistor is used as a first end of the output sub-circuit; a second pole of the third transistor is used as a third end of the output sub-circuit; a control electrode of the third transistor is used as a first control end of the output sub-circuit; a first pole of the twelfth transistor serves as a second end of the output sub-circuit; a second pole of the twelfth transistor serves as a fourth end of the output sub-circuit; a control electrode of the twelfth transistor is used as a second control end of the output sub-circuit;

a first electrode of the eighth transistor is electrically connected with the first power supply end; a second pole of the ninth transistor and a first end of the second capacitor are electrically connected with the second power supply end together; a second pole of the eighth transistor, a first pole of the ninth transistor, and a second end of the second capacitor are electrically connected to a second pole of the fifteenth transistor in common; a control electrode of the eighth transistor is electrically connected with a pull-up control node of the pull-up sub-circuit;

a first electrode of the fifteenth transistor is electrically connected with the second power supply end, and a control electrode of the fifteenth transistor is electrically connected with the first scanning end;

a second pole of the ninth transistor is electrically connected to the control electrode of the third transistor, a second pole of the fourteenth transistor is electrically connected to the control electrode of the twelfth transistor, and the control electrode of the ninth transistor and the control electrode of the fourteenth transistor are both electrically connected to the first power supply terminal;

a first electrode of the third transistor is electrically connected to the third clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the fourth clock signal terminal, a second electrode of the third transistor is electrically connected to the first output terminal, and a second electrode of the twelfth transistor is electrically connected to the second output terminal.

10. A gate drive circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 9;

the first input end of the first-stage shift register is connected with the initial signal end, the second output end of the Nth-stage shift register is connected with the first input end of the (N + 1) th-stage shift register, and the first output end of the (N + 1) th-stage shift register is connected with the second input end of the Nth-stage shift register.

11. A driving method of a shift register, applied to the shift register according to any one of claims 1 to 9, comprising:

in an output phase, the pull-down compensation sub-circuit provides a signal of a second power supply end to a pull-down node of the pull-down sub-circuit under the control of the first input end, and the first control end of the pull-down sub-circuit provides the signal of the second power supply end to the pull-down node of the pull-down sub-circuit under the control of a pull-up control node of the pull-up sub-circuit, so that the potential of the pull-down node of the pull-down sub-circuit is pulled down; the output sub-circuit provides a signal of a third clock signal end to the first output end under the control of the first pull-up node, and provides a signal of the second clock signal end to the second output end under the control of the second pull-up node.

12. A display device comprising the gate driver circuit according to claim 10.

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