CN103559913A - Shifting register - Google Patents
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- CN103559913A CN103559913A CN201310566513.4A CN201310566513A CN103559913A CN 103559913 A CN103559913 A CN 103559913A CN 201310566513 A CN201310566513 A CN 201310566513A CN 103559913 A CN103559913 A CN 103559913A
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Abstract
The invention provides a shifting register which comprises a control signal generation circuit, wherein the control signal generation circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein the first end of the second transistor is electrically coupled to the second end of the first transistor to form a first node, the first node is also electrically connected to a current shifting signal output end, the first end of the fourth transistor is electrically coupled to the second end of the third transistor to form a second node, and the second node is also electrically connected to a control signal. A feedback capacitor is also arranged between the current shifting signal output end and a next-stage shifting signal output end. A potential of the first node is reduced to be below a difference value between a second preset voltage and a threshold voltage by a pulse falling edge of a next-stage shifting signal through the feedback capacitor. Compared with the prior art, the shifting register has the advantages that a low potential of an emitting signal can be kept stable, and the risk of controlling a pixel switch is reduced.
Description
Technical Field
The present invention relates to a shift register, and more particularly, to a shift register for a pixel compensation circuit of an active matrix organic light emitting diode display.
Background
The Organic Light Emitting Diode (OLED) can be classified into a Passive Matrix OLED (PMOLED) and an Active Matrix OLED (AMOLED) according to a driving method. For AMOLED, each pixel has a capacitor for storing data, and each pixel is maintained in a light-emitting state. The power consumption of the AMOLED is significantly less than that of the PMOLED, and the driving method thereof is suitable for developing a large-sized and high-resolution display, so that the AMOLED is a main development direction in the future.
A shift register is a widely used electronic component, and its trace is found in many electronic products. In short, a plurality of shift registers are commonly cascaded together to form a shift register group, and an electronic signal is transmitted from a shift register of a previous stage to a shift register of a next stage. Therefore, through the delay time of signal transmission in the shift register group, an electronic signal can exert correct effects at different time and different positions. In the prior art, when the AMOLED display operates an emission signal required by a P-type MOS (Metal oxide semiconductor), the inverter under the P-type driving architecture cannot provide a stable output at a low voltage level, thereby increasing the risk of controlling the P-type MOS. For example, the voltage potential of the emission signal driving the P-type MOS in the ideal state is the low threshold voltage VGLHowever, the voltage potential actually outputted may be (V)GL+VTH) The threshold voltage of one transistor is higher than the low threshold voltage, which will undoubtedly increase the uncertainty of pixel control, and further affect the picture quality of the display.
In view of the above, how to design a novel shift register or to improve the existing shift register to ensure the transmission will be surely guaranteedThe voltage potential of the signal reaches a low threshold voltage VGL. To reduce or eliminate the unstable signal potential, a problem to be solved by those skilled in the art is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the shift registers for AMOLED in the prior art, the present invention provides a novel shift register capable of reducing the unstable signal potential.
According to an aspect of the present invention, there is provided a shift register suitable for an Active Matrix Organic Light Emitting Diode (AMOLED) display, the shift register including a control signal generating circuit, the control signal generating circuit including:
the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;
a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a first clock signal, the first terminal of the second transistor is electrically coupled to the second terminal of the first transistor to form a first node, the second terminal of the second transistor is electrically coupled to a second predetermined voltage, wherein the second predetermined voltage is smaller than the first predetermined voltage, and the first node is further electrically connected to the current shift signal output terminal;
a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to the first node, and the first terminal of the third transistor is electrically coupled to the first predetermined voltage;
a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous-stage signal, the first terminal of the fourth transistor is electrically coupled to the second terminal of the third transistor to form a second node, the second terminal of the fourth transistor is electrically coupled to the second predetermined voltage, and the second node is further electrically connected to a control signal;
a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the fifth transistor is electrically connected to a post signal associated with the pre signal; and
a sixth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the sixth transistor being electrically connected to the second node, the first terminal of the sixth transistor being electrically coupled to the second terminal of the fifth transistor, the second terminal of the sixth transistor receiving a second clock signal, a first capacitor being present between the first terminal of the sixth transistor and the second node,
the current shift signal output end and the next shift signal output end further include a feedback capacitor therebetween, and a pulse falling edge of the next shift signal pulls down the potential of the first node to a level lower than a difference between the second preset voltage and a threshold voltage, where the threshold voltage is a threshold voltage of the transistor.
In one embodiment, the shift register further includes a driving circuit, and the driving circuit includes: a first input end electrically connected to the second node for receiving the control signal; a second input end electrically connected to the first node for receiving the current shift signal; and the output end outputs an emission signal to drive the organic light-emitting diode according to the logic operation between the control signal and the current shift signal.
In one embodiment, the driving circuit includes: a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the second node, and the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage; and an eighth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor and the second terminal of the seventh transistor are both electrically connected to the output terminal of the driving circuit, and the second terminal of the eighth transistor is electrically coupled to the second preset voltage.
In one embodiment, the seventh transistor and the eighth transistor are both pmos transistors.
In one embodiment, when the second node is at a high potential and the potential of the first node is less than a difference between the second predetermined voltage and a threshold voltage, the seventh transistor is turned off, the eighth transistor is turned on, and the potential of the emission signal is equal to the second predetermined voltage.
In one embodiment, when the second node is at a low potential and the potential of the first node is equal to the first preset voltage, the seventh transistor is turned on, the eighth transistor is turned off, and the potential of the emission signal is equal to the first preset voltage.
In an embodiment of the present invention, the second clock signal sequentially includes a first pulse signal, a second pulse signal, and a third pulse signal, and the first clock signal sequentially includes the second pulse signal, the third pulse signal, and the first pulse signal.
In one embodiment, the first to sixth transistors are all pmos transistors.
According to another aspect of the present invention, there is provided a shift register suitable for an Active Matrix Organic Light Emitting Diode (AMOLED) display, the shift register including a control signal generating circuit, the control signal generating circuit including:
the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;
a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a current stage signal associated with the previous stage signal, the first terminal of the second transistor is electrically coupled to the first predetermined voltage, the second terminal of the second transistor is electrically connected to the second terminal of the first transistor to form a first node, and the first node is further electrically connected to the current shift signal output terminal;
a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to a post signal associated with the pre signal, the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor, the second terminal of the third transistor is electrically coupled to a second predetermined voltage, and the second predetermined voltage is less than the first predetermined voltage;
a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous stage signal, the first terminal of the fourth transistor is electrically connected to a control signal, and the second terminal of the fourth transistor is electrically coupled to the second preset voltage;
a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor to form a second node, the first terminal of the fifth transistor is electrically coupled to the control terminal of the second transistor, and the second terminal of the fifth transistor is electrically connected to a clock signal;
a sixth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the sixth transistor is electrically connected to the first terminal of the fourth transistor;
a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage, the second terminal of the seventh transistor is electrically connected to the first terminal of the fifth transistor, and a first capacitor is further included between the second terminal of the seventh transistor and the second terminal of the sixth transistor; and
an eighth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the eighth transistor being electrically connected to an inverted clock signal, the first terminal of the eighth transistor being electrically connected to the first predetermined voltage, the second terminal of the eighth transistor being electrically connected to the first terminal of the fifth transistor,
the current shift signal output end and the next shift signal output end further include a feedback capacitor therebetween, and a pulse falling edge of the next shift signal pulls down the potential of the first node to a level lower than a difference between the second preset voltage and a threshold voltage, where the threshold voltage is a threshold voltage of the transistor.
In one embodiment, the shift register further includes a driving circuit, and the driving circuit includes: a ninth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the ninth transistor being electrically connected to the second node for receiving the control signal, the first terminal of the ninth transistor being electrically coupled to the first predetermined voltage; and a tenth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the tenth transistor is electrically connected to the first node to receive the current shift signal, the first terminal of the tenth transistor and the second terminal of the ninth transistor are both electrically connected to the output terminal of the driving circuit, the second terminal of the tenth transistor is electrically coupled to the second preset voltage, and the output terminal of the driving circuit outputs an emission signal according to a logic operation between the control signal and the current shift signal to drive the organic light emitting diode.
By adopting the shift register of the invention, the first end of the second transistor is electrically coupled to the second end of the first transistor so as to form a first node, the first node is electrically connected to the current shift signal output end, the first end of the fourth transistor is electrically coupled to the second end of the third transistor so as to form a second node, the second node is electrically connected to a control signal, and a feedback capacitor is arranged between the current shift signal output end and the next shift signal output end. Compared with the prior art, the shift register can enable the falling edge pulse of the next stage of shift signal to be coupled to the first node through the feedback capacitor, so that the potential of the shift register is pulled down to be lower than the difference value between the second preset voltage and the threshold voltage of the transistor, the voltage potential of the emission signal can reach the second preset voltage, and the low potential of the emission signal can be kept stable.
Drawings
The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
fig. 1 shows a circuit configuration diagram of a shift register in the prior art;
FIG. 2 shows timing waveforms of main signals of the shift register of FIG. 1;
FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present invention;
FIG. 4 illustrates timing waveforms of main signals of the shift register of FIG. 3;
FIG. 5 is a diagram showing the on and off states of the switching tubes of the shift register of FIG. 3 during the falling edge pulse of the next stage shift signal; and
fig. 6 is a schematic circuit diagram of a shift register according to another embodiment of the invention.
Detailed Description
In order to make the present disclosure more complete and complete, reference is made to the accompanying drawings, in which like references indicate similar or analogous elements, and to the various embodiments of the invention described below. However, it will be understood by those of ordinary skill in the art that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for illustrative purposes and are not drawn to scale.
Specific embodiments of various aspects of the present invention are described in further detail below with reference to the accompanying drawings.
Fig. 1 is a circuit configuration diagram of a shift register in the related art, and fig. 2 is a timing waveform diagram of main signals of the shift register of fig. 1.
Referring to fig. 1 and 2, the conventional shift register obtains an output signal N from input signals (N-1), CK, and XCK. Wherein, N-1 represents a previous stage signal, CK represents a clock signal, and XCK represents an inverted clock signal. It should be understood by those skilled in the art that when a pmos transistor is taken as an example, the control terminal of the transistor is a gate, the first terminal of the transistor may correspond to a source (or drain), and the second terminal of the transistor may correspond to a drain (or source).
The control terminal of the first transistor T1 receives a previous stage signal (N-1). A first terminal of the first transistor T1 is coupled to the first predetermined voltage VGH. The second terminal of the first transistor T1 is connected to the first terminal of the fourth transistor T4 and the control terminal of the fifth transistor T5. The control terminal of the second transistor T2 receives the previous stage signal (N-1). A first terminal of the second transistor T2 is electrically coupled to the control terminal of the third transistor T3 and a second terminal of the fifth transistor T5.
The first terminal of the third transistor T3 is electrically coupled to the second terminal of the sixth transistor T6, and the second terminal of the third transistor T3 is electrically coupled to a clock signal CK. A control terminal of the third transistor T3 is electrically connected to the first terminal of the second transistor T2 and the second terminal of the fifth transistor T5. The control terminal of the fourth transistor T4 receives an inverted clock signal XCK. The first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the first transistor T1, and the first terminal of the fourth transistor T4, the second terminal of the first transistor T1, the control terminal of the fifth transistor T5 and the control terminal of the sixth transistor T6 are all electrically connected to the current shift signal output terminal Q. The second terminal of the fourth transistor T4 is electrically coupled to the second predetermined voltage VGL. For example, the first preset voltage VGH corresponds to a high voltage level, and the second preset voltage VGL corresponds to a low voltage level.
The control terminal of the fifth transistor T5 is electrically connected to the second terminal of the first transistor T1 and the first terminal of the fourth transistor T4. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the second transistor T2. In addition, the second terminal of the fifth transistor T5, the first terminal of the second transistor T2, and the control terminal of the third transistor T3 are all electrically connected to the control signal output terminal BT. The control terminal of the sixth transistor T6 is also electrically connected to the second terminal of the first transistor T1. The first terminal of the sixth transistor T6 is electrically coupled to the first predetermined voltage VGH. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the third transistor T3. In addition, a capacitor C1 is included between the second terminal of the sixth transistor T6 and the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 includes a capacitor C2 between the second terminal and the second predetermined voltage VGL.
Referring to fig. 1 and 2, when the previous-stage signal (N-1) continues to be high in the first pulse signal CLK1 and the second pulse signal CLK2 and the third pulse signal CLK3 is negative, the voltage level at the control signal output terminal BT is at the same levelNow the ladder type descends. After that, when the first pulse signal CLK1 is negative and the second pulse signal CLK2 and the third pulse signal CLK3 continue to be high, the voltage potential at the control signal output terminal BT further decreases. However, when the AMOLED display operates the emission signal required by the P-type MOS, the inverter under the P-type driving scheme cannot provide a stable output at a low voltage level, thereby increasing the risk of controlling the P-type MOS. For example, the voltage potential of the emission signal driving the P-type MOS in the ideal state is the low threshold voltage VGLHowever, the voltage potential actually outputted may be (V)GL+VTH) The threshold voltage of one transistor is higher than the low threshold voltage, which will undoubtedly increase the uncertainty of pixel control, and further affect the picture quality of the display.
In order to effectively improve or eliminate the above-mentioned defects, fig. 3 shows a circuit structure diagram of a shift register according to an embodiment of the present invention, and fig. 4 shows a timing waveform diagram of main signals of the shift register of fig. 3.
Referring to fig. 3, the shift register of the present invention includes a control signal generating circuit 10. The control signal generation circuit 10 includes six transistors (i.e., transistors T1 to T6) and two capacitors (i.e., capacitors C1 and Cf). For example, the first to sixth transistors T1 to T6 are pmos transistors. Of course, in other embodiments, the first to sixth transistors T1 to T6 may also be N-type MOS transistors.
Similarly, the control terminal of the first transistor T1 receives a previous stage signal (N-1). The first terminal of the first transistor T1 is electrically coupled to a first predetermined voltage VGH. The control terminal of the second transistor T2 receives a first clock signal XCK. The first terminal of the second transistor T2 is electrically coupled to the second terminal of the first transistor T1 to form a first node P1. The second terminal of the second transistor T2 is electrically coupled to a second predetermined voltage VGL. The second preset voltage VGL is less than the first preset voltage VGH. The first node P1 is also electrically connected to the current shift signal output terminal Q.
A control terminal of the third transistor T3 is electrically connected to the first node P1. A first terminal of the third transistor T3 is electrically coupled to the first predetermined voltage VGH. The control terminal of the fourth transistor T4 receives the previous stage signal (N-1). The first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the third transistor T3 to form a second node P2. The second terminal of the fourth transistor T4 is electrically coupled to the second predetermined voltage VGL. The second node P2 is also electrically connected to a control signal output terminal BT.
The control terminal of the fifth transistor T5 is electrically connected to the first node P1. The first terminal of the fifth transistor T5 is electrically coupled to the first predetermined voltage VGH. The second terminal of the fifth transistor T5 is electrically connected to a next-stage signal N associated with the previous-stage signal (N-1). The control terminal of the sixth transistor T6 is electrically connected to the second node P2. The first terminal of the sixth transistor T6 is electrically coupled to the second terminal of the fifth transistor T5. The second terminal of the sixth transistor T6 receives a second clock signal CK. A first capacitor C1 is disposed between the first terminal of the sixth transistor T6 and the second node P2.
It should be noted that, compared to the prior art, in the circuit architecture of the shift register of the present invention, a feedback capacitor Cf is further included between the current shift signal output terminal Q and the next shift signal output terminal (Q + 1). The pulse falling edge of the next-stage shift signal (Q + 1) pulls the potential of the first node P1 down to be lower than the difference between the second preset voltage VGL and a threshold voltage Vth (e.g., a threshold voltage of a transistor) through the feedback capacitor Cf, so that the voltage potential of the emission signal EM output by the driving circuit 20 can actually reach the second preset voltage VGL, that is, the low potential of the emission signal is kept stable, and the control risk of the pixel switch is prevented from increasing.
In one embodiment, the second clock signal CK sequentially includes a first pulse signal CLK1, a second pulse signal CLK2, and a third pulse signal CLK 3. The first clock signal XCK includes a second pulse signal CLK2, a third pulse signal CLK3, and a first pulse signal CLK1 in this order. As shown in fig. 4, when the previous-stage signal (N-1) continues to be at a high level in the first pulse signal CLK1 and the second pulse signal CLK2 and the third pulse signal CLK3 is a negative pulse, the voltage potential at the control signal output terminal BT is decreased in a step-like manner, as shown in fig. 2. When the first pulse signal CLK1 is negative and the second pulse signal CLK2 and the third pulse signal CLK3 continue to be high, the voltage level at the control signal output terminal BT further decreases, and the voltage at the shift signal output terminal Q continues to be maintained at the high voltage level VGH. Then, when the second pulse signal CLK2 is negative and the first pulse signal CLK1 and the third pulse signal CLK3 continue to be high, the voltage level of the control signal output terminal BT is raised in a stepwise manner, and the voltage level of the current shift signal output terminal Q is lowered from the high voltage level VGH to VGL + | Vth |. Since the feedback capacitor Cf is included between the current shift signal output terminal Q and the next shift signal output terminal (Q + 1), when the third pulse signal CLK3 is negative and the second pulse signal CLK2 and the first pulse signal CLK1 are continuously high, the pulse falling edge of the next shift signal (Q + 1) pulls the potential of the first node P1 down to a value less than the difference between the second predetermined voltage VGL and a threshold voltage Vth through the coupling effect of the feedback capacitor Cf, i.e., the voltage value of the first node P1 at this time is less than the threshold voltage Vth.
In one embodiment, the shift register further includes a driving circuit 20. The driving circuit 20 includes a first input terminal, a second input terminal and an output terminal. The first input terminal is electrically connected to the second node P2 for receiving the control signal BT. The second input terminal is electrically connected to the first node P1 for receiving the current shift signal Q. The output terminal outputs an emission signal EM to drive an Organic Light Emitting Diode (OLED) according to a logical operation between the control signal BT and the current shift signal Q. Fig. 3 also schematically depicts a circuit implementation architecture of the driving circuit 20. Specifically, the driving circuit 20 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is electrically connected to the second node P2 (i.e., the control signal terminal BT), and the first terminal of the seventh transistor T7 is electrically coupled to the first predetermined voltage VGH. The control terminal of the eighth transistor T8 is electrically connected to the first node P1 (i.e., the current shift signal terminal Q), the first terminal of the eighth transistor T8 and the second terminal of the seventh transistor T7 are electrically connected to the output terminal of the driving circuit 20, and the second terminal of the eighth transistor T8 is electrically coupled to the second predetermined voltage VGL.
In practical operation, when the second node P2 is at a high level and the potential of the first node P1 is less than the difference between the second predetermined voltage VGL and a threshold voltage Vth, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, and the potential of the emission signal EM is equal to the second predetermined voltage VGL. When the second node P2 is at the low level and the potential of the first node P1 is equal to the first predetermined voltage VGH, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, and the potential of the emission signal EM is equal to the first predetermined voltage VGH.
Fig. 5 is a diagram showing the on and off states of each switching tube of the shift register of fig. 3 during the falling edge pulse of the next stage shift signal.
Referring to fig. 5 and 4, if the previous-stage signal (N-1) is at a high voltage potential, both the transistors T1 and T4 are in an off state. At this time, since the clock signals CK and XCK are also at the high voltage potential, the transistors T2 and T6 are also in the off state. When the next shift signal (Q + 1) is a pulse falling edge, the first node P1 is at a low level due to the coupling effect of the feedback capacitor Cf, and the transistors T3 and T5 are turned on.
Fig. 6 is a schematic circuit diagram of a shift register according to another embodiment of the invention. Referring to fig. 6, the shift register includes a control signal generating circuit 30. The control signal generation circuit 30 includes eight transistors (i.e., transistors T1-T8) and two capacitors (i.e., capacitors C1 and Cf). For example, the first to eighth transistors T1 to T8 are pmos transistors. Of course, in other embodiments, the first to eighth transistors T1 to T8 may also be N-type MOS transistors.
Specifically, the control terminal of the first transistor T1 receives a previous stage signal (N-1). The first terminal of the first transistor T1 is electrically coupled to the first predetermined voltage VGH. The control terminal of the second transistor T2 receives a current stage signal N associated with the previous stage signal (N-1). A first terminal of the second transistor T2 is electrically coupled to the first predetermined voltage VGH. The second terminal of the second transistor T2 is electrically connected to the second terminal of the first transistor T1 to form a first node P1, and the node P1 is also electrically connected to the current shift signal output terminal Q.
The control terminal of the third transistor T3 is electrically connected to a next-stage signal (N + 1) associated with the previous-stage signal (N-1). The first terminal of the third transistor T3 is electrically coupled to the second terminal of the second transistor T2, and the second terminal of the third transistor T3 is electrically coupled to a second predetermined voltage VGL. The control terminal of the fourth transistor T4 receives the previous signal (N-1), the first terminal of the fourth transistor T4 is electrically connected to a second node P2, and the second terminal of the fourth transistor T4 is electrically coupled to the second predetermined voltage VGL.
The control terminal of the fifth transistor T5 is electrically connected to the first terminal of the fourth transistor T4 to form a second node P2, the first terminal of the fifth transistor T5 is electrically coupled to the control terminal of the second transistor T2, and the second terminal of the fifth transistor T5 is electrically connected to a clock signal CK. The control terminal of the sixth transistor T6 is electrically connected to the first node P1, the first terminal of the sixth transistor T6 is electrically coupled to the first predetermined voltage VGH, and the second terminal of the sixth transistor T6 is electrically connected to the first terminal of the fourth transistor T4.
The control terminal of the seventh transistor T7 is electrically connected to the first node P1, the first terminal of the seventh transistor T7 is electrically coupled to the first predetermined voltage VGH, and the second terminal of the seventh transistor T7 is electrically connected to the first terminal of the fifth transistor T5. A first capacitor C1 is further included between the second terminal of the seventh transistor T7 and the second terminal of the sixth transistor T6. The control terminal of the eighth transistor T8 is electrically connected to an inverted clock signal XCK, the first terminal of the eighth transistor T8 is electrically connected to the first predetermined voltage VGH, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal of the fifth transistor T5.
Similar to fig. 3, in this embodiment, a feedback capacitor Cf is further included between the current shift signal output terminal Q of the shift register and the next shift signal output terminal (Q + 1), and the pulse falling edge of the next shift signal pulls the potential of the first node P1 to be lower than the difference between the second preset voltage VGL and a threshold voltage Vth through the feedback capacitor Cf, so that the voltage potential of the emission signal EM output by the driving circuit can actually reach the second preset voltage VGL, i.e., the low potential of the emission signal is kept stable, and the control risk of the pixel switch is prevented from increasing. Since the architecture of the driving circuit is the same as that of the driving circuit 20 in fig. 3, the description thereof is omitted.
By adopting the shift register of the invention, the first end of the second transistor is electrically coupled to the second end of the first transistor so as to form a first node, the first node is electrically connected to the current shift signal output end, the first end of the fourth transistor is electrically coupled to the second end of the third transistor so as to form a second node, the second node is electrically connected to a control signal, and a feedback capacitor is arranged between the current shift signal output end and the next shift signal output end. Compared with the prior art, the shift register can enable the falling edge pulse of the next stage of shift signal to be coupled to the first node through the feedback capacitor, so that the potential of the shift register is pulled down to be lower than the difference value between the second preset voltage and the threshold voltage of the transistor, the voltage potential of the emission signal can reach the second preset voltage, and the low potential of the emission signal can be kept stable.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (10)
1. A shift register suitable for an active matrix organic light emitting diode display, wherein the shift register comprises a control signal generating circuit, and the control signal generating circuit comprises:
the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;
a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a first clock signal, the first terminal of the second transistor is electrically coupled to the second terminal of the first transistor to form a first node, the second terminal of the second transistor is electrically coupled to a second predetermined voltage, wherein the second predetermined voltage is smaller than the first predetermined voltage, and the first node is further electrically connected to the current shift signal output terminal;
a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to the first node, and the first terminal of the third transistor is electrically coupled to the first predetermined voltage;
a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous-stage signal, the first terminal of the fourth transistor is electrically coupled to the second terminal of the third transistor to form a second node, the second terminal of the fourth transistor is electrically coupled to the second predetermined voltage, and the second node is further electrically connected to a control signal;
a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the fifth transistor is electrically connected to a post signal associated with the pre signal; and
a sixth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the sixth transistor being electrically connected to the second node, the first terminal of the sixth transistor being electrically coupled to the second terminal of the fifth transistor, the second terminal of the sixth transistor receiving a second clock signal, a first capacitor being present between the first terminal of the sixth transistor and the second node,
a feedback capacitor is further included between the current shift signal output terminal and the next shift signal output terminal, and a pulse falling edge of the next shift signal pulls down the potential of the first node to be less than a difference between the second preset voltage and a threshold voltage through the feedback capacitor, where the threshold voltage is a threshold voltage of the transistor.
2. The shift register of claim 1, further comprising a driving circuit, the driving circuit comprising:
a first input end electrically connected to the second node for receiving the control signal;
a second input end electrically connected to the first node for receiving the current shift signal; and
and the output end outputs an emission signal to drive the organic light-emitting diode according to the logic operation between the control signal and the current shift signal.
3. The shift register according to claim 2, wherein the driving circuit comprises:
a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the second node, and the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage;
an eighth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor and the second terminal of the seventh transistor are both electrically connected to the output terminal of the driving circuit, and the second terminal of the eighth transistor is electrically coupled to the second preset voltage.
4. The shift register according to claim 3, wherein the seventh transistor and the eighth transistor are both P-type metal oxide semiconductor transistors.
5. The shift register of claim 4, wherein when the second node is high and the potential of the first node is less than a difference between the second predetermined voltage and a threshold voltage, the seventh transistor is turned off, the eighth transistor is turned on, and the potential of the emission signal is equal to the second predetermined voltage.
6. The shift register according to claim 4, wherein when the second node is at a low potential and the potential of the first node is equal to the first predetermined voltage, the seventh transistor is turned on, the eighth transistor is turned off, and the potential of the emission signal is equal to the first predetermined voltage.
7. The shift register according to claim 1, wherein the second clock signal sequentially includes a first pulse signal, a second pulse signal, and a third pulse signal, and the first clock signal sequentially includes the second pulse signal, the third pulse signal, and the first pulse signal.
8. The shift register according to claim 1, wherein the first to sixth transistors are all P-type metal oxide semiconductor transistors.
9. A shift register suitable for an active matrix organic light emitting diode display, wherein the shift register comprises a control signal generating circuit, and the control signal generating circuit comprises:
the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;
a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a current stage signal associated with the previous stage signal, the first terminal of the second transistor is electrically coupled to the first predetermined voltage, the second terminal of the second transistor is electrically connected to the second terminal of the first transistor to form a first node, and the first node is further electrically connected to the current shift signal output terminal;
a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to a post signal associated with the pre signal, the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor, the second terminal of the third transistor is electrically coupled to a second predetermined voltage, and the second predetermined voltage is less than the first predetermined voltage;
a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous stage signal, the first terminal of the fourth transistor is electrically connected to a control signal, and the second terminal of the fourth transistor is electrically coupled to the second preset voltage;
a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor to form a second node, the first terminal of the fifth transistor is electrically coupled to the control terminal of the second transistor, and the second terminal of the fifth transistor is electrically connected to a clock signal;
a sixth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the sixth transistor is electrically connected to the first terminal of the fourth transistor;
a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage, the second terminal of the seventh transistor is electrically connected to the first terminal of the fifth transistor, and a first capacitor is further included between the second terminal of the seventh transistor and the second terminal of the sixth transistor; and
an eighth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the eighth transistor being electrically connected to an inverted clock signal, the first terminal of the eighth transistor being electrically connected to the first predetermined voltage, the second terminal of the eighth transistor being electrically connected to the first terminal of the fifth transistor,
a feedback capacitor is further included between the current shift signal output terminal and the next shift signal output terminal, and a pulse falling edge of the next shift signal pulls down the potential of the first node to be less than a difference between the second preset voltage and a threshold voltage through the feedback capacitor, where the threshold voltage is a threshold voltage of the transistor.
10. The shift register of claim 9, further comprising a driver circuit, the driver circuit comprising:
a ninth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the ninth transistor being electrically connected to the second node for receiving the control signal, the first terminal of the ninth transistor being electrically coupled to the first predetermined voltage; and
a tenth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the tenth transistor being electrically connected to the first node for receiving the current shift signal, the first terminal of the tenth transistor and the second terminal of the ninth transistor being electrically connected to the output terminal of the driving circuit, the second terminal of the tenth transistor being electrically coupled to the second predetermined voltage,
the output end of the driving circuit outputs an emission signal according to the logical operation between the control signal and the current shift signal so as to drive the organic light-emitting diode.
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|---|---|---|---|
| CN201310566513.4A CN103559913A (en) | 2013-11-14 | 2013-11-14 | Shifting register |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310566513.4A CN103559913A (en) | 2013-11-14 | 2013-11-14 | Shifting register |
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| CN103559913A true CN103559913A (en) | 2014-02-05 |
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| CN104700899A (en) * | 2015-01-28 | 2015-06-10 | 友达光电股份有限公司 | Shift register circuit |
| CN105632561A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shift register, driving method, grid driving circuit and display device |
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| CN107358902A (en) * | 2016-05-09 | 2017-11-17 | 三星显示有限公司 | Display panel drive, display device and the method for driving display panel |
| EP3232430A4 (en) * | 2014-12-10 | 2018-07-04 | Boe Technology Group Co. Ltd. | Shift register and drive method therefor, shift scanning circuit and display device |
| CN112309295A (en) * | 2019-07-29 | 2021-02-02 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3232430A4 (en) * | 2014-12-10 | 2018-07-04 | Boe Technology Group Co. Ltd. | Shift register and drive method therefor, shift scanning circuit and display device |
| US9653179B2 (en) | 2014-12-30 | 2017-05-16 | Shanghai Tianma AM-OLED Co., Ltd. | Shift register, driving method and gate driving circuit |
| CN104700899A (en) * | 2015-01-28 | 2015-06-10 | 友达光电股份有限公司 | Shift register circuit |
| CN104700899B (en) * | 2015-01-28 | 2018-02-13 | 友达光电股份有限公司 | Shift register circuit |
| CN105632561A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shift register, driving method, grid driving circuit and display device |
| WO2017118136A1 (en) * | 2016-01-05 | 2017-07-13 | 京东方科技集团股份有限公司 | Shift register and drive method therefor, gate drive circuit, and display device |
| US9966957B2 (en) | 2016-01-05 | 2018-05-08 | Boe Technology Group Co., Ltd. | Shift register and a driving method thereof, a gate driving circuit and a display device |
| CN105632561B (en) * | 2016-01-05 | 2018-09-07 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| CN107358902A (en) * | 2016-05-09 | 2017-11-17 | 三星显示有限公司 | Display panel drive, display device and the method for driving display panel |
| CN112309295A (en) * | 2019-07-29 | 2021-02-02 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
| CN112309295B (en) * | 2019-07-29 | 2023-12-08 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and display device |
| CN113936585A (en) * | 2021-11-08 | 2022-01-14 | 福建华佳彩有限公司 | GIP circuit and method for reducing display abnormity |
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