CN106548747A - Shift register cell and its driving method, gate driver circuit and display device - Google Patents
Shift register cell and its driving method, gate driver circuit and display device Download PDFInfo
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- CN106548747A CN106548747A CN201710065699.3A CN201710065699A CN106548747A CN 106548747 A CN106548747 A CN 106548747A CN 201710065699 A CN201710065699 A CN 201710065699A CN 106548747 A CN106548747 A CN 106548747A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of shift register cell and its driving method, gate driver circuit and display device, belong to display technology field.The shift register cell includes：Input module, output module and drop-down module；The drop-down module is for, under the control of second clock signal, carrying out noise reduction to pull-up node and outfan.As the duration that the second clock signal of the second clock signal end output is in the first current potential in blanking period is more than 0, therefore can ensure that the drop-down module can continue noise reduction to be carried out to pull-up node and outfan in blanking period, it is ensured that the display effect of display device.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of shift register cell and its driving method, grid drive
Galvanic electricity road and display device.
Background technology
Display device needs to carry out pixel cell using shift register (i.e. gate driver circuit) in display image
Scanning, shift register include the shift register cell of multiple cascades, each shift register cell correspondence one-row pixels list
Unit, is realized driving the progressive scan of each row pixel cell in display device by the shift register cell of the plurality of cascade, with
Display image.
There is a kind of shift register cell in correlation technique, the shift register cell includes multiple transistors and electric capacity
Device.The plurality of transistor and capacitor are connected with multiple signal ends respectively, can be in the control of the signal of the plurality of signal end output
Under system, the current potential height of the outfan of the shift register cell is controlled.
But, the interval between the shift register previous frame end of scan starts to next frame scan, also referred to as blanking
Stage (English：Vertical Blank；Referred to as：V Blank) in, the signal of each signal end output is in electronegative potential, often
Transistor in individual shift register cell for noise reduction is carried out to outfan possibly effectively cannot be opened so that shift register
There is noise in the outfan of unit, affect the display effect of display device.
The content of the invention
There is noise in blanking period in order to solve the outfan of shift register cell in correlation technique, affect to show dress
The problem of the display effect put, the invention provides a kind of shift register cell and its driving method, gate driver circuit and
Display device.The technical scheme is as follows：
First aspect, there is provided a kind of shift register cell, the shift register cell include：
Input module, output module and drop-down module；
The input module respectively with input signal end, reset signal end, the first control signal end, the second control signal end
Connect with pull-up node, in the input signal from the input signal end, from the of first control signal end
One control signal, the reset signal from the reset signal end and the second control signal from second control signal end
Control under, control the current potential of the pull-up node；
The output module is connected with the first clock signal terminal, the pull-up node and outfan respectively, for described
Under the control of pull-up node, the first clock signal from first clock signal terminal is exported to the outfan；
The drop-down module respectively with second clock signal end, power supply signal end, the pull-up node and the outfan
Connection, under the control of the second clock signal from the second clock signal end, to the pull-up node and described
Outfan exports the power supply signal from the power supply signal end；
Wherein, the second clock signal of second clock signal end output in blanking period in the first current potential when
It is long to be more than 0.
Optionally, the drop-down module includes：Control submodule and drop-down submodule；
The control submodule respectively with the second clock signal end, the power supply signal end, the pull-up node, institute
Outfan and pull-down node connection are stated, in the second clock signal, the power supply signal, the pull-up node and described
Under the control of outfan, the current potential of the pull-down node is controlled；
The drop-down submodule respectively with the pull-down node, the power supply signal end, the pull-up node and described defeated
Go out end connection, for, under the control of the pull-down node, the power supply letter being exported to the pull-up node and the outfan
Number.
Optionally, the control submodule, including：The first transistor, transistor seconds, third transistor and the first electric capacity
Device；
The grid of the first transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end, the
Two poles are connected with the pull-down node；
The grid of the transistor seconds and the first pole are connected with the second clock signal end, and the second pole is drop-down with described
Node connects；
The grid of the third transistor is connected with the outfan, and the first pole is connected with the power supply signal end, and second
Pole is connected with the pull-down node；
One end of first capacitor is connected with the pull-down node, and the other end is connected with the power supply signal end.
Optionally, the drop-down submodule, including：4th transistor and the 5th transistor；
The grid of the 4th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the
Two poles are connected with the outfan；
The grid of the 5th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the
Two poles are connected with the pull-up node.
Optionally, the input module, including：6th transistor and the 7th transistor；The output module, including：The
Eight transistors and the second capacitor；
The grid of the 6th transistor is connected with the input signal end, and the first pole is connected with first control signal end
Connect, the second pole is connected with the pull-up node；
The grid of the 7th transistor is connected with the reset signal end, and the first pole is connected with second control signal end
Connect, the second pole is connected with the pull-up node；
The grid of the 8th transistor is connected with the pull-up node, and the first pole is connected with first clock signal terminal
Connect, the second pole is connected with the outfan；
One end of second capacitor is connected with the pull-up node, and the other end is connected with the outfan.
Optionally, the second clock signal of the second clock signal end output is in blanking period and the week in sweep phase
Phase is identical, and dutycycle is identical.
Second aspect, there is provided a kind of driving method of shift register cell, the shift register cell include：It is defeated
Enter module, output module and drop-down module；Methods described includes：Sweep phase and blanking period；
In the sweep phase, when input signal end output input signal be the first current potential, the first control signal end
When first control signal of output is the first current potential, the input module pulls up node and exports first control signal, institute
Output module is stated under the control of the pull-up node, the first clock from the first clock signal terminal is exported to the outfan
Signal,
When reset signal end output reset signal be the first current potential, the second control signal end output the second control signal
For the second current potential when, the input module exports second control signal to the pull-up node,
When the second clock signal of second clock signal end output is the first current potential, the drop-down module is described second
Under the control of clock signal, the power supply signal from power supply signal end is exported to the pull-up node and the outfan, it is described
Power supply signal is in the second current potential；
In the blanking period, the second clock signal of second clock signal end output in the first current potential when
Long to be more than 0, the drop-down module continues to the pull-up node and the outfan under the control of the second clock signal
Export the power supply signal.
Optionally, the second clock signal of the second clock signal end output is in the blanking period and in the scanning
The cycle phase in stage is same, and dutycycle is identical.
The third aspect, there is provided a kind of gate driver circuit, the gate driver circuit include：
The shift register cell as described in relation to the first aspect of at least two cascades；
Wherein, each shift register cell is connected with the first clock signal terminal and second clock signal end respectively, described
Duration of first clock signal of the first clock signal terminal output in blanking period in the first current potential is more than 0, described second
Duration of the second clock signal of clock signal terminal output in blanking period in the first current potential is more than 0.
Fourth aspect, there is provided a kind of display device, the display device include：Raster data model as described in the third aspect
Circuit.
The beneficial effect brought of technical scheme that the present invention is provided is：
The invention provides a kind of shift register cell and its driving method, gate driver circuit and display device.Should
Shift register cell includes drop-down module, the drop-down module can under the control of second clock signal, to pull-up node and
Outfan noise reduction.As the second clock signal end can alternately export the letter of the first current potential and the second current potential in blanking period
Number, therefore can ensure that the drop-down module persistently can carry out noise reduction to pull-up node and outfan in blanking period, it is ensured that it is aobvious
The display effect of showing device.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to making needed for embodiment description
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, can be obtaining other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation of shift register cell provided in an embodiment of the present invention；
Fig. 2 is a kind of sequential chart of second clock signal provided in an embodiment of the present invention；
Fig. 3 is the structural representation of another kind of shift register cell provided in an embodiment of the present invention；
Fig. 4 is the structural representation of another shift register cell provided in an embodiment of the present invention；
Fig. 5 is a kind of flow chart of the driving method of shift register cell provided in an embodiment of the present invention；
Fig. 6 is a kind of sequential chart of the driving process of shift register cell provided in an embodiment of the present invention；
Fig. 7 is the sequential chart of the driving process of shift register cell in correlation technique；
Fig. 8 is a kind of structural representation of gate driver circuit provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
The transistor adopted in all embodiments of the invention can be thin film transistor (TFT) or field effect transistor or other characteristics
Identical device, is mainly switching transistor according to the transistor adopted by effect embodiments of the invention in circuit.By
Source electrode, drain electrode in the switching transistor for adopting here is symmetrical, so its source electrode, drain electrode can be exchange.At this
In bright embodiment, wherein will be referred to as the first order by source electrode, drain electrode is referred to as the second level.Specify the centre of transistor by the form in accompanying drawing
Hold for grid, signal input part be source electrode, signal output part for drain electrode.Additionally, the switch crystal adopted by the embodiment of the present invention
Pipe can include any one in p-type switching transistor and N-type switching transistor, wherein, p-type switching transistor is in grid for low
Turn on during current potential, end when grid is high potential, N-type switching transistor is turned on when grid is high potential, be low in grid
End during current potential.Additionally, the multiple signals in each embodiment of the invention are all to having the first current potential and the second current potential.First is electric
Position and the second current potential only represent the current potential of the signal 2 quantity of states, and in not representing in full, the first current potential or the second current potential have
Specific numerical value.
Fig. 1 is a kind of structural representation of shift register cell provided in an embodiment of the present invention, as shown in figure 1, the shifting
Bit register unit can include：Input module 10, output module 20 and drop-down module 30.
Wherein, the input module 10 respectively with input signal end IN, reset signal end RST, the first control signal end CN,
Two control signal ends CNB and pull-up node PU connection, for the input signal from input signal end IN, from this first
First control signal of control signal end CN, the reset signal from reset signal end RST and from second control signal
Under the control of second control signal of end CNB, the current potential of pull-up node PU is controlled.
The output module 20 is connected with the first clock signal terminal CK, pull-up node PU and outfan OUT respectively, for
Under the control of pull-up node PU, the first clock signal from first clock signal terminal CK is exported to outfan OUT.
The drop-down module 30 respectively with second clock signal end CKB, power supply signal end VSS, pull-up node PU and this is defeated
Go out and hold OUT to connect, under the control of the second clock signal from second clock signal end CKB, to the pull-up node
PU and outfan OUT exports the power supply signal from power supply signal end VSS.
Wherein, the second clock signal of second clock signal end CKB outputs is in the first current potential in blanking period
Duration is more than 0.First current potential can be effective current potential of the second clock signal.For example, the second clock signal is in blanking
The current potential in stage can be continuously the first current potential, or, the second clock signal can be alternately the in the current potential of blanking period
One current potential and the second current potential.Example, Fig. 2 is the of a kind of second clock signal end CKB output provided in an embodiment of the present invention
The sequential chart of two clock signals, as shown in Fig. 2 second clock signal end CKB can be in the scanning rank of shift register cell
Section T1 normally exports the first current potential and the alternate clock signal of the second current potential.Also, in blanking period T2, the second clock
Signal can be continued to output alternately as the first current potential and the signal of the second current potential, wherein, first current potential is second electric relative to this
Position is high potential.
In sum, a kind of shift register cell is embodiments provided, the shift register cell includes
Drop-down module, the drop-down module can be under the controls of second clock signal, to pull-up node and outfan noise reduction.Due to this
Duration of the second clock signal of two clock signal terminals output in blanking period in the first current potential is more than 0, therefore can protect
Demonstrate,proving the drop-down module persistently can carry out noise reduction to pull-up node and outfan in blanking period, it is ensured that the display effect of display device
Really.
Fig. 3 is the structural representation of another kind of shift register cell provided in an embodiment of the present invention, as shown in figure 3, should
Drop-down module 30 can include：Control submodule 301 and drop-down submodule 302.
The control submodule 301 respectively with second clock signal end CKB, power supply signal end VSS, the pull-up node
PU, outfan OUT and pull-down node PD connection, for the second clock signal, the power supply signal, pull-up node PU and
Under the control of outfan OUT, the current potential of pull-down node PD is controlled.
The drop-down submodule 302 respectively with pull-down node PD, power supply signal end VSS, pull-up node PU and this is defeated
Go out and hold OUT to connect, for, under the control of pull-down node PD, the power supply being exported to pull-up node PU and outfan OUT
Signal.
Further, with reference to Fig. 4, the control submodule 301 can include：The first transistor M1, transistor seconds M2,
Three transistor M3 and the first capacitor C1.
The grid of the first transistor M1 is connected with pull-up node PU, and the first pole is connected with power supply signal end VSS, the
Two poles are connected with pull-down node PD.
The grid of transistor seconds M2 and the first pole are connected with second clock signal end CKB, and the second pole is drop-down with this
Node PD connects.
The grid of third transistor M3 is connected with outfan OUT, and the first pole is connected with power supply signal end VSS, the
Two poles are connected with pull-down node PD.
One end of first capacitor C1 is connected with pull-down node PD, and the other end is connected with power supply signal end VSS.
With reference to Fig. 4, the drop-down submodule 302 can include：4th transistor M4 and the 5th transistor M5.
The grid of the 4th transistor M4 is connected with pull-down node PD, and the first pole is connected with power supply signal end VSS, the
Two poles are connected with outfan OUT.
The grid of the 5th transistor M5 is connected with pull-down node PD, and the first pole is connected with power supply signal end VSS, the
Two poles are connected with pull-up node PU.
Optionally, as shown in figure 4, the input module 10 can include：6th transistor M6 and the 7th transistor M7；This is defeated
Go out module 20, including：8th transistor M8 and the second capacitor C2.
The grid of the 6th transistor M6 is connected with input signal end IN, and the first pole is connected with first control signal end CN
Connect, the second pole is connected with pull-up node PU.
The grid of the 7th transistor M7 is connected with reset signal end RST, the first pole and second control signal end CNB
Connection, the second pole is connected with pull-up node PU.
The grid of the 8th transistor M8 is connected with pull-up node PU, and the first pole is connected with first clock signal terminal CK
Connect, the second pole is connected with outfan OUT.
One end of second capacitor C2 is connected with pull-up node PU, and the other end is connected with outfan OUT.
In embodiments of the present invention, the second clock signal end CKB output second clock signal blanking period with
The cycle phase of sweep phase is same, and dutycycle is identical.That is to say, as shown in Fig. 2 second clock signal end CKB can be in scanning
Stage T1 and blanking period T2 persistently export same clock signal, so as to simplify the control to second clock signal end CKB.
In sum, a kind of shift register cell is embodiments provided, the shift register cell includes
Drop-down module, the drop-down module can carry out noise reduction to pull-up node and outfan under the control of second clock signal.Due to
Duration of the second clock signal of the second clock signal end output in blanking period in the first current potential is more than 0, therefore can
To ensure that the drop-down module persistently can carry out noise reduction to pull-up node and outfan in blanking period, it is ensured that display device it is aobvious
Show effect.
Fig. 5 is a kind of flow chart of the driving method of shift register cell provided in an embodiment of the present invention, and the method can
For driving the shift register cell as shown in Fig. 1, Fig. 3 or Fig. 4, the shift register cell include：Input mould
Block 10, output module 20 and drop-down module 30；With reference to Fig. 4, the method can include：
Step 401, in sweep phase, when input signal end IN output input signal be the first current potential, first control
When first control signal of signal end CN outputs is the first current potential, the input module 10 pulls up node PU and exports first control
Signal, the output module 20 are exported from the first clock signal terminal CK to outfan OUT under the control of pull-up node PU
The first clock signal,
When the reset signal of reset signal end RST outputs is the first current potential, the second of the output of the second control signal end CNB controls
When signal processed is the second current potential, the input module 10 exports second control signal to pull-up node PU,
When the second clock signal of second clock signal end CKB outputs is the first current potential, the drop-down module 30 this
Under the control of two clock signals, the power supply letter from power supply signal end VSS is exported to pull-up node PU and outfan OUT
Number, the power supply signal is in the second current potential.
Step 402, in blanking period, the second clock signal of second clock signal end CKB outputs is in first electric
The duration of position is more than 0, and the drop-down module 30 continues to pull-up node PU and the output under the control of the second clock signal
End OUT exports the power supply signal.
Fig. 6 is a kind of sequential chart of the driving process of shift register cell provided in an embodiment of the present invention, can from Fig. 6
To find out, signal that the second clock signal end CKB is exported in blanking period T2 can with export in sweep phase T1
The cycle phase of signal is same, and dutycycle is identical.Or, the signal that the second clock signal end CKB is exported in blanking period T2
Cycle and dutycycle can also be adjusted according to practical situation, and the embodiment of the present invention is not limited to this.
Further, by taking the shift register cell shown in Fig. 3 as an example, explain in detail the principle of the driving method.The drive
Sweep phase T1 in dynamic method can specifically include：Output stage, reseting stage and noise reduction stage.Wherein, in the output rank
Duan Zhong, input signal end IN output input signal be the first current potential, the 6th transistor M6 open, the first control signal end CN to
Pull-up node PU export the first control signal, first control signal be the first current potential, the 8th transistor M8 open, the first clock
Signal end CK exports the first clock signal to outfan OUT, so as to drive corresponding pixel cell；Simultaneously as the pull-up section
Point PU is the first current potential, and the first transistor M1 is in opening；Outfan OUT be the first current potential, third transistor M3
In opening, power supply signal end VSS is pulled down at node PD outputs by the first transistor M1 and third transistor M3
In the power supply signal of the second current potential so that the 4th transistor M4 and the 5th transistor M5 shut-offs, to avoid the letter to outfan OUT
Number impact.
In the reseting stage, reset signal end RST output reset signal be the first current potential, the second control signal end
CNB pulls up second control signal of the node PU outputs in the second current potential, so as to reset to pull-up node PU, now
8th transistor M8, the first transistor M1 and the shut-off of third transistor M3.
In the noise reduction stage, second clock signal end CKB output second clock signal be the first current potential, the second crystal
Pipe M2 is opened, and second clock signal end CKB pulls down node PD and export the second clock signal so that the 4th transistor M4 and
5th transistor M5 is opened, and power supply signal end VSS pulls up electricity of the node PU and outfan OUT outputs in the second current potential respectively
Source signal, so as to carry out noise reduction to pull-up node PU and outfan OUT.
Further, the shift register cell can enter into blanking period T2, with reference to Fig. 7, in the related, respectively
Individual signal end (including second clock signal end CKB) is the letter in the second current potential in the signal of blanking period T2 outputs
Number.As, in blanking period T2, second clock signal end CKB can not continue to charge to pull-down node PD, therefore such as Fig. 4 institutes
Show, in blanking period T2, need by the first capacitor C1 in the control submodule 301 to maintain pull-down node PD
Current potential, so that drop-down submodule 302 persistently can carry out noise reduction to pull-up node PU and outfan OUT.
But, when the leakage current of the first transistor M1 and third transistor M3 is larger, the current potential of pull-down node PD can drop
It is low.The 4th transistor M4 and the 5th transistor M5 may be caused effectively cannot to open, so as to cannot be to pull-up node PU and output
End OUT carries out effective noise reduction.Further, since the parasitic capacitance between the first clock signal terminal CK and pull-up node PU is larger,
When next frame scan starts, pull-up node PU can couple the waveform of the first clock signal so that the 8th transistor M8 is opened extremely
Open, cause to show abnormal.Due in gate driver circuit, the charging of pull-down node PD of last what shift register cell
Time is shorter, and it is more that the current potential of pull-down node PD of last what shift register cell declines, so display floater
Lower end easily occurs showing abnormal.Example, in Fig. 7, PD1 can be second level shift register cell in gate driver circuit
In pull-down node, PD2 can be the pull-down node in gate driver circuit in penultimate stage shift register cell.From figure
As can be seen that in blanking period T2 in 7, it is more that the current potential of pull-down node PD2 declines, accordingly, display floater lower end with
The corresponding pixel cell of last what shift register cell easily occurs showing abnormal.
And in embodiments of the present invention, with reference to Fig. 6, second clock signal end CKB export in blanking period T2 second
Duration of the clock signal in the first current potential is more than 0, and such as second clock signal can be alternately in the current potential of blanking period T2
For the first current potential and the second current potential.Therefore, when the second clock signal is in the first current potential, pull-down node PD can be entered
Row charges；When the second clock signal is in the second current potential, pull-down node PD can be kept by the first capacitor C1
Current potential.The continuous conversion of the signal potential exported by second clock signal end CKB, constantly can be entered to pull-down node PD
Row charges so that the current potential of pull-down node PD persistently keeps the first current potential in blanking period T2.Accordingly, the 4th is brilliant
Body pipe M4 and the 5th transistor M5 can be always maintained at the state of effective unlatching in blanking period T2, and then on can causing
Node PU and outfan OUT is drawn to be always maintained at the second current potential.That is to say, pull-up node PU and outfan OUT can be carried out
Continue noise reduction, so as to ensure the display effect of display device.Example, as shown in fig. 6, in the driving shown in the embodiment of the present invention
In method, pull-down node PD1 in gate driver circuit in the shift register cell of the second level, and fall in gate driver circuit
Pull-down node PD2 in number second level shift register cell can persistently keep the first current potential in blanking period T2.
It should be noted that in the above-described embodiments, be the with first to the 8th transistor as N-type transistor, and first
Current potential is relative to the explanation carried out as a example by the second current potential high potential.Certainly, first to the 8th transistor can also adopt P
Transistor npn npn, when first to the 8th transistor adopts P-type transistor, first current potential relative to second current potential can be
Electronegative potential, and the potential change of each signal end can (the i.e. phase place of the two contrary with the potential change shown in Fig. 6 or Fig. 7
Difference is 180 degree).
In sum, a kind of driving method of shift register cell is embodiments provided, in blanking period,
Duration of the second clock signal end in the first current potential is more than 0, therefore can enable the drop-down module in blanking period
Noise reduction is carried out to pull-up node and outfan persistently, it is ensured that the display effect of display device.
Fig. 8 is a kind of structural representation of gate driver circuit provided in an embodiment of the present invention, as shown in figure 8, the grid
Drive circuit can include：The shift register cells 00 of at least two cascades, wherein each shift register cell can be
Shift register cell as shown in Fig. 1, Fig. 3 or Fig. 4.
As can be seen from Figure 8, each shift register cell is believed with the first clock signal terminal CK and second clock respectively
Number end CKB connection.With reference to Fig. 6, the first clock signal of first clock signal terminal CK outputs is in first in blanking period
The duration of current potential is more than 0, and the second clock signal of second clock signal end CKB outputs is in the first current potential in blanking period
Duration be more than 0.Also, it can also be seen that first clock signal is identical with the frequency of second clock signal from Fig. 6, phase
Position is contrary.
Additionally, understanding with reference to Fig. 8, the input signal end IN in each shift register cell can be posted with upper level displacement
The outfan OUT connections of storage unit, the reset signal end RST of each shift register cell can be with next stage shift LD
The outfan OUT connections of device unit, and the input signal end IN of the first order shift register cell in the gate driver circuit
It is connected with frame open signal end STV.By the control to first control signal end CN and the second control signal end CNB, can be with
So that each shift register cell in the gate driver circuit realizes the positive and negative bilateral scanning to display device.
For example, the first control signal when the output of the first control signal end CN in the first current potential, the second control signal end
When CNB outputs are in the second control signal of the second current potential, each shift register in the gate driver circuit can be caused
Unit starts to start successively from first order shift register cell, it is possible thereby to realize the forward scan to display device.When
First control signal of the one control signal end CN output in the second current potential, the output of the second control signal end CNB are electric in first
During the second control signal of position, each shift register cell in the gate driver circuit can be caused to shift from afterbody
Register cell starts to start successively, it is possible thereby to realize the reverse scan to display device.
The embodiment of the present invention provides a kind of display device, and the display device can include gate driver circuit, and the grid drives
Galvanic electricity road can be as shown in Figure 8.The display device can be：Liquid crystal panel, Electronic Paper, oled panel, AMOLED panel, handss
Any product with display function such as machine, panel computer, television set, display, notebook computer, DPF, navigator
Or part.
Those skilled in the art can be understood that, for convenience and simplicity of description, the displacement of foregoing description
The specific work process of register cell and gate driver circuit, may be referred to the corresponding process in preceding method embodiment,
This repeats no more.
The foregoing is only presently preferred embodiments of the present invention, not to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.
Claims (10)
1. a kind of shift register cell, it is characterised in that the shift register cell includes：
Input module, output module and drop-down module；
The input module respectively with input signal end, reset signal end, the first control signal end, the second control signal end and on
Node connection is drawn, for controlling in the input signal from the input signal end, from the first of first control signal end
The control of signal processed, the reset signal from the reset signal end and the second control signal from second control signal end
Under system, the current potential of the pull-up node is controlled；
The output module is connected with the first clock signal terminal, the pull-up node and outfan respectively, in the pull-up
Under the control of node, the first clock signal from first clock signal terminal is exported to the outfan；
The drop-down module is connected with second clock signal end, power supply signal end, the pull-up node and the outfan respectively,
For under the control of the second clock signal from the second clock signal end, to the pull-up node and the outfan
Export the power supply signal from the power supply signal end；
Wherein, the second clock signal of second clock signal end output in blanking period in the first current potential when grow up
In 0.
2. shift register cell according to claim 1, it is characterised in that the drop-down module includes：Control submodule
Block and drop-down submodule；
The control submodule respectively with the second clock signal end, the power supply signal end, the pull-up node, described defeated
Go out end and pull-down node connection, in the second clock signal, the power supply signal, the pull-up node and the output
Under the control at end, the current potential of the pull-down node is controlled；
The drop-down submodule respectively with the pull-down node, the power supply signal end, the pull-up node and the outfan
Connection, for, under the control of the pull-down node, exporting the power supply signal to the pull-up node and the outfan.
3. shift register cell according to claim 2, it is characterised in that the control submodule, including：First is brilliant
Body pipe, transistor seconds, third transistor and the first capacitor；
The grid of the first transistor is connected with the pull-up node, and the first pole is connected with the power supply signal end, the second pole
It is connected with the pull-down node；
The grid of the transistor seconds and the first pole are connected with the second clock signal end, the second pole and the pull-down node
Connection；
The grid of the third transistor is connected with the outfan, and the first pole is connected with the power supply signal end, the second pole with
The pull-down node connection；
One end of first capacitor is connected with the pull-down node, and the other end is connected with the power supply signal end.
4. shift register cell according to claim 2, it is characterised in that the drop-down submodule, including：4th is brilliant
Body pipe and the 5th transistor；
The grid of the 4th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the second pole
It is connected with the outfan；
The grid of the 5th transistor is connected with the pull-down node, and the first pole is connected with the power supply signal end, the second pole
It is connected with the pull-up node.
5. shift register cell according to claim 1, it is characterised in that the input module, including：6th crystal
Pipe and the 7th transistor；The output module, including：8th transistor and the second capacitor；
The grid of the 6th transistor is connected with the input signal end, and the first pole is connected with first control signal end,
Second pole is connected with the pull-up node；
The grid of the 7th transistor is connected with the reset signal end, and the first pole is connected with second control signal end,
Second pole is connected with the pull-up node；
The grid of the 8th transistor is connected with the pull-up node, and the first pole is connected with first clock signal terminal, the
Two poles are connected with the outfan；
One end of second capacitor is connected with the pull-up node, and the other end is connected with the outfan.
6. according to the arbitrary described shift register cell of claim 1 to 5, it is characterised in that
The second clock signal of the second clock signal end output same, duty in blanking period and in the cycle phase of sweep phase
Than identical.
7. a kind of driving method of shift register cell, it is characterised in that the shift register cell includes：Input mould
Block, output module and drop-down module；Methods described includes：Sweep phase and blanking period；
In the sweep phase, when input signal end output input signal be the first current potential, the first control signal end output
The first control signal when being the first current potential, the input module pulls up node and exports first control signal, described defeated
Go out module under the control of the pull-up node, the first clock letter from the first clock signal terminal is exported to the outfan
Number,
When the reset signal of reset signal end output is the first current potential, the second control signal of the second control signal end output is the
During two current potentials, the input module exports second control signal to the pull-up node,
When the second clock signal of second clock signal end output is the first current potential, the drop-down module is in the second clock
Under the control of signal, the power supply signal from power supply signal end, the power supply are exported to the pull-up node and the outfan
Signal is in the second current potential；
In the blanking period, the second clock signal of second clock signal end output in the first current potential when grow up
In 0, the drop-down module under the control of the second clock signal continues to the pull-up node and the outfan to export
The power supply signal.
8. method according to claim 7, it is characterised in that
The second clock signal of the second clock signal end output is in the blanking period and the cycle in the sweep phase
Identical, dutycycle is identical.
9. a kind of gate driver circuit, it is characterised in that the gate driver circuit includes：
The shift register cell as described in claim 1 to 6 is arbitrary of at least two cascades；
Wherein, each shift register cell is connected with the first clock signal terminal and second clock signal end respectively, and described first
Duration of first clock signal of clock signal terminal output in blanking period in the first current potential is more than 0, the second clock
Duration of the second clock signal of signal end output in blanking period in the first current potential is more than 0.
10. a kind of display device, it is characterised in that the display device includes：Raster data model electricity as claimed in claim 9
Road.
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