CN108648715B - Shift register, display panel, and shift register driving method - Google Patents
Shift register, display panel, and shift register driving method Download PDFInfo
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- CN108648715B CN108648715B CN201810784529.5A CN201810784529A CN108648715B CN 108648715 B CN108648715 B CN 108648715B CN 201810784529 A CN201810784529 A CN 201810784529A CN 108648715 B CN108648715 B CN 108648715B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract
The invention discloses a shift register, a display panel and a driving method of the shift register, wherein the shift register in the display panel comprises a control module and a pull-down maintaining module, the pull-down maintaining module further comprises a high-frequency signal combination circuit, the high-frequency signal combination circuit comprises a first switch, a second switch and a third switch, the control end of the first switch is electrically coupled with a clock signal, the first end of the first switch is electrically coupled with a clock signal of a previous stage, the control end of the second switch is electrically coupled with a working point voltage signal, the first end of the second switch is electrically coupled with the second end of the first switch, the control end of the third switch is electrically coupled with the second end of the second switch, the first end of the third switch is electrically coupled with the working point voltage signal, and the second end of the third switch is electrically coupled with a low preset potential. Therefore, the high-frequency signal combination circuit can remove ripple signals generated by clock signals and avoid misoperation of a grid circuit.
Description
Technical Field
The present invention relates to a display panel, and more particularly, to a shift register of a display panel and a driving method for eliminating ripple of a high frequency signal combining circuit in the shift register.
Background
In order to save cost, the display panel industry such as liquid crystal display panels has widely adopted the Gate Driver on Array (GOA) technology. The conventional lcd panel technology relies on a source driver chip (source IC) for transmitting signals by controlling voltages and a Gate driver chip (Gate IC) for controlling and determining the amount of light transmission by using transistors as switches.
The array substrate type driving technology is to abandon the traditional grid driving chip and replace the traditional grid driving chip with a grid driving circuit structure directly manufactured on a glass substrate of a liquid crystal display panel, and because the grid driving circuit structure utilizes an exposure and development mode to generate a plurality of logic circuits related to a shift register at the edge of the glass substrate, the aim of reducing the cost can be achieved no matter the material or the manufacturing process, and the effect of reducing the frame of the liquid crystal display can be achieved.
The principle of the array substrate type driving technique is developed based on a thompson circuit, and in order to achieve a smooth driving effect, pre-charging is usually performed at a working point (referred to as a "quick point") to achieve a voltage level of a higher level, so that a gate scanning signal required by a gate line can be smoothly transmitted when a switch of a transistor is turned on.
However, the clock signal is a periodic signal, and when the gate scan signal is not required to be generated, a ripple (ripple) signal is generated due to the operating point voltage signal coupled to the operating point, which causes a very short malfunction of the gate line.
Therefore, it is one of the problems to be solved by those skilled in the art how to remove the ripple signal generated by the clock signal to prevent the gate line from generating malfunction.
Disclosure of Invention
The invention provides a shift register, a display panel and a driving method of the shift register, which can effectively remove ripple signals generated by clock signals, thereby avoiding false operation of a grid circuit.
An embodiment of the present invention provides a shift register, which is a Gate driving circuit structure, and is used for a Gate Driver on Array (GOA) display panel, such as a liquid crystal display panel, where the liquid crystal display panel has a plurality of n cascaded shift registers, n is a positive integer greater than 2, the nth shift register receives an nth-1 Gate signal of a previous stage to transmit a Gate scanning signal Gn of the previous stage to a Gate line, and the shift register has an operating point voltage signal Qn of the previous stage. The shift register comprises a pull-down maintaining module and a control module.
The control module is electrically coupled to the pull-down maintaining module and is used for generating a correct time sequence to control the pull-down maintaining module. The pull-down maintaining module is electrically coupled to a low preset potential and is used for eliminating noise of a working point voltage in the shift register, and the pull-down maintaining module further comprises a high-frequency signal combination circuit. The high frequency signal combining circuit includes a first switch, a second switch, and a third switch.
The control terminal of the first switch is electrically coupled to one of the clock signal CKn-1 of the previous stage and the clock signal CKn of the previous stage, and the first terminal of the first switch is electrically coupled to the other of the clock signal CKn-1 and the clock signal CKn.
The control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
The control end of the third switch is electrically coupled to the second end of the second switch, the first end of the third switch is electrically coupled to the operating point voltage signal Qn, and the second end of the third switch is electrically coupled to the low predetermined voltage Vss.
The control terminal of the first switch may be electrically coupled to the clock signal CKn, and the first terminal of the first switch may be electrically coupled to the clock signal CKn-1. Therefore, the shift register is provided with a high-frequency signal combination circuit, so that ripple signals generated by the clock signal CKn can be effectively removed, and misoperation of a grid circuit can be avoided.
It should be noted that the first switch may be a first transistor, the second switch may be a second transistor, and the third switch may be a third transistor.
In this embodiment, the shift register may further include an input module, an output module, and a feedback module.
The input module is used for receiving the gate signal of the (n-1) th stage and generating the working point voltage of the shift register according to the gate signal of the (n-1) th stage.
The output module is configured to receive a clock signal CKn and a working point voltage for precharging the shift register to become a precharge level, couple the precharge level to the working point voltage signal Qn according to the clock signal CKn, and output a gate scan signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module is used for receiving a feedback signal and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
Another embodiment of the present invention provides a display panel and a high frequency signal combining circuit used in the display panel, the high frequency signal combining circuit being used for a liquid crystal display panel of an array substrate type driving technology, the liquid crystal display panel having n cascaded shift registers, n being a positive integer greater than 2, the nth shift register receiving a gate signal of an n-1 th stage to transmit a gate scanning signal Gn through a gate line, wherein the shift register has an operating point voltage signal Qn.
The pull-down maintaining module in the shift register is provided with the high-frequency signal combination circuit and is used for eliminating noise of the working point voltage of the shift register. The high frequency signal combining circuit includes a first switch, a second switch, and a third switch.
The control terminal of the first switch is electrically coupled to one of the clock signal CKn-1 and the clock signal CKn, and the first terminal of the first switch is electrically coupled to the other of the clock signal CKn-1 and the clock signal CKn.
The control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
The control end of the third switch is electrically coupled to the second end of the second switch, the first end of the third switch is electrically coupled to the operating point voltage signal Qn, and the second end of the third switch is electrically coupled to the low predetermined voltage Vss.
Further, the control terminal of the first switch may be electrically coupled to the clock signal CKn, and the first terminal of the first switch may be electrically coupled to the clock signal CKn-1. Therefore, the shift register is provided with a high-frequency signal combination circuit, so that ripple signals generated by the clock signal CKn can be effectively removed, and misoperation of a grid circuit can be avoided.
In addition, the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
In this embodiment, the shift register may further include a control module, an input module, an output module, and a feedback module.
The control module is electrically coupled to the pull-down maintaining module and is used for generating a correct time sequence to control the pull-down maintaining module.
The input module is used for receiving the gate signal of the (n-1) th stage and generating the working point voltage of the shift register according to the gate signal of the (n-1) th stage.
The output module is configured to receive a clock signal CKn and a working point voltage for precharging the shift register to become a precharge level, couple the precharge level to the working point voltage signal Qn according to the clock signal CKn, and output a gate scan signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module is used for receiving a feedback signal and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
In addition, another embodiment of the present invention provides a driving method for eliminating ripples, which is used for a liquid crystal display panel of an array substrate type driving technology, wherein the liquid crystal display panel has n cascaded shift registers, and n is a positive integer greater than 2. The driving method includes the steps of:
the nth shift register receives the gate signal of the (n-1) th stage to transmit the gate scanning signal Gn through the gate line, and has an operating point voltage signal Qn. The pull-down maintaining module in the shift register is provided with the high-frequency signal combination circuit, and the high-frequency signal combination circuit comprises a first switch, a second switch and a third switch;
transmitting a clock signal CKn-1 to a first terminal of the first switch;
transmitting a clock signal CKn to a control terminal of the first switch, wherein a first terminal of the second switch is electrically coupled to a second terminal of the first switch;
transmitting the operating point voltage signal Qn to the control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and
and transmitting the operating point voltage signal Qn to a first end of the third switch, wherein a second end of the third switch is electrically coupled to a low predetermined potential Vss, and the low predetermined potential Vss pulls down the operating point voltage signal Qn.
Further, as the driving method, the nth shift register receives the gate signal of the (n-1) th stage to transmit the gate scanning signal Gn through the gate line, wherein the shift register has the operating point voltage signal Qn. According to the above steps, the driving method further includes the steps of:
receiving the gate signal of the (n-1) th level, and generating the working point voltage of the shift register according to the gate signal of the (n-1) th level;
maintaining the working point voltage of the shift register at a low preset potential;
the shift register is used for receiving a clock signal CKn and pre-charging a working point voltage of the shift register into a pre-charging potential, and coupling the pre-charging potential into a working point voltage signal Qn according to the clock signal CKn;
outputting the gate scanning signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn; and
receiving a feedback signal, and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
Therefore, the shift register, the display panel and the driving method of the shift register in the embodiment of the invention can effectively remove ripple signals generated by clock signals CKn and can avoid misoperation of a grid line by adding a high-frequency signal combination circuit in the shift register.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following detailed description will be given with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a liquid crystal display panel with a shift register according to the present invention.
FIG. 2A is a functional relationship diagram of the shift register of the present invention.
FIG. 2B is a diagram of an embodiment of a shift register of the present invention.
Fig. 3 is a circuit diagram of the high frequency signal combining circuit of the present invention.
FIG. 4 is a waveform diagram illustrating levels of various signals according to the present invention.
Fig. 5 is a flowchart of a driving method performed by the high frequency signal combining circuit of the present invention.
FIG. 6 is a flow chart of a driving method for a shift register according to the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the positional or orientational relationships indicated in the drawings to facilitate the description of the invention and to simplify the description, and are not intended to indicate or imply that the device or component being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1, fig. 1 is a schematic diagram of a liquid crystal display panel 10 in which a shift register 30 of the present invention is located. An embodiment of the invention provides a shift register 30 for a Gate Driver on Array (GOA) display panel, such as a liquid crystal display panel 10, and the following description will take the liquid crystal display panel 10 as an example. The liquid crystal display panel 10 has a plurality of n cascaded shift registers 30, n is a positive integer greater than 2, the nth shift register 30 receives the (n-1) th gate signal of the previous stage to transmit the gate scanning signal Gn of the stage to the gate line 32, wherein the operating point of the shift register 30 has the operating point voltage signal Qn of the stage.
In the figure, the liquid crystal display panel 10 still has the source driver chips 12, and the array substrate type driving technique omits the gate driver chips, and instead, as shown in the figure, a plurality of shift registers 30 are directly disposed on the glass substrate as circuits for driving the gate lines 32. Each shift register 30 receives a gate signal of a previous stage to transmit a gate scan signal through a gate line 32.
Referring to fig. 2A and fig. 2B, fig. 2A is a functional correlation diagram of the shift register 30 according to the present invention. FIG. 2B is a diagram of an embodiment of a shift register 30 according to the present invention. In the embodiment, the nth shift register 30 is illustrated, wherein the nth shift register 30 includes a pull-down maintaining module 58, a control module 56, an input module 50, an output module 52, and a feedback module 54.
The shift register 30 receives the previous stage gate signal and the clock signal CKn to generate the desired operating point voltage signal Qn and the gate scan signal Gn. However, the clock signal CKn is a periodic signal, and when the gate scan signal Gn is not needed to be output, the clock signal CKn is also coupled to the operating point voltage signal, which may cause a ripple signal, so that the gate line 32 may malfunction.
Therefore, a high frequency signal combination circuit 5802 is added to the pull-down maintaining module 58 to solve this problem. The pull-down maintaining module 58 is electrically coupled to a low predetermined voltage Vss for eliminating noise of the operating point voltage of the shift register 30. The high frequency signal combination circuit 5802 can effectively remove the ripple signal generated by the clock signal CKn, thereby preventing the gate line 32 from generating malfunction.
The control module 56 is electrically coupled to the low predetermined voltage Vss and electrically coupled to the pull-down maintaining module 58 for generating a correct timing to control the pull-down maintaining module 58.
The input module 50 is configured to receive the gate signal of the (n-1) th stage, and generate an operating point voltage of the shift register 30 according to the gate signal of the (n-1) th stage.
The output module 52 is configured to receive a clock signal CKn and a working point voltage for precharging the shift register circuit (shift register) to a precharge level, couple the precharge level to a working point voltage signal Qn according to the clock signal CKn, and output a gate scanning signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module 54 is configured to receive a feedback signal Gn +, and pull down the potentials of the operating point voltage signal Qn and the gate scan signal Gn to a low preset potential according to the feedback signal Gn +.
Further, referring to the embodiment of fig. 2B, as an embodiment of a 6CK clock signal, in order to generate the gate scan signal G3 for the 3 rd gate line 32, the input module 50 has a transistor switch, and generates the operating point voltage required by the shift register 30 for the operating point of the shift register 30 after receiving the gate signal F2.
The output module 52 includes two transistor switches, the control terminal of the left transistor switch pre-charges the operating point voltage of the operating point of the shift register 30 to a pre-charge level and couples the pre-charge level to the operating point voltage signal Q3 according to the clock signal CK3, the first terminal of the transistor switch receives the clock signal CK3, and the second terminal of the transistor switch generates the gate signal F3 required to activate the post-stage shift register 30 and the gate line 32.
The control terminal of the right transistor switch receives the operating point voltage signal Q3, the control terminal of the transistor switch receives the clock signal CK3 according to the operating point voltage signal Q3, and the first terminal of the transistor switch outputs a gate scan signal G3 to the gate line 32 from the second terminal.
The feedback module 54 also includes two transistor switches, control terminals of which are coupled to the gate scan signal G7 of the next stage, the gate scan signal G7 is used as the feedback signal G7 for terminating the gate scan signal G3. The second terminals of the two transistor switches are coupled to the low predetermined potential Vss, and when the left transistor switch receives the gate scan signal G7 of the next stage, the potentials of the operating point voltage signal Q3 and the gate scan signal G3 are respectively pulled down to the low predetermined potential Vss according to the feedback signal G7, thereby terminating the gate line 32.
Fig. 3 is a circuit diagram of the high frequency signal combining circuit 5802 of the present invention. The high frequency signal combining circuit 5802 includes a first switch 40, a second switch 42, and a third switch 44.
The control terminal 40G of the first switch 40 is electrically coupled to one of the clock signal CKn-1 of the previous stage and the clock signal CKn of the previous stage, and the first terminal 40D of the first switch 40 is electrically coupled to the other of the clock signal CKn-1 and the clock signal CKn.
In the embodiment of the 6CK clock signal, the high frequency signal combining circuit 5802 of the 3 rd shift register 30 is illustrated, wherein the control terminal 40G of the first switch 40 is electrically coupled to the clock signal CK3, and the first terminal 40D of the first switch 40 is electrically coupled to the clock signal CK 2. When the clock signal CK3 passes through the control terminal 40G to open the first switch 40, the pull-down signal PQ3 of the intersection of the clock signal CK3 and the clock signal CK2 is transmitted to the second terminal 40S of the first switch 40.
The control terminal 42G of the second switch 42 is electrically coupled to the operating point voltage signal Q3, and the first terminal 42D of the second switch 42 is electrically coupled to the second terminal of the first switch 40. Therefore, when the operating point voltage signal Q3 turns on the second switch 42 through the control terminal 42G, the pull-down signal PQ3 is transmitted to the second terminal 42S of the second switch 42.
The control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, the first terminal 44D of the third switch 44 is electrically coupled to the operating point voltage signal Q3, and the second terminal 44S of the third switch 44 is electrically coupled to the low predetermined potential Vss.
Therefore, when the pull-down signal PQ3 turns on the third switch 44 through the control terminal 44G, the low predetermined voltage Vss at the second terminal 44S will pull down the operating point voltage signal Q3 at the first terminal 44D.
Therefore, when the ripple signal occurs in the operating point voltage signal Q3, the second switch 42 is turned on, so that the pull-down signal PQ3 turns on the third switch 44, and the operating point voltage signal Q3 is pulled down to the low predetermined level Vss, thereby eliminating the ripple signal.
Note that the first switch 40 is a first transistor, the second switch 42 is a second transistor, and the third switch 44 is a third transistor.
Referring to fig. 4, fig. 4 is a waveform diagram illustrating levels of various signals according to the present invention. Each signal has different levels, i.e. the voltage value of the high level can represent a valid signal. The figure still shows an embodiment of a 6CK clock signal, which is CK1, CK2, CK3, CK4, CK5, and CK6, and the waveforms are shown in time sequence.
The operating point voltage signal Q3 is coupled to the clock signal CK3 by precharging to form an ideal waveform, so as to pull up the clock signal CK3 to a high voltage level, effectively turn on the transistor switch, and enable the gate scan signal G3 to be transmitted to the gate line 32.
In order to effectively pull down the ripple signal Ri when the operating point voltage signal Q3 generates the ripple signal Ri, the high frequency signal combination circuit 5802 generates the pull-down signal PQ3 formed by the intersection of the clock signal CK2 and the clock signal CK3, so as to effectively and rapidly pull down the ripple signal Ri of the operating point voltage signal Q3 to the low predetermined voltage Vss, thereby reducing the noise.
In addition, according to the above illustration, another embodiment of the present invention provides a display panel, such as the liquid crystal display panel 10, and the high frequency signal combining circuit 5802 in the display panel, wherein the high frequency signal combining circuit 5802 is used for the liquid crystal display panel 10 of the array substrate type driving technology. The liquid crystal display panel 10 has n cascaded shift registers 30 and a gate line 32 electrically coupled to the shift registers 30, where n is a positive integer greater than 2, the nth shift register 30 receives a gate signal of an (n-1) th stage to transmit a gate scanning signal Gn through the gate line 32, and the shift register 30 has a working point voltage signal Qn. The pull-down maintaining module 58 in the shift register 30 has the high frequency signal combining circuit 5802, and the pull-down maintaining module 58 is used for eliminating noise of the operating point voltage of the shift register 30.
The high frequency signal combining circuit 5802 further includes a first switch 40, a second switch 42, and a third switch 44.
The control terminal of the first switch 40 is electrically coupled to one of the clock signal CKn-1 and the clock signal CKn, and the first terminal of the first switch 40 is electrically coupled to the other of the clock signal CKn-1 and the clock signal CKn.
The control terminal of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch 42 is electrically coupled to the second terminal of the first switch 40.
A control terminal of the third switch 44 is electrically coupled to the second terminal of the second switch 42, a first terminal of the third switch 44 is electrically coupled to the operating point voltage signal Qn, and a second terminal of the third switch 44 is electrically coupled to the low predetermined potential Vss.
The high frequency signal combination circuit 5802 is disposed in the pull-down maintaining module 58, and is capable of generating a pull-down signal PQ3 formed by intersecting the clock signal CK2 with the clock signal CK3, and the pull-down signal PQ3 is capable of effectively removing a ripple signal Ri generated by the clock signal CK3 in the operating point voltage signal Qn, thereby preventing the gate line 32 from generating a malfunction.
As in the high frequency signal combining circuit 5802, the control terminal of the first switch 40 may be electrically coupled to the clock signal CKn, and the first terminal of the first switch 40 may be electrically coupled to the clock signal CKn-1.
Note that the first switch 40 is a first transistor, the second switch 42 is a second transistor, and the third switch 44 is a third transistor.
Further, the shift register 30 may further include a control module 56, an input module 50, an output module 52, and a feedback module 54.
The control module 56 is electrically coupled to the pull-down maintaining module 58, and is used for generating a timing sequence to control the pull-down maintaining module 58.
The input module 50 is configured to receive the gate signal of the (n-1) th stage, and generate an operating point voltage of the shift register 30 according to the gate signal of the (n-1) th stage.
The output module 52 is configured to receive a clock signal CKn and a working point voltage for precharging the shift register circuit (shift register) to a precharge level, couple the precharge level to a working point voltage signal Qn according to the clock signal CKn, and output a gate scanning signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module 54 is configured to receive a feedback signal and pull down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
Referring to fig. 5, fig. 5 is a flowchart illustrating a driving method performed by the high-frequency signal combining circuit 5802 according to the present invention. Another embodiment of the present invention provides a driving method of a shift register, which is used for a liquid crystal display panel 10 of an array substrate type driving technology, wherein the liquid crystal display panel 10 has n cascaded shift registers 30, and n is a positive integer greater than 2. The driving method includes the steps of:
step one (S01): the nth shift register 30 receives the gate signal of the (n-1) th stage to transmit the gate scan signal Gn through the gate line 32, and the shift register 30 has an operating point voltage signal Qn. The pull-down maintaining module 58 in the shift register 30 has the high frequency signal combining circuit 5802, and the high frequency signal combining circuit 5802 includes a first switch 40, a second switch 42, and a third switch 44.
Step two (S02): the clock signal CKn-1 is transmitted to the first terminal 40D of the first switch 40.
Step three (S03): it is determined whether the control terminal 40G of the first switch 40 receives the clock signal CKn. When the third step (S03) is yes, the pull-down signal PQ3 formed by the intersection of the clock signal CK2 and the clock signal CK3 is transmitted to the first end 42D of the second switch 42, and the fifth step (S05) is performed.
Step four (S04): the operating point voltage signal Qn is transmitted to the first terminal 44D of the third switch 44, wherein the control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, and the second terminal 44S of the third switch 44 is electrically coupled to the low predetermined potential Vss.
Step five (S05): it is determined whether the control terminal 42G of the second switch 42 receives the operating point voltage signal Qn. If the step five (S05) is yes, the pull-down signal PQ3 is transmitted to the second terminal 42S of the second switch 42, and the step six (S06) is performed in cooperation with the step four (S04).
In step six (S06), the pull-down signal PQ3 turns on the control terminal 44G of the third switch 44 and pulls down the operating point voltage signal Qn of the first terminal 44D to the low predetermined voltage Vss. Therefore, the ripple signal Ri of the operating point voltage signal Qn is pulled down by the low predetermined potential Vss, thereby removing the noise of the gate scanning signal Gn.
Referring to fig. 6, fig. 6 is a flowchart illustrating a driving method of the shift register 30 according to the present invention. As mentioned above, the nth shift register 30 in fig. 5 receives the gate signal of the (n-1) th stage to transmit the gate scanning signal Gn through the gate line 32, wherein the shift register 30 has the operating point voltage signal Qn. According to the foregoing, the driving method further comprises the steps of:
in the first step (S11), the gate signal of the (n-1) th stage is received, and the operating point voltage of the shift register 30 is generated based on the gate signal of the (n-1) th stage.
And a second step (S12) of maintaining the operating point voltage of the shift register 30 at a low predetermined potential.
And a third step (S13) for receiving the clock signal CKn and precharging the working point voltage of the shift register 30 to the precharge level, and coupling the precharge level to the working point voltage signal Qn according to the clock signal CKn.
And a fourth step (S14) of outputting the gate scanning signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.
The above-mentioned step one (S11), step one (S12), step one (S13), and step one (S14) describe in detail how step one (S01) of the example of fig. 5 is performed.
Next, step two (S02), step three (S03), step four (S04), step five (S05), and step six (S06) in the example of fig. 5 are performed. Subsequently, step one of fig. 6 is performed (S15): and receiving a feedback signal, and pulling down the potential of the working point voltage signal Qn or the grid scanning signal Gn to a low preset potential according to the feedback signal.
In summary, the shift register 30, the display panel and the driving method of the shift register according to the embodiment of the invention utilize the high frequency signal combination circuit 5802 additionally arranged in the shift register 30, so as to effectively remove the ripple signal generated by the operating point voltage signal Qn and prevent the gate line 32 from generating a malfunction.
Although the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A shift register for a display panel of an array substrate type driving technology, the display panel having a plurality of cascaded shift registers receiving a gate signal of a previous stage to transmit a gate scan signal to a gate line, wherein the shift register has an operating point voltage signal, the shift register comprising:
a pull-down maintaining module electrically coupled to the low predetermined voltage level for eliminating noise of the operating point voltage of the shift register, the pull-down maintaining module further comprising:
a high frequency signal combination circuit, including a first switch, a second switch, and a third switch, wherein a control terminal of the first switch is electrically coupled to a previous clock signal and one of the previous clock signals, a first terminal of the first switch is electrically coupled to the previous clock signal and the other of the previous clock signals, a control terminal of the second switch is electrically coupled to the operating point voltage signal, a first terminal of the second switch is electrically coupled to a second terminal of the first switch, a control terminal of the third switch is electrically coupled to a second terminal of the second switch, a first terminal of the third switch is electrically coupled to the operating point voltage signal, and a second terminal of the third switch is electrically coupled to a low preset potential; and
and the control module is electrically coupled with the pull-down maintaining module and used for generating a time sequence to control the pull-down maintaining module.
2. The shift register as claimed in claim 1, wherein the control terminal of the first switch is electrically coupled to the clock signal of the stage, and the first terminal of the first switch is electrically coupled to the clock signal of the previous stage.
3. The shift register of claim 1, further comprising:
the input module is used for receiving the grid signal of the previous stage and generating the working point voltage of the shift register according to the grid signal of the previous stage;
the output module is used for receiving a clock signal and pre-charging the working point voltage of the shift register into a pre-charging potential, coupling the pre-charging potential into the working point voltage signal according to the clock signal, and outputting a grid scanning signal according to the coupled working point voltage signal and the clock signal;
and the feedback module is used for receiving a feedback signal and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
4. The shift register of claim 1, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
5. A display panel for an array substrate type driving technique, the display panel comprising:
a plurality of gate lines; and
a plurality of cascaded shift registers, the shift registers being electrically coupled to the gate lines, the shift registers receiving a gate signal of a previous stage to transmit a gate scan signal to the gate lines, wherein the shift registers have operating point voltage signals, the shift registers including a pull-down maintaining module, the pull-down maintaining module being configured to eliminate noise of the operating point voltage of the shift registers, the pull-down maintaining module including:
a high frequency signal combining circuit, the high frequency signal combining circuit comprising:
a first switch, a control terminal of the first switch being electrically coupled to one of the clock signal of the previous stage and the clock signal of the previous stage, a first terminal of the first switch being electrically coupled to the other of the clock signal of the previous stage and the clock signal of the previous stage,
a second switch having a control terminal electrically coupled to the operating point voltage signal, a first terminal electrically coupled to the second terminal of the first switch, and
a control terminal of the third switch is electrically coupled to the second terminal of the second switch, a first terminal of the third switch is electrically coupled to the operating point voltage signal, and a second terminal of the third switch is electrically coupled to the low predetermined potential.
6. The display panel of claim 5, wherein the control terminal of the first switch is electrically coupled to the clock signal of the first stage, and the first terminal of the first switch is electrically coupled to the clock signal of the previous stage.
7. The display panel of claim 5, wherein the shift register further comprises:
the control module is electrically coupled with the pull-down maintaining module and used for generating a time sequence to control the pull-down maintaining module;
the input module is used for receiving the grid signal of the previous stage and generating the working point voltage of the shift register according to the grid signal of the previous stage;
the output module is used for receiving a clock signal and pre-charging the working point voltage of the shift register into a pre-charging potential, coupling the pre-charging potential into the working point voltage signal according to the clock signal, and outputting a grid scanning signal according to the coupled working point voltage signal and the clock signal;
and the feedback module is used for receiving a feedback signal and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
8. The display panel according to claim 5, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
9. A driving method of a shift register, the driving method being used for a display panel of an array substrate type driving technique, the display panel having a plurality of cascaded shift registers, the driving method comprising the steps of:
the shift register receives a grid signal of a previous stage to transmit a grid scanning signal through a grid line, and is provided with a working point voltage signal, wherein a pull-down maintaining module in the shift register is provided with a high-frequency signal combination circuit, and the high-frequency signal combination circuit comprises a first switch, a second switch and a third switch;
transmitting a clock signal of a previous stage to a first end of the first switch;
transmitting the clock signal of the stage to the control terminal of the first switch, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch;
transmitting the operating point voltage signal to a control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and
and transmitting the operating point voltage signal to a first end of the third switch, wherein a second end of the third switch is electrically coupled to a low preset potential, and the low preset potential pulls down the operating point voltage signal.
10. The driving method as claimed in claim 9, wherein the shift register receives a gate signal of a previous stage to transmit a gate scan signal through a gate line, wherein the shift register has an operating point voltage signal, the driving method further comprising the steps of:
receiving a grid signal of a previous stage, and generating a working point voltage of the shift register according to the grid signal of the previous stage;
maintaining the working point voltage of the shift register at a low preset potential;
the shift register is used for receiving a clock signal and pre-charging a working point voltage of the shift register into a pre-charging potential, and coupling the pre-charging potential into the working point voltage signal according to the clock signal;
outputting the grid scanning signal according to the coupled working point voltage signal and the clock signal; and
and receiving a feedback signal, and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
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| CN201810784529.5A CN108648715B (en) | 2018-07-17 | 2018-07-17 | Shift register, display panel, and shift register driving method |
| PCT/CN2018/105075 WO2020015095A1 (en) | 2018-07-17 | 2018-09-11 | Shift register, display panel, and method for driving shift register |
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| CN201810784529.5A CN108648715B (en) | 2018-07-17 | 2018-07-17 | Shift register, display panel, and shift register driving method |
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| CN109300445B (en) * | 2018-12-05 | 2021-11-30 | 惠科股份有限公司 | Array substrate row driving circuit and display device |
| CN109389957A (en) * | 2018-12-05 | 2019-02-26 | 惠科股份有限公司 | Array substrate horizontal drive circuit and display device |
| CN114067759B (en) * | 2020-07-31 | 2022-12-23 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
| CN113257202B (en) * | 2021-04-30 | 2022-04-19 | 北海惠科光电技术有限公司 | Gate drive circuit and drive method of display panel and display device |
| CN113421516A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and display panel |
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| WO2020015095A1 (en) | 2020-01-23 |
| CN108648715A (en) | 2018-10-12 |
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