CN108922485B - Gate drive circuit structure, display panel and drive method of gate drive circuit structure - Google Patents
Gate drive circuit structure, display panel and drive method of gate drive circuit structure Download PDFInfo
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- CN108922485B CN108922485B CN201810785645.9A CN201810785645A CN108922485B CN 108922485 B CN108922485 B CN 108922485B CN 201810785645 A CN201810785645 A CN 201810785645A CN 108922485 B CN108922485 B CN 108922485B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a grid driving circuit structure, a display panel and a driving method of the grid driving circuit structure, which are used for the display panel of the array substrate type driving technology.A sub pull-down circuit is additionally arranged in a shift register, and is electrically coupled with a grid line and comprises a first switch, a second switch and a third switch, wherein the control end of the first switch can be electrically coupled with the clock signal of the front stage and the clock signal of the rear stage, the control end of the second switch is electrically coupled with a working point voltage signal, the first end of the second switch is electrically coupled with the second end of the first switch, the control end of the third switch is electrically coupled with the second end of the second switch, the first end of the third switch is electrically coupled with a grid scanning signal, and the second end of the third switch is electrically coupled with a low preset potential. Therefore, the sub pull-down circuit can effectively pull down the grid scanning signal, reduce the error-proof charging time and increase the charging time.
Description
Technical Field
The present invention relates to a display panel, and more particularly, to a gate driving circuit structure in a display panel and a driving method of the gate driving circuit structure.
Background
In order to save cost, the display panel industry such as liquid crystal display panels has widely adopted the Gate Driver on Array (GOA) technology. The technology of the liquid crystal display panel relies on a Source driver chip (Source IC) for transmitting a signal by controlling a voltage and a Gate driver chip (Gate IC) for controlling and determining a light transmission amount by using a transistor as a switch.
The array substrate type driving technology is to abandon a gate driving chip and replace the gate driving circuit structure with a gate driving chip directly manufactured on a glass substrate of a liquid crystal display panel, and because the gate driving circuit structure utilizes an exposure and development mode to generate a logic circuit on the edge of the glass substrate, the effect of reducing the cost can be achieved no matter the material or the manufacturing process, and the effect of reducing the frame of the liquid crystal display can be achieved.
The principle of the array substrate type driving technique is developed based on Thompson (Thompson) circuits, and in order to achieve a smooth driving effect, pre-charging is usually performed at a working point (quadrature point) to achieve a higher level voltage level, so that a subsequent voltage level can be coupled with a clock signal to form an ideal signal waveform, and thus, when a switch of a transistor is turned on, a gate scanning signal required by a gate line can be smoothly transmitted.
In addition, for the charging time of a pixel unit in the lcd panel, a wrong charging prevention time (gate Tf) is set to lower the high voltage level at the end of the signal, and the smaller the wrong charging prevention time is, the better the wrong charging prevention time is.
Therefore, it is one of the problems to be solved by those skilled in the art how to reduce the error-proof charging time as much as possible when the gate scan signal is pulled down, so as to increase the charging time.
Disclosure of Invention
The invention provides a grid driving circuit structure, a display panel and a driving method of the grid driving circuit structure, which can effectively pull down grid scanning signals, reduce the mis-charging prevention time and further increase the charging time.
An embodiment of the invention provides a gate driving circuit structure for a gate driver on Array (GOA) display panel. The gate driving circuit structure includes a plurality of cascaded shift registers (shift registers) such as n.
N of the n cascaded shift registers is a positive integer greater than 2. The nth shift register is described, and the shift register includes a shift register circuit and a sub pull-down circuit.
The shift register circuit receives a gate signal of a previous stage, such as an n-1 th stage, to transmit a gate scan signal Gn of the stage through a gate line, wherein an operating point of the shift register circuit has an operating point voltage signal Qn of the stage.
The sub pull-down circuit is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch.
The control end of the first switch is electrically coupled to one of the clock signal CKn-2 of the previous stage and the clock signal CKn +1 of the next stage, and the first end of the first switch is electrically coupled to the other of the clock signal CKn-2 and the clock signal CKn + 1.
The control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
A control terminal of the third switch is electrically coupled to the second terminal of the second switch, a first terminal of the third switch is electrically coupled to the gate scan signal Gn, and a second terminal of the third switch is electrically coupled to the low predetermined potential Vss.
To further illustrate, in one embodiment, the control terminal of the first switch may be electrically coupled to the clock signal CKn-2, and the first terminal of the first switch may be electrically coupled to the clock signal CKn + 1.
In the foregoing embodiments, the shift register circuit may further include an input module, an output module, and a feedback module.
The input module is used for receiving the grid signal of the (n-1) th level and generating the working point voltage of the shift temporary storage circuit according to the grid signal of the (n-1) th level.
The output module is configured to receive a clock signal CKn and a working point voltage for precharging the shift register circuit to a precharge level, couple the precharge level to the working point voltage signal Qn according to the clock signal CKn, and output a gate scan signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module is used for receiving a feedback signal and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
Furthermore, the shift register circuit may further include a control module and a pull-down maintaining module.
The control module is electrically coupled to the low preset potential. The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the working point voltage of the shift register circuit at the low preset potential.
In addition, as in the foregoing gate driving circuit structure, the first switch may be a first transistor, the second switch may be a second transistor, and the third switch may be a third transistor.
Another embodiment of the present invention provides a display panel and a shift register in the display panel, wherein the shift register is used for a display panel of an array substrate type driving technology, the display panel has n cascaded shift registers, and n is a positive integer greater than 2.
The shift register circuit of the nth shift register is used for receiving the gate signal of the (n-1) th stage so as to transmit the gate scanning signal Gn through a gate line. The shift register circuit has a working point voltage signal Qn. The shift register comprises a shift register circuit and a sub pull-down circuit.
The sub pull-down circuit of the nth shift register is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch.
The control terminal of the first switch is electrically coupled to the clock signal CKn-2, and the first terminal of the first switch is electrically coupled to the clock signal CKn + 1.
The control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
A control terminal of the third switch is electrically coupled to the second terminal of the second switch, a first terminal of the third switch is electrically coupled to the gate scan signal Gn, and a second terminal of the third switch is electrically coupled to the low predetermined potential Vss.
In this embodiment, the shift register circuit may further include an input module, an output module, and a feedback module.
The input module is used for receiving the grid signal of the (n-1) th level and generating the working point voltage of the shift temporary storage circuit according to the grid signal of the (n-1) th level.
The output module is configured to receive a clock signal CKn and a working point voltage for precharging the shift register circuit to a precharge level, couple the precharge level to the working point voltage signal Qn according to the clock signal CKn, and output a gate scan signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module is used for receiving a feedback signal and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
Furthermore, as described above, the shift register circuit may further include a control module and a pull-down maintaining module.
The control module is electrically coupled to the low preset potential. The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the working point voltage of the shift register circuit at the low preset potential.
In addition, another embodiment of the present invention provides a driving method of a gate driving circuit structure for a display panel of an array substrate type driving technology, the gate driving circuit structure having n cascaded shift registers, n being a positive integer greater than 2. The driving method includes the steps of:
the nth shift register receives a gate signal of the (n-1) th stage to transmit a gate scanning signal Gn through a gate line, the shift register has a working point voltage signal Qn, wherein the gate line is electrically coupled to a sub pull-down circuit, and the sub pull-down circuit includes a first switch, a second switch, and a third switch;
transmitting a clock signal CKn +1 to the first terminal of the first switch;
transmitting a clock signal CKn-2 to a control terminal of the first switch, wherein a first terminal of the second switch is electrically coupled to a second terminal of the first switch;
transmitting the operating point voltage signal Qn to the control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and
transmitting the gate scan signal Gn to a first end of the third switch, wherein a second end of the third switch is electrically coupled to a low predetermined potential Vss, wherein the low predetermined potential Vss pulls down the gate scan signal Gn.
As described above, the nth shift register receives the gate signal of the (n-1) th stage to transmit the gate scan signal Gn through the gate line, wherein the shift register has the operating point voltage signal Qn. With regard to the foregoing steps, the driving method may further include the steps of:
receiving the grid signal of the (n-1) th level, and generating the working point voltage of the shift register according to the grid signal of the (n-1) th level;
maintaining the working point voltage of the shift register at a low preset potential;
the shift register is used for receiving a clock signal CKn and pre-charging a working point voltage of the shift register into a pre-charging potential, and coupling the pre-charging potential into a working point voltage signal Qn according to the clock signal CKn;
outputting the gate scanning signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn; and
receiving a feedback signal, and pulling down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
According to the gate driving circuit structure, the display panel and the driving method of the gate driving circuit structure, the newly-added sub pull-down circuit is utilized, the gate scanning signal can be effectively pulled down, the mis-charging prevention time is shortened, and the charging time can be further prolonged.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects and features of the present invention more clearly understood, the following detailed description will be given with reference to the accompanying drawings by way of specific embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a display panel and a gate driving circuit structure according to the present invention.
FIG. 2A is a functional relationship diagram of the shift register of the present invention.
FIG. 2B is a diagram of an embodiment of a shift register of the present invention.
Fig. 3 is a schematic diagram of an electronic pull-down circuit of the present invention.
FIG. 4 is a waveform diagram illustrating levels of various signals according to the present invention.
Fig. 5 is a flow chart of a driving method performed by the electronic pull-down circuit of the present invention.
FIG. 6 is a flow chart of a driving method for a shift register according to the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the positional or orientational relationships indicated in the drawings to facilitate the description of the invention and to simplify the description, and are not intended to indicate or imply that the device or component being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1, fig. 1 is a schematic diagram of a display panel 10 and a gate driving circuit structure 20 according to the present invention. An embodiment of the present invention provides a gate driving circuit structure 20 for a display panel of an array substrate type driving technology, wherein the gate driving circuit structure 20 includes a plurality of n cascaded shift registers 30, where n is a positive integer greater than 2.
The display panel 10 still has the source driver 12, but the array substrate type driving technique abandons the gate driver, and instead, the gate driver circuit structure 20 is directly disposed on the glass substrate as shown in the figure. In the gate driving circuit structure 20, which is a plurality of shift registers 30, each shift register 30 receives a gate signal of a previous stage to transmit a gate scanning signal Gn of the previous stage through a gate line 32.
Referring to fig. 2A and fig. 2B, fig. 2A is a functional correlation diagram of the shift register 30 according to the present invention. FIG. 2B is a diagram of an embodiment of a shift register 30 according to the present invention. In the embodiment, the nth shift register 30 is illustrated, wherein the nth shift register 30 includes a shift register circuit 3002 and a sub pull-down circuit 3004.
The nth shift register circuit 3002 is configured to generate a gate scan signal Gn for the nth gate line 32 after receiving a gate signal Fn-1 of a previous stage, for example, the nth-1 stage. The working point in the shift register circuit 3002 has a working point voltage, which is pre-charged and coupled to a working point voltage signal Qn with a more ideal waveform. The shift register circuit 3002 further comprises an input module 50, an output module 52, a feedback module 54, a control module 56, and a pull-down maintaining module 58.
The input module 50 is configured to receive the gate signal Fn-1 of the (n-1) th stage, and generate an operating point voltage of the shift register circuit 3002 according to the gate signal Fn-1 of the (n-1) th stage.
The output module 52 is configured to receive the clock signal CKn of the stage, precharge the working point voltage of the shift register circuit 3002 to a precharge level, couple the precharge level to the working point voltage signal Qn according to the clock signal CKn, and output the gate scanning signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module 54 is configured to receive a feedback signal Gn + from the post-stage shift register 30, and pull down the working point voltage signal Qn or the gate scan signal Gn to a low predetermined potential Vss according to the feedback signal Gn +. The feedback signal Gn + is the gate scanning signal Gn + of the rear pole, and the gate scanning signal Gn of this time is turned off by the generation of the gate scanning signal Gn + of the rear pole.
It should be noted that the control module 56 is electrically coupled to the low predetermined potential Vss and is electrically coupled to the pull-down maintaining module 58.
The pull-down maintaining module 58 is electrically coupled to the low predetermined voltage level and is controlled by the control module 56 to maintain the operating point voltage of the shift register circuit 3002 at the low predetermined voltage level, so as to remove the noise at the operating point.
The sub pull-down circuit 3004 is electrically coupled to the gate line 32, and can effectively and rapidly pull down the gate scan signal G3 to the low predetermined voltage Vss when the gate scan signal Gn is ended, thereby reducing the mis-charging time and further increasing the charging time.
Further illustrated is the embodiment of FIG. 2B, which is an embodiment of a 4CK clock signal. In order to generate the gate scan signal G3 for the 3 rd gate line 32, the input module 50 has a transistor switch, which receives the gate signal F2 of the previous stage and generates the operating point voltage required by the shift register circuit 3002 for the operating point of the shift register circuit 3002.
The output module 52 includes two transistor switches, wherein the control terminal of the left transistor switch pre-charges the operating point voltage of the shift register circuit 3002 to a pre-charge level and couples the pre-charge level to the operating point voltage signal Q3 according to the clock signal CK3, the first terminal of the transistor switch receives the clock signal CK3, and the second terminal of the transistor switch generates the gate signal F3 required to activate the shift register 30 of the next stage and the gate line 32 of the next stage.
The control terminal of the right transistor switch receives the operating point voltage signal Q3, the control terminal of the transistor switch receives the clock signal CK3 according to the operating point voltage signal Q3, and the first terminal of the transistor switch outputs a gate scan signal G3 to the gate line 32 from the second terminal.
The feedback module 54 also includes two transistor switches, control terminals of which are coupled to the gate scan signal G7 of the next stage, and the gate scan signal G7 is used as a feedback signal for terminating the operating point voltage signal Q3 or the gate scan signal G3. The second terminals of the two transistor switches are coupled to the low predetermined potential Vss, and when the two transistor switches receive the gate scan signal G7 of the subsequent stage, the two transistor switches respectively pull down the potentials of the operating point voltage signal Q3 and the gate scan signal G3 to the low predetermined potential Vss according to the feedback signal G7, thereby terminating the gate line 32.
It should be noted that the control module 56 is electrically coupled to the low predetermined potential Vss and is electrically coupled to the pull-down maintaining module 58. The pull-down maintaining module 58 is electrically coupled to the low preset voltage level, and is controlled by the control module 56 to maintain the operating point voltage of the shift register circuit 3002 at the low preset voltage level, so as to remove the noise at the operating point.
The sub pull-down circuit 3004 is electrically coupled to the gate line 32, and can effectively and rapidly pull down the gate scan signal G3 to the low predetermined voltage Vss when the gate scan signal G3 is predetermined to be over, thereby reducing the mis-charging prevention time and further increasing the charging time.
Referring to fig. 3, fig. 3 is a schematic diagram of the sub-pull-down circuit 3004 according to the present invention. The sub-pull-down circuit 3004 is electrically coupled to the gate line 32 and includes a first switch 40, a second switch 42, and a third switch 44.
The control terminal 40G of the first switch 40 can be electrically coupled to one of the clock signal CKn-2 of the previous stage and the clock signal CKn +1 of the next stage, and the first terminal 40D of the first switch 40 can be electrically coupled to the other of the clock signal CKn-2 and the clock signal CKn + 1.
The example of the 4CK clock signal is still illustrated, in which the control terminal 40G of the first switch 40 is electrically coupled to the clock signal CK1, and the first terminal 40D of the first switch 40 is electrically coupled to the clock signal CK 4. When the clock signal CK1 arrives at the control terminal 40G, the first switch 40 is turned on, and the pull-down signal PG3 at the intersection of the clock signal CK1 and the clock signal CK4 is transmitted to the second terminal 40S of the first switch 40.
The control terminal 42G of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and the first terminal 42D of the second switch 42 is electrically coupled to the second terminal 40S of the first switch 40.
In the illustrated example, when the control terminal 42G of the second switch 42 receives the operating point voltage signal Q3, the second switch 42 is turned on, and the signal at the second terminal 40S of the first switch 40 is transmitted from the first terminal 42D of the second switch 42 to the second terminal 42S of the second switch 42, thereby transmitting the pull-down signal PG3 at the intersection of the clock signal CK1 and the clock signal CK 4.
The control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, the first terminal 44D of the third switch 44 is electrically coupled to the gate scan signal Gn, and the second terminal 44S of the third switch 44 is electrically coupled to the low predetermined potential Vss.
In the illustrated embodiment, the third switch 44 is opened after the control terminal 44G of the third switch 44 receives the pull-down signal PG 3. Because the first end 44D of the third switch 44 is electrically coupled to the gate scan signal G3, and the second end 44S of the third switch 44 is electrically coupled to the low predetermined potential Vss, when the control ends 40G and 42G of the first switch 40 and the second switch 42 are both turned on, the third switch 44 is turned on by the pull-down signal PG3 formed by the intersection of the clock signal CK1 and the clock signal CK4, so that the gate scan signal G3 can be effectively and rapidly pulled down to the low predetermined potential Vss, thereby reducing the mis-charging prevention time and increasing the charging time.
Note that the first switch 40 is a first transistor, the second switch 42 is a second transistor, and the third switch 44 is a third transistor.
Referring to fig. 4, fig. 4 is a waveform diagram illustrating levels of various signals according to the present invention. Each signal has different levels, i.e. the voltage value of the high level can represent a valid signal. The figure still shows an embodiment of 4CK clock signals, which are CK1, CK2, CK3 and CK4, respectively, and the waveforms are shown in time sequence.
The operating point voltage signal Q3 is pre-charged and then coupled with the clock signal CK3 to form an ideal waveform, so as to smoothly pull up to a high voltage level, efficiently turn on the transistor switch, and smoothly transmit the gate scan signal G3 to the gate line 32. The gate scan signal G7 is used as a feedback signal to pull down the operating point voltage signal Q3 to the low predetermined voltage Vss.
In order to effectively pull down the gate scan signal G3, the pull-down signal PG3 generated by the intersection of the clock signal CK1 and the clock signal CK4 by the sub-pull-down circuit 3004 can effectively and rapidly pull down the gate scan signal G3 to the low predetermined potential Vss, thereby reducing the mis-charging prevention time and further increasing the charging time.
In addition, according to the aforementioned illustration, another embodiment of the present invention provides a display panel and a shift register 30 in the display panel, wherein the shift register 30 is used for a display panel 10 of an array substrate type driving technology, the display panel 10 has n cascaded shift registers 30, and n is a positive integer greater than 2. The shift register 30 includes a shift register circuit 3002 and a sub pull-down circuit 3004.
The shift register circuit 3002 of the nth shift register 30 is used for receiving the gate signal of the (n-1) th stage to transmit the gate scanning signal Gn through the gate line 32. The shift register circuit 3002 has an operating point voltage signal Qn.
The sub-pull-down circuit 3004 of the nth shift register 30 is electrically coupled to the gate line 32, and the shift register 30 includes a first switch 40, a second switch 42, and a third switch 44.
The control terminal of the first switch 40 is electrically coupled to the clock signal CKn-2, and the first terminal of the first switch 40 is electrically coupled to the clock signal CKn + 1.
The control terminal of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch 42 is electrically coupled to the second terminal of the first switch 40.
A control terminal of the third switch 44 is electrically coupled to the second terminal of the second switch 42, a first terminal of the third switch 44 is electrically coupled to the gate scan signal Gn, and a second terminal of the third switch 44 is electrically coupled to the low predetermined potential Vss. Thus, the pull-down signal PG3 generated by the first switch 40, the second switch 42, and the third switch 44 can effectively pull down the gate scan signal Gn to the low predetermined potential Vss.
It should be noted that the shift register circuit 3002 further includes an input module 50, an output module 52, a feedback module 54, a control module 56, and a pull-down maintaining module 58.
The input module 50 is configured to receive the gate signal of the (n-1) th stage, and generate an operating point voltage of the shift register circuit 3002 according to the gate signal of the (n-1) th stage.
The output module 52 is configured to receive a clock signal CKn and a working point voltage for precharging the shift register 3002 to obtain a precharge level, couple the precharge level to a working point voltage signal Qn according to the clock signal CKn, and output a gate scan signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The feedback module 54 is configured to receive a feedback signal and pull down the potential of the gate scanning signal Gn to a low preset potential according to the feedback signal.
The control module 56 is electrically coupled to the low predetermined voltage level. The pull-down maintaining module 58 is electrically coupled to the control module 56 and the low preset voltage level, and is controlled by the control module 56 to maintain the operating point voltage of the shift register circuit 3002 at the low preset voltage level.
Therefore, the pull-down signal PG3 generated by the sub-pull-down circuit 3004 can effectively and rapidly pull down the gate scan signal G3 to the low predetermined potential Vss when the gate scan signal Gn is terminated, thereby reducing the mis-charging prevention time and further increasing the charging time.
In addition, another embodiment of the present invention provides a driving method of the gate driving circuit structure 20. Referring to fig. 5, fig. 5 is a flowchart illustrating a driving method performed by the sub pull-down circuit 3004 according to the present invention. The gate driving circuit structure 20 is used for a display panel 10 of an array substrate type driving technology, and the gate driving circuit structure 20 has n cascaded shift registers 30, where n is a positive integer greater than 2. The driving method includes the steps of:
step one (S01): the nth shift register 30 receives the gate signal of the (n-1) th stage to transmit the gate scan signal Gn through the gate line 32, and the shift register 30 has an operating point voltage signal Qn. The gate line 32 is electrically coupled to the sub-pull-down circuit 3004, and the sub-pull-down circuit 3004 includes a first switch 40, a second switch 42, and a third switch 44.
Step two (S02): the clock signal CKn +1 is transmitted to the first terminal 40D of the first switch 40.
Step three (S03): it is determined whether the control terminal 40G of the first switch 40 receives the clock signal CKn-2. If the third step (S03) is yes, the clock signal CKn +1 is transmitted to the second terminal 40S of the first switch 40 and the first terminal 42D of the second switch 42, and the fifth step (S05) is performed.
Step four (S04): the gate scan signal Gn is transmitted to the first end 44D of the third switch 44, wherein the second end 44S of the third switch 44 is electrically coupled to the low predetermined potential Vss.
Step five (S05): it is determined whether the control terminal 42G of the second switch 42 receives the operating point voltage signal Qn. The control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, and if the step five (S05) is yes, the pull-down signal of the intersection of the clock signal CKn-2 and the clock signal CKn +1 is transmitted to the second terminal 42S of the second switch 42, and the step six (S06) is performed in conjunction with the step four (S04).
Step six (S06): at this time, the pull-down signals generated by the first switch 40 and the second switch 42 open the third switch 44 through the control terminal 44G of the third switch 44, so that the low predetermined potential Vss at the second terminal 44S of the third switch 44 pulls down the gate scan signal Gn at the first terminal 44D of the third switch 44, thereby reducing the mis-charging prevention time and further increasing the charging time.
Referring to fig. 6, fig. 6 is a flowchart illustrating a driving method of the shift register 30 according to the present disclosure. As in the driving method described above, step one (S01) is to receive the gate signal of the (n-1) th stage from the nth shift register 30 to transmit the gate scan signal Gn through the gate line 32, wherein the shift register 30 has the operating point voltage signal Qn. In view of the foregoing, the driving method further includes the steps of:
one of the first steps (S11): the gate signal of the (n-1) th stage is received, and the operating point voltage of the shift register 30 is generated according to the gate signal of the (n-1) th stage.
Step two (S12): the working point voltage of the shift register 30 is maintained at a low predetermined level.
Third step (S13): the circuit is used for receiving a clock signal CKn and precharging the working point voltage of the shift register 30 to a precharge level, and coupling the precharge level to the working point voltage signal Qn according to the clock signal CKn.
Step four (S14): and outputting the gate scanning signal Gn according to the coupled working point voltage signal Qn and the clock signal CKn.
The above-mentioned one step (S11), two steps (S12), three steps (S13), and four steps (S14) describe in detail how the step one (S01) of the example of fig. 5 is performed.
Next, step two (S02), step three (S03), step four (S04), step five (S05), and step six (S06) in the example of fig. 5 are performed. Subsequently, the fifth step of the first step of fig. 6 is performed (S15): and receiving a feedback signal, and pulling down the potential of the working point voltage signal Qn or the grid scanning signal Gn to a low preset potential according to the feedback signal.
In summary, the gate driving circuit structure 20, the display panel 10 and the driving method of the gate driving circuit structure 20 according to the embodiment of the invention utilize the newly added sub pull-down circuit 3004 to effectively pull down the gate scanning signal Gn, reduce the mis-charging prevention time and further increase the charging time.
In some embodiments, the display panel may be, for example, a liquid crystal display panel, a QLED display panel, an OLED display panel, a curved display panel, or other display panel.
Although the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A gate driving circuit structure for a display panel of an array substrate type driving technology, the gate driving circuit structure comprising:
a plurality of cascaded shift registers, wherein the shift registers comprise:
the shift temporary storage circuit receives a grid signal of a previous stage so as to transmit a grid scanning signal through a grid line, wherein the shift temporary storage circuit is provided with a working point voltage signal; and
a sub pull-down circuit electrically coupled to the gate line, including a first switch, a second switch, and a third switch,
the control end of the first switch is electrically coupled to one of the clock signal of the previous stage and the clock signal of the next stage, the first end of the first switch is electrically coupled to the other of the clock signal of the previous stage and the clock signal of the next stage,
the control end of the second switch is electrically coupled to the operating point voltage signal, the first end of the second switch is electrically coupled to the second end of the first switch,
the control end of the third switch is electrically coupled to the second end of the second switch, the first end of the third switch is electrically coupled to the gate scanning signal, and the second end of the third switch is electrically coupled to the low preset potential.
2. The gate driver circuit structure of claim 1, wherein the control terminal of the first switch is electrically coupled to a clock signal of a previous stage, and the first terminal of the first switch is electrically coupled to a clock signal of a next stage.
3. The gate driver circuit structure of claim 1, wherein the shift register circuit comprises:
the input module is used for receiving the grid signal of the previous stage and generating the working point voltage of the shift temporary storage circuit according to the grid signal of the previous stage;
the output module is used for receiving a clock signal of a current stage and pre-charging a working point voltage of the shift temporary storage circuit to be a pre-charging potential, coupling the pre-charging potential into the working point voltage signal according to the clock signal of the current stage, and outputting a grid scanning signal according to the coupled working point voltage signal and the clock signal of the current stage;
and the feedback module is used for receiving a feedback signal and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
4. The gate driver circuit structure of claim 1, wherein the shift register circuit comprises:
the control module is electrically coupled with the low preset potential; and
and the pull-down maintaining module is electrically coupled with the control module and the low preset potential, and is controlled by the control module to maintain the working point voltage of the shift register circuit at the low preset potential.
5. The gate driver circuit structure of claim 1, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
6. A display panel for an array substrate type driving technique, the display panel comprising:
the shift register comprises a shift register circuit and a sub pull-down circuit;
the shift temporary storage circuit is used for receiving a grid signal of a previous stage so as to transmit a grid scanning signal through a grid line, and the shift temporary storage circuit is provided with a working point voltage signal; and
a sub pull-down circuit electrically coupled to the gate line, the sub pull-down circuit including a first switch, a second switch, and a third switch;
the control end of the first switch is electrically coupled with a clock signal of a previous stage, and the first end of the first switch is electrically coupled with a clock signal of a next stage;
the control end of the second switch is electrically coupled to the operating point voltage signal, and the first end of the second switch is electrically coupled to the second end of the first switch;
the control end of the third switch is electrically coupled to the second end of the second switch, the first end of the third switch is electrically coupled to the gate scanning signal, and the second end of the third switch is electrically coupled to the low preset potential.
7. The display panel of claim 6, wherein the shift register circuit comprises:
the input module is used for receiving the grid signal of the previous stage and generating the working point voltage of the shift temporary storage circuit according to the grid signal of the previous stage;
the output module is used for receiving a clock signal of a current stage and pre-charging a working point voltage of the shift temporary storage circuit to be a pre-charging potential, coupling the pre-charging potential into the working point voltage signal according to the clock signal of the current stage, and outputting a grid scanning signal according to the coupled working point voltage signal and the clock signal of the current stage;
and the feedback module is used for receiving a feedback signal and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
8. The display panel of claim 6, wherein the shift register circuit comprises:
the control module is electrically coupled with the low preset potential; and
and the pull-down maintaining module is electrically coupled with the control module and the low preset potential, and is controlled by the control module to maintain the working point voltage of the shift register circuit at the low preset potential.
9. A driving method of a gate driving circuit structure for a display panel of an array substrate type driving technique, the gate driving circuit structure having a plurality of cascaded shift registers, the driving method comprising the steps of:
the shift register receives a grid signal of a previous stage to transmit a grid scanning signal through a grid line, and is provided with a working point voltage signal, wherein the grid line is electrically coupled with a sub pull-down circuit, and the sub pull-down circuit comprises a first switch, a second switch and a third switch;
transmitting the clock signal of the next stage to the first end of the first switch;
transmitting the first-stage clock signal to the control terminal of the first switch, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch;
transmitting the operating point voltage signal to a control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and
and transmitting the grid scanning signal to a first end of the third switch, wherein a second end of the third switch is electrically coupled with a low preset potential, and the low preset potential pulls down the grid scanning signal.
10. The driving method as claimed in claim 9, wherein the shift register receives a gate signal of a previous stage to transmit a gate scan signal through a gate line, wherein the shift register has an operating point voltage signal, the driving method further comprising the steps of:
receiving a grid signal of a previous stage, and generating a working point voltage of the shift register according to the grid signal of the previous stage;
maintaining the working point voltage of the shift register at a low preset potential;
the shift register is used for receiving a clock signal of a current stage and pre-charging a working point voltage of the shift register into a pre-charging potential, and coupling the pre-charging potential into the working point voltage signal according to the clock signal of the current stage;
outputting the grid scanning signal according to the coupled working point voltage signal and the clock signal of the current stage; and
and receiving a feedback signal, and pulling down the potential of the grid scanning signal to a low preset potential according to the feedback signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810785645.9A CN108922485B (en) | 2018-07-17 | 2018-07-17 | Gate drive circuit structure, display panel and drive method of gate drive circuit structure |
| PCT/CN2018/109758 WO2020015206A1 (en) | 2018-07-17 | 2018-10-11 | Gate driving circuit structure, display panel, and driving method for gate driving circuit structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810785645.9A CN108922485B (en) | 2018-07-17 | 2018-07-17 | Gate drive circuit structure, display panel and drive method of gate drive circuit structure |
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| CN108922485B true CN108922485B (en) | 2020-06-12 |
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| CN109300445B (en) * | 2018-12-05 | 2021-11-30 | 惠科股份有限公司 | Array substrate row driving circuit and display device |
| CN109389957A (en) * | 2018-12-05 | 2019-02-26 | 惠科股份有限公司 | Array substrate horizontal drive circuit and display device |
| TWI690912B (en) * | 2019-02-13 | 2020-04-11 | 友達光電股份有限公司 | Display panel and driving method |
| CN114067759B (en) * | 2020-07-31 | 2022-12-23 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
| TWI744096B (en) * | 2020-11-18 | 2021-10-21 | 友達光電股份有限公司 | Gate of array driving circuit |
| CN113380168B (en) * | 2021-05-20 | 2022-09-27 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
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| CN103474017B (en) * | 2013-09-12 | 2016-01-27 | 北京京东方光电科技有限公司 | Shift register cell, gate driver circuit and display device |
| CN104134430B (en) * | 2014-07-04 | 2016-08-17 | 京东方科技集团股份有限公司 | A kind of shift register, gate driver circuit and display device |
| TWI541779B (en) * | 2014-07-18 | 2016-07-11 | 友達光電股份有限公司 | Shift register and method of driving shift register |
| CN104392701B (en) * | 2014-11-07 | 2016-09-14 | 深圳市华星光电技术有限公司 | Scan drive circuit for oxide semiconductor thin-film transistor |
| JP6677383B2 (en) * | 2015-03-03 | 2020-04-08 | 天馬微電子有限公司 | Electronic circuit, scanning circuit, display device, and method for extending life of electronic circuit |
| CN104952406B (en) * | 2015-06-08 | 2017-08-01 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| CN105118419B (en) * | 2015-09-28 | 2017-11-10 | 深圳市华星光电技术有限公司 | A kind of display device, TFT substrate and GOA drive circuits |
| CN105206243B (en) * | 2015-10-28 | 2017-10-17 | 京东方科技集团股份有限公司 | A kind of shift register, grid integrated drive electronics and display device |
| CN105336300B (en) * | 2015-12-04 | 2019-03-26 | 昆山龙腾光电有限公司 | Shift register, gate driving circuit and display device |
| CN106205538A (en) * | 2016-08-31 | 2016-12-07 | 深圳市华星光电技术有限公司 | A kind of GOA driver element and drive circuit |
| CN107068093A (en) * | 2017-05-05 | 2017-08-18 | 惠科股份有限公司 | Shift scratch circuit and its display panel of application |
| CN106910484B (en) * | 2017-05-09 | 2019-06-21 | 惠科股份有限公司 | A kind of display device and its driving circuit and method |
| CN107871486A (en) * | 2017-12-21 | 2018-04-03 | 惠科股份有限公司 | Display device and shift scratch circuit |
| CN108231020A (en) * | 2017-12-26 | 2018-06-29 | 惠科股份有限公司 | Shift scratch circuit and display panel |
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| WO2020015206A1 (en) | 2020-01-23 |
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