WO2020015206A1

WO2020015206A1 - Gate driving circuit structure, display panel, and driving method for gate driving circuit structure

Info

Publication number: WO2020015206A1
Application number: PCT/CN2018/109758
Authority: WO
Inventors: 单剑锋
Original assignee: 惠科股份有限公司
Priority date: 2018-07-17
Filing date: 2018-10-11
Publication date: 2020-01-23
Also published as: CN108922485B; CN108922485A

Abstract

Disclosed are a gate driving circuit structure, a display panel, and a driving method for the gate driving circuit structure. In the display panel applied to gate driver on array technology, a shift register is additionally provided with a pull-down sub-circuit, and the pull-down sub-circuit is electrically coupled to a gate line and comprises a first switch, a second switch and a third switch, wherein a control end of the first switch may be electrically coupled to a previous-two-stage clock signal, and a first end of the first switch may be electrically coupled to a next-stage clock signal; a control end of the second switch is electrically coupled to a working point voltage signal, and a first end of the second switch is electrically coupled to a second end of the first switch; and a control end of the third switch is electrically coupled to a second end of the second switch, a first end of the third switch is electrically coupled to a gate scanning signal, and a second end of the third switch is electrically coupled to a preset low potential.

Description

Gate driving circuit structure, display panel, and driving method of gate driving circuit structure

Technical field

The present disclosure relates to a display panel, and particularly to a gate driving circuit structure and a driving method of the gate driving circuit structure in the display panel.

Background technique

In order to save costs, the display panel industry, such as liquid crystal display panels, has widely adopted the array substrate type drive technology (Gate, Driver, Array, GOA). The technology of the liquid crystal display panel relies on a source driver IC (gate IC) and a gate driver IC (gate IC) to drive. The former controls voltage to transmit signals, and the latter uses transistors as switches to control and determine the amount of light transmission.

The array substrate type driving technology is to abandon the gate driving chip and replace the gate driving circuit structure directly on the glass substrate of the liquid crystal display panel. Since the gate driving circuit structure uses the exposure and development method, it is generated on the edge of the glass substrate. Logic circuit, so whether it is in material or manufacturing process, it can achieve the effect of reducing costs, and can also achieve the effect of reducing the LCD display frame.

The principle of the array substrate type driving technology is developed based on the Thompson circuit. In order to achieve a smooth driving effect, it is usually precharged at the Quiescent point to achieve a higher voltage level. This enables subsequent coupling with the clock signal into an ideal signal waveform, whereby when the transistor switch is turned on, the gate scanning signal required by the gate line can be smoothly transmitted.

In addition, for the charging time for charging a pixel unit in a liquid crystal display panel, there will be a gate error time (Tf) at the end of the signal to pull down the high-level voltage level. The smaller the better.

Therefore, how to reduce the error-proof charging time as much as possible when pulling down the gate-level scanning signal to increase the charging time has become one of the problems to be solved by those skilled in the art.

Summary of the invention

The present disclosure proposes a gate driving circuit structure, a display panel, and a driving method of the gate driving circuit structure, which can effectively pull down the gate-level scanning signal, reduce the time for preventing wrong charging, and further increase the charging time.

An embodiment of the present disclosure provides a gate driving circuit structure for a display panel of an array substrate-type driving technology (Gate Driver Array). The gate driving circuit structure includes n cascaded shift registers.

For the n cascaded shift registers, n is a positive integer greater than 2. The n-th shift register is described. The shift register includes a shift register circuit and a sub-pull-down circuit.

The shift register circuit receives a gate signal of the previous stage, such as the n-1 stage, to transmit the gate scan signal Gn of this stage through a gate line. The operating point of the shift register circuit has The operating point voltage signal Qn of this stage.

The sub pull-down circuit is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch.

The control terminal of the first switch is electrically coupled to one of the clock signal CKn-2 in the first stage and the clock signal CKn + 1 in the latter stage, and the first terminal of the first switch is electrically coupled. The other one of the clock signal CKn-2 and the clock signal CKn + 1.

The control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.

The control terminal of the third switch is electrically coupled to the second terminal of the second switch, and the first terminal of the third switch is electrically coupled to the gate scanning signal Gn. The two terminals are electrically coupled to a low preset potential Vss.

To further explain, in one embodiment, the control terminal of the first switch may be an electrically coupled clock signal CKn-2, and the first terminal of the first switch may be an electrically coupled clock signal CKn + 1.

In the foregoing embodiment, the shift temporary storage circuit may further include an input module, an output module, and a feedback module.

The input module is configured to receive an n-1th gate signal and generate an operating point voltage of the shift temporary storage circuit according to the n-1th gate signal.

The output module is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal CKn. Qn, and output a gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.

The feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.

Further, the shift temporary storage circuit may further include a control module and a pull-down maintaining module.

The control module is electrically coupled to the low preset potential. The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the operating point voltage of the shift temporary storage circuit to a low preset potential.

It is added that, as in the foregoing gate driving circuit structure, the first switch may be a first transistor, the second switch may be a second transistor, and the third switch may be a third transistor.

Another embodiment of the present disclosure provides a display panel and a shift register in the display panel. The shift register is used for a display panel of an array substrate type driving technology, and the display panel has n cascaded shifts. Register, n is a positive integer greater than 2.

The shift register circuit of the n-th shift register is configured to receive a gate signal of the n-1th stage to transmit a gate scan signal Gn through a gate line. The shift temporary storage circuit has an operating point voltage signal Qn. The shift register includes a shift register circuit and a sub-pull-down circuit.

The sub pull-down circuit of the n-th shift register is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch.

The control terminal of the first switch is electrically coupled to the clock signal CKn-2, and the first terminal of the first switch is electrically coupled to the clock signal CKn + 1.

In this embodiment, the shift temporary storage circuit may further include an input module, an output module, and a feedback module.

The output module is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal CKn Qn, and output a gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.

Further, like the aforementioned shift register, the shift register circuit may further include a control module and a pull-down maintaining module.

In addition, another embodiment of the present disclosure provides a driving method of a gate driving circuit structure for a display panel of an array substrate type driving technology, the gate driving circuit structure having n stages Associated shift register, n is a positive integer greater than 2. The driving method includes the following steps:

The nth shift register receives a gate signal of the n-1th stage to transmit a gate scan signal Gn through a gate line. The shift register has an operating point voltage signal Qn, where the gate The line is electrically coupled to a sub-pull-down circuit, which includes a first switch, a second switch, and a third switch;

Transmitting a clock signal CKn + 1 to a first terminal of the first switch;

Transmitting a clock signal CKn-2 to the control terminal of the first switch, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch;

Transmitting the operating point voltage signal Qn to the control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and

Transmitting the gate scanning signal Gn to a first terminal of the third switch, and the second terminal of the third switch is electrically coupled to a low preset potential Vss, where the low preset potential Vss will pull the gate low Stage scanning signal Gn.

As in the foregoing driving method, for the n-th shift register, a gate signal of the n-1th stage is received to transmit a gate-scan signal Gn through a gate line, wherein the shift register has an operation Point voltage signal Qn. Regarding the foregoing steps, the driving method may further include the following steps:

Receiving a gate signal of the n-1th stage and generating a working point voltage of the shift register according to the gate signal of the n-1th stage;

Maintaining the operating point voltage of the shift register to a low preset potential;

For receiving a clock signal CKn and pre-charging the operating point voltage of the shift register to become a pre-charging potential, and coupling the pre-charging bit into the operating-point voltage signal Qn according to the clock signal CKn;

Outputting the gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn; and

Receiving a feedback signal, and pulling the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.

A gate driving circuit structure, a display panel, and a driving method of the gate driving circuit structure according to the embodiments of the present disclosure. The newly-added sub-pull-down circuit can effectively pull down the gate-level scanning signal and reduce the time for preventing wrong charging. , Which can increase the charging time.

The above description is only an overview of the technical solutions of the present disclosure. In order to understand the technical means of the present disclosure more clearly, it can be implemented in accordance with the content of the description, and in order to make the above and other objects and features of the present disclosure more comprehensible, the following Specific examples are given below, and in conjunction with the drawings, the detailed description is as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the description, for illustrating the embodiments of the present application, and to explain the principles of the present application together with the text description. Obviously, the drawings in the following description are just some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without paying creative labor. In the drawings:

FIG. 1 is a schematic diagram of a display panel and a gate driving circuit structure according to the present disclosure.

FIG. 2A is a functional correlation diagram of a shift register of the present disclosure.

FIG. 2B is a schematic diagram of an embodiment of a shift register according to the present disclosure.

FIG. 3 is a schematic diagram of a sub-pull-down circuit of the present disclosure.

FIG. 4 is a waveform diagram of levels of various signals of the present disclosure.

FIG. 5 is a flowchart of a driving method performed by a sub-pull-down circuit of the present disclosure.

FIG. 6 is a flowchart of a driving method performed by a shift register of the present disclosure.

detailed description

The specific structural and functional details disclosed herein are merely representative and are used for the purpose of describing exemplary embodiments of the present disclosure. This disclosure may, however, be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein.

In the description of this disclosure, it needs to be understood that the terms "center", "horizontal", "up", "down", "left", "right", "vertical", "horizontal", "top", The directions or positions indicated by "bottom", "inside", "outside", etc. are based on the directions or position relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying the means referred to Or a component must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation on this disclosure. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present disclosure, unless otherwise stated, "a plurality" means two or more. In addition, the term "including" and any variations thereof are intended to cover non-exclusive inclusion.

In the description of this disclosure, it should be noted that the terms "installation", "connected", and "connected" should be understood in a broad sense unless explicitly stated and limited otherwise. For example, they can be fixed or removable. Connected or integrated; it can be mechanical or electrical; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure may be understood on a case-by-case basis.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "an" are intended to include the plural. It should also be understood that the terms "including" and / or "comprising" as used herein specify the presence of stated features, integers, steps, operations, units and / or components without precluding the presence or addition of one or more Other features, integers, steps, operations, units, components, and / or combinations thereof.

Please refer to FIG. 1, which is a schematic diagram of a display panel 10 and a gate driving circuit structure 20 of the present disclosure. An embodiment of the present disclosure provides a gate driving circuit structure 20 for a display panel of an array substrate type driving technology. The gate driving circuit structure 20 includes a plurality of n cascaded shift registers 30. , N is a positive integer greater than 2.

The display panel 10 in the figure still has a source driving chip 12, but the array substrate type driving technology abandons the gate driving chip and replaces the gate driving circuit structure 20 directly on the glass substrate as shown in the figure. In the gate driving circuit structure 20, there are actually a plurality of shift registers 30. Each shift register 30 receives a gate signal of a previous stage to transmit the gate of the stage through the gate line 32. Scan signal Gn.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a functional correlation diagram of the shift register 30 of the present disclosure. FIG. 2B is a schematic diagram of an embodiment of a shift register 30 according to the present disclosure. The n-th shift register 30 is described in this embodiment. The n-th shift register 30 includes a shift register circuit 3002 and a sub-pull-down circuit 3004.

The n-th shift register circuit 3002 is configured to generate a gate scanning signal Gn for the n-th gate line 32 after receiving the gate-level signal Fn-1 of the previous stage, such as the n-1 stage. The working point in the circuit of the shift temporary storage circuit 3002 has a working point voltage, which can be coupled into a more ideal working point voltage signal Qn after being precharged. The shift temporary storage circuit 3002 further includes an input module 50, an output module 52, a feedback module 54, a control module 56, and a pull-down maintaining module 58.

The input module 50 is configured to receive a gate signal Fn-1 of the n-1th stage and generate an operating point voltage of the shift temporary storage circuit 3002 according to the gate signal Fn-1 of the n-1th stage.

The output module 52 is configured to receive a clock signal CKn of this stage, and precharge the operating point voltage of the shift temporary storage circuit 3002 into a precharge bit, and couple the precharge bit into a desired voltage according to the clock signal CKn. The operating point voltage signal Qn is described, and a gate scan signal Gn is output according to the coupled operating point voltage signal Qn and the clock signal CKn.

The feedback module 54 is configured to receive a feedback signal Gn + from the post-stage shift register 30 and pull the potential of the operating point voltage signal Qn or the gate scan signal Gn to a low preset according to the feedback signal Gn + Potential Vss. The feedback signal Gn + means the gate scan signal Gn + of the rear pole, and the generation of the gate scan signal Gn + of the subsequent pole is used to turn off the current gate scan signal Gn.

It is added that the control module 56 is electrically coupled to the low preset potential Vss, and is electrically coupled to the pull-down maintaining module 58.

The pull-down maintaining module 58 is electrically coupled to the low preset potential, and is controlled by the control module 56 to maintain the operating point voltage of the shift register circuit 3002 to a low preset potential to remove noise at the operating point. .

The sub pull-down circuit 3004 is electrically coupled to the gate line 32, and can effectively and quickly pull down the gate scan signal G3 to a low preset potential Vss at the end of the gate scan signal Gn, which can reduce the anti-charge time, and Can increase charging time.

Further description is made with the embodiment of FIG. 2B, which is an embodiment of a 4CK clock signal. In order to generate a gate scanning signal G3 for the third gate line 32, the input module 50 has a transistor switch. After receiving the previous stage gate signal F2, the shift temporary generating circuit 3002 generates the shift temporary signal. The required operating point voltage of the circuit 3002 is stored.

The output module 52 includes two transistor switches. The control terminal of the transistor switch on the left will first precharge the operating point voltage of the shift register circuit 3002 into a precharge bit, and couple the precharge bit according to the clock signal CK3. Become the operating point voltage signal Q3, the first end of this transistor switch receives the clock signal CK3, and the second end of this transistor switch generates the shift register 30 and the gate line 32 required for starting the subsequent stage. Gate signal F3.

The control terminal of the right transistor switch receives the operating point voltage signal Q3. The control terminal of the transistor switch receives the clock signal CK3 according to the operating point voltage signal Q3, and the first terminal of the transistor switch receives the clock signal CK3 from the second terminal. A gate scan signal G3 is output to the gate line 32.

The feedback module 54 also includes two transistor switches, and the control terminals of the two transistor switches are coupled to the gate scanning signal G7 of the subsequent stage. This gate scanning signal G7 is used as a feedback signal to end the operating point voltage signal Q3. Or the gate scan signal G3. The second ends of the two transistor switches are both coupled to a low preset potential Vss. When the two transistor switches receive the gate scanning signal G7 of the subsequent stage, the operating point voltage signal Q3 is respectively received according to the feedback signal G7. And the potential of the gate scan signal G3 is pulled down to a low preset potential Vss, so that the gate line 32 ends the signal.

It is added that the control module 56 is electrically coupled to the low preset potential Vss, and is electrically coupled to the pull-down maintaining module 58. The pull-down maintaining module 58 is electrically coupled to the low preset potential, and is controlled by the control module 56 to maintain the operating point voltage of the shift register circuit 3002 to a low preset potential to remove noise at the operating point.

The sub pull-down circuit 3004 is electrically coupled to the gate line 32, and can effectively and quickly pull down the gate scan signal G3 to a low preset potential Vss when the gate scan signal G3 is scheduled to end, which can reduce the time for preventing wrong charging. This can increase the charging time.

Please further refer to FIG. 3, which is a schematic diagram of a sub pull-down circuit 3004 according to the present disclosure. The sub pull-down circuit 3004 is electrically coupled to the gate line 32 and includes a first switch 40, a second switch 42, and a third switch 44.

The control terminal 40G of the first switch 40 can be electrically coupled to one of the clock signal CKn-2 of the first stage and the clock signal CKn + 1 of the second stage. The first terminal of the first switch 40 The 40D can be electrically coupled to another signal of the clock signal CKn-2 and the clock signal CKn + 1.

The illustration is still described with the foregoing embodiment of the 4CK clock signal. The control terminal 40G of the first switch 40 in the figure is electrically coupled to the clock signal CK1, and the first terminal 40D of the first switch 40 is electrically coupled to the clock. Signal CK4. When the clock signal CK1 arrives at the control terminal 40G, the first switch 40 is turned on, and the pull-down signal PG3 at the intersection of the clock signal CK1 and the clock signal CK4 is transmitted to the second terminal 40S of the first switch 40.

The control terminal 42G of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and the first terminal 42D of the second switch 42 is electrically coupled to the second terminal 40S of the first switch 40.

In the illustration, when the control terminal 42G of the second switch 42 receives the operating point voltage signal Q3, the second switch 42 will be opened, and then the signal from the second terminal 40S of the first switch 40 One end 42D is transmitted to the second end 42S of the second switch 42, and thus the pull-down signal PG3 at which the clock signal CK1 and the clock signal CK4 intersect is transmitted.

The control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, and the first terminal 44D of the third switch 44 is electrically coupled to the gate scanning signal Gn. The second terminal 44S of the third switch 44 is electrically coupled to a low preset potential Vss.

In the figure, after the control terminal 44G of the third switch 44 receives the pull-down signal PG3, the third switch 44 is turned on. Because the first terminal 44D of the third switch 44 is electrically coupled to the gate scanning signal G3, and the second terminal 44S of the third switch 44 is electrically coupled to a low preset potential Vss. When both the

control terminals

40G and 42G of the switch 40 and the second switch 42 are turned on, the pull-down signal PG3, which is the intersection of the clock signal CK1 and the clock signal CK4, will open the third switch 44, which can effectively and quickly pull down The gate scan signal G3 to a low preset potential Vss can reduce the time for preventing wrong charging, thereby increasing the charging time.

It is added that the first switch 40 is a first transistor, the second switch 42 is a second transistor, and the third switch 44 is a third transistor.

For waveforms generated by signals, please refer to FIG. 4. FIG. 4 is a schematic waveform diagram of levels of various signals of the present disclosure. Each signal has a different level, that is, a high voltage value can represent a valid signal. The illustration is still illustrated by the embodiment of the 4CK clock signal. The clock signals are CK1, CK2, CK3, and CK4, respectively.

The operating point voltage signal Q3 is pre-charged and then coupled with the clock signal CK3 into a more ideal waveform, so that it can be smoothly pulled up to a high voltage level, and the transistor switch is efficiently turned on, so that the gate scan signal G3 is smoothly transmitted. To the gate line 32. The gate scan signal G7 is used as a feedback signal to pull the operating point voltage signal Q3 to a low preset potential Vss.

In order to effectively pull down the gate scan signal G3, the pull-down signal PG3 at the intersection of the clock signal CK1 and the clock signal CK4 generated by the sub-pull-down circuit 3004 can effectively and quickly pull down the gate scan signal G3 to a low preset potential. Vss can reduce the time to prevent wrong charging, which can increase the charging time.

In addition, according to the foregoing drawings, another embodiment of the present disclosure provides a display panel and a shift register 30 in the display panel. The shift register 30 is used for a display panel 10 of an array substrate type driving technology. The display panel 10 has n cascaded shift registers 30, where n is a positive integer greater than two. The shift register 30 includes a shift register circuit 3002 and a sub-pull-down circuit 3004.

The shift register circuit 3002 of the n-th shift register 30 is configured to receive a gate signal of the n-1th stage to transmit the gate scan signal Gn through the gate line 32. The shift temporary storage circuit 3002 has an operating point voltage signal Qn.

The sub pull-down circuit 3004 of the n-th shift register 30 is electrically coupled to the gate line 32. The shift register 30 includes a first switch 40, a second switch 42, and a third switch 44.

The control terminal of the first switch 40 is electrically coupled to the clock signal CKn-2, and the first terminal of the first switch 40 is electrically coupled to the clock signal CKn + 1.

A control terminal of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and a first terminal of the second switch 42 is electrically coupled to a second terminal of the first switch 40.

The control terminal of the third switch 44 is electrically coupled to the second terminal of the second switch 42, and the first terminal of the third switch 44 is electrically coupled to the gate scanning signal Gn. The second terminal of the switch 44 is electrically coupled to the low preset potential Vss. Thereby, the pull-down signal PG3 generated by the first switch 40, the second switch 42, and the third switch 44 can effectively pull down the gate scanning signal Gn to a low preset potential Vss.

It is added that the shift temporary storage circuit 3002 further includes an input module 50, an output module 52, a feedback module 54, a control module 56, and a pull-down maintaining module 58.

The input module 50 is configured to receive a gate signal of the n-1th stage and generate an operating point voltage of the shift temporary storage circuit 3002 according to the gate signal of the n-1th stage.

The output module 52 is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit 3002 into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal CKn. Qn, and output a gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.

The feedback module 54 is configured to receive a feedback signal and pull the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.

The control module 56 is electrically coupled to the low preset potential. The pull-down maintaining module 58 is electrically coupled to the control module 56 and the low preset potential, and is controlled by the control module 56 to maintain the operating point voltage of the shift temporary storage circuit 3002 to a low preset potential.

With this, the pull-down signal PG3 generated by the sub-pull-down circuit 3004 can effectively and quickly pull down the gate scan signal G3 to a low preset potential Vss when the gate scan signal Gn is scheduled to end, and can reduce the time for preventing wrong charging This can increase the charging time.

In addition, another embodiment of the present disclosure provides a driving method of the gate driving circuit structure 20. Please refer to FIG. 5, which is a flowchart of a driving method performed by the sub pull-down circuit 3004 of the present disclosure. The gate driving circuit structure 20 is used for a display panel 10 of an array substrate type driving technology. The gate driving circuit structure 20 has n cascaded shift registers 30, where n is a positive integer greater than two. The driving method includes the following steps:

Step 1 (S01): The n-th shift register 30 receives the gate signal of the n-1th stage to transmit the gate-scan signal Gn through the gate line 32. The shift register 30 has Operating point voltage signal Qn. The gate line 32 is electrically coupled to the sub-pull-down circuit 3004. The sub-pull-down circuit 3004 includes a first switch 40, a second switch 42, and a third switch 44.

Step 2 (S02): transmitting a clock signal CKn + 1 to the first terminal 40D of the first switch 40.

Step three (S03): determine whether the control terminal 40G of the first switch 40 receives a clock signal CKn-2. Wherein, the first end 42D of the second switch 42 is electrically coupled to the second end 40S of the first switch 40, and if step three (S03) is YES, the clock signal CKn + 1 will be transmitted to the first switch. The second end 40S of 40 and the first end 42D of the second switch 42 are performed, and step 5 is performed (S05).

Step 4 (S04): transmitting the gate scanning signal Gn to the first terminal 44D of the third switch 44, wherein the second terminal 44S of the third switch 44 is electrically coupled to a low preset potential Vss.

Step 5 (S05): Determine whether the control terminal 42G of the second switch 42 receives the operating point voltage signal Qn. Wherein, the control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42. If step 5 (S05) is YES, the clock signal CKn-2 and the clock signal CKn + 1 intersect. The pull-down signal will be transmitted to the second end 42S of the second switch 42, and step 6 (S06) is performed in cooperation with step 4 (S04).

Step 6 (S06): At this time, the pull-down signals generated by the first switch 40 and the second switch 42 will open the third switch 44 through the control terminal 44G of the third switch 44. Therefore, the second end 44S of the third switch 44 The low preset potential Vss will pull down the gate scanning signal Gn of the first end 44D of the third switch 44 to reduce the time for preventing wrong charging, thereby increasing the charging time.

Please refer to FIG. 6, which is a flowchart of a driving method performed by the shift register 30 of the present disclosure. As in the aforementioned driving method, step one (S01) is that the n-th shift register 30 receives the gate signal of the n-1th stage to transmit the gate scanning signal Gn through the gate line 32, wherein The shift register 30 has an operating point voltage signal Qn. In view of the foregoing, the driving method further includes the following steps:

One of the first steps (S11): receiving the gate signal of the n-1th stage, and generating the operating point voltage of the shift register 30 according to the gate signal of the n-1th stage.

Step 1 bis (S12): maintaining the operating point voltage of the shift register 30 to a low preset potential.

Step 1 ter (S13): for receiving a clock signal CKn and pre-charging the operating point voltage of the shift register 30 to become a pre-charge bit, and coupling the pre-charge bit into all the bits according to the clock signal CKn The operating point voltage signal Qn is described.

Step 4 (S14): output the gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.

The first step (S11), the first step (S12), the first step (S13), and the first step (S14) of step 1 described above describe in detail how to execute step 1 (S01) of FIG. 5.

Next, step 2 (S02), step 3 (S03), step 4 (S04), step 5 (S05), and step 6 (S06) of the example shown in FIG. 5 are performed. Subsequently, step 5 (S15) in FIG. 6 is performed: receiving a feedback signal, and pulling the potential of the operating point voltage signal Qn or the gate scan signal Gn to a low preset potential according to the feedback signal.

In the embodiment of the driving method of the shift register 30 of the present disclosure, the shift register 30 also includes a shift register circuit 3002 and a sub-pull-down circuit 3004. The shift temporary storage circuit 3002 further includes an input module 50, an output module 52, a feedback module 54, a control module 56, and a pull-down maintaining module 58. The first switch 40 is a first transistor, the second switch 42 is a second transistor, and the third switch 44 is a third transistor. The relative operating relationship of the above related components in the driving method has been described in the previous implementation, so it is not repeated here.

To sum up, the gate driving circuit structure 20, the display panel 10, and the driving method of the gate driving circuit structure 20 according to the embodiments of the present disclosure can effectively pull down the gate scanning by using the newly-added sub-pull-down circuit 3004. The signal Gn reduces the time to prevent wrong charging, which can increase the charging time.

In some embodiments, the display panel may be, for example, a liquid crystal display panel, a QLED display panel, an OLED display panel, a curved display panel, or other display panels.

The above are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure in any form. Although the present disclosure has been disclosed as above with specific embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may be familiar with the present disclosure. Without departing from the scope of the technical solution of the present disclosure, when the method and technical content disclosed above can be used to make a few changes or modifications to equivalent equivalent embodiments, as long as it does not depart from the technical solution of the present disclosure, Any simple modifications, equivalent changes, and modifications made to the above embodiments by the disclosed technical essence still fall within the scope of the technical solutions of the present disclosure.

Claims

A gate driving circuit structure for a display panel of an array substrate type driving technology, wherein the gate driving circuit structure includes:

Multiple cascaded shift registers, wherein the shift registers include:

A shift register circuit that receives a gate signal of a previous stage to transmit a gate scan signal through a gate line, wherein the shift register circuit has an operating point voltage signal; and

The sub pull-down circuit is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch.

The control terminal of the first switch is electrically coupled to one of the clock signals of the second stage and the clock signal of the second stage, and the first terminal of the first switch is electrically coupled to the clock signal of the first stage. And another one of the clock signals in the latter stage,

The control terminal of the second switch is electrically coupled to the operating point voltage signal, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.

The control terminal of the third switch is electrically coupled to the second terminal of the second switch, the first terminal of the third switch is electrically coupled to the gate scan signal, and the second terminal of the third switch The terminal is electrically coupled to a low preset potential.
The gate driving circuit structure according to claim 1, wherein a control terminal of the first switch is electrically coupled to the clock signal of the first two stages, and a first terminal of the first switch is electrically coupled to the second stage of the clock signal. Clock signal.
The gate driving circuit structure according to claim 1, wherein the shift temporary storage circuit comprises:

An input module for receiving a gate-level signal of a previous stage and generating a working point voltage of the shift temporary storage circuit according to the gate-level signal of the previous stage; and

An output module, configured to receive a clock signal and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal; and The coupled operating point voltage signal and the clock signal output a gate scan signal.
The gate driving circuit structure according to claim 3, wherein the shift temporary storage circuit further comprises:

The feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal to a low preset potential according to the feedback signal.
The gate driving circuit structure according to claim 1, wherein the shift temporary storage circuit comprises:

A control module electrically coupled to the low preset potential; and

The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the operating point voltage of the shift temporary storage circuit to a low preset potential.
The gate driving circuit structure according to claim 1, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
A display panel for an array substrate type driving technology, wherein the display panel includes:

Multiple cascaded shift registers, the shift registers including a shift register circuit and a sub-pull-down circuit;

A shift register circuit for receiving a gate signal of a previous stage to transmit a gate scan signal through a gate line, wherein the shift register circuit has an operating point voltage signal; and

A sub-pull-down circuit, which is electrically coupled to the gate line and includes a first switch, a second switch, and a third switch;

Wherein, the control terminal of the first switch is electrically coupled to the clock signal of the second stage, and the first terminal of the first switch is electrically coupled to the clock signal of the second stage;

A control terminal of the second switch is electrically coupled to the operating point voltage signal, and a first terminal of the second switch is electrically coupled to a second terminal of the first switch;

The control terminal of the third switch is electrically coupled to the second terminal of the second switch, the first terminal of the third switch is electrically coupled to the gate scan signal, and the second terminal of the third switch The terminal is electrically coupled to a low preset potential.
The display panel according to claim 7, wherein the shift temporary storage circuit comprises:

An input module for receiving a gate-level signal of a previous stage and generating a working point voltage of the shift temporary storage circuit according to the gate-level signal of the previous stage; and

An output module, configured to receive a clock signal and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal; and The coupled operating point voltage signal and the clock signal output a gate scan signal.
The display panel according to claim 8, wherein the shift temporary storage circuit further comprises:

A feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal to a low preset potential according to the feedback signal.
The display panel according to claim 7, wherein the shift temporary storage circuit comprises:

A control module electrically coupled to the low preset potential; and

The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the operating point voltage of the shift temporary storage circuit to a low preset potential.
The display panel according to claim 7, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.
A driving method of a gate driving circuit structure for a display panel of an array substrate type driving technology, the gate driving circuit structure having a plurality of cascaded shift registers, wherein The driving method includes the following steps:

The shift register receives a gate signal of a previous stage to transmit a gate scanning signal through a gate line. The shift register has a voltage signal at an operating point, and the gate line is electrically coupled to a pull-down device. A circuit, the sub pull-down circuit includes a first switch, a second switch, and a third switch;

Transmitting a clock signal of a subsequent stage to a first end of the first switch;

Transmitting a first-stage clock signal to a control terminal of the first switch, wherein a first terminal of the second switch is electrically coupled to a second terminal of the first switch;

Transmitting the operating point voltage signal to a control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and

Transmitting the gate scanning signal to a first terminal of the third switch, and the second terminal of the third switch is electrically coupled to a low preset potential, where the low preset potential will pull the gate scanning signal low .
The driving method according to claim 12, for the shift register receiving a gate signal of a previous stage to transmit a gate scanning signal through a gate line, wherein the shift register has an operating point voltage Signal, wherein the driving method further includes the following steps:

Receiving the gate-level signal of the previous stage, and generating the operating point voltage of the shift register according to the gate-level signal of the previous stage;

Maintaining the operating point voltage of the shift register to a low preset potential;

Used to receive a clock signal and precharge the operating point voltage of the shift register into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal;

Outputting the gate scan signal according to the coupled operating point voltage signal and the clock signal; and

Receive a feedback signal, and pull down the potential of the gate scan signal to a low preset potential according to the feedback signal.
The driving method according to claim 13, wherein the shift register comprises a shift register circuit and a sub-pull-down circuit, and the shift register circuit is configured to receive a gate signal of a previous stage to pass The gate line transmits a gate-level scanning signal, wherein the shift register circuit has an operating point voltage signal.
The driving method according to claim 14, wherein the shift temporary storage circuit comprises:

An input module for receiving a gate-level signal of a previous stage and generating a working point voltage of the shift temporary storage circuit according to the gate-level signal of the previous stage; and

An output module, configured to receive a clock signal and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal; and The coupled operating point voltage signal and the clock signal output a gate scan signal.
The driving method according to claim 15, wherein the shift temporary storage circuit further comprises:

A feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal to a low preset potential according to the feedback signal.
The driving method according to claim 14, wherein the shift temporary storage circuit comprises:

A control module electrically coupled to the low preset potential; and

The pull-down maintaining module is electrically coupled to the control module and the low preset potential, and is controlled by the control module to maintain the operating point voltage of the shift temporary storage circuit to a low preset potential.
The driving method according to claim 14, wherein the first switch is a first transistor, the second switch is a second transistor, and the third switch is a third transistor.