CN113380168B - Shift register, gate drive circuit and display panel - Google Patents
Shift register, gate drive circuit and display panel Download PDFInfo
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- CN113380168B CN113380168B CN202110550936.1A CN202110550936A CN113380168B CN 113380168 B CN113380168 B CN 113380168B CN 202110550936 A CN202110550936 A CN 202110550936A CN 113380168 B CN113380168 B CN 113380168B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The shift register comprises a main circuit and an enable control switch, wherein the main circuit is used for outputting an initial grid scanning signal in a scanning period of a current scanning line according to a received clock signal; the enabling control switch is used for filtering the initial grid scanning signal according to the enabling signal to obtain a grid scanning signal with the trailing time shorter than that of the initial grid scanning signal, and outputting the grid scanning signal to a corresponding scanning line from the output end of the shift register; the initial grid scanning signals are filtered to improve tailing, and the phenomenon that the scanning lines of the display panel are still in an opening state when the scanning lines are closed due to the serious tailing phenomenon, so that the data voltage corresponding to the next row of scanning lines is charged to the pixel electrodes of the current scanning lines, wrong charging is formed, and the display quality of the display panel is influenced is prevented.
Description
Technical Field
The application relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display panel.
Background
The display panel has many advantages of thin body, power saving, no radiation, etc., and is widely used, such as a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a computer screen, or a notebook computer screen, etc. In display panels with various architectures, a shift register GOA (gate on array) circuit has become the mainstream due to the advantage of a narrow frame.
The gate scan signal output to the display panel by each stage of the shift register generates a tailing phenomenon due to RC delay. When the trailing phenomenon, that is, the falling edge of the gate scan signal is delayed or the time of the falling edge is too long, the scan line of the display panel should be turned off, and the trailing phenomenon is still turned on, the data voltage corresponding to the next row of scan lines is charged to the pixel electrode of the current scan line, so that a mis-charge is formed, and the display quality of the display panel is affected.
Disclosure of Invention
The application aims to provide a shift register, a grid driving circuit and a display panel, which can solve the problem of trailing of the waveform of a grid scanning signal.
The application discloses a shift register, which comprises a main circuit and an enable control switch; the main circuit is used for outputting an initial grid scanning signal in the scanning period of the current scanning line according to the received clock signal; the input end of the enable control switch is connected to the output end of the main circuit, and the control end of the enable control switch is used for receiving an enable signal; the main circuit comprises a charging module, an output module, a pull-down module and a pull-down maintaining module; the control end and the input end of the charging module are used for receiving a grid starting signal or a superior level transmission signal; the control end of the output module is connected with the output end of the charging module, and the input end of the output module is used for receiving the clock signal; the control end of the pull-down module is used for receiving a grid scanning signal output by the shift register of the rear stage, the input end of the pull-down module is connected to the output end of the output module, and the output end of the pull-down module is coupled with a standard low level signal; the input end of the pull-down maintaining module is connected with the output end of the charging module, the output end of the pull-down maintaining module is coupled with a standard low level signal, and the electric potential of the output end of the charging module is pulled down to the electric potential of the standard low level signal in non-scanning time; the enable control switch is configured to filter the initial gate scan signal according to the enable signal to obtain the gate scan signal with a trailing time shorter than that of the initial gate scan signal, and output the gate scan signal from an output end of the shift register to the current scan line.
Optionally, an input end of the enable control switch is connected to an output end of the output module, and an output end of the enable control switch is respectively connected to an input end of the pull-down module and the current scan line corresponding to the current shift register.
Optionally, an input end of the enable control switch is connected to an output end of the output module, and an output end of the enable control switch is connected to the current scan line corresponding to the current shift register.
Optionally, the enable control switch is a high-level conducting switch, the enable signal includes a high-level square wave, a rising edge of the high-level square wave corresponds to a start time of an ideal scanning period of the current scanning line, and a falling edge of the high-level square wave is earlier than an end time of the ideal scanning period of the current scanning line by a first preset time; the first preset time is greater than 1 microsecond and less than 2 microseconds.
Optionally, the enable control switch is a high-level conducting switch, the enable signal includes a high-level square wave, a rising edge of the high-level square wave corresponds to a start time of an ideal scanning period of the current scanning line, and a falling edge of the high-level square wave corresponds to an end time of the ideal scanning period of the current scanning line.
Optionally, the enable control switch is a high-level conducting switch, the enable signal includes a high-level square wave, a rising edge of the high-level square wave corresponds to a start time of an ideal scanning period of a current scanning line, and a falling edge of the high-level square wave is later than an end time of the ideal scanning period of the current scanning line by a second preset time; the second preset time is greater than 0 and less than 5 microseconds.
Optionally, the end time of the ideal scanning period corresponding to the nth shift register and the start time interval of the ideal scanning period corresponding to the (n + 2) th shift register are third preset times; the third preset time is more than or equal to 1 microsecond and less than or equal to 2 microseconds; and the value of n is more than or equal to 1, and less than or equal to the total number of the shift registers in the grid drive circuit minus 2.
Optionally, the enable signal includes a first enable signal and a second enable signal; the first enabling signal comprises a plurality of high-level square waves, and the high-level square waves are arranged corresponding to the ideal scanning periods of the scanning lines in odd columns; the second enabling signal comprises a plurality of high-level square waves which are arranged corresponding to ideal scanning periods of a plurality of scanning lines in even columns.
The application also discloses a gate driving circuit, which comprises a plurality of cascaded shift registers.
The application also discloses a display panel, including many scanning lines and as above gate drive circuit, every in the gate drive circuit shift register's output corresponds and connects in one the scanning line, and export gate drive circuit grid scanning signal is current the scanning line.
Compared with a scheme of directly outputting an initial grid scanning signal, the method has the advantages that the enabling control switch is arranged at the output end of the main circuit of each stage of the shift register, the enabling control switch filters the initial grid scanning signal according to the enabling signal to obtain the grid scanning signal with the trailing time shorter than that of the initial grid scanning signal, the grid scanning signal is output to the corresponding scanning line from the output end of the shift register, the enabling control switch is turned off at the falling edge of the grid scanning signal, the trailing part of the grid scanning signal cannot be output, filtering is achieved, the trailing problem of the grid scanning signal output to the current scanning line is improved, mis-charging is prevented, and display quality is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic view of an exemplary display device of the present application;
FIG. 2 is a diagram illustrating a gate scan signal charging period waveform according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a gate driving circuit of a display panel according to another embodiment of the present application;
FIG. 5 is a schematic diagram illustrating waveforms of gate scan signals after improvement according to an embodiment of the present application;
FIG. 6 is a waveform diagram of an enable signal according to an embodiment of the present application;
FIG. 7 is a waveform diagram of an enable signal according to an embodiment of the present application;
FIG. 8 is a waveform diagram of another enable signal of an embodiment of the present application;
FIG. 9 is a waveform diagram of an enable signal according to an embodiment of the present application;
fig. 10 is a schematic diagram of a gate driving circuit of a display panel according to another embodiment of the present application;
FIG. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;
fig. 12 is a schematic diagram of a display device according to an embodiment of the present application.
100, a display panel; 200. a gate drive circuit; 210. a drive circuit board; 220. a driving chip; 230. a shift register; 240. a main circuit; 241. a charging module; 242. an output module; 243. a pull-down module; 244. a pull-down maintenance module; 245. a first pull-down maintenance module; 246. a second pull-down maintenance module; 250. enabling the control switch; 251. a first enable control switch; 252. a second enable control switch; 300. a display device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
Fig. 1 is an exemplary display device in the present application, where the display device 300 includes a display panel 100 and a driving circuit board 210, the display panel includes a gate driving circuit 200, the driving circuit board 210 is connected to the display panel through a source chip on film 220, the display panel 100 includes a plurality of scanning lines, the gate driving circuit 200 includes a plurality of cascaded shift registers 230, an output end of each shift register 230 is correspondingly connected to one scanning line, and each shift register 230 outputs a gate scanning signal.
Fig. 2 is a waveform diagram of a Gate scan signal Charging period of the display panel 100 of fig. 1, where due to an RC delay effect, a first Charging phase (i.e., Data Tr) of a Gate scan signal is performed, where a waveform rises in a curve, and then enters a normal Charging time phase (i.e., Charging time), the waveform is gentle, and then the Gate scan signal waveform is performed in a third phase (i.e., Gate IF), where in an ideal state, the waveform should change from a high level to a low level instantly, but due to the RC delay, the waveform curves down and exhibits a tailing effect, where a duration of the third phase is a duration of a tailing time, and the tailing time is a time from a highest point to a lowest point of the Gate scan signal waveform. When the scan line of the display panel 100 should be turned off, the tailing phenomenon is still in an on state, which may cause the pixel corresponding to the current scan line to be charged to the voltage of the pixel corresponding to the next row of scan line by mistake, resulting in a wrong charge, which indirectly causes insufficient charge, and further affects the display of the display panel 100.
In order to improve the tailing problem, the application improves the grid drive circuit of the display device: fig. 3 is a modified schematic diagram of a gate driving circuit, where the gate driving circuit 200 includes a plurality of cascaded shift registers 230, an output terminal of each shift register 230 is correspondingly connected to one scan line, and each shift register 230 includes a main circuit 240 and an enable control switch 250; the main circuit 240 is configured to output an initial gate scan signal in a scan period of a current scan line according to a received clock signal; the input terminal of the enable control switch 250 is connected to the output terminal of the main circuit 240, and the control terminal of the enable control switch 250 is configured to receive an enable signal; the enable control switch 250 is configured to filter the initial gate scan signal according to the enable signal to obtain the gate scan signal with a tail time shorter than that of the initial gate scan signal, and output the gate scan signal from the output end of the shift register 230 to the current scan line.
For an exemplary gate driving circuit, an enable control switch is arranged at an output end of a main circuit of each stage of shift register, the enable control switch filters the initial gate scanning signal according to the enable signal to obtain the gate scanning signal with the trailing time shorter than that of the initial gate scanning signal, the gate scanning signal is output to the corresponding scanning line from the output end of the shift register, and the enable control switch is turned off at the falling edge of the gate scanning signal, so that the trailing part of the gate scanning signal cannot be output to realize filtering, the trailing problem of the gate scanning signal output to the current scanning line is improved, and mischarging is prevented.
As shown in fig. 4, in particular, the main circuit 240 in the shift register in the gate driving circuit includes a charging module 241, an output module 242, a pull-down module 243, and a pull-down maintaining module 244; the control end and the input end of the charging module 241 are configured to receive a gate start signal or a superior level transmission signal, where the superior level transmission signal is a level transmission signal corresponding to the upper two-level shift register 230 corresponding to the current-level shift register 230, and may also be a level transmission signal corresponding to the upper shift register 230; a control end of the output module 242 is connected to an output end of the charging module 241, and an input end of the output module 242 is configured to receive the clock signal; the control end of the pull-down module 243 is configured to receive the gate scan signal output by the shift register 230 of the subsequent stage, and the output end of the pull-down module 243 is coupled to a standard low level signal VSS; the input end of the pull-down maintaining module 244 is connected to the output end of the charging module 241, the output end of the pull-down maintaining module 244 is coupled to a standard low level signal VSS, and the voltage level of the output end of the charging module 241 is pulled down to the voltage level of the standard low level signal during the non-scanning time; the pull-down maintaining module includes a first pull-down maintaining module 245 and a second pull-down maintaining module 246, and the second pull-down maintaining module 246 is connected to the output terminal of the charging module, wherein the standard low signal is a reference level of a logic low level, such as 0 v.
The input end of the enable control switch is connected to the output end of the output module, the output end of the enable control switch is respectively connected to the input end of the pull-down module and the current scanning line corresponding to the shift register, the pull-down module directly pulls down the potential of the output end of the enable control switch to the potential of the standard low level signal, the first pull-down maintaining module 245 and the second pull-down maintaining module 246 pull down the potential of the output end of the charging module 241 to the potential of the standard low level signal, and thus the potential of the whole shift register is pulled down to prevent the output of the next shift register from being influenced.
In addition, more specifically, for the above modules, the corresponding switches are mainly selected to be connected, the charging module 241 includes a first switching tube T1, a control end and an input end of the first switching tube T1 are used for receiving a gate start signal or a higher-level transmission signal, the input module includes a fifth switching tube T5 and a second switching tube T2, control ends of the fifth switching tube T5 and the second switching tube T2 are simultaneously connected to an output end of the first switch T1, input ends of the fifth switching tube T5 and the second switching tube T2 are simultaneously connected to the clock signal, and an output end of the fifth switching tube T5 is connected to a control end and an input end of the first switching tube T1; the enable control switch 250 comprises a sixth switch tube T6, a control terminal of the sixth switch tube T6 is configured to receive an enable signal, and an input terminal of the sixth switch tube T6 is connected to the output terminal of the second switch tube T2; the pull-down module 243 includes a fourth switch tube T4 and a third switch tube T3, control ends of the fourth switch tube T4 and the third switch tube T3 are simultaneously connected to a scan line corresponding to the backward 4-stage shift register 230 of the current stage scan line, output ends of the fourth switch tube T4 and the third switch tube T3 are simultaneously connected to a standard low-level signal, an input end of the fourth switch tube T4 is connected to a control end of the second switch tube T2, and an input end of the third switch tube T3 is connected to an output end of the second switch tube T2.
Fig. 5 is a schematic diagram illustrating a waveform of an improved gate scan signal according to an embodiment of the present application, in which the gate driving circuit disclosed in the above embodiment is to filter an initial gate scan signal G (n) output by an output module to obtain a gate scan signal G' (n) with improved tailing; wherein Q is a signal waveform of the control end of the output module 242, oe (n) is a signal waveform of the enable signal, and T is an ideal scanning period of the current scanning line that is not affected by the impedance to generate deformation; the enable signal oe (n) controls the enable control switch 242 to filter the initial gate scanning signal G (n) to obtain a gate scanning signal G' (n), and when the initial gate scanning signal of each stage is switched from a high level to a low level, the enable control switch is connected to an enable signal to rapidly turn off the gate scanning signal, thereby preventing mis-charging and improving the tailing problem.
Specific waveforms of the enable signal of the present application include, but are not limited to, the following three waveform diagrams:
fig. 6 is a schematic waveform diagram of one of the enable signals of the present application, where N clock signals are shown, and each of the clock signals includes a plurality of high-level square waves to drive each stage of shift registers of the gate driving circuit; taking the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 as an example, the first high-level square wave of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 is used for outputting initial gate scan signals G1, G2, G3 and G4 of the first-stage to fourth-stage shift registers, respectively, the falling edge of G1 corresponds to the rising edge of G3, the falling edge of G3 corresponds to the rising edge of G5, the falling edge of Gn corresponds to the falling edge of Gn +2, and n is a positive integer greater than or equal to 1.
The enabling control switch is a high-level conducting switch, the enabling signal comprises a high-level square wave, the rising edge of the high-level square wave corresponds to the starting moment of the ideal scanning period of the current scanning line, and the falling edge of the high-level square wave is earlier than the ending moment of the ideal scanning period of the current scanning line by a first preset time; the first preset time (t1) is greater than 1 microsecond and less than 2 microseconds, each enable signal corresponds to one enable control switch, and each enable signal is output by a corresponding pin.
In order to reduce the number of enable signals, the present application improves to obtain enable signals OE (1) and OE (2) as in fig. 6;
namely, the enable signals comprise a first enable signal OE (1) and a second enable signal OE (2); the first enabling signal comprises a plurality of high-level square waves which are arranged corresponding to the ideal scanning period of the scanning lines in the odd columns; the second enabling signal comprises a plurality of high-level square waves which are arranged corresponding to ideal scanning periods of the scanning lines in even columns. In this way, only two enable signals are needed to complete the control of all the enable control switches, as shown in fig. 4, the control end of the enable control switch in the first stage of shift register is connected to the high-level square wave OE1 in the first enable signal OE (1), the control end of the third stage of enable control switch is connected to the OE3 in the first enable signal OE (1), and the time interval between the falling edge of OE1 and the rising edge of OE3 is the first preset time t 1; similarly, the control terminal of the enable control switch in the second stage shift register is connected to OE2, the control terminal of the fourth stage enable control switch is connected to OE4, and the interval between the falling edge of OE2 and the rising edge of OE4 is also the first predetermined time t 1.
The embodiment improves the tailing problem under the conditions of reducing the use of the number of the enabling signals and reducing the improvement cost; specifically, the first stage shift register improves the tailing problem in the high level period of OE1, and in other high-voltage square wave periods subsequent to OE1, although the enable control switch of the first stage shift register is also turned on, the output module no longer outputs the signal, and the pull-down module operates at this time to pull down the potential at the input end of the pull-down module to the potential of the standard low level signal, so that the embodiment shown in fig. 6 has no influence on the waveform of the gate scan signal, but can greatly reduce the number of enable signals, and reduce the cost and the wiring pressure.
Fig. 7 is a waveform diagram of another enable signal in the enable signals of the present application, and unlike the waveform diagram of the enable signal in fig. 6, a rising edge of the high-level square wave corresponds to a start time of an ideal scan period of a current scan line, and a falling edge of the high-level square wave is later than an end time of the ideal scan period of the current scan line by a second preset time; each enable signal corresponds to one enable control switch, each enable signal is output by a corresponding pin, the second preset time (t2) is greater than 0 and less than 5 microseconds, if the trailing time is within (0,5) us, the trailing time is allowed in practical situations, the charging result of the pixel corresponding to the scanning line cannot be influenced, but because the trailing time is still in fact, the effect of the trailing edge of the high-level square wave is the best 2us later than the end time of the ideal scanning period of the current scanning line.
Also in order to reduce the number of enable signals, the present application improves to obtain enable signals OE (1) and OE (2) as in fig. 7; the rising edge of OE (1) is later than the T start time by T1, the falling edge is later than the T end time by T2, T1 is larger than T2 by T3, i.e. T1 is T2+ T3, and T3 is larger than 1 and smaller than 2 us; and T1 is less than or equal to 5us, so the enable control switches of the corresponding odd columns can be connected to a pin to receive a first enable signal OE (1), the high-level square waves of OE (1) can be passed from the first square wave to the nth square wave to correspond to the first gate scan signal to the 2N-1 gate scan signal in the gate scan signals, the enable control switches of the corresponding even columns can be connected to a pin to receive a second enable signal OE (2), and the high-level square waves of OE (2) can be passed from the first square wave to the nth square wave to correspond to the second gate scan signal to the 2N gate scan signal in the gate scan signals, thereby greatly reducing the number of enable signals, and reducing the cost and wiring pressure.
Of course, it may also be set that only the rising edge of the first high-level square wave and the rising edge of the second high-level square wave correspond to the start time of the ideal scanning period of the current scanning line, and from the third high-level square wave, whether the rising edge of the high-level square wave corresponds to the start time of the ideal scanning period of the current scanning line is not limited, and only the falling edge of the high-level square wave is limited to be 0 to 5us later than the end time of the ideal scanning period of the current scanning line, which may be specifically shown in fig. 8.
Fig. 9 is a waveform diagram of another enable signal in the enable signals of the present application, where a rising edge of the high-level square wave corresponds to a start time of an ideal scan period of a current scan line, a falling edge of the high-level square wave corresponds to an end time of the ideal scan period of the current scan line, and when the end time of the ideal scan period of the current scan line is reached, the enable signals simultaneously control to turn on the enable control switches, so as to directly pull down the current scan line from a high level to a potential of a standard low-level signal, thereby improving tailing.
In order to reduce the number of enable signals, the end time of the ideal scan period corresponding to the nth shift register 230 and the start time interval of the ideal scan period corresponding to the (n + 2) th shift register 230 are third preset times; the value of n is more than or equal to 1, and less than or equal to the total number of the shift registers in the grid drive circuit minus 2; the third predetermined time (t3) is greater than or equal to 1 microsecond and less than or equal to 2 microseconds, because the end time of the ideal scanning period corresponding to the nth shift register 230 is normal, which corresponds exactly to the start of the ideal scan period corresponding to the (n + 2) th of said shift register 230, such that the enable signal will stay high, thereby affecting the normal charging of the pixel, the end time of the ideal scanning period corresponding to the nth shift register 230, the ideal scan period corresponding to the (n + 2) th shift register 230 starts at an interval of 1us to 2us, the enable signal has a short low level, so that the normal operation of the scan signal is not affected, specifically, the end time of the ideal scanning period corresponding to the nth shift register 230 is generally set, the interval of the start time of the ideal scanning period corresponding to the (n + 2) th shift register 230 is 2 us.
As shown in fig. 10, as another embodiment of the present application, a gate driving circuit 200 of a display panel 100 is disclosed, which is different from the gate driving circuit 200, wherein an input end of the enable control switch 250 is respectively connected to a second output end of the output module 242 and an input end of the pull-down module 243, and an output end of the enable control switch 250 outputs the filtered gate scan signal to the scan line corresponding to the current shift register 230.
As shown in fig. 11, the present application further discloses a gate driving circuit 200 of a display panel 100, and specifically as shown in the following figure, the number of the enable control switches 250 is two, and the enable control switches include a first enable control switch 251 and a second enable control switch 252, wherein a control terminal of the first enable control switch 251 is configured to receive an enable signal, an input terminal of the first enable control switch 251 is connected to a second output terminal of the output module 242, an output terminal of the enable control switch 250 is connected to an input terminal of the pull-down module 243, a control terminal of the second enable control switch 252 is configured to receive an enable signal connected to a control terminal of the first enable control switch 251, an input terminal of the second enable control switch 252 is connected to an output terminal of the first enable control switch 251, a gate scan signal filtered by an output terminal of the first enable control switch 251 of the second enable control switch 252 is filtered again, and outputs the signal to the scan line corresponding to the current shift register 230 through the output terminal, twice filtering is performed, and the influence of T3 on the waveform of the finally output gate scan signal can be reduced.
As shown in fig. 12, as an embodiment of the present application, a display device is disclosed, where the display device 300 includes a driving circuit board 210 and a display panel 100, the display panel 100 includes a gate driving circuit 230 disclosed in any one of the present application and a plurality of scan lines, an output end of each shift register in the gate driving circuit is correspondingly connected to one scan line, and outputs a gate scanning signal of the gate driving circuit to the current scan line; specifically, the driving circuit board 210 generates an enable signal and outputs the enable signal to a control terminal of an enable control switch in the gate driving circuit 230, controls the enable control switch to be turned on or off, and performs filtering processing on an initial gate scanning signal output by a main circuit in the gate driving circuit 230 to obtain a gate scanning signal with a trailing time shorter than that of the initial gate scanning signal, so as to drive the display panel 100.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (9)
1. A shift register, comprising:
the main circuit is used for outputting an initial grid scanning signal in the scanning period of the current scanning line according to the received clock signal; and
the input end of the enable control switch is connected with the output end of the main circuit, and the control end of the enable control switch is used for receiving an enable signal;
the main circuit comprises:
the control end and the input end of the charging module are respectively used for receiving a grid starting signal or a superior level transmission signal;
the control end of the output module is connected with the output end of the charging module, and the input end of the output module is used for receiving the clock signal;
the control end of the pull-down module is used for receiving a grid scanning signal output by the shift register of the rear stage, the input end of the pull-down module is connected to the output end of the output module, and the output end of the pull-down module is coupled with a standard low level signal; and
the input end of the pull-down maintaining module is connected with the output end of the charging module, the output end of the pull-down maintaining module is coupled with a standard low level signal, and the potential of the output end of the charging module is pulled down to the potential of the standard low level signal in the non-scanning time;
the enable control switch is used for filtering the initial grid scanning signal according to the enable signal to obtain a grid scanning signal with the trailing time shorter than that of the initial grid scanning signal, and outputting the grid scanning signal to the current scanning line from the output end of the shift register;
the input end of the enable control switch is connected to the output end of the output module, and the output end of the enable control switch is respectively connected to the input end of the pull-down module and the current scanning line corresponding to the current shift register;
and each enabling control switch filters the initial grid scanning signal corresponding to one row of scanning lines to output.
2. A shift register as claimed in claim 1, wherein the enable control switch is a high-level conducting switch, the enable signal comprises a high-level square wave, a rising edge of the high-level square wave corresponds to a start time of an ideal scan period of the current scan line, and a falling edge of the high-level square wave is earlier than an end time of the ideal scan period of the current scan line by a first preset time;
the first preset time is greater than 1 microsecond and less than 2 microseconds.
3. A shift register as claimed in claim 1, characterized in that the enable control switch is a high-level conducting switch, the enable signal comprises a high-level square wave, the rising edge of the high-level square wave corresponds to the start time of the ideal scan period of the current scan line, and the falling edge of the high-level square wave corresponds to the end time of the ideal scan period of the current scan line.
4. A shift register as claimed in claim 1, wherein the enable control switch is a high-level conducting switch, the enable signal comprises a high-level square wave, a rising edge of the high-level square wave corresponds to a start time of an ideal scan period of a current scan line, and a falling edge of the high-level square wave is later than an end time of the ideal scan period of the current scan line by a second preset time;
the second preset time is greater than 0 and less than 5 microseconds.
5. A shift register as claimed in claim 3, characterized in that the end time of the ideal scan cycle corresponding to the nth shift register is separated from the start time of the ideal scan cycle corresponding to the (n + 2) th shift register by a third predetermined time;
the third preset time is more than or equal to 1 microsecond and less than or equal to 2 microseconds;
and the value of n is more than or equal to 1, and less than or equal to the total number of the shift registers in the grid drive circuit minus 2.
6. A shift register as claimed in any one of claims 2 to 5, in which the enable signal comprises a first enable signal and a second enable signal;
the first enabling signal comprises a plurality of high-level square waves, and the high-level square waves are arranged corresponding to the ideal scanning periods of the scanning lines in odd columns;
the second enable signal comprises a plurality of high-level square waves which are arranged corresponding to ideal scanning periods of a plurality of scanning lines in even columns.
7. A shift register, comprising:
the main circuit is used for outputting an initial grid scanning signal in the scanning period of the current scanning line according to the received clock signal; and
the input end of the enable control switch is connected with the output end of the main circuit, and the control end of the enable control switch is used for receiving an enable signal;
the main circuit comprises:
the control end and the input end of the charging module are respectively used for receiving a grid starting signal or a superior level transmission signal;
the control end of the output module is connected with the output end of the charging module, and the input end of the output module is used for receiving the clock signal;
the control end of the pull-down module is used for receiving a grid scanning signal output by the shift register of the rear stage, the input end of the pull-down module is connected to the output end of the output module, and the output end of the pull-down module is coupled with a standard low level signal; and
the input end of the pull-down maintaining module is connected with the output end of the charging module, the output end of the pull-down maintaining module is coupled with a standard low level signal, and the potential of the output end of the charging module is pulled down to the potential of the standard low level signal in the non-scanning time;
the enable control switch is used for filtering the initial grid scanning signal according to the enable signal to obtain a grid scanning signal with the trailing time shorter than that of the initial grid scanning signal, and outputting the grid scanning signal to the current scanning line from the output end of the shift register;
the input end of the enable control switch is connected to the output end of the output module, and the output end of the enable control switch is respectively connected to the input end of the pull-down module and the current scanning line corresponding to the current shift register;
the input end of the enable control switch is connected with the output end of the output module, and the output end of the enable control switch is connected with the current scanning line corresponding to the current shift register;
and each enabling control switch filters the initial grid scanning signal corresponding to one row of scanning lines to output.
8. A gate drive circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 7.
9. A display panel, comprising a plurality of scan lines and the gate driving circuit as claimed in claim 8, wherein the output terminal of each of the shift registers in the gate driving circuit is connected to one of the scan lines, and outputs the gate scan signal of the gate driving circuit to the current scan line.
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