CN104835466B - Scan driving circuit, array substrate, display device and driving method - Google Patents
Scan driving circuit, array substrate, display device and driving method Download PDFInfo
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- CN104835466B CN104835466B CN201510260153.4A CN201510260153A CN104835466B CN 104835466 B CN104835466 B CN 104835466B CN 201510260153 A CN201510260153 A CN 201510260153A CN 104835466 B CN104835466 B CN 104835466B
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Abstract
The invention discloses a scan driving circuit, a driving method of the scan driving circuit, an array substrate and a display device. The scan driving circuit comprises a plurality of output ends, and is characterized by further comprising a plurality of stages of shift register units and a plurality of stages of switching units, wherein the plurality of stages of shift register units are used for outputting pulse signals stage by stage under driving of at least one first clock signal; the plurality of stages of switching units are connected with the plurality of stages of shift register units respectively, and each switching unit comprises at least two switching elements; a first end of any one of the switching elements is connected to one of at least two second clock signals, a second end is connected to an output end of the scan driving circuit, and a third end is connected to the shift register unit which is connected with the switching unit where the switching element is located; the switching element is used for conducting the first end and the second end when the third end receives the pulse signals; and a period of the first clock signal is greater than a period of the second clock signal. Technical problems of single output signal time sequence and high change cost of an existing scan driving circuit can be solved.
Description
Technical field
The present invention relates to field of liquid crystal display, and in particular to a kind of scan drive circuit, array base palte, display device and drive
Dynamic method.
Background technology
Existing GOA (Gate Driver On Array, array base palte row drives) technology is by by scan drive circuit
It is produced on the array base palte of display floater, saves the processing technology and binding technique of scanning drive chip, battle array can be reduced
The manufacturing cost of row substrate and display floater.Due to being directly produced on array base palte, existing scan drive circuit, especially
With reference to the scan drive circuit of double grid (Dual-Gate) technique, after completing generally there is fixed and single circuit to tie
Structure, type of drive and output signal sequential, and be difficult to be modified.Therefore, if for faulty restoration, product reformation or product
The demands of aspect such as upgrading, when being adjusted original output signal sequential of scan drive circuit, then generally require to abandon
Original circuit simultaneously re-starts the design or making of circuit structure so that cost is greatly increased.
The content of the invention
For defect of the prior art, the present invention provides a kind of scan drive circuit, array base palte, display device and drive
Dynamic method, can change the driver' s timing of drive circuit, and low in energy consumption.
In a first aspect, a kind of scan drive circuit, including several outfans, it is characterised in that the circuit also includes：
Multi-stage shift register unit, the multi-stage shift register unit is used at least one first clock signals
Output pulse signal step by step under driving；
The multiple-pole switch unit being connected one by one with the multi-stage shift register unit, the switch element includes at least two
Individual switch element；
Wherein, the first end of any one of switch element connects at least two second clock signals, the
Two ends connect an outfan of the scan drive circuit, and the switch element that three-terminal link is located with the switch element is connected
Shift register cell；The switch element is used for the conducting first end and second when the 3rd termination receives the pulse signal
End；Cycle of the cycle of first clock signal more than the second clock signal.
Alternatively, if the scan drive circuit is included with all switch elements in all switch elements correspondingly
Dry outfan；It is connected with the second end of the switch element corresponding to the outfan of either switch element.
Alternatively, the scan drive circuit includes m levels shift register cell and m level switch elements；The m levels switch
Any level switch element in unit includes n switch element, and the 3rd end of the n switch element is all connected with the displacement of this grade
Register cell；The first end of the n switch element and the one-to-one connection of n second clock signal；
Second end of all of switch element and the one-to-one connection of m × n outfan in the m levels switch element；It is described
M, n are all higher than being equal to 2.
Alternatively, corresponding to each switch element, the scan drive circuit includes one group of outfan；Except the first order
Outside any level described in switch element, the second end and in switch element described in upper level of a switch element open
The second end for closing element connects the same outfan of the scan drive circuit；It is all described in the same switch element
The outfan that second end of switch element is connected is different.
Alternatively, the scan drive circuit includes m levels shift register cell and m level switch elements；The m levels switch
Any level switch element in unit includes n switch element, and the 3rd end of the n switch element is posted with the displacement of this grade
Storage unit is connected, the first end of the n switch element and the one-to-one connection of n second clock signal；In addition to the first order
N switch element of any level switch element include a first kind switch element, n-2 Equations of The Second Kind switch element and one
3rd class switch element；
The scan drive circuit includes n+ (m-1) (n-1) individual outfans, front n outfan and first order switch element
N switch element the one-to-one connection in the second end, afterwards (m-1) (n-1) individual outfan and all of Equations of The Second Kind switch element and
The one-to-one connection of all of 3rd class switch element；Second end and first of the first kind switch element in the switch element of the second level
Second end of a switch element in level switch element is connected；In any level switch element in addition to the first order and the second level
The second end of first kind switch element be connected with the second end of the 3rd class switch element in upper level switch element；The m,
N is all higher than being equal to 2.
Alternatively, corresponding to each described outfan of the scan drive circuit, it is provided with one and connects the outfan
Reset unit；Arbitrary reset unit is used to be pulled down to the current potential of the output for being connected when reset signal is received
Predetermined level.
Alternatively, arbitrary reset unit include first film transistor, the source electrode of the first film transistor and
One in drain electrode connects the outfan that the reset unit is connected, another connection predetermined level；The first film crystal
Shift register cell described in the grid connection one-level of pipe, the reset signal is the described of this grade of shift register cell output
Pulse signal；
The series of the shift register cell that arbitrary first film transistor is connected is more than first thin corresponding to this
The series of the shift register cell of the outfan that film transistor is connected.
Alternatively, the switch element is thin film transistor (TFT), and the first end of the switch element is respectively thin with the second end
One in the source electrode and drain electrode of film transistor；3rd end of the switch element is the grid of thin film transistor (TFT).
Alternatively, arbitrary shift register cell include input, outfan and reset terminal, for it is described at least
Input is connect into signal under the driving of one the first clock signal to export in output time delay；Except the last
In the multi-stage shift register unit, the outfan connection next stage shift register cell of any level shift register cell
Input；In the multi-stage shift register unit in addition to the first order, the output of any level shift register cell
The reset terminal of end connection upper level shift register cell.
Second aspect, present invention also offers a kind of array base palte, including the above-mentioned scan drive circuit of any one.
The third aspect, present invention also offers a kind of display device, including the above-mentioned array base palte of any one.
Fourth aspect, present invention also offers a kind of driving method of scan drive circuit, including：
By N number of first clock signal input with the period 1 to the multi-stage shift register unit, so that described
Multi-stage shift register unit step by step output pulse width be the period 1 1/N pulse signal；
By at least two second clocks signal input with second round to the multiple-pole switch unit, so that institute
State multiple-pole switch unit under the control of the pulse signal according at least two second clocks signal sequentially generate for
In the scanning signal that the output of each scan drive circuit is exported；
The period 1 is N times of the second round, and the N is more than or equal to 2.
Alternatively, the summation of the dutycycle of at least two second clocks signal is more than 100%.
As shown from the above technical solution, scan drive circuit provided by the present invention can be believed with least two second clocks
Number it is different and there are different output signal sequential, thus can be by the input signal outside adjustment come in various outputs
Flexibly switch between signal sequence, thus can to a certain extent solve the output signal sequential list of existing scan drive circuit
One and change high cost technical problem, be conducive to the reduction of cost under faulty restoration, product reformation or product up-gradation scene.Separately
On the one hand, due to the present invention in a shift register cell can be used for the output of fine scanning signal, it is thus of the invention
Be conducive to the reduction of electronic component total quantity and the reduction of corresponding cost.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description makees a simple introduction, it should be apparent that, drawings in the following description are these
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of electrical block diagram of scan drive circuit in one embodiment of the invention；
Fig. 2 is a kind of electrical block diagram of shift register cell in one embodiment of the invention；
Fig. 3 is the circuit timing diagram of shift register cell shown in Fig. 2；
Fig. 4 is a kind of sequential chart of drive signal of the scan drive circuit shown in Fig. 1；
Fig. 5 is the sequential chart of another drive signal of the scan drive circuit shown in Fig. 1；
Fig. 6 is the sequential chart of another kind of drive signal of the scan drive circuit shown in Fig. 1；
Fig. 7 is the sequential chart of another drive signal of the scan drive circuit shown in Fig. 1；
Fig. 8 is a kind of electrical block diagram of scan drive circuit in further embodiment of this invention；
Fig. 9 is a kind of sequential chart of drive signal of the scan drive circuit shown in Fig. 8；
Figure 10 is the sequential chart of another drive signal of the scan drive circuit shown in Fig. 8；
Figure 11 is a kind of electrical block diagram of scan drive circuit in another embodiment of the present invention；
Figure 12 is a kind of electrical block diagram of scan drive circuit in further embodiment of the present invention.
Specific embodiment
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than the embodiment of whole.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The embodiment of the present invention provides a kind of scan drive circuit with several outfans, and the circuit includes stages shift
Register cell and the multiple-pole switch unit being connected one by one with the multi-stage shift register unit, stages shift deposit therein
Device unit is used under the driving of at least one first clock signals output pulse signal step by step.It is understood that by scanning
The basic function of drive circuit, can be with those skilled in the art it can be deduced that above-mentioned outfan is for scanning signal
The various structures or existence form of understanding.It will also be appreciated that at least one first clock signals are with some cycles
Clock signal, each shift register cell can export above-mentioned pulse letter under the driving of first clock signal
Number, and multi-stage shift register unit can under suitable cascade system with least one first clock signals matchingly by
Level output pulse signal.It should be noted that the multi-stage shift register unit with above-mentioned functions and characteristic is ability technology
Personnel are readily obtained according to shift-register circuit of the prior art, will not be described here.
On the other hand, above-mentioned switch element includes at least two switch elements.Wherein, the first of any one switch element
One at least two second clock signals of end connection, the second end connects an outfan of above-mentioned scan drive circuit, the
The shift register cell that the switch element that three-terminal link is located with the switch element is connected；Above-mentioned switch element is used for the 3rd
Conducting first end and the second end when termination receives above-mentioned pulse signal；When the cycle of above-mentioned first clock signal is more than above-mentioned second
The cycle of clock signal.
It should be understood that the specific implementation of switch element can be in the prior art electronic devices and components according to device
Part characteristic is selected, such as transistor, Hall switching element and relay etc..It will also be appreciated that above-mentioned at least two
Second clock signal is one group has a clock signal of some cycles, and the cycle of second clock signal is when being less than above-mentioned first
The cycle of clock signal.All switches based on this, in the presence of the pulse signal for exporting line by line, in above-mentioned multiple-pole switch unit
Element can be opened step by step so that corresponding outfan can be exported and a second clock signal waveform identical scanning signal.
It is not difficult to visualize, under a kind of specific application scenarios, the embodiment of the present invention can realize pulse with reference to appropriate setting
Scanning signal several outputs output step by step (specific example can participate in embodiments below).Additionally,
The different settings of each side according to embodiments of the present invention, the embodiment of the present invention can also realize the scanning letter of various multi-forms
Number output.
It should be noted that above-mentioned, " (any one switch element) second end connects the one of above-mentioned scan drive circuit
Individual outfan " is not precluded from the feelings of the same outfan of the second end connection scan drive circuit of plural switch element
Condition, but in order that scan drive circuit can according to needed for concrete application scene will as be scanned the output of signal,
Those skilled in the art can be electric with the second end and which turntable driving that each switch element is selected by the way of appropriate
The outfan on road is connected, and the present invention is without limitation.
Compared with prior art, the scan drive circuit that the embodiment of the present invention is provided can be with least two second clocks
Signal different and there are different output signal sequential, thus can be by the input signal outside adjustment come various defeated
To go out flexibly switch between signal sequence, thus can to a certain extent solve the output signal sequential of existing scan drive circuit
Technical problem that is single and changing high cost, is conducive to the reduction of cost under faulty restoration, product reformation or product up-gradation scene.
On the other hand, due to the embodiment of the present invention in a shift register cell can be used for the output of fine scanning signal, because
And the embodiment of the present invention is conducive to the reduction of electronic component total quantity and the reduction of corresponding cost.
Used as a specific example, Fig. 1 is a kind of circuit structure of scan drive circuit in one embodiment of the invention
Schematic diagram.As shown in figure 1, the scan drive circuit includes multiple shift register cells (such as U1, U2, U3 in Fig. 1, not entirely
Portion illustrates), multiple switch unit (such as S1, S2 in Fig. 1, being not entirely shown), wherein：
There is certain cascade connection between above-mentioned multiple shift register cells, specifically include：First order shift LD
Input IN connection initial signals STV of device unit U1, reset terminal connects the outfan of second level shift register cell U2
OUT；The input connection upper level displacement of remaining shift register cell at different levels outside first order shift register cell U1 is posted
The outfan of storage unit, reset terminal connects the outfan of next stage shift register cell, such as second level shift register
The input IN of unit U2 connects the outfan OUT, first order shift register cell U1 of first order shift register cell U1
Reset terminal connect second level shift register cell U2 outfan OUT.Meanwhile, first order shift register cell U1 with open
Close cell S 1 to be connected, second level shift register cell U2 is connected with switch element S2, the like.In addition, multiple shiftings
Driving signal input CLKA, CLKB and VSS of bit register unit be respectively connecting to two the first clock signal clk A,
CLKB and predeterminated voltage VSS.
Specifically, Fig. 2 is a kind of electrical block diagram of shift register cell in one embodiment of the invention.As schemed
Shown in 2, any of the above-described grade of shift register cell includes thin film transistor (TFT) T1~T4, electric capacity C1~C2.Wherein, thin film is brilliant
The grid of body pipe T1 is connected after being connected with source electrode with the input IN of the shift register cell, and drain electrode is with thin film transistor (TFT) T2's
Source electrode connects.The grid of thin film transistor (TFT) T2 connects answering for the shift register cell after being connected with the grid of thin film transistor (TFT) T4
Position end, drain electrode connects the predeterminated voltage VSS of the shift register cell after being connected with the drain electrode of thin film transistor (TFT) T4.Film crystal
Pipe T4 connects the circuit node P between thin film transistor (TFT) T1 and thin film transistor (TFT) T2 through electric capacity C2, and is connected by electric capacity C1
It is connected to CLKA.The grid of thin film transistor (TFT) T3 is connected to circuit node P, and source electrode is connected to the input of the shift register cell
CLKB, drain electrode connects the outfan OUT of the shift register cell.
Fig. 3 is the circuit timing diagram of shift register cell shown in Fig. 2.As shown in figure 3, above-mentioned shift register cell
Circuit work schedule is as described below：
When CLKA be high level, CLKB be low level when, circuit node P be high level, now thin film transistor (TFT) T3 open,
Outfan OUT (n) is low level.When CLKA be low level, CLKB be high level when, circuit node P be low level, film crystal
Pipe T3 does not work, and outfan OUT (n) is low level.
When input IN be high level, CLKA be high level, CLKB be low level when, electric capacity C2 charges first, reaches thin
After the gate turn-on voltage of film transistor T3, outfan OUT is high level；In next sequential, because electric capacity C2 keeps filling
Electricity condition, thin film transistor (TFT) T3 is opened, and now, is exported after the high level of CLKB is amplified.
When reset signal RESET is high level, thin film transistor (TFT) T2 and T4 are opened, and the voltage at electric capacity C2 two ends is forced
Predeterminated voltage VSS is pulled down to, the voltage for making outfan OUT is VSS, so as to realize resetting.
For the shift register cell for being arranged on n-th grade, because outfan OUT (n) of the shift register cell is gone back
The reset terminal RESET of (n-1)th grade of shift register cell of connection, therefore within this time period, the n-1 level shift register cells
Outfan OUT (n-1) be output as low level.Because outfan OUT (n) is also connected with the defeated of n+1 level shift register cells
Enter and hold IN, therefore in subsequent time period, outfan OUT (n+1) the output high level of the n+1 level shift register cells, this
When n-th grade of shift register cell outfan OUT (n) recover low level.
Because the dutycycle of CLKA and CLKB is 50%, therefore can ensure that every one-level shift register cell is exported
Pulse signal be respectively provided with identical pulse width.Thus, above-mentioned multi-stage shift register unit can realize pulse signal
Export step by step.It should be understood that the circuit that above-mentioned shift register cell has in any one embodiment of the present invention
Can be as shown in above-mentioned circuit, but it can also be replaced by the shift-register circuit under any one other forms, this
Invention is without limitation.
It should be noted that, although multi-stage shift register unit is at as shown in Figure 3 two in the embodiment of the present invention
Work under the driving of the first clock signal clk A and CLKB, but the first clock signal in the other embodiment of the present invention
Quantity can also be 3,4,5 or more, and can realize that multistage pulses are believed by mode similar as above
Number output, will not be described here.
On the other hand, in the scan drive circuit shown in Fig. 1, including with all switch elements in all switch elements
One-to-one several outfans；All it is connected with the second end of the switch element corresponding to the outfan of either switch element,
Specifically：
Scan drive circuit includes m levels shift register cell and m level switch elements；Any level is opened in m level switch elements
Closing unit includes 4 switch elements, and the first end of 4 switch elements connects with the one-to-one connection of 4 second clock signals, the 3rd end
Connect the shift register cell of this grade；The second end of all of switch element is one-to-one with 4m outfan in m level switch elements
Connection；M is more than or equal to 2.For example, in switch element S1 all switch elements three-terminal link shift register cell U1
Outfan OUT.The first end of all switch elements all connects 4 second clock signals (in Fig. 1 in switch element S1
CLK1, CLK2, CLK3, CLK4) in one.The second end of all switch elements is all connected with the turntable driving in switch element S1
One outfan (OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 in Fig. 1) of module.
More specifically, all switch elements in the embodiment of the present invention are thin film transistor (TFT) --- the first of switch element
End is respectively one in the source electrode of thin film transistor (TFT) and drain electrode with the second end, and the 3rd end of switch element is thin film transistor (TFT)
Grid.By taking first order switch element S1 as an example, the grid of thin film transistor (TFT) Q1~Q4 is connected to the outfan OUT of U1, source electrode with
One in drain electrode is respectively connecting to CLK1~CLK4, and another is respectively connecting to the outfan of the scan drive circuit
OUTPUT1~OUTPUT4.
Fig. 4 is a kind of drive signal sequential chart of the scan drive circuit shown in Fig. 1.As shown in figure 4, CLK1~CLK4
Dutycycle is identical to be 25%, and a phase place delayed fixed value successively.When shift register cell U1 receives initial letter
During number STV, in the presence of CLKA, CLKB, outfan OUT can export the pulse signal of high level, now in switch element S1
Thin film transistor (TFT) Q1~Q4 can open, i.e. the source electrode of thin film transistor (TFT) Q1~Q4 and drain electrode conducting, CLK1~CLK4 can pass through
Thin film transistor (TFT) Q1~Q4 is transmitted to the outfan OUTPUT1~OUTPUT4 of the turntable driving module.
The input IN of shift register cell U2 receives the signal of shift register cell U1 outfan OUT,
In the presence of CLKA, CLKB, outfan OUT2 can export the pulse signal of high level, so that in the switch element S2 of the second level
All of thin film transistor (TFT) Q5~Q8 is opened.CLK1~CLK4 can be transmitted to the turntable driving mould by thin film transistor (TFT) Q5~Q8
Outfan OUTPUT5~the OUTPUT8 of block.
Similarly, with m levels shift register cell output pulse signal step by step, the outfan of scan drive circuit can be by
The waveform identical scanning letter of waveform and a pulse in CLK1~CLK4 is sequentially output according to the order in Fig. 1 from top to bottom
Number, so as to realize the step by step output of the scanning signal in several outputs of above-mentioned pulse.
It should be noted that, although in the embodiment of the present invention each switch element include 4 switch elements, and respectively with
The outfan of 4 second clock signals and 4 scan drive circuits is connected, but its quantity can also be 2,3,5,6
Or it is more.For more generally, above-mentioned scan drive circuit can include m levels shift register cell and m level switch elements；
Any level switch element includes n switch element, the first end of n switch element and n second clock letter in m level switch elements
Number one-to-one connection, the shift register cell of three-terminal link this grade；The second of all of switch element in m level switch elements
End and the one-to-one connection of m × n outfan；M, n are all higher than being equal to 2.Thus, it is possible to realize list by mode similar as above
Step by step output of the scanning signal of pulse in several outputs.
Fig. 5 to Fig. 7 is the sequential chart of other several drive signals of the scan drive circuit shown in Fig. 1.With shown in Fig. 4
Drive signal identical is that the dutycycle of CLK1~CLK4 is still 25% in Fig. 5 to Fig. 7；And the drive signal shown in Fig. 4 is not
With CLK1~CLK4 is in the sequentially otherwise varied of delayed phase.With corresponding with first order shift register cell U1
As a example by switch element S1, under the sequential of the drive signal shown in Fig. 4, the outfan OUTPUT1 of scan drive circuit~
The order of OUTPUT4 output scanning signals is OUTPUT1 → OUTPUT2 → OUTPUT3 → OUTPUT4；And in the drive shown in Fig. 5
Under the sequential of dynamic signal, the order of the outfan OUTPUT1~OUTPUT4 output scanning signals of scan drive circuit is
OUTPUT1→OUTPUT3→OUTPUT2→OUTPUT4；Under the sequential of the drive signal shown in Fig. 6, scan drive circuit
The order of outfan OUTPUT1~OUTPUT4 output scanning signals is OUTPUT4 → OUTPUT3 → OUTPUT2 → OUTPUT1；
Under the sequential of the drive signal shown in Fig. 7, the outfan OUTPUT1~OUTPUT4 output scanning signals of scan drive circuit
Order be OUTPUT4 → OUTPUT2 → OUTPUT3 → OUTPUT1.
As can be seen that the embodiment of the present invention can pass through in the case where the circuit structure of scan drive circuit is not changed
Change drive signal sequential come adjust each output scanning signal output order.By contrast, it is of the prior art to sweep
Drive circuit is retouched if necessary to change the output order of scanning signal, then will generally be related at least part of circuit connecting relation
Change, running cost may be very high.Therefore, the embodiment of the present invention can to a certain extent solve existing turntable driving
The output signal sequential of circuit is single and change the technical problem of high cost.It is understood that the scanning of the embodiment of the present invention
Drive circuit can also by other means adjust the sequential of above-mentioned drive signal with realize other forms scanning signal it is defeated
Go out.
Fig. 8 is a kind of electrical block diagram of scan drive circuit in further embodiment of this invention.Referring to Fig. 8, this is swept
Drive circuit is retouched including m levels shift register cell and m level switch elements；Any level switch in the m levels switch element is single
Unit includes 4 switch elements, and the 3rd end of this 4 switch elements is connected with the shift register cell of this grade, first end and 4
The one-to-one connection of individual second clock signal；4 switch elements of any level switch element in addition to the first order include 1 first
Class switch element, 2 Equations of The Second Kind switch elements and 1 the 3rd class switch element.Scan drive circuit in the embodiment of the present invention
Specifically include the one-to-one company in the second end of 4 switch elements of 3m+1 outfan, front 4 outfans and first order switch element
Connect, rear 3m-3 outfan and all of Equations of The Second Kind switch element and the one-to-one connection of all of 3rd class switch element；Second
Second end of a switch element in second end and first order switch element of the first kind switch element in level switch element
It is connected；In second end of the first kind switch element in any level switch element in addition to the first order and upper level switch element
The 3rd class switch element the second end be connected；The m is more than or equal to 2.As can be seen that corresponding to each switch element, scanning
Drive circuit all includes one group of outfan；In any level switch element in addition to the first order, the second end of a switch element
With the same outfan that the second end of a switch element in upper level switch element is connected scan drive circuit；It is same to open
In closing unit, the outfan that the second end of all switch elements is connected is different.
For example, corresponding to second level shift register cell U2, second level switch element S2 includes 4 as switch
Thin film transistor (TFT) Q5~the Q8 of element, Q5 therein belong to first kind switch element, and Q6 and Q7 belongs to Equations of The Second Kind switch element, Q8
Belong to the 3rd class switch element.As can be seen that the grid of thin film transistor (TFT) Q1~Q4 is connected to the outfan OUT of U2, source electrode with
One in drain electrode is respectively connecting to CLK1~CLK4, and another is connected to an outfan of the scan drive circuit.Specifically
Ground, first 4 of 3m+1 outfan with the 4 switch element Q1~one-to-one connections of Q4 of first order switch element, rear 3m-3 is individual
Outfan is with all of Equations of The Second Kind switch element (such as Q6, Q7, Q10, the Q11 in Fig. 8) and all of 3rd class switch element (such as
Q8 and Q12 in Fig. 8) one-to-one connection.Meanwhile, second end of the first kind switch element Q5 in the switch element S2 of the second level with
Second end of a switch element Q4 in first order switch element is connected, in any level switch element in addition to the first order
The 3rd class switch in second end and upper level switch element of first kind switch element (such as Q1, Q5, Q9 and the Q13 in Fig. 8)
Second end of element is connected.
Based on said structure, the switch element of any two-stage neighboring in addition to the first order can share a scanning and drive
The outfan on galvanic electricity road, such that it is able to realize that scan drive circuit enters the function of line precharge to image element circuit.
For example, Fig. 9 is a kind of sequential chart of drive signal of the scan drive circuit shown in Fig. 8.Referring to Fig. 9, this
At least two second clock signals in inventive embodiments include four 1~CLK4 of clock signal clk as shown in Figure 9, its
The dutycycle of the most advanced CLK1 of the middle phase place and most delayed CLK4 of phase place is the half of the dutycycle of CLK2, CLK3.Certainly, it is right
In other any number of second clock signals, equally can have：The most advanced second clock signal of phase place is most delayed with phase place
Second clock signal dutycycle be other any one second clock signals dutycycle half.
It is understood that image element circuit can be by when the scanning signal that scan drive circuit is exported is received
Data voltage on data wire write to be located pixel in, and connect string pixel data wire can with scanning signal
The data voltage of every one-row pixels is sequentially output in the case of sequential is corresponding.And for the embodiment of the present invention, specific data electricity
Pressure write situation is changed into following flow processs：
By taking the switch element S1 corresponding to first order shift register cell U1 as an example：Q1~Q4 is in ii, III, IV rank
Unlatching in section can cause OUTPUT1~OUTPUT4 in the ripple of ii, the output waveform in III, IV stage and CLK1~CLK4
Shape is corresponding, and the unlatching of Q5, Q6 within the V stages can cause the output waveform of OUTPUT4, OUTPUT5 within the V stages point
It is not corresponding with CLK1 and CLK2.Unshowned in the accompanying drawings to be, OUTPUT1 (can such as may be used in stage i for high level
To be realized by being superimposed an external signal corresponding with initial signal STV sequential).Assume that OUTPUT1~OUTPUT5 is used respectively
In provide the first to fifth line pixel scanning signal, so as to：
In stage i, the image element circuit of the first row is the precharge of the first row pixel using the voltage on data wire, that is,
Before the electric capacity charging that data voltage starts equivalent for the first row pixel, fill for the electric capacity first with the voltage on data wire
Electric a period of time, so as to the electric capacity can more quickly reach the shape full of electric charge compared to situation about starting to charge up from zero potential
State；
In phase il, the image element circuit of the first row by data voltage corresponding with the first row pixel on data wire write to
In the first row pixel, the image element circuit of the second row is the second row picture using data voltage corresponding with the first row pixel on data wire
Element precharge；
In ii I-stage, the image element circuit of the second row writes data voltage corresponding with the second row pixel on data wire
Into the second row pixel, the image element circuit of the third line is the third line using data voltage corresponding with the second row pixel on data wire
Pixel is pre-charged；
In stage iv, the image element circuit of the third line by data voltage corresponding with the third line pixel on data wire write to
In the third line pixel, the image element circuit of fourth line is fourth line picture using data voltage corresponding with the third line pixel on data wire
Element precharge；
In the V stages, the image element circuit of fourth line by data voltage corresponding with fourth line pixel on data wire write to
In fourth line pixel, while the image element circuit of fifth line is the 5th using data voltage corresponding with fourth line pixel on data wire
Row pixel is pre-charged.
By that analogy, it can be seen that the image element circuit per a line may be by and upper one before write data voltage
The corresponding data voltage of row pixel is the precharge of one's own profession pixel, so as to realize that existing scan drive circuit carries out preliminary filling to image element circuit
The function of electricity.
Similarly, Figure 10 is the sequential chart of another drive signal of the scan drive circuit shown in Fig. 8, and shown in Fig. 9
Drive signal except that, the drive signal shown in Figure 10 is in the sequentially all differences of Phase delay.To shift with the first order
As a example by the corresponding switch element S1 of register cell U1, under the sequential of the drive signal shown in Fig. 9, the output of scan drive circuit
The order of end OUTPUT1~OUTPUT4 output scanning signals is OUTPUT1 → OUTPUT2 → OUTPUT3 → OUTPUT4；And scheme
Under the sequential of the drive signal shown in 10, the outfan OUTPUT1~OUTPUT4 of scan drive circuit exports the suitable of scanning signal
Sequence is OUTPUT1 → OUTPUT3 → OUTPUT2 → OUTPUT4.
As can be seen that the embodiment of the present invention can pass through in the case where the circuit structure of scan drive circuit is not changed
Change drive signal sequential come adjust each output scanning signal output order.By contrast, it is of the prior art to sweep
Drive circuit is retouched if necessary to change the output order of scanning signal, then will generally be related at least part of circuit connecting relation
Change, running cost may be very high.Therefore, the embodiment of the present invention can to a certain extent solve existing turntable driving
The output signal sequential of circuit is single and change the technical problem of high cost.It is understood that the scanning of the embodiment of the present invention
Drive circuit can also by other means adjust the sequential of above-mentioned drive signal with realize other forms scanning signal it is defeated
Go out.
Although in embodiments of the present invention it is understood that each switch element includes 4 in the embodiment of the present invention
Switch element, and being connected with the outfan of 4 second clock signals and 4 scan drive circuits respectively, but its quantity can be with
Be 2 (there is no Equations of The Second Kind switch element), 3,5,6 or more.For more generally, above-mentioned scan drive circuit
M levels shift register cell and m level switch elements can be included；Any level switch element in the m levels switch element includes n
Individual switch element, the 3rd end of the n switch element is connected with the shift register cell of this grade, the n switch unit
The first end of part and the one-to-one connection of n second clock signal；N switch unit of any level switch element in addition to the first order
Part includes first kind switch element, n-2 Equations of The Second Kind switch element and a 3rd class switch element；The turntable driving
Circuit includes the second end of n switch element of n+ (m-1) (n-1) individual outfans, front n outfan and first order switch element
One-to-one connection, afterwards (m-1) (n-1) individual outfan and all of Equations of The Second Kind switch element and all of 3rd class switch element one
Connect to one；Second end of the first kind switch element in the switch element of the second level switchs with first order switch element
Second end of element is connected；Second of the first kind switch element in any level switch element in addition to the first order and the second level
End is connected with the second end of the 3rd class switch element in upper level switch element；Described m, n are all higher than being equal to 2.
Figure 11 is a kind of electrical block diagram of scan drive circuit in another embodiment of the present invention.Referring to Figure 11,
It can be seen that the scan drive circuit shown in Figure 11 also includes on the basis of the circuit structure of the scan drive circuit shown in Fig. 1
Several reset units (as shown in R1, R2 in Figure 11).Figure 12 is a kind of turntable driving electricity in further embodiment of the present invention
The electrical block diagram on road, referring to Figure 12, it can be seen that the scan drive circuit shown in Figure 12 is in the turntable driving shown in Fig. 8
Also include several reset units on the basis of the circuit structure of circuit (as shown in R1, R2 in Figure 12).
In the scan drive circuit shown in Figure 11 and Figure 12, corresponding to each described outfan of scan drive circuit,
It is equipped with a reset unit for connecting the outfan.Wherein, arbitrary reset unit is used for when reset signal is received
The current potential of the output for being connected is pulled down to into predetermined level.It is understood that the reset unit in the embodiment of the present invention
Can be used for for outfan default electronegative potential being remained in not output signal, can effectively reduce output noise,
Avoid output by mistake.
More specifically, the arbitrary reset unit shown in Figure 11 and Figure 12 includes a corresponding first film transistor
(such as reset unit R1 includes that Rst1, reset unit R2 include Rst2, and the rest may be inferred).It is therein by taking reset unit R1 as an example
One in the source electrode and drain electrode of first film transistor Rst1 connects the outfan OUTPUT1 that reset unit R1 is connected,
Another connection predetermined level Vss；Shift register cell U2 described in the grid connection one-level of first film transistor Rst1,
Above-mentioned reset signal is the pulse signal of this grade of shift register cell U2 outputs.So as in second level shift register
During unit U2 output pulse signals, the Rst1 in reset unit R1 can just be pulled down to the current potential at outfan OUTPUT1
Predetermined level Vss, so as to realize the function of above-mentioned reset unit.
It is to be understood, however, that the shift register cell that the grid of first film transistor Rst1 is connected can also be
U3, U4, U5 etc., those skilled in the art can be selected according to concrete application scene, and the present invention is without limitation.
That is, the grid that can make arbitrary first film transistor connects shift register cell described in one-level, and causes arbitrary described
The series of the shift register cell that first film transistor is connected is more than what is connected corresponding to the first film transistor
The series of the shift register cell of outfan.
It is further to note that in description of the various embodiments of the present invention to thin film transistor (TFT), employ " source electrode with
Form of presentation as one in drain electrode connection ..., another connection ... ", to this skilled artisan would appreciate that
, different types of thin film transistor (TFT) can have the one kind in two kinds of connected modes, therefore specifically adopt any connection
Mode can be determined with specific reference to the type of device of application scenarios and thin film transistor (TFT).Especially, have in thin film transistor (TFT)
It is equivalent using above-mentioned any connected mode when source electrode is with drain electrode symmetrical structure, the present invention is without limitation.
Based on same inventive concept, embodiments provide a kind of array base palte, including it is above-mentioned any one
Scan drive circuit.For example, can include being formed in bottom by certain manufacturing process using the array base palte of GOA technologies
Scan drive circuit on plate, and the array base palte formed using other technologies can include as chip bonding sweeping in base plate
Retouch drive circuit, or including being formed in the scan drive circuit that is connected with the circuit on base plate in flexible circuit version.
Based on same inventive concept, the embodiment of the present invention provides a kind of display including above-mentioned any one array base palte
Device, the display device can be：Display floater, mobile phone, panel computer, television set, notebook computer, DPF, navigation
Any product with display function such as instrument or part.The display device is due to including the display of above-mentioned any one array base palte
Device, thus same technical problem can be solved, and identical technique effect is obtained, will not be described in detail herein.
Based on same inventive concept, a kind of above-mentioned scan drive circuit of any one is embodiments provided
Driving method, including：
By N number of first clock signal input with the period 1 to the multi-stage shift register unit, so that described
Multi-stage shift register unit step by step output pulse width be the period 1 1/N pulse signal；
By at least two second clocks signal input with second round to the multiple-pole switch unit, so that institute
State multiple-pole switch unit under the control of the pulse signal according at least two second clocks signal sequentially generate for
In the scanning signal that the output of each scan drive circuit is exported；
The period 1 is N times of the second round, and the N is more than or equal to 2.
For example, in N=4, with the period 14 the first clock signals can be including 4 dutycycles
25% and the clock signal in phase place delayed 1/4 cycle successively.The pulse signal exported so as to multi-stage shift register unit
Pulse width is also the 1/4 of the period 1.Because the period 1 is institute in 4 times of second round, therefore every one-level switch element
There is the time that switch element is opened to be 1/4 period 1, that is, 1 times of second round, it is possible to many within this period
Level switch element can sequentially generate the scanning signal for exporting in the output of each scan drive circuit.
On the other hand, the summation of the dutycycle of above-mentioned at least two second clocks signal can be more than 100%.Now, must
So there are at least two second clock signals to be at the same time the situation of high level in a cycle internal memory, therefore scanning can be coordinated to drive
The structure on galvanic electricity road realizes the pre-charging functions realized in above-mentioned Fig. 9 to Figure 10.
It is understood that the driving method in the embodiment of the present invention is corresponding to the above-mentioned turntable driving electricity of any one
Road, it is possible to the concrete form of any one in such as Fig. 4 to Fig. 7 and Fig. 9 to Figure 10, will not be described here.
In describing the invention it should be noted that term " on ", the orientation of the instruction such as D score or position relationship be base
In orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than indicates or imply
The device or element of indication must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to this
The restriction of invention.Unless otherwise clearly defined and limited, term " installation ", " connected ", " connection " should be interpreted broadly, example
Such as, can be fixedly connected, or be detachably connected, or be integrally connected；Can be mechanically connected, or be electrically connected
Connect；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, can be the connection of two element internals.For this
For the those of ordinary skill in field, above-mentioned term concrete meaning in the present invention can be as the case may be understood.
Also, it should be noted that herein, such as first and second or the like relational terms are used merely to one
Entity or operation make a distinction with another entity or operation, and not necessarily require or imply between these entities or operation
There is any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to contain
Lid nonexcludability is included, so that a series of process, method, article or equipment including key elements not only will including those
Element, but also including other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that
Also there is other identical element in process, method, article or equipment including the key element.
Above example only to illustrate technical scheme, rather than a limitation；Although with reference to the foregoing embodiments
The present invention has been described in detail, it will be understood by those within the art that：It still can be to aforementioned each enforcement
Technical scheme described in example is modified, or carries out equivalent to which part technical characteristic；And these modification or
Replace, do not make the spirit and scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.
Claims (10)
1. a kind of scan drive circuit, including several outfans, it is characterised in that the circuit also includes：
Multi-stage shift register unit, the multi-stage shift register unit is used for the driving at least two the first clock signals
Under output pulse signal step by step；
The multiple-pole switch unit being connected one by one with the multi-stage shift register unit, the switch element is opened including at least two
Close element；
Wherein, the first end of any one of switch element connects at least two second clock signals, the second end
Connect an outfan of the scan drive circuit, the shifting that the switch element that three-terminal link is located with the switch element is connected
Bit register unit；The switch element is used for conducting first end and the second end when the 3rd termination receives the pulse signal；
Cycle of the cycle of first clock signal more than the second clock signal；
Corresponding to each switch element, the scan drive circuit includes one group of outfan；It is arbitrary in addition to the first order
In the level switch element, the of a switch element in the second end of a switch element and switch element described in upper level
Two ends connect the same outfan of the scan drive circuit；In the same switch element, all switch elements
The outfan that second end is connected is different.
2. scan drive circuit as claimed in claim 1, it is characterised in that the scan drive circuit includes that the displacement of m levels is posted
Storage unit and m level switch elements；Any level switch element in the m levels switch element includes n switch element, the n
3rd end of individual switch element is connected with the shift register cell of this grade, the first end of the n switch element with n the
The one-to-one connection of two clock signals；N switch element of any level switch element in addition to the first order includes a first kind
Switch element, n-2 Equations of The Second Kind switch element and a 3rd class switch element；
The scan drive circuit includes n+ (m-1) (n-1) individual outfans, and front n outfan is individual with the n of first order switch element
The one-to-one connection in second end of switch element, afterwards (m-1) (n-1) individual outfan and all of Equations of The Second Kind switch element and all of
The one-to-one connection of 3rd class switch element；Second end of the first kind switch element in the switch element of the second level switchs with the first order
Second end of a switch element in unit is connected；In addition to the first order and the second level in any level switch element first
Second end of class switch element is connected with the second end of the 3rd class switch element in upper level switch element；Described m, n are big
In equal to 2.
3. scan drive circuit as claimed in claim 1, it is characterised in that corresponding to each institute of the scan drive circuit
Outfan is stated, a reset unit for connecting the outfan is provided with；Arbitrary reset unit is used to receive reset signal
When the current potential of the output for being connected is pulled down to into predetermined level.
4. scan drive circuit as claimed in claim 3, it is characterised in that arbitrary reset unit includes that the first film is brilliant
Body pipe, in the source electrode and drain electrode of the first film transistor connects the outfan that the reset unit is connected, another
Individual connection predetermined level；Shift register cell described in the grid connection one-level of the first film transistor, the reset letter
Number for the output of this grade of shift register cell the pulse signal；
The series of the shift register cell that arbitrary first film transistor is connected is more than brilliant corresponding to the first film
The series of the shift register cell of the outfan that body pipe is connected.
5. the scan drive circuit as described in any one in Claims 1-4, it is characterised in that the switch element is thin
Film transistor, the first end of the switch element is respectively one in the source electrode of thin film transistor (TFT) and drain electrode with the second end；Institute
State the grid of the 3rd end for thin film transistor (TFT) of switch element.
6. the scan drive circuit as described in any one in Claims 1-4, it is characterised in that arbitrary shift LD
Device unit includes input, outfan and reset terminal, for being input under at least driving of two the first clock signals
End connects signal and exports in output time delay；It is arbitrary in the multi-stage shift register unit except the last
The outfan of level shift register cell connects the input of next stage shift register cell；Described in addition to the first order
In multi-stage shift register unit, the outfan of any level shift register cell connects answering for upper level shift register cell
Position end.
7. a kind of array base palte, it is characterised in that include the scan drive circuit as described in any one in claim 1 to 6.
8. a kind of display device, it is characterised in that including array base palte as claimed in claim 7.
9. a kind of driving method of the scan drive circuit as described in any one in claim 1 to 6, it is characterised in that bag
Include：
By N number of first clock signal input with the period 1 to the multi-stage shift register unit, so that described multistage
Shift register cell step by step output pulse width be the period 1 1/N pulse signal；
By at least two second clocks signal input with second round to the multiple-pole switch unit, so that described many
Level switch element is sequentially generated for every under the control of the pulse signal according at least two second clocks signal
The scanning signal of the output output of scan drive circuit described in；
The period 1 is N times of the second round, and the N is more than or equal to 2.
10. driving method as claimed in claim 9, it is characterised in that the dutycycle of at least two second clocks signal
Summation be more than 100%.
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| CN201510260153.4A CN104835466B (en) | 2015-05-20 | 2015-05-20 | Scan driving circuit, array substrate, display device and driving method |
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| CN105070244B (en) * | 2015-09-18 | 2017-10-03 | 京东方科技集团股份有限公司 | Drive circuit and its driving method, touch-control display panel and touch control display apparatus |
| CN105118470B (en) | 2015-09-28 | 2018-06-22 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and grid drive method, array substrate and display panel |
| CN105788555B (en) * | 2016-05-19 | 2018-04-10 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN105810136B (en) | 2016-05-23 | 2019-04-02 | 武汉华星光电技术有限公司 | Array substrate tests circuit, display panel and flat display apparatus |
| CN106251804B (en) * | 2016-09-30 | 2018-12-21 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN106652949B (en) * | 2016-12-28 | 2019-03-26 | 深圳市华星光电技术有限公司 | Gate driving circuit and liquid crystal display device |
| CN106847155B (en) * | 2017-02-27 | 2021-03-19 | 上海中航光电子有限公司 | GOA circuit, array substrate and display device |
| CN109036325B (en) * | 2018-10-11 | 2021-04-23 | 信利半导体有限公司 | Scanning drive circuit and display device |
| CN111210755A (en) * | 2020-02-25 | 2020-05-29 | 合肥京东方光电科技有限公司 | Shift register, grid drive circuit and display panel |
| CN111292689B (en) * | 2020-03-20 | 2021-08-24 | 深圳市华星光电半导体显示技术有限公司 | Driving method and driving device of GOA circuit |
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| KR100545027B1 (en) * | 2003-06-26 | 2006-01-24 | 엘지.필립스 엘시디 주식회사 | Apparatus and method for driving of liquid crystal display device |
| KR20080020063A (en) * | 2006-08-30 | 2008-03-05 | 삼성전자주식회사 | Shift resister |
| CN103578433B (en) * | 2012-07-24 | 2015-10-07 | 北京京东方光电科技有限公司 | A kind of gate driver circuit, method and liquid crystal display |
| CN102903322B (en) * | 2012-09-28 | 2015-11-11 | 合肥京东方光电科技有限公司 | Shift register and driving method thereof and array base palte, display device |
| TWI473069B (en) * | 2012-12-27 | 2015-02-11 | Innocom Tech Shenzhen Co Ltd | Gate driving device |
| TWI478132B (en) * | 2013-06-14 | 2015-03-21 | Au Optronics Corp | Gate driver circuit |
| CN103474040B (en) * | 2013-09-06 | 2015-06-24 | 合肥京东方光电科技有限公司 | Grid electrode drive unit, grid electrode drive circuit and display device |
| CN103700354B (en) * | 2013-12-18 | 2017-02-08 | 合肥京东方光电科技有限公司 | Grid electrode driving circuit and display device |
| CN104157248A (en) * | 2014-05-08 | 2014-11-19 | 京东方科技集团股份有限公司 | Gate driving circuit, gate driving method and display device |
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