CN106847155B

CN106847155B - GOA circuit, array substrate and display device

Info

Publication number: CN106847155B
Application number: CN201710109275.2A
Authority: CN
Inventors: 席克瑞; 崔婷婷
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2017-02-27
Filing date: 2017-02-27
Publication date: 2021-03-19
Anticipated expiration: 2037-02-27
Also published as: CN106847155A

Abstract

The invention discloses a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: the first GOA module comprises M first GOA units, each first GOA unit outputs a first scanning signal step by step at the output end of the first GOA unit, the second GOA module comprises N second GOA units, each second GOA unit outputs a second scanning signal step by step at the output end of the second GOA unit when the first scanning signal is a first effective signal, and each second scanning signal is used for controlling the gating of one pixel. The GOA circuit achieves the purpose of controlling the gating state of M multiplied by N pixels through M + N GOA units, so that the number of the GOA units in the GOA circuit is greatly reduced, the size of the GOA circuit is further reduced, and the difficulty of realizing a narrow frame by using a display device of the GOA circuit is also reduced.

Description

GOA circuit, array substrate and display device

Technical Field

The invention relates to the technical field of display, in particular to a GOA circuit, an array substrate and a display device.

Background

With the continuous development of display technology, the application of display devices is more and more extensive, and the requirements of users on the functions and the appearance of the display devices are more and more diversified. Among them, a display device having a narrow frame is a target of people's pursuit because of its excellent appearance and grip.

In a display device, the size of a Gate On Array (GOA) circuit determines to some extent the size of the frame of the display device. Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit in the prior art, and as can be seen from fig. 1, the GOA circuit in the prior art includes a plurality of GOA units 10 and a plurality of switching tubes 20, a second end of each switching tube 20 is electrically connected to a pixel, each GOA unit 10 is electrically connected to a control end of one switching tube 20, and first ends of the switching tubes 20 are electrically connected to each other; in the working process, the GOA unit 10 in the GOA circuit sequentially outputs valid signals to the plurality of switching tubes 20 to control the plurality of switching tubes 20 to be sequentially turned on. Because the number of the GOA units in the conventional GOA circuit needs to be consistent with the number of pixels of the display device, the number of the GOA units in the GOA circuit increases with the increasing number of pixels of the display device, thereby increasing the difficulty of implementing a narrow frame of the display device.

Disclosure of Invention

In view of this, the present invention provides a GOA circuit, an array substrate and a display device, so as to achieve the purpose of reducing the number of GOA units in the GOA circuit, thereby reducing the volume of the GOA circuit and reducing the difficulty of implementing a narrow frame of the display device.

To achieve the above object, in one aspect, the present invention provides:

a GOA circuit, comprising: a first GOA module and a second GOA module,

the first GOA module comprises M first GOA units, the output end of each first GOA unit outputs a first scanning signal step by step,

the second GOA module includes N second GOA units, and when the first scanning signal is a first valid signal, an output end of each second GOA unit outputs a second scanning signal step by step, and each second scanning signal is used for controlling one pixel gating.

In another aspect, the present invention provides an array substrate, including a plurality of scan lines and the GOA circuit described in any one of the above, where output ends of the GOA circuit are connected to the pixels in a one-to-one correspondence manner through the scan lines in sequence.

In another aspect, the present invention provides a display device including the array substrate as described in the above paragraph.

In view of the foregoing technical solutions, an embodiment of the present invention provides a GOA circuit, an array substrate, and a display device, where the GOA circuit includes a first GOA module composed of M first GOA units and a second GOA module composed of N second GOA units, an output end of each first GOA unit outputs a first scanning signal step by step, and an output end of each second GOA unit outputs a second scanning signal step by step when the first scanning signal is a first valid signal, so as to implement a function of sequentially controlling pixel gating. The GOA circuit achieves the purpose of controlling the gating state of M × N pixels by M + N GOA units, thereby greatly reducing the number of GOA units in the GOA circuit, for example, the number of pixels is 960 × 640, M is 960, N is 640, compared with the GOA circuit in the prior art, the GOA circuit reduces (960 × 640- (960+640) ═)612800 GOA units, thereby greatly reducing the volume of the GOA circuit, and also greatly reducing the difficulty of implementing a narrow bezel by using a display device of the GOA circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a GOA circuit in the prior art;

fig. 2 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a driving timing sequence of the GOA circuit shown in FIG. 2;

fig. 4 is a schematic structural diagram of a GOA circuit according to another embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a driving timing sequence of the GOA circuit shown in FIG. 4;

fig. 6 is a schematic structural diagram of a GOA circuit according to a preferred embodiment of the present application;

fig. 7 is a schematic structural diagram of a GOA circuit according to another preferred embodiment of the present application;

fig. 8 is a schematic diagram of a driving timing sequence of the GOA circuit shown in fig. 7.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the present application provides a GOA circuit, referring to fig. 2, where fig. 2 is a schematic structural diagram of the GOA circuit; the method comprises the following steps: a first GOA module 100 and a second GOA module 200,

the first GOA module 100 comprises M first GOA units 110, wherein the output of each first GOA unit 110 outputs a first scanning signal in a progressive manner,

the second GOA module 200 includes N second GOA units 210, and when the first scanning signal is the first valid signal, each second GOA unit 210 outputs a second scanning signal step by step at its output end, and each second scanning signal is used to control one pixel gate.

For clarity, in fig. 2, the connection structure of the GOA circuits is described by taking an example that M is 4, N is 4, and the number of pixels is 16, where the first GOA module 100 includes 4 first GOA units 110, each first GOA unit 110 is electrically connected to four pixels, and the four pixels are electrically connected to 4 second GOA units 210 in the second GOA module 200, respectively. Referring to fig. 3, fig. 3 is a circuit driving timing diagram of the first and

second GOA modules

100 and 200 of the GOA circuit shown in fig. 2; when the first scanning signal output by one first GOA unit 110 is a first valid signal (high level), the output end of each second GOA unit 210 outputs a second scanning signal step by step to control the gating of the pixels electrically connected thereto. In the GOA circuit shown in fig. 2, the purpose of controlling 16 pixel strobes is achieved by 8 GOA units, which is reduced by 8 GOA units compared to the GOA circuit in the prior art. Therefore, the number of the GOA units in the GOA circuit is reduced, the size of the GOA circuit is further reduced, and the difficulty of realizing a narrow frame by using the display device of the GOA circuit is reduced.

In addition, values of M and N may be the same or different, for example, in another embodiment of the present application, referring to fig. 4 and fig. 5, fig. 4 is a schematic structural diagram of the GOA circuit, and fig. 5 is a circuit driving timing diagram of the first GOA module 100 and the second GOA module 200 of the GOA circuit shown in fig. 4; in this embodiment, the first GOA module 100 of the GOA circuit includes 2 first GOA units 110, and the second GOA module 200 includes 4 second GOA units 210 for controlling the gating status of 8 pixels. In the present embodiment, the GOA circuit has 2 GOA units less than the GOA circuit in the prior art.

In practical applications, the number of pixels controlled by the GOA circuit is generally huge, for example, the number of pixels is 960 × 640, M is 960, and N is 640, compared with the GOA circuit in the prior art, the GOA circuit reduces (960 × 640- (960+640) ═ 612800 GOA units, so that the number of GOA units in the GOA circuit is greatly reduced, the size of the GOA circuit is further reduced, and the difficulty of implementing a narrow frame by using a display device of the GOA circuit is also reduced. Of course, when the number of pixels is 960 × 640 — 614400, the GOA circuits with different values of M and N may be used to complete the function of controlling the gating states of the 614400 pixels, for example, a GOA circuit with M being 512 and N being 1200 may be selected to complete the above function.

It should be noted that, in other embodiments of the present application, the first valid signal may also be a low level, and the present application does not limit the specific kind of the first valid signal, which is determined according to the actual situation.

On the basis of the foregoing embodiments, in an embodiment of the present application, referring to fig. 6 and fig. 3, fig. 6 is a schematic structural diagram of the GOA circuit, and the GOA circuit further includes: the gating circuit 300, the gating circuit 300 includes a plurality of gating units 310, each gating unit 310 is connected to a pixel, the gating unit 310 includes a first switching tube 311 and a second switching tube 312;

a first end of each of the first switching tubes 311 is connected, a second end of the first switching tube 311 in the same gating unit 310 is connected to a first end of the second switching tube 312, a second end of the second switching tube 312 is connected to the corresponding pixel, a control end of the first switching tube 311 is connected to an output end of the first GOA unit 110, and a control end of the second switching tube 312 is connected to an output end of the second GOA unit 210.

In this embodiment, the circuit driving timings of the first GOA module 100 and the second GOA module 200 of the GOA circuit are shown in fig. 3; similarly, in fig. 6, the connection structure of the GOA circuits is illustrated by taking M as 4, N as 4, and the number of pixels as 16 as an example, each of the first GOA units 110 is electrically connected to 4 pixels through the first switching tube 311 and the second switching tube 312 of the gating circuit 300, and the 4 pixels are electrically connected to 4 second GOA units 210 through the gating circuit 300.

The first switch tube 311 and the second switch tube 312 may be both N-type transistors or both P-type transistors. When the first switch tube 311 and the second switch tube 312 are both N-type transistors, the first effective signal is at a high level; when the first switch tube 311 and the second switch tube 312 are both P-type transistors, the first active signal is at a low level. The specific types of the first switch tube 311 and the second switch tube 312 are not limited in this application, and are determined according to actual situations.

In the working process, in the continuous process that the first scanning signal output by the first GOA unit 110 is the first valid signal, the first switching tube 311 in the gating unit 310 connected thereto is turned on, and the second GOA unit 210 outputs the second scanning signal step by step to turn on the second switching tube 312 of the gating unit 310 connected to the first GOA unit 110, so as to sequentially control the gating of the pixels connected to the first GOA unit 110.

On the basis of the foregoing embodiments, in another embodiment of the present application, referring to fig. 7 and fig. 8, fig. 7 is a schematic structural diagram of the GOA circuit, and fig. 8 is a schematic driving timing diagram of the GOA circuit shown in fig. 7; the GAO circuit further includes: the third GOA module 400 is configured to,

the third GOA module 400 includes X third GOA units 410, and when the second scanning signal is the first valid signal, each third GOA unit 410 outputs a third scanning signal stage by stage at its output end, and each third scanning signal is used to control one pixel gate.

In this embodiment, the GOA circuit uses M + N + X GOA units, and can achieve the purpose of controlling gating of M × N × X pixels. Further reducing the GOA units is achieved, specifically, taking fig. 7 as an example, in fig. 7, where M ═ N ═ X ═ 2, each of the first GOA units 110 is electrically connected to 4 pixels through the gating circuit 300, respectively, among the 4 pixels electrically connected to each of the first GOA units 110, each of the second GOA units 210 is electrically connected to two of the pixels, and each of the third GOA units 410 is electrically connected to two of the other pixels. The GOA circuit shown in fig. 7 achieves the purpose of controlling the gate of 2 × 2 × 2 × 8 pixels by using 2+2+2 — 6 GOA units, and the number of GOA units in the GOA circuit is reduced. And when the number of pixels is large, the number of GOA units is reduced more than that of the GOA circuits having only the first and

second GOA modules

100 and 200, for example, when the number of pixels is 15625, the number of GOA circuits having only the first and

second GOA modules

100 and 200 requires a minimum of 125+ 125-250 GOA units (125 × 125-15625); the GOA circuit in this embodiment only needs 25+25+25 to 75 GOA units (25 × 25 × 25 to 15625), which further reduces the number of GOA units required by the GOA circuit.

Still referring to fig. 7, the GOA circuit further includes a gating circuit 300, where the gating circuit 300 includes a plurality of gating units 310, each gating unit 310 is connected to one pixel, and the gating unit 310 includes a first switching tube 311, a second switching tube 312, and a third switching tube 313;

a first end of each of the first switching tubes 311 is connected, a second end of the first switching tube 311 in the same gating unit 310 is connected to a first end of the second switching tube 312, a second end of the second switching tube 312 is connected to a first end of the third switching tube 313, a second end of the third switching tube 313 is connected to the corresponding pixel, a control end of the first switching tube 311 is connected to an output end of the first GOA unit 110, a control end of the second switching tube 312 is connected to an output end of the second GOA unit 210, and a control end of the third switching tube 313 is connected to an output end of the third GOA unit 310.

Similarly, the first switch tube 311, the second switch tube 312, and the third switch tube 313 may all be N-type transistors, and may also all be P-type transistors. When the first switch tube 311, the second switch tube 312 and the third switch tube 313 are all N-type transistors, the first active signal is at a high level; when the first switch tube 311, the second switch tube 312, and the third switch tube 313 are all P-type transistors, the first active signal is at a low level. The specific types of the first switch tube 311, the second switch tube 312, and the third switch tube 313 are not limited in this application, and are determined according to the actual situation.

Correspondingly, an embodiment of the present application further provides an array substrate, which includes a plurality of scan lines and the GOA circuit according to any of the above embodiments, wherein output ends of the GOA circuit are sequentially connected to the pixels through the scan lines in a one-to-one correspondence manner.

Correspondingly, the embodiment of the application also provides a display device, which comprises the array substrate in the embodiment.

To sum up, the embodiment of the application provides a GOA circuit, array substrate and display device, wherein, the GOA circuit includes the first GOA module that comprises M first GOA units and the second GOA module that comprises N second GOA units, every first GOA unit's output exports first scanning signal step by step, every the second GOA unit is in when first scanning signal is first effective signal, its output exports second scanning signal step by step to realize controlling the function that the pixel strobes in proper order. The GOA circuit achieves the purpose of controlling the gating state of M × N pixels by M + N GOA units, thereby greatly reducing the number of GOA units in the GOA circuit, for example, the number of pixels is 960 × 640, M is 960, N is 640, compared with the GOA circuit in the prior art, 612800 GOA units are reduced, (960 × 640- (960+ 640)), thereby greatly reducing the volume of the GOA circuit, and also greatly reducing the difficulty of implementing a narrow frame by using a display device of the GOA circuit.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A GOA circuit, comprising: a first GOA module and a second GOA module,

the first GOA module comprises M first GOA units, the output ends of the M first GOA units output first scanning signals step by step,

the second GOA module comprises N second GOA units, the output end of the N second GOA units outputs second scanning signals step by step when the first scanning signals are first effective signals, and each second scanning signal is used for controlling the gating of M pixels;

each first GOA unit is electrically connected with N pixels, and the N pixels are respectively electrically connected with N second GOA units in the second GOA module;

the pixel driving circuit further comprises a gating circuit, wherein the gating circuit comprises a plurality of gating units, each gating unit is connected with one pixel, and each gating unit comprises a first switching tube and a second switching tube;

the first ends of the first switch tubes are connected, the second ends of the first switch tubes in the same gating unit are connected with the first ends of the second switch tubes, the second ends of the second switch tubes are connected with the corresponding pixels, the control ends of the first switch tubes are connected with the output end of the first GOA unit, and the control ends of the second switch tubes are connected with the output end of the second GOA unit.

2. The GOA circuit according to claim 1, wherein the first switch tube and the second switch tube are both N-type transistors or P-type transistors.

3. A GOA circuit, comprising: the system comprises a first GOA module, a second GOA module and a third GOA module;

the second GOA module comprises N second GOA units, and the output ends of the N second GOA units output second scanning signals step by step when the first scanning signals are first effective signals;

the third GOA module comprises X third GOA units, and when the second scanning signal is the first valid signal, the output ends of the X third GOA units output the third scanning signals step by step, and each third scanning signal is used for controlling the gating of M × N pixels;

each first GOA unit is electrically connected with N X pixels, and the N X pixels are respectively electrically connected with N second GOA units and X third GOA units;

the pixel driving circuit further comprises a gating circuit, wherein the gating circuit comprises a plurality of gating units, each gating unit is connected with one pixel, and each gating unit comprises a first switching tube, a second switching tube and a third switching tube;

the first ends of the first switch tubes are connected, the second ends of the first switch tubes in the gating unit are connected with the first ends of the second switch tubes, the second ends of the second switch tubes are connected with the first ends of the third switch tubes, the second ends of the third switch tubes are connected with the corresponding pixels, the control ends of the first switch tubes are connected with the output end of the first GOA unit, the control ends of the second switch tubes are connected with the output end of the second GOA unit, and the control ends of the third switch tubes are connected with the output end of the third GOA unit.

4. The GOA circuit according to claim 3, wherein the first switch tube, the second switch tube and the third switch tube are all N-type transistors or P-type transistors.

5. An array substrate, comprising a plurality of scanning lines and the GOA circuit as claimed in any one of claims 1-2 or 3-4, wherein output ends of the GOA circuit are connected with the pixels in a one-to-one correspondence manner sequentially through the scanning lines.

6. A display device comprising the array substrate according to claim 5.