CN106847155A - A kind of GOA circuits, array base palte and display device - Google Patents
A kind of GOA circuits, array base palte and display device Download PDFInfo
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- CN106847155A CN106847155A CN201710109275.2A CN201710109275A CN106847155A CN 106847155 A CN106847155 A CN 106847155A CN 201710109275 A CN201710109275 A CN 201710109275A CN 106847155 A CN106847155 A CN 106847155A
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- goa
- switch pipe
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- pixel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a kind of GOA circuits, array base palte and display device, wherein, GOA circuits include：First GOA modules and the 2nd GOA modules, the first GOA modules include M the first GOA unit, the output end of each first GOA unit exports the first scanning signal step by step, the 2nd GOA modules include N number of second GOA unit, each described second GOA unit is when first scanning signal is the first useful signal, its output end exports the second scanning signal step by step, and each described second scanning signal is used to control a pixel gating.The GOA circuits are realized the purpose of the strobe state of control M × N number of pixel by M+N GOA unit, so as to greatly reduce the quantity of GOA unit in GOA circuits, and then the volume of GOA circuits is reduced, also reduce the difficulty that narrow frame is realized using the display device of the GOA circuits.
Description
Technical field
The present invention relates to display technology field, more specifically to a kind of GOA circuits, array base palte and display device.
Background technology
With continuing to develop for Display Technique, the application of display device is more and more extensive, work(of the user for display device
Can be also more and more diversified with the requirement of outward appearance.Wherein, the display device with narrow frame is due to its excellent perception and gripping
The object that sense is pursued as people.
In a display device, the size of raster data model (Gate on Array, GOA) circuit decides to a certain extent
The size of the frame of display device.With reference to Fig. 1, Fig. 1 is the structural representation of GOA circuits of the prior art, can be with from Fig. 1
Find out, GOA circuits of the prior art include multiple GOA units 10 and multiple switch pipe 20, the second end of each switching tube 20
With the electrical connection of pixel, each GOA unit 10 electrically connects with the control end of a switching tube 20, the first end of switching tube 20 that
This electrical connection；In the course of the work, the GOA unit 10 in GOA circuits is followed successively by the output useful signal of multiple switch pipe 20, to control
Multiple switch pipe 20 processed is opened successively.Because in traditional GOA circuits, the quantity of GOA unit needs the picture with display device
Prime number amount is consistent, therefore being continuously increased with display device pixel quantity, and the quantity of the GOA unit in GOA circuits is also therewith
Increase, so as to increased the difficulty that display device realizes narrow frame.
The content of the invention
In view of this, the invention provides a kind of GOA circuits, array base palte and display device, to realize reducing GOA circuits
The quantity of middle GOA unit, so as to reduce the volume of GOA circuits, reduces the purpose that display device realizes the difficulty of narrow frame.
To achieve the above object, on the one hand, the present invention is provided：
A kind of GOA circuits, including：First GOA modules and the 2nd GOA modules,
The first GOA modules include M the first GOA unit, and the output end of each first GOA unit is exported step by step
First scanning signal,
The 2nd GOA modules include N number of second GOA unit, and each described second GOA unit is in the described first scanning letter
Number for the first useful signal when, its output end exports the second scanning signal step by step, each described second scanning signal be used for control
One pixel gating.
On the other hand, the present invention provides a kind of array base palte, including multi-strip scanning line and as described in above-mentioned any one
GOA circuits, the output end of the GOA circuits passes sequentially through the scan line and is connected one to one with the pixel.
Another further aspect, the present invention provides a kind of display device, including the array base palte described in as described above.
From above-mentioned technical proposal as can be seen that the embodiment of the invention provides a kind of GOA circuits, array base palte and display dress
Put, wherein, the GOA circuits include the GOA modules being made up of M the first GOA unit and by N number of second GOA unit structure
Into the 2nd GOA modules, the output end of each first GOA unit exports the first scanning signal step by step, and each described second
When first scanning signal is the first useful signal, its output end exports the second scanning signal to GOA unit step by step, to realize
The function that control pixel is gated successively.The GOA circuits are realized the gating shape of control M × N number of pixel by M+N GOA unit
The purpose of state, so as to greatly reduce the quantity of GOA unit in GOA circuits, is such as 960 × 640, M=with pixel quantity
As a example by 960, N=640, the GOA circuits reduce (960 × 640- (960+640) compared to GOA circuits of the prior art
=) 612800 GOA units, and then the volume of GOA circuits is greatly reduced, also largely reduce using described
The display device of GOA circuits realizes the difficulty of narrow frame.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is the structural representation of GOA circuits of the prior art；
A kind of structural representation of GOA circuits that Fig. 2 is provided for one embodiment of the application；
Fig. 3 is the driver' s timing schematic diagram of the GOA circuits shown in Fig. 2；
A kind of structural representation of GOA circuits that Fig. 4 is provided for another embodiment of the application；
Fig. 5 is the driver' s timing schematic diagram of the GOA circuits shown in Fig. 4；
A kind of structural representation of GOA circuits that Fig. 6 is provided for a preferred embodiment of the application；
A kind of structural representation of GOA circuits that Fig. 7 is provided for another preferred embodiment of the application；
Fig. 8 is the driver' s timing schematic diagram of the GOA circuits shown in Fig. 7.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiment of the present application provides a kind of GOA circuits, and with reference to Fig. 2, Fig. 2 is the structural representation of GOA circuits；Including：
First GOA modules 100 and the 2nd GOA modules 200,
The first GOA modules 100 include M the first GOA unit 110, the output of each first GOA unit 110
End exports the first scanning signal step by step,
The 2nd GOA modules 200 include N number of second GOA unit 210, and each described second GOA unit 210 is described
When first scanning signal is the first useful signal, its output end exports the second scanning signal step by step, each described second scanning letter
Number for controlling pixel gating.
It should be noted that clear in order to show, with M=4 in Fig. 2, N=4, pixel quantity is to the GOA as a example by 16
The attachment structure of circuit is illustrated, and a GOA modules 100 include 4 the first GOA units 110, and each GOA is mono-
Unit 110 electrically connects with four pixels, and this four pixels are electric with 4 the second GOA units 210 in the 2nd GOA modules 200 respectively
Connection.With reference to Fig. 3, Fig. 3 is a GOA modules 100 and the circuit drives of the 2nd GOA modules 200 of the GOA circuits shown in Fig. 2
Timing diagram；When first scanning signal of the output of the first GOA unit 110 is the first useful signal (high level), often
The output end of individual second GOA unit 210 exports the second scanning signal step by step, to control the pixel being connected electrically to gate.In Fig. 2
In shown GOA circuits, the purpose that 16 pixels of control are gated is realized with 8 GOA units, compared to of the prior art
GOA circuits reduce 8 GOA units.It is achieved thereby that reducing the quantity of GOA unit in GOA circuits, and then reduce the GOA
The difficulty of narrow frame is realized in the volume of circuit, reduction using the display device of the GOA circuits.
In addition, the value of M and N can be with identical, it is also possible to different, such as in another embodiment of the application, reference
Fig. 4 and Fig. 5, Fig. 4 are the structural representation of the GOA circuits, and Fig. 5 is the He of a GOA modules 100 of the GOA circuits shown in Fig. 4
The circuit drives timing diagram of the 2nd GOA modules 200；In the present embodiment, GOA modules 100 of GOA circuits include 2 the
One GOA unit 110, the 2nd GOA modules 200 include 4 the second GOA units 210, for controlling 8 strobe states of pixel.
In the present embodiment, the GOA circuits reduce 2 GOA units compared to GOA circuits of the prior art.
In actual applications, the pixel quantity of the GOA circuits control is general more huge, for example, be with pixel quantity
960 × 640, M=960, as a example by N=640, the GOA circuits reduce compared to GOA circuits of the prior art (960 ×
640- (960+640)=) 612800 GOA units, so as to greatly reduce the quantity of the GOA unit in the GOA circuits, enter
And the volume of GOA circuits is reduced, also reduce the difficulty that narrow frame is realized using the display device of the GOA circuits.Certainly
, when pixel quantity is 960 × 640=614400, the GOA electricity of the value with different M and N can also be utilized
Road completes to control 614400 functions of the strobe state of pixel, for example, M=512 can be chosen, the GOA circuits of N=1200
To complete above-mentioned functions.
Also, it should be noted that in the other embodiment of the application, first useful signal can also be low level,
The application is not limited the specific species of first useful signal, specific depending on actual conditions.
It is the GOA with reference to Fig. 6 and Fig. 3, Fig. 6 in one embodiment of the application on the basis of above-described embodiment
The structural representation of circuit, GOA circuits also include：Gating circuit 300, gating circuit 300 includes multiple gating units 310, often
Individual gating unit 310 is connected with a pixel, and gating unit 310 includes first switch pipe 311 and second switch pipe 312；
The first end of each first switch pipe 311 is connected, the first switch in the same gating unit 310
Second end of pipe 311 is connected with the first end of the second switch pipe 312, the second end of the second switch pipe 312 with it is corresponding
The pixel be connected, the control end of the first switch pipe 311 is connected with the output end of first GOA unit 110, described
The control end of second switch pipe 312 is connected with the output end of second GOA unit 210.
In the present embodiment, during the circuit drives of a GOA modules 100 of the GOA circuits and the 2nd GOA modules 200
Sequence is as shown in Figure 3；Likewise, in figure 6 still with M=4, N=4, pixel quantity is the connection knot to the GOA circuits as a example by 16
Structure is illustrated, and each described first GOA unit 110 is opened by the first switch pipe 311 of the gating circuit 300 and second
Close pipe 312 to be electrically connected with 4 pixels, this 4 pixels are by the gating circuit 300 respectively at 4 second GOA units
210 electrical connections.
It should be noted that the first switch pipe 311 and second switch pipe 312 can be N-type transistor, can be with
It is P-type transistor.When the first switch pipe 311 and second switch pipe 312 are N-type transistor, described first is effective
Signal is high level；When the first switch pipe 311 and second switch pipe 312 are P-type transistor, described first effectively believes
Number be low level.The application is not limited the specific species of the first switch pipe 311, second switch pipe 312, is specifically regarded
Depending on actual conditions.
In the course of the work, the first scanning signal in first GOA unit 110 output is holding for the first useful signal
During continuous, the first switch pipe 311 in connected gating unit 310 is opened, and second GOA unit 210 is defeated step by step
Go out the second scanning signal to open the second switch pipe 312 of the gating unit 310 being connected with first GOA unit 110, to realize
The purpose of the pixel gating that control is connected with first GOA unit 110 successively.
It is described with reference to Fig. 7 and Fig. 8, Fig. 7 in another embodiment of the application on the basis of above-described embodiment
The structural representation of GOA circuits, Fig. 8 is the driver' s timing schematic diagram of the GOA circuits shown in Fig. 7；The GAO circuits also include：
3rd GOA modules 400,
The 3rd GOA modules 400 include X the 3rd GOA unit 410, and each described 3rd GOA unit 410 is described
When second scanning signal is the first useful signal, its output end exports the 3rd scanning signal step by step, each described 3rd scanning letter
Number for controlling pixel gating.
In the present embodiment, the GOA circuits use M+N+X GOA unit, it is possible to achieve control M × N × X pixel
The purpose of gating.The reduction of GOA unit is further realized, specifically, by taking Fig. 7 as an example, in the figure 7, M=N=X=2, each institute
State the first GOA unit 110 to be electrically connected with 4 pixels by the gating circuit 300 respectively, in each first GOA unit
In 4 pixels of 110 electrical connections, each second GOA unit 210 is electrically connected with two of which pixel, each the 3rd GOA unit
410 electrically connect with wherein two other pixel.GOA circuits shown in Fig. 7 realize control 2 using 2+2+2=6 GOA unit
× 2 × 2=8 purpose of pixel gating, reduces the quantity of GOA unit in GOA circuits.And when pixel quantity is more,
The GOA unit quantity that it is reduced is more compared to the GOA circuits only with a GOA modules 100 and the 2nd GOA modules 200, example
Such as, when pixel quantity is 15625, only there is a GOA modules 100 and the GOA circuits of the 2nd GOA modules 200 at least to need
125+125=250 GOA unit (125 × 125=15625)；And GOA circuits in the present embodiment at least only need to 25+25
+ 25=75 GOA unit (25 × 25 × 25=15625), the GOA required for further reducing the GOA circuits is mono-
First quantity.
Referring still to Fig. 7, the GOA circuits also include gating circuit 300, and the gating circuit 300 includes multiple gating
Unit 310, each gating unit 310 is connected with a pixel, and the gating unit 310 includes that first switch pipe 311, second open
Close the switching tube 313 of pipe 312 and the 3rd；
The first end of each first switch pipe 311 is connected, the first switch in the same gating unit 310
Second end of pipe 311 is connected with the first end of the second switch pipe 312, the second end of the second switch pipe 312 with it is described
The first end of the 3rd switching tube 313 is connected, and the second end of the 3rd switching tube 313 is connected with the corresponding pixel, described
The control end of first switch pipe 311 is connected with the output end of first GOA unit 110, the control of the second switch pipe 312
End is connected with the output end of second GOA unit 210, control end and the 3rd GOA unit of the 3rd switching tube 313
310 output end is connected.
Likewise, the first switch pipe 311, the second switch pipe 312 and the 3rd switching tube 313 can be equal
It is N-type transistor, P-type transistor can also be.When the first switch pipe 311, the second switch pipe 312 and described
When 3rd switching tube 313 is N-type transistor, first useful signal is high level；When the first switch pipe 311, institute
State second switch pipe 312 and when the 3rd switching tube 313 is P-type transistor, first useful signal is low level.
The application to the specific species of the first switch pipe 311, the second switch pipe 312 and the 3rd switching tube 313 simultaneously
Do not limit, it is specific depending on actual conditions.
Accordingly, the embodiment of the present application additionally provides a kind of array base palte, including multi-strip scanning line and any as described above
GOA circuits described in embodiment, the output end of the GOA circuits passes sequentially through the scan line and is corresponded with the pixel and connects
Connect.
Accordingly, the embodiment of the present application additionally provides a kind of display device, including the array base as described in above-mentioned embodiment
Plate.
In sum, the embodiment of the present application provides a kind of GOA circuits, array base palte and display device, wherein, it is described
GOA circuits include the GOA modules being made up of M the first GOA unit and the 2nd GOA moulds being made up of N number of second GOA unit
Block, the output end of each first GOA unit exports the first scanning signal step by step, and each described second GOA unit is described
When first scanning signal is the first useful signal, its output end exports the second scanning signal step by step, to realize controlling pixel successively
The function of gating.The GOA circuits are realized the purpose of the strobe state of control M × N number of pixel by M+N GOA unit, so that
The quantity of GOA unit in GOA circuits is greatly reduced, is such as 960 × 640 with pixel quantity, M=960, N=640 are
Example, (960 × 640- (960+640)=) 612800 GOA units are reduced compared to GOA circuits of the prior art, and then
The volume of GOA circuits is greatly reduced, is also largely reduced and is realized narrow side using the display device of the GOA circuits
The difficulty of frame.
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.To the upper of the disclosed embodiments
State bright, professional and technical personnel in the field is realized or use the present invention.To various modifications of these embodiments to ability
Be will be apparent for the professional and technical personnel in domain, generic principles defined herein can not depart from it is of the invention
In the case of spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the most wide scope consistent with principles disclosed herein and features of novelty.
Claims (8)
1. a kind of GOA circuits, it is characterised in that including：First GOA modules and the 2nd GOA modules,
The first GOA modules include M the first GOA unit, and the output end of each first GOA unit exports first step by step
Scanning signal,
The 2nd GOA modules include N number of second GOA unit, and each described second GOA unit is in first scanning signal
During the first useful signal, its output end exports the second scanning signal step by step, and each described second scanning signal is used to control one
Pixel is gated.
2. GOA circuits according to claim 1, it is characterised in that also including gating circuit, the gating circuit includes many
Individual gating unit, each gating unit is connected with a pixel, and the gating unit includes first switch pipe and second switch
Pipe；
The first end of each first switch pipe is connected, the second end of the first switch pipe in the same gating unit
First end with the second switch pipe is connected, and the second end of the second switch pipe is connected with the corresponding pixel, described
The control end of first switch pipe is connected with the output end of first GOA unit, the control end of the second switch pipe with it is described
The output end of the second GOA unit is connected.
3. GOA circuits according to claim 2, it is characterised in that the first switch pipe and the second switch pipe
It is N-type transistor or P-type transistor.
4. GOA circuits according to claim 1, it is characterised in that also include：3rd GOA modules,
The 3rd GOA modules include X the 3rd GOA unit, and each described 3rd GOA unit is in second scanning signal
During the first useful signal, its output end exports the 3rd scanning signal step by step, and each described 3rd scanning signal is used to control one
Pixel is gated.
5. GOA circuits according to claim 4, it is characterised in that also including gating circuit, the gating circuit includes many
Individual gating unit, each gating unit is connected with a pixel, the gating unit include first switch pipe, second switch pipe with
And the 3rd switching tube；
The first end of each first switch pipe is connected, the second end of the first switch pipe in the same gating unit
First end with the second switch pipe is connected, the first end phase of the second end of the second switch pipe and the 3rd switching tube
Even, the second end of the 3rd switching tube is connected with the corresponding pixel, the control end of the first switch pipe and described the
The output end of one GOA unit is connected, and the control end of the second switch pipe is connected with the output end of second GOA unit, institute
The control end for stating the 3rd switching tube is connected with the output end of the 3rd GOA unit.
6. GOA circuits according to claim 5, it is characterised in that the first switch pipe, the second switch pipe and
3rd switching tube is N-type transistor or P-type transistor.
7. a kind of array base palte, it is characterised in that the GOA including multi-strip scanning line and as described in claim any one of 1-6
Circuit, the output end of the GOA circuits passes sequentially through the scan line and is connected one to one with the pixel.
8. a kind of display device, it is characterised in that including array base palte as claimed in claim 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710109275.2A CN106847155B (en) | 2017-02-27 | 2017-02-27 | GOA circuit, array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710109275.2A CN106847155B (en) | 2017-02-27 | 2017-02-27 | GOA circuit, array substrate and display device |
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| CN106847155B CN106847155B (en) | 2021-03-19 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656066A (en) * | 2018-12-24 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and display device |
| CN110910775A (en) * | 2019-11-26 | 2020-03-24 | 深圳市华星光电半导体显示技术有限公司 | Display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070103346A1 (en) * | 2005-11-04 | 2007-05-10 | Novatek Microelectronics Corp. | Matrix decoder |
| CN103345911A (en) * | 2013-06-26 | 2013-10-09 | 京东方科技集团股份有限公司 | Shifting register unit, gate drive circuit and display device |
| CN103390392A (en) * | 2013-07-18 | 2013-11-13 | 合肥京东方光电科技有限公司 | GOA (gate driver on array) circuit, array substrate, display device and driving method |
| US20140055329A1 (en) * | 2011-04-28 | 2014-02-27 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| CN104217694A (en) * | 2014-09-04 | 2014-12-17 | 深圳市华星光电技术有限公司 | Scanning driving circuit and display panel |
| CN104835466A (en) * | 2015-05-20 | 2015-08-12 | 京东方科技集团股份有限公司 | Scan driving circuit, array substrate, display device and driving method |
| CN105096874A (en) * | 2015-08-12 | 2015-11-25 | 武汉华星光电技术有限公司 | GOA (Gate Driver On Array) circuit, array substrate and liquid crystal display |
-
2017
- 2017-02-27 CN CN201710109275.2A patent/CN106847155B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070103346A1 (en) * | 2005-11-04 | 2007-05-10 | Novatek Microelectronics Corp. | Matrix decoder |
| US20140055329A1 (en) * | 2011-04-28 | 2014-02-27 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| CN103345911A (en) * | 2013-06-26 | 2013-10-09 | 京东方科技集团股份有限公司 | Shifting register unit, gate drive circuit and display device |
| CN103390392A (en) * | 2013-07-18 | 2013-11-13 | 合肥京东方光电科技有限公司 | GOA (gate driver on array) circuit, array substrate, display device and driving method |
| CN104217694A (en) * | 2014-09-04 | 2014-12-17 | 深圳市华星光电技术有限公司 | Scanning driving circuit and display panel |
| CN104835466A (en) * | 2015-05-20 | 2015-08-12 | 京东方科技集团股份有限公司 | Scan driving circuit, array substrate, display device and driving method |
| CN105096874A (en) * | 2015-08-12 | 2015-11-25 | 武汉华星光电技术有限公司 | GOA (Gate Driver On Array) circuit, array substrate and liquid crystal display |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656066A (en) * | 2018-12-24 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel and display device |
| CN110910775A (en) * | 2019-11-26 | 2020-03-24 | 深圳市华星光电半导体显示技术有限公司 | Display device |
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| CN106847155B (en) | 2021-03-19 |
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