CN106023935B - Liquid crystal display device and its driving method - Google Patents
Liquid crystal display device and its driving method Download PDFInfo
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- CN106023935B CN106023935B CN201610599679.XA CN201610599679A CN106023935B CN 106023935 B CN106023935 B CN 106023935B CN 201610599679 A CN201610599679 A CN 201610599679A CN 106023935 B CN106023935 B CN 106023935B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
- G09G3/364—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with use of subpixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention discloses a kind of liquid crystal display devices comprising: liquid crystal display panel, including display area and fan-out area are provided with sub-pixel in the display area in array, correspond to each column sub-pixel in the fan-out area and be respectively arranged with connecting line；Source electrode driver provides data-signal to sub-pixel by the connecting line；Gate drivers generate corresponding scanning signal according to top rake voltage and improve to sub-pixel；Top rake circuit, for providing top rake voltage to gate drivers；Wherein, the rising edge of the top rake voltage has preceding top rake, and failing edge has rear top rake；The rising edge of the scanning signal has the first rake, and failing edge has the second rake.The present invention also provides the driving methods of liquid crystal display device as described above.Effective charging time of the sub-pixel of each region reaches unanimity in display panel in the present invention so that the sub-pixel of both sides of the display panel region and intermediate region charging uniformly, improve colour cast the problem of, mention high display quality.
Description
Technical field
The present invention relates to display technology field, in particular to a kind of liquid crystal display device and its driving method.
Background technique
Liquid crystal display (Liquid Crystal Display, LCD) is the display equipment of planar ultra-thin, it is by certain
The colour or monochrome pixels of quantity form, and are placed in front of light source or reflecting surface.Liquid crystal display power consumption is very low, and has
High image quality, small in size, light-weight feature, therefore favored by everybody, become the mainstream of display.
Generally, the display panel in liquid crystal display includes scan line and data line, and data line passes through source electrode driver
It drives, scan line driven by gate drivers.Due in existing large scale liquid crystal panel, from source electrode driver to aobvious
Show that the signal wire at panel both ends is longer than the signal wire in source electrode driver to panel center, such that data line in panel
WOA (Wire on Array) cabling in the resistance value for being fanned out to the area (Fanout) there are larger difference, and such resistance difference meeting
Lead to the poor display effect of panel, and then influences display quality.
Fig. 1 be it is existing it is a kind of using three gates (Tri-Gate) drive framework liquid crystal display device schematic diagram, Fig. 2 be as
The structural schematic diagram of the pixel unit of the liquid crystal display device of Fig. 1.Referring to Fig.1 and 2, having in display panel therein more
The pixel unit of a array arrangement, wherein each pixel unit P includes sub-pixel R, G, B along column direction sequential, son
Pixel R, G, B respectively by corresponding switch element and corresponding scan line (such as G1~G6 in Fig. 2) and data line (such as
D1~D5 in Fig. 2) it is electrically connected.Since this kind drives framework, corresponding each pixel unit only has a data line and three are swept
Retouch line, that is to say, that the data-signal of each pixel unit is transmitted by a data line, is sequentially transmitted by three scan lines
The signal of the switch element of each sub-pixel is opened, and then realizes the complete display of each pixel unit, to save source electrode
The quantity of driver reduces the cost of liquid crystal display panel.
However, by taking Fig. 1 as an example, it is assumed that source electrode driver only one, such that the WOA of the data line in panel is walked
There are larger differences for resistance value of the line in the area Fanout.As shown in Figure 1, due to the WOA for being output to panel both ends of source electrode driver
Cable run distance L1Much larger than the distance L that source electrode driver is output to panel center2, therefore the WOA cabling of the data line of two sides is total
Resistance value can reach 5K Ω~7K Ω, and the resistance value of the WOA cabling of intermediate data line only has 300~500 Ω.In this way, biggish
The resistance value of WOA cabling can make data line that can generate serious RC retardation ratio when transmitting data-signal, LCD display board ends
The charging rate of pixel obviously lags the pixel among panel, and each pixel charging of panel is uneven, will lead to shown by panel
There is color offset phenomenon in picture, influences to show quality.
Problem as described above is described in detail in one specific example of lower mask.It is Fig. 1 institute refering to Fig. 3 a and Fig. 3 b, Fig. 3 a
The liquid crystal display device shown data line D when showing low ash rank colour mixture picturen/2The voltage wave of (data line positioned at panel center)
Shape figure, Fig. 3 b are liquid crystal display device shown in FIG. 1 data line D when showing low ash rank colour mixture picture1(it is located at panel most edge
Data line, be also possible to Dn) voltage oscillogram.Herein, using the yellow picture of 128 grayscale as low ash rank colour mixture picture
An example, red R, green G, each hue region indigo plant B grayscale value be respectively 128,128 and 0.
A referring to figure 3., VGH indicate that grid on-state voltage, VGH (off) indicate that grid ON state is finally closed some voltage and (claimed
For top rake voltage), it is a certain special voltage of grid on-state voltage, V128Indicate the voltage of display grayscale value 128.Due to position
Data line D in panel centern/2WOA cabling resistance value it is minimum, therefore can filling the sub-pixel of the corresponding data line
Electricity condition is considered as perfect condition, i.e. any variation does not occur for the charging voltage of R sub-pixel and G sub-pixel.Moreover, R sub-pixel and G
The charging time of sub-pixel is identical, is T2.In this way, the region of display panel corresponding with these sub-pixels can show it is desired
Yellow picture, be not in color offset phenomenon.
And in fig 3b, 90%*V128The effective voltage for indicating display grayscale value 128, is the electricity for showing grayscale value 128
The 90% of pressure value selects 90% or more voltage value can be with as effective voltage certainly.Due to being located at the data line of panel side
D1WOA cabling resistance value it is very big, the RC retardation ratio of generation is also larger, thus cause the charging voltage of R sub-pixel and G sub-pixel send out
Changing, for R sub-pixel, due to RC retardation ratio effect, the charging time of R sub-pixel is also greatly reduced (as schemed
Effective charging time T in 3b1), T1With T2Differ larger.It is will lead in this way corresponding to data line D1R sub-pixel charging electricity
It measures and corresponds to Dn/2The charge capacity of R sub-pixel there are biggish differences, that is, both sides of the display panel region and intermediate region
Sub-pixel charging it is uneven, will lead to picture shown by panel and color offset phenomenon occur, influence to show quality.
Summary of the invention
In view of the deficiencies in the prior art, the present invention provides a kind of liquid crystal display device and its driving method, by sweeping
The waveform for retouching signal is improved so that in display panel effective charging time of the sub-pixel of each region reach unanimity, make
The problem of sub-pixel charging for obtaining both sides of the display panel region and intermediate region is uniform, improves colour cast, mentions high display quality.
To achieve the goals above, present invention employs the following technical solutions:
A kind of liquid crystal display device comprising: liquid crystal display panel, including display area and fan-out area, the display area
In be provided with sub-pixel in array, each column sub-pixel is corresponded in the fan-out area and is respectively arranged with connecting line；Source electrode drives
Dynamic device provides data-signal to sub-pixel by the connecting line in the fan-out area；Gate drivers are produced according to top rake voltage
Raw corresponding scanning signal is improved to the sub-pixel；Top rake circuit, for providing top rake voltage to the gate drivers；Its
In, the rising edge of the top rake voltage has preceding top rake, and failing edge has rear top rake；The rising edge of the scanning signal corresponds to
The preceding top rake has the first rake, and failing edge, which corresponds to the rear top rake, has the second rake.
Wherein, the top rake circuit includes: DC voltage input end and top rake voltage output end；Switching circuit will input
DC voltage be converted to top rake voltage and export；First control circuit is connected to the DC voltage input end and described opens
Between powered-down road；The first control circuit, which receives the first clock signal and generates first control signal, is connected to the switch electricity
Road is converted to the top rake voltage that rising edge has preceding top rake to control the switching circuit for DC voltage；Second control circuit,
It is connected between the top rake voltage output end and the switching circuit；The second control circuit receives the second clock signal simultaneously
It generates second control signal and is connected to the switching circuit, to control the failing edge tool of the top rake voltage of the switching circuit output
There is rear top rake.
Wherein, the switching circuit includes a p-type metal-oxide-semiconductor, and the drain electrode of the p-type metal-oxide-semiconductor is connected to the DC voltage
Input terminal, source electrode are connected to the top rake voltage output end, and grid is connected to the first control circuit；The first control electricity
Road includes first resistor, second resistance, the first N-type metal-oxide-semiconductor and first capacitor；The first resistor and second resistance are mutually gone here and there
Connection, the first resistor are connected to the DC voltage input end, and the second resistance is connected to the first N-type metal-oxide-semiconductor
Drain electrode；The source electrode of the first N-type metal-oxide-semiconductor is connected to ground, and grid receives first clock signal；The one of the first capacitor
End is connected to ground, and the other end is connected between the first resistor and second resistance and is also connected to the grid of the p-type metal-oxide-semiconductor
Pole；The second control circuit includes 3rd resistor, the second N-type metal-oxide-semiconductor and the second capacitor；One end of the 3rd resistor connects
To the source electrode of the p-type metal-oxide-semiconductor, the other end is connected to the drain electrode of the second N-type metal-oxide-semiconductor；The source of the second N-type metal-oxide-semiconductor
Pole is connected to ground, and grid receives second clock signal；One end of second capacitor is connected to ground, and the other end is connected to institute
State top rake voltage output end；Wherein, when first clock signal is high level, the second clock signal is low level；Work as institute
State the first clock signal be low level when, the second clock signal be high level.
Wherein, a reverse phase is connected between the grid of the first N-type metal-oxide-semiconductor and the grid of the second N-type metal-oxide-semiconductor
Device, received first clock signal of the grid of the first N-type metal-oxide-semiconductor are believed by forming second timing after the phase inverter
Number.
Wherein, the time span that first rake is adjusted by adjusting the capacitance of the first capacitor, passes through
The capacitance of second capacitor is adjusted to adjust the time span of second rake.
Wherein, first rake is between preceding top rake voltage and the on-state voltage of the scanning signal, and described
Two rakes are located between the on-state voltage and rear top rake voltage of the scanning signal.
Wherein, criss-cross multiple data lines and multi-strip scanning line, the sub-pixel are provided in the display area
Positioned at the intersection region of data line and scan line, all sub-pixels with a line are connected to same scan line, and same row owns
Sub-pixel connects same data line；Wherein, each data line is corresponded by a connecting line in the fan-out area
Ground is connected to the source electrode driver, and each column sub-pixel includes the red sub-pixel being periodically arranged successively, green sub-pixels
And blue subpixels.
Wherein, the time span of first rake is T3；For the sub- picture of a most marginal column in the display panel
The voltage of element, the signal delay as caused by the impedance of the connecting line in the fan-out area, the data-signal has risen to
The time span for imitating charging voltage is T4；Wherein, T3=(1 ± 5%) T4。
Wherein, effective charging voltage is 90% or more of target charging voltage.
The present invention also provides the driving methods of liquid crystal display device as described above comprising: it is produced by source electrode driver
Raw data-signal is supplied to sub-pixel by the connecting line in fan-out area；Generating a rising edge by top rake circuit has preceding top rake
And there is failing edge the top rake voltage of rear top rake to be supplied to gate drivers；One is generated according to top rake voltage by gate drivers
Rising edge with the first rake and failing edge there is the scanning signal of the second rake to improve to sub-pixel.
Liquid crystal display device and its driving method provided in an embodiment of the present invention, generating a rising edge by top rake circuit has
There is the top rake voltage of rear top rake to be supplied to gate drivers, the scanning signal that gate drivers generate for preceding top rake and failing edge
Waveform there is the first rake in rising edge, that is, delay the charging initial time of each sub-pixel, the charging postponed rises
Time beginning is roughly the same with the delay time of data-signal most marginal in display panel, so that display panel intermediate region has
Effect charging time and effective charging time of two side areas reach unanimity, so that the son in both sides of the display panel region and intermediate region
The problem of pixel charging is uniform, improves colour cast, mentions high display quality.
Detailed description of the invention
Fig. 1 is a kind of existing schematic diagram using three gate liquid crystal display devices；
Fig. 2 is the structural schematic diagram of the pixel unit of the liquid crystal display device such as Fig. 1；
Fig. 3 a be liquid crystal display device shown in FIG. 1 when showing low ash rank colour mixture picture positioned at the data line in panel center
Voltage oscillogram；
Fig. 3 b is that liquid crystal display device shown in FIG. 1 is located at the most marginal data of panel when showing low ash rank colour mixture picture
The voltage oscillogram of line；
Fig. 4 is the schematic diagram of liquid crystal display device provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of top rake circuit provided in an embodiment of the present invention；
Fig. 6 is input and the signal output waveform figure of the top rake circuit such as Fig. 5；
Fig. 7 a is that the liquid crystal display device of the embodiment of the present invention is central positioned at panel when showing low ash rank colour mixture picture
The voltage oscillogram of data line；
Fig. 7 b is that the liquid crystal display device of the embodiment of the present invention is located at panel most edge when showing low ash rank colour mixture picture
Data line voltage oscillogram.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, with reference to the accompanying drawing to specific reality of the invention
The mode of applying is described in detail.The example of these preferred embodiments is illustrated in the accompanying drawings.Shown in attached drawing and according to
The embodiments of the present invention of attached drawing description are only exemplary, and the present invention is not limited to these embodiments.
Here, it should also be noted that, in order to avoid having obscured the present invention because of unnecessary details, in the accompanying drawings only
Show with closely related structure and/or processing step according to the solution of the present invention, and be omitted little with relationship of the present invention
Other details.
The present embodiment provides firstly a kind of liquid crystal display device, as shown in figure 4, the liquid crystal display device includes display
Panel 10, source electrode driver 20, gate drivers 30 and sequence controller 40, gate drivers 30 are also connected with top rake circuit
50。
Wherein, the sequence controller 40 is used for the source electrode driver 20 and the gate drivers 30 and top rake
Circuit 50 provides timing control signal, and also sends picture signal to be shown to the source electrode driver 20.The source electrode
Driver 20 generates corresponding according to the timing control signal and picture signal to be shown that receive from the sequence controller 40
Data-signal be supplied to the display panel 10, the gate drivers 30 are produced according to timing control signal and top rake voltage
Raw corresponding scanning signal is supplied to the display panel 10, and the top rake circuit 50 generates top rake electricity according to timing control signal
Pressure is supplied to the gate drivers 30.
Wherein, as shown in figure 4, the display panel 10 includes display area 11 and fan-out area 12.In display area 11
It is provided with criss-cross multiple data lines D1、Dn/2、DnWith multi-strip scanning line S1、Sn, the intersection region of data line and scan line
It is formed with sub-pixel Px, all sub-pixel Px with a line are connected to same scan line, all sub-pixel Px connections of same row
Same data line, it should be noted that in Fig. 4 the merely exemplary a part of data line for showing display area 11 and scan line with
And sub-pixel Px.In the present embodiment, identical as the structure of Fig. 2, the corresponding three sub-pixel Px of each pixel unit P are perpendicular
It arranges (in same row), the corresponding three sub-pixel Px of each pixel unit P are followed successively by red sub-pixel R, green sub-pixels G
With blue subpixels B.Further, connecting line L is provided in the fan-out area 121、Ln, each connecting line and a data line
It is connected with each other.Source drive module 20 provides data to each column sub-pixel Px by each connecting line and its corresponding data line
Signal, gate drivers 30 provide scanning signal to every a line sub-pixel Px by every scan line.
Wherein, the rising edge for the top rake voltage that top rake circuit 50 generates in the present embodiment has preceding top rake, and failing edge has
Top rake afterwards.Correspondingly, the rising edge for the scanning signal that gate drivers 30 generate, which corresponds to the preceding top rake, has the first inclination
Portion, failing edge, which corresponds to the rear top rake, has the second rake.
Rising edge to scanning signal is provided with the first rake, when delaying the charging starting of each sub-pixel
Between, so that effective charging time of display panel intermediate region and effective charging time of two side areas reach unanimity, so that aobvious
Show that the sub-pixel charging of panel two side areas and intermediate region is uniform, achievees the purpose that improve colour cast.
Specifically, the top rake circuit 50 in the present embodiment is as shown in figure 5, the top rake circuit 50 is inputted including DC voltage
End 51, top rake voltage output end 52, switching circuit 53, first control circuit 54 and second control circuit 55.Wherein, direct current
Input terminal 51 is pressed to receive DC voltage from voltage source, the DC voltage of input is converted to top rake voltage, top rake electricity by switching circuit
Press output end 52 by the top rake voltage output of conversion formation to gate drivers.First control circuit 54 is connected to the direct current
It presses between input terminal 51 and the switching circuit 53, the first control circuit 54 receives the first clock signal and generates the first control
Signal processed is connected to the switching circuit 53, cuts before being converted to rising edge to control the switching circuit 53 for DC voltage and having
The top rake voltage at angle；Second control circuit 55 is connected between the top rake voltage output end 52 and the switching circuit 53, institute
It states the second clock signal of reception of second control circuit 55 and generates second control signal and be connected to the switching circuit 53, with control
The failing edge for the top rake voltage that the switching circuit 53 exports has rear top rake.Wherein, the first clock signal and the second timing letter
It number is provided by sequence controller.
Specifically, a kind of specific circuit structure of the top rake circuit 50 is as shown in figure 5, the switching circuit 53 includes
One p-type metal-oxide-semiconductor Q1, the p-type metal-oxide-semiconductor Q1Drain electrode be connected to the DC voltage input end 51, source electrode is connected to the top rake
Voltage output end 52, grid are connected to the first control circuit 54.The first control circuit 54 includes first resistor R1,
Two resistance R2, the first N-type metal-oxide-semiconductor Q2With first capacitor C1；The first resistor R1With second resistance R2It is serially connected, described first
Resistance R1It is connected to the DC voltage input end 51, the second resistance R2It is connected to the first N-type metal-oxide-semiconductor Q2Drain electrode；
The first N-type metal-oxide-semiconductor Q2Source electrode be connected to ground, grid receive the first clock signal GVON；The first capacitor C1One end
It is connected to ground, the other end is connected to the first resistor R1With second resistance R2Between and be also connected to the p-type metal-oxide-semiconductor
Grid Q1.The second control circuit 55 includes 3rd resistor R3, the second N-type metal-oxide-semiconductor Q3With the second capacitor C2；The third electricity
Hinder R3One end be connected to the p-type metal-oxide-semiconductor Q1Source electrode, the other end is connected to the second N-type metal-oxide-semiconductor Q3Drain electrode；It is described
Second N-type metal-oxide-semiconductor Q3Source electrode be connected to ground, grid receive the second clock signal GVOFF；The second capacitor C2One end with
Ground connection, the other end are connected to top rake voltage output end 52.Wherein, when the first clock signal GVON is high level, the
Two clock signal GVOFF are low level；When the first clock signal GVON is low level, the second clock signal GVOFF is
High level.It, can be by timing control since the level of the first clock signal GVON and the second clock signal GVOFF are reverse phases
The same signal pins of device processed provide, as long as increasing by one instead in the first clock signal GVON and the second clock signal GVOFF
Phase device, specific in the present embodiment, as shown in figure 5, the first N-type metal-oxide-semiconductor Q2Grid and the second N-type MOS
Pipe Q3Grid between be connected with a phase inverter 56, the first N-type metal-oxide-semiconductor Q2The received first clock signal GVON of grid
By forming the second clock signal GVOFF after the phase inverter 56.
Refering to the waveform diagram of Fig. 6, wherein VGHP indicates that the DC voltage of input, VG indicate the top rake voltage of output.Such as Fig. 5
Shown in top rake circuit 50 specific work process it is as follows:
When the first clock signal GVON is high level, the second clock signal GVOFF is low level, at this time the first control electricity
The first N-type metal-oxide-semiconductor Q in road 542It is connected, the second N-type metal-oxide-semiconductor Q in second control circuit 553Cut-off.First capacitor C1Pass through
Second resistance R2Electric discharge, first capacitor C1The current potential at both ends is gradually lower and makes p-type metal-oxide-semiconductor Q1It is gradually opened, by the straight of input
Galvanic electricity pressure VGHP is converted to top rake voltage VG, and the top rake voltage VG of output climbs lofty perch from low spot, the rising of top rake voltage VG
Along with preceding top rake.
When the first clock signal GVON is low level, the second clock signal GVOFF is high level, at this time the first control electricity
The first N-type metal-oxide-semiconductor Q in road 542End, the second N-type metal-oxide-semiconductor Q in second control circuit 553Conducting.Second capacitor C2Pass through
3rd resistor R3Electric discharge, the second capacitor C2The current potential at both ends is gradually lower, and the top rake voltage VG of output drops to low spot from high point,
The failing edge of top rake voltage VG has rear top rake.
Further, gate drivers 30 are according to top rake voltage generation scanning signal, therefore the rising edge of scanning signal
Top rake has the after there is preceding top rake corresponding to the top rake voltage the first rake, failing edge to correspond to the top rake voltage
Two rakes.Wherein by adjusting the first capacitor C1Capacitance to adjust the time span of first rake, lead to
It crosses and adjusts the second capacitor C2Capacitance to adjust the time span of second rake.
It specifically, is liquid crystal display device in the embodiment of the present invention in display low ash rank refering to Fig. 7 a and Fig. 7 b, Fig. 7 a
Data line D when colour mixture picturen/2The voltage oscillogram of (data line positioned at panel center), Fig. 7 b are in the embodiment of the present invention
Liquid crystal display device data line D when showing low ash rank colour mixture picture1(it is located at the most marginal data line of panel, is also possible to Dn)
Voltage oscillogram.In figure, VGH indicates that the on-state voltage of scanning signal, VGH (off) indicate that ON state is finally closed some voltage and (claimed
For rear top rake voltage), it is a certain special voltage of on-state voltage, top rake voltage, V before VGH ' is indicated128Indicate display grayscale value
128 voltage, 90%*V128The effective voltage for indicating display grayscale value 128, is the voltage value for showing grayscale value 128
90%, certainly, 90% or more voltage value is selected to be ok as effective voltage.
Herein, an example using the yellow picture of 128 grayscale as low ash rank colour mixture picture, red R, green G, indigo plant B are each
The grayscale value of hue region is respectively 128,128 and 0.Fig. 7 a is please referred to, due to being located at the data line D in panel centern/2WOA
The resistance value of cabling is minimum, therefore the charged state of the sub-pixel of the corresponding data line can be considered as perfect condition, i.e. R picture
Any variation does not occur for the charging voltage of element and G sub-pixel.And the rising edge of scanning voltage signal has the first rake, decline
Along having the second rake, specific as in Fig. 7 a, first rake is located at preceding top rake voltage VGH ' and the scanning signal
On-state voltage VGH between, second rake is located at the on-state voltage VGH and rear top rake voltage VGH of the scanning signal
(off) between.The time span of first rake is T3, in T3Period in, scanning voltage signal is ramp-up period,
The charging ability of data line is weaker.Therefore, effective charging time T of each sub-pixel1ON state is risen to for scanning voltage signal
Voltage VGH starts, until the period between rear top rake voltage VGH (off), with the existing charging situation phase as in Fig. 3 a
Than keeping effective charging time T for being located at the region in panel center1On the basis of, data line is weakened to each height picture
(charging time is by T for the charging ability of element2It is reduced to T1).Fig. 7 b is please referred to, due to being located at the data line D of panel side1WOA
The resistance value of cabling is very big, and the RC retardation ratio of generation is also larger, therefore the charging voltage of R sub-pixel and G sub-pixel is caused to change,
For R sub-pixel, due to RC retardation ratio effect, the voltage of data-signal rises to the when span of effective charging voltage
Degree is T4, the voltage of data-signal rises to the time point of effective charging voltage and scanning voltage signal rises to on-state voltage
The time point of VGH is identical, and therefore, effective charging time of each sub-pixel is also T1, that is, the when span of the first rake of control
Spend T3End point and the voltage of data-signal rise to the time span T of effective charging voltage4End point it is roughly the same, can
The error for allowing to have 5% or so.
Based on above scanning signal, effective charging time T is being kept1On the basis of, it is located at panel center by reducing
Region sub-pixel charging time so that effective charging time of display panel intermediate region and two side areas are effectively filled
The electric time reaches unanimity so that the sub-pixel of both sides of the display panel region and intermediate region charging uniformly, improve colour cast the problem of,
Mention high display quality.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The above is only the specific embodiment of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (7)
1. a kind of liquid crystal display device characterized by comprising
Liquid crystal display panel, including display area and fan-out area are provided with sub-pixel in the display area in array, described to be fanned out to
Correspond to each column sub-pixel in region and is respectively arranged with connecting line；Criss-cross a plurality of number is provided in the display area
According to line and multi-strip scanning line, the sub-pixel is located at the intersection region of data line and scan line, and all sub-pixels with a line connect
It is connected to same scan line, all sub-pixels of same row connect same data line；Wherein, each data line is fanned out to by described
A connecting line in region is connected to source electrode driver correspondingly, and each column sub-pixel includes periodically being arranged successively
Red sub-pixel, green sub-pixels and blue subpixels；
Source electrode driver provides data-signal to sub-pixel by the connecting line in the fan-out area；
Gate drivers generate corresponding scanning signal according to top rake voltage and are supplied to the sub-pixel；
Top rake circuit, for providing top rake voltage to the gate drivers；
Wherein, the rising edge of the top rake voltage has preceding top rake, and failing edge has rear top rake；The rising edge of the scanning signal
There is the first rake corresponding to the preceding top rake, failing edge, which corresponds to the rear top rake, has the second rake；
First rake is between preceding top rake voltage and the on-state voltage of the scanning signal, second inclination position
Between the on-state voltage and rear top rake voltage of the scanning signal；
The time span of first rake is T3；For column sub-pixel most marginal in the display area, due to described
Signal delay caused by the impedance of connecting line in fan-out area, the voltage of the data-signal rise to effective charging voltage
Time span is T4；Wherein correspond to the charge cycle of each sub-pixel, time span T3End point and time span T4's
End point is identical.
2. liquid crystal display device according to claim 1, which is characterized in that the top rake circuit includes:
DC voltage input end and top rake voltage output end；
The DC voltage of input is converted to top rake voltage and exported by switching circuit；
First control circuit is connected between the DC voltage input end and the switching circuit；The first control circuit
It receives the first clock signal and generates first control signal and be connected to the switching circuit, to control the switching circuit for direct current
Voltage is converted to the top rake voltage that rising edge has preceding top rake；
Second control circuit is connected between the top rake voltage output end and the switching circuit；The second control circuit
It receives the second clock signal and generates second control signal and be connected to the switching circuit, to control the switching circuit output
The failing edge of top rake voltage has rear top rake.
3. liquid crystal display device according to claim 2, which is characterized in that the switching circuit includes a p-type metal-oxide-semiconductor,
The drain electrode of the p-type metal-oxide-semiconductor is connected to the DC voltage input end, and source electrode is connected to the top rake voltage output end, grid
It is connected to the first control circuit；
The first control circuit includes first resistor, second resistance, the first N-type metal-oxide-semiconductor and first capacitor；The first resistor
It is serially connected with second resistance, the first resistor is connected to the DC voltage input end, and the second resistance is connected to institute
State the drain electrode of the first N-type metal-oxide-semiconductor；The source electrode of the first N-type metal-oxide-semiconductor is connected to ground, and grid receives first clock signal；
One end of the first capacitor is connected to ground, and the other end is connected between the first resistor and second resistance and is also connected to
The grid of the p-type metal-oxide-semiconductor；
The second control circuit includes 3rd resistor, the second N-type metal-oxide-semiconductor and the second capacitor；One end of the 3rd resistor connects
It is connected to the source electrode of the p-type metal-oxide-semiconductor, the other end is connected to the drain electrode of the second N-type metal-oxide-semiconductor；The second N-type metal-oxide-semiconductor
Source electrode is connected to ground, and grid receives second clock signal；One end of second capacitor is connected to ground, and the other end is connected to
The top rake voltage output end；
Wherein, when first clock signal is high level, the second clock signal is low level；When first clock signal
When for low level, the second clock signal is high level.
4. liquid crystal display device according to claim 3, which is characterized in that the grid of the first N-type metal-oxide-semiconductor with it is described
A phase inverter, received first clock signal of the grid of the first N-type metal-oxide-semiconductor are connected between the grid of second N-type metal-oxide-semiconductor
By forming second clock signal after the phase inverter.
5. liquid crystal display device according to claim 3, which is characterized in that by adjusting the capacitance of the first capacitor
To adjust the time span of first rake, by adjusting the capacitance of second capacitor to adjust second inclination
The time span in portion.
6. liquid crystal display device according to claim 1, which is characterized in that effective charging voltage is target charging electricity
90% or more of pressure.
7. a kind of driving method of the liquid crystal display device as described in claim 1-6 is any characterized by comprising
Data-signal is generated by source electrode driver, sub-pixel is supplied to by the connecting line in fan-out area；
Generating a rising edge by top rake circuit with preceding top rake and failing edge there is the top rake voltage of rear top rake to be supplied to grid
Driver；
Generating a rising edge according to top rake voltage by gate drivers has the second inclination with the first rake and failing edge
The scanning signal in portion is supplied to sub-pixel.
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| CN108305589B (en) * | 2016-12-28 | 2022-12-30 | 矽创电子股份有限公司 | Driving module and driving method of display device |
| CN106847215B (en) * | 2017-03-02 | 2019-07-26 | 昆山龙腾光电有限公司 | Display device |
| CN107545873A (en) * | 2017-10-26 | 2018-01-05 | 惠科股份有限公司 | A kind of display device |
| CN107665687A (en) * | 2017-10-26 | 2018-02-06 | 惠科股份有限公司 | A kind of display device |
| CN108172189B (en) * | 2018-01-07 | 2020-05-05 | 浙江黄岩黎明实业有限公司 | Liquid crystal display device for forklift |
| CN108154861B (en) * | 2018-01-24 | 2020-10-30 | 昆山龙腾光电股份有限公司 | Chamfering voltage generating circuit and liquid crystal display device |
| CN108831404B (en) * | 2018-09-11 | 2020-08-11 | 惠科股份有限公司 | Display panel, driving method thereof and display device |
| CN109345989A (en) * | 2018-11-30 | 2019-02-15 | 苏州华兴源创科技股份有限公司 | A kind of driving method detecting liquid crystal display panel |
| CN109493818A (en) * | 2018-12-12 | 2019-03-19 | 惠科股份有限公司 | The driving circuit and device of display device, display panel |
| CN109509455A (en) * | 2018-12-25 | 2019-03-22 | 惠科股份有限公司 | Driving method, display device and the storage medium of display panel |
| CN113763858B (en) * | 2021-08-31 | 2022-05-10 | 惠科股份有限公司 | Display panel driving method, device, computer equipment and storage medium |
| CN114242007B (en) * | 2021-12-10 | 2023-06-30 | 重庆惠科金渝光电科技有限公司 | Pixel driving method and display device |
| CN114220374B (en) * | 2021-12-23 | 2024-03-26 | 绵阳惠科光电科技有限公司 | Display panel's chamfer circuit and display panel |
| CN114927112A (en) * | 2022-05-19 | 2022-08-19 | 滁州惠科光电科技有限公司 | Control method and control circuit of display panel and display device |
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| KR101483627B1 (en) * | 2008-07-29 | 2015-01-19 | 삼성디스플레이 주식회사 | Display device |
| JP2010032938A (en) * | 2008-07-31 | 2010-02-12 | Hitachi Displays Ltd | Liquid crystal display |
| CN103198804B (en) * | 2013-03-27 | 2015-09-16 | 深圳市华星光电技术有限公司 | A kind of liquid crystal indicator and driving method thereof |
| CN103247280B (en) * | 2013-05-14 | 2016-02-03 | 深圳市华星光电技术有限公司 | Top rake circuit and control method thereof |
| CN104332148A (en) * | 2014-11-20 | 2015-02-04 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and drive method thereof |
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