CN106847215B - Display device - Google Patents
Display device Download PDFInfo
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- CN106847215B CN106847215B CN201710121270.1A CN201710121270A CN106847215B CN 106847215 B CN106847215 B CN 106847215B CN 201710121270 A CN201710121270 A CN 201710121270A CN 106847215 B CN106847215 B CN 106847215B
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- 239000013078 crystal Substances 0.000 claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 16
- 230000005611 electricity Effects 0.000 description 6
- 210000002858 crystal cell Anatomy 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 3
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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Abstract
The invention discloses a kind of display devices, comprising: display panel；Power supply chip is connect with display panel, for providing supply voltage, and first group of clock signal of generation for display panel；Driving chip, for generating gain selection signals and grayscale signal according to second group of clock signal to drive display panel to show image；First time sequence adjusting circuit, is connected between driving chip and power supply chip, for first group of clock signal to be converted to second group of clock signal.Display device provided by the invention, it is converted into second group of clock signal needed for driving chip by first group of clock signal that the first time sequence adjusting circuit provides power supply chip, liquid crystal display device caused by timing needed for solving the problems, such as the timing of power supply chip offer and driving chip mismatches cannot normally be shown.
Description
Technical field
The invention belongs to display technology fields, more particularly, to a kind of display device.
Background technique
Since liquid crystal display device has many advantages, such as frivolous, energy saving, low-power consumption, TV, computer, hand have been widely used in it
In the electronic equipments such as machine, digital camera.
Fig. 1 shows the schematic block diagram of display device according to prior art.As shown in Figure 1, display device includes display
Panel 10, driving chip (Driver IC) 20 and power supply chip (Power IC) 30.Although display panel 10 not especially into
Row diagram, but it is configured with multiple pixels in a matrix form on the glass substrate, each pixel has the film being connected in series brilliant
Body pipe and liquid crystal cell.Common electric potential Vcom is applied to the liquid crystal cell of each pixel.The selection terminal of thin film transistor (TFT) is to arrange
Be connected to controlling grid scan line G1~Gm for unit, the signal terminal of thin film transistor (TFT) with behavior unit be connected to gated sweep
The source data line S1~Sn configured on the direction that line G1~Gm intersects.
In Fig. 1, driving chip 20 includes sequence controller 21, gate drivers 22 and source electrode driver 23, grid
Driver 22 is connect with a plurality of controlling grid scan line G1~Gm, for providing grid power supply, source electrode driver 23 and a plurality of source electrode number
According to line S1~Sn connection, for providing gray scale voltage.Sequence controller 21 respectively with gate drivers 22 and source electrode driver
23 are connected, to provide various clock signals to gate drivers 22 and source electrode driver 23.Within a frame period, lead to
Crossing as unit of controlling grid scan line, which is connected the thin film transistor (TFT) of pixel, carrys out selection gate scan line, in each of controlling grid scan line
Apply grayscale voltage from source data line S1~Sn to liquid crystal cell (during level display) during selection.The gray scale electricity applied
The capacitive component for being maintained as liquid crystal cell before select next time by cut-off due to thin film transistor (TFT) is pressed, liquid crystal cell is kept
Shutter (shutter) state of part.
The sequence controller 21 of liquid crystal display device needs external power supply chip 30 to provide DC voltage+5V or+12V.
For example, external power supply chip 30 to driving chip 20 provide source electrode positive pressure VSP, source electrode negative pressure VSN, grid positive pressure VGH and
Grid negative pressure VGL, however the timing and sequence controller 21 of VSP, VSN, VGH and VGL of the external offer of power supply chip 30
The timing of VSP, VSN, VGH and VGL of required outside are possible to inconsistent.
Fig. 2 a shows the waveform diagram for first group of clock signal that power supply chip provides in display device according to prior art.
As shown in Figure 2 a, the electrifying timing sequence that external power supply chip 30 provides is that VSP, VGH, VSN are powered on simultaneously；And VGL VSP,
It is powered on after VGH, VSN.Fig. 2 b shows second group of clock signal needed for driving chip in display device according to prior art
Waveform diagram.As shown in Figure 2 b, the electrifying timing sequence that driving chip 20 provides are as follows: VSP is powered on after rear VGH is powered on again, VGL is powered on
VSN is powered on again.As described above, the required electrifying timing sequence of electrifying timing sequence and driving chip 20 that power supply chip 30 provides is not
Match, cause liquid crystal display device that cannot normally show, or even will cause the damage of driving chip 20, influences service life.
Summary of the invention
The purpose of the present invention is to provide a kind of display devices.
According to an aspect of the present invention, a kind of display device is provided, comprising: display panel；Power supply chip, with the display
Panel connection, for providing supply voltage, and first group of clock signal of generation for the display panel；Driving chip, with institute
Display panel connection is stated, for generating gain selection signals and grayscale signal according to second group of clock signal to drive the display
Display panel image；First time sequence adjusting circuit is connected between the driving chip and power supply chip, when for by first group
Sequential signal is converted to second group of clock signal.
Preferably, the display panel has a plurality of grid line and multiple data lines intersected with each other and in the grid
Multiple pixels that the infall of line and the data line is formed；And the supply voltage includes grid voltage and source voltage.
Preferably, the driving chip includes: sequence controller, for providing second group of clock signal and display data
Signal；Gate drivers, for generating gain selection signals according to the grid voltage and applying the gain selection signals
To the grid line；Source electrode driver, for generating grayscale corresponding with the display data signal according to the source voltage
Voltage, and the gray scale voltage is applied to the data line.
Preferably, first group of clock signal includes third clock signal and the 4th clock signal, at described second group
Sequential signal includes the 5th clock signal and the 6th clock signal.
Preferably, first time sequence adjusting circuit includes: the first timing adjustment unit, for turning third clock signal
Change the 5th clock signal into；Second timing adjustment unit, for the 4th clock signal to be converted into the 6th clock signal；Wherein,
The third clock signal is the clock signal of grid negative pressure and source electrode negative pressure that power supply chip provides；4th clock signal
The clock signal of the grid positive pressure and source electrode positive pressure that are provided for power supply chip；5th clock signal is needed for driving chip
The clock signal of grid negative pressure and source electrode negative pressure；6th clock signal be grid positive pressure and source electrode needed for driving chip just
The clock signal of pressure.
Preferably, the first timing adjustment unit includes the first transistor and first resistor, wherein the first crystal
The control electrode of pipe is connected with the first signal input part；First pole of the first transistor is connected by first resistor and ground terminal
It connects；Second pole of the first transistor is connected with second signal input terminal；The control electrode of the first transistor and the first letter
Number output end is connected；Node between the first pole and first resistor of the first transistor is connected with second signal output end；
First signal input part is connected with grid negative pressure；The second signal input terminal is connected with source electrode negative pressure.
Preferably, the second adjustment unit includes second transistor and second resistance；Wherein, the second transistor
Control electrode is connected with third signal input part；First pole of the second transistor passes through second resistance and the second transistor
Control electrode connection；Node between the first pole and second resistance of the second transistor is connected with fourth signal input terminal；
The control electrode of the second transistor is connected with third signal output end；Second pole of the second transistor and fourth signal are defeated
Outlet is connected；
The third signal input part is connected with source electrode positive pressure, and the fourth signal input terminal is connected with grid positive pressure.
Preferably, the display device further includes the second time sequence adjusting circuit, for according to the first of driving chip the control
Signal and the first supply voltage generate second control signal, wherein the second control signal is for making power supply chip work
And generate first group of clock signal.
Preferably, the driving chip generates the first control signal according to second source voltage, wherein described first
Control signal is universal input/output interface signal.
Preferably, second time sequence adjusting circuit includes third transistor and 3rd resistor, wherein the third crystal
The control electrode of pipe is connected with the first control signal；First pole of the third transistor passes through 3rd resistor and the third
The control electrode of transistor connects；Node and second source voltage between first pole of the third transistor and 3rd resistor are believed
Number be connected；Second pole of the third transistor is connected with power supply chip, for exporting second control signal.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal is converted into second group of clock signal needed for driving chip, solves the timing and driving chip of power supply chip offer
The problem of liquid crystal display device caused by required timing mismatches cannot normally be shown.The second time sequence adjusting circuit is utilized simultaneously
Power supply chip works normally after so that driving chip is completed initialization, provides supply voltage to driving chip, keeps display normal, steady
It is fixed, improve the reliability of display device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic block diagram of display device according to prior art；
Fig. 2 a shows the waveform diagram for first group of clock signal that power supply chip provides in display device according to prior art；
Fig. 2 b shows the waveform diagram of second group of clock signal needed for driving chip in display device according to prior art；
Fig. 3 shows the schematic block diagram of display device according to an embodiment of the present invention；
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to an embodiment of the present invention.
Fig. 5 shows the schematic block diagram of display device according to an embodiment of the present invention；
Fig. 6 shows the circuit diagram of the second time sequence adjusting circuit of display device according to an embodiment of the present invention.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
The present invention can be presented in a variety of manners, some of them example explained below.
Fig. 3 shows the schematic block diagram of the display device provided according to embodiments of the present invention.As shown in figure 3, described aobvious
Showing device includes display panel 10, driving chip 20, power supply chip 30 and the first time sequence adjusting circuit 40.
Display panel 10 has a plurality of gate lines G 1-Gm and multiple data lines S1-Sn intersected with each other and in the grid
Multiple pixels that the infall of polar curve G1-Gm and the data line S1-Sn are formed.
Power supply chip 30 provides supply voltage for the display panel and generates first group of clock signal, wherein described
Supply voltage includes grid voltage and source voltage.Grid voltage is the open and close voltage of pixel upper switch pipe, is added in out
On the grid for closing pipe, including grid positive pressure VGH, grid negative pressure VGL, wherein VGH high level, which is opened, gives pixel capacitor charging,
VGL negative voltage turns off the switch pipe.Source voltage is liquid crystal drive power supply, can be to the capacitor charging of control pixel light transmission, packet
Include source electrode positive pressure VSP, source electrode negative pressure VSN.
Driving chip 20 is connect with the display panel 10, generates gain selection signals and ash according to second group of clock signal
Rank signal is to drive the display panel 10 to show image.
In the present embodiment, driving chip 20 includes sequence controller 21, gate drivers 22 and source electrode driver 23,
In, sequence controller 21 is for providing second group of clock signal and display data signal；Gate drivers 22 are used for according to institute
Grid voltage is stated to generate gain selection signals (VGH, VGL) and the gain selection signals are applied to the gate lines G 1-Gm；
Source electrode driver 23 is used to generate grayscale electricity corresponding with the display data signal according to the source voltage (VSP, VSN)
Pressure, and the gray scale voltage is applied to the data line S1-Sn.
First time sequence adjusting circuit 40 is connected between the driving chip 20 and power supply chip 30, for by first group
Clock signal is converted to second group of clock signal.
In the present embodiment, first group of clock signal includes third clock signal and the 4th clock signal, and described
Two groups of clock signals include the 5th clock signal and the 6th clock signal.First group of clock signal and second group of clock signal are
Clock signal between VGH, VGL, VSP, VSN.Third clock signal is the timing letter of VSN and VGL that power supply chip 30 provides
Number, the 4th clock signal is the clock signal of VSP and VGH that power supply chip 30 provides；5th clock signal is driving chip 20
The clock signal of required VSN and VGL, the 6th clock signal are the clock signal of VSP and VGH needed for driving chip 20.
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to an embodiment of the present invention.Such as Fig. 4 institute
Show, first time sequence adjusting circuit 40 includes the first timing adjustment unit 41 and the second timing adjustment unit 42, wherein first
Timing adjustment unit 41 is used to third clock signal being converted into the 5th clock signal；Second timing adjustment unit 42 is used for the
Four clock signals are converted into the 6th clock signal.
The first timing adjustment unit 41 includes the first transistor Q1 and first resistor R1, wherein the first crystal
The control electrode of pipe Q1 is connected with the first signal input part；The first pole of the first transistor Q1 passes through first resistor R1 and ground terminal
GND connection；The second pole of the first transistor Q1 is connected with second signal input terminal；The control electrode of the first transistor Q1 and the
One signal output end is connected；Node and second signal output end phase between the first pole of the first transistor Q1 and first resistor R1
Even.
Wherein, first signal input part is connected with grid negative pressure VGL；The second signal input terminal and source electrode negative pressure
VSN is connected.
In the present embodiment, the first transistor Q1 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, and have cut-in voltage UGS(th), wherein UGS(th)<0.Work as UGS<UGS(th)When, at the first transistor Q1
In on state, i.e. variable resistance area；Work as UGS>UGS(th)When, the first transistor Q1 is in off state.
When power supply chip 30 first exports VSN, the grid and source electrode of the first transistor Q1 is low level, the first transistor
Q1 is in off state, is input to the VSN=0 of driving chip 20.After grid negative pressure VGL is exported, at the first transistor Q1
In on state, source electrode negative pressure VSN is exported from second signal output end at this time, i.e., only after grid negative pressure VGL is exported, source
Pole negative pressure VSN could be exported to driving chip 20, and driving core is given in output after realization grid negative pressure VGL first exports source electrode negative pressure VSN
The timing of piece 20.
The second adjustment unit 42 includes second transistor Q2 and second resistance R2；Wherein, the second transistor Q2
Control electrode be connected with third signal input part；The first pole of second transistor Q2 passes through second resistance R2 and second crystal
The control electrode of pipe Q2 connects；Node and fourth signal input terminal phase between the first pole of second transistor Q2 and second resistance R2
Even；The control electrode of second transistor Q2 is connected with third signal output end；The second pole of second transistor Q2 and fourth signal are defeated
Outlet is connected.
Wherein, the third signal input part is connected with source electrode positive pressure VSP, the fourth signal input terminal and grid positive pressure
VGH is connected.
In the present embodiment, second transistor Q2 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, and have cut-in voltage UGS(th), wherein UGS(th)<0.Work as UGS<UGS(th)When, at second transistor Q2
In on state, i.e. variable resistance area；Work as UGS>UGS(th)When, second transistor Q2 is in off state.
When power supply chip 30 exports VGH, the grid voltage of second transistor Q2 is equal with source voltage, second transistor
In off state, it is input to the VGH=0 of driving chip 20, when source electrode positive pressure VSP is exported, second transistor Q2 is in
On state, grid positive pressure VGH is exported from fourth signal output end at this time, i.e., only after source electrode positive pressure VSP is exported, grid
Positive pressure VGH can just be exported to driving chip 20, and driving core is given in output after realization source electrode positive pressure VSP first exports grid positive pressure VGH
The timing of piece 20.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal is converted into second group of clock signal needed for driving chip, solves the timing and driving chip of power supply chip offer
The problem of liquid crystal display device caused by required timing mismatches cannot normally be shown.
Fig. 5 shows the schematic block diagram of the display device provided according to embodiments of the present invention.As shown in figure 5, described aobvious
Showing device includes display panel 10, driving chip 20, power supply chip 30, the first time sequence adjusting circuit 40 and the second timing adjustment electricity
Road 50.
Display panel 10 has a plurality of gate lines G 1-Gm and multiple data lines S1-Sn intersected with each other and in the grid
Multiple pixels that the infall of polar curve G1-Gm and the data line S1-Sn are formed.
Power supply chip 30 provides supply voltage for the display panel and generates first group of clock signal, wherein described
Supply voltage includes grid voltage and source voltage.Grid voltage is the open and close voltage of pixel upper switch pipe, is added in out
On the grid for closing pipe, including grid positive pressure VGH, grid negative pressure VGL, wherein VGH high level, which is opened, gives pixel capacitor charging,
VGL negative voltage turns off the switch pipe.Source voltage is liquid crystal drive power supply, can be to the capacitor charging of control pixel light transmission, packet
Include source electrode positive pressure VSP, source electrode negative pressure VSN.
Driving chip 20 is connect with the display panel 10, generates gain selection signals and ash according to second group of clock signal
Rank signal is to drive the display panel 10 to show image.
In the present embodiment, driving chip 20 includes sequence controller 21, gate drivers 22 and source electrode driver 23,
In, sequence controller 21 is for providing second group of clock signal and display data signal；Gate drivers 22 are used for according to institute
Grid voltage is stated to generate gain selection signals (VGH, VGL) and the gain selection signals are applied to the gate lines G 1-Gm；
Source electrode driver 23 is used to generate grayscale electricity corresponding with the display data signal according to the source voltage (VSP, VSN)
Pressure, and the gray scale voltage is applied to the data line S1-Sn.
First time sequence adjusting circuit 40 is connected between the driving chip 20 and power supply chip 30, for by first group
Clock signal is converted to second group of clock signal.
In the present embodiment, first group of clock signal includes third clock signal and the 4th clock signal, and described
Two groups of clock signals include the 5th clock signal and the 6th clock signal.First group of clock signal and second group of clock signal are
Clock signal between VGH, VGL, VSP, VSN.Third clock signal is the timing letter of VSN and VGL that power supply chip 30 provides
Number, the 4th clock signal is the clock signal of VSP and VGH that power supply chip 30 provides；5th clock signal is driving chip 20
The clock signal of required VSN and VGL, the 6th clock signal are the clock signal of VSP and VGH needed for driving chip 20.
Fig. 4 shows the circuit diagram of the first time sequence adjusting circuit of display device according to an embodiment of the present invention.Such as Fig. 4 institute
Show, first time sequence adjusting circuit 40 includes the first timing adjustment unit 41 and the second timing adjustment unit 42, wherein first
Timing adjustment unit 41 is used to third clock signal being converted into the 5th clock signal；Second timing adjustment unit 42 is used for the
Four clock signals are converted into the 6th clock signal.
The first timing adjustment unit 41 includes the first transistor Q1 and first resistor R1, wherein the first crystal
The control electrode of pipe Q1 is connected with the first signal input part；The first pole of the first transistor Q1 passes through first resistor R1 and ground terminal
GND connection；The second pole of the first transistor Q1 is connected with second signal input terminal；The control electrode of the first transistor Q1 and the
One signal output end is connected；Node and second signal output end phase between the first pole of the first transistor Q1 and first resistor R1
Even.
Wherein, first signal input part is connected with grid negative pressure VGL；The second signal input terminal and source electrode negative pressure
VSN is connected.
In the present embodiment, the first transistor Q1 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, and have cut-in voltage UGS(th), wherein UGS(th)<0.Work as UGS<UGS(th)When, at the first transistor Q1
In on state, i.e. variable resistance area；Work as UGS>UGS(th)When, the first transistor Q1 is in off state.
When power supply chip 30 first exports VSN, the grid and source electrode of the first transistor Q1 is low level, the first transistor
Q1 is in off state, is input to the VSN=0 of driving chip 20.After grid negative pressure VGL is exported, at the first transistor Q1
In on state, source electrode negative pressure VSN is exported from second signal output end at this time, i.e., only after grid negative pressure VGL is exported, source
Pole negative pressure VSN could be exported to driving chip 20, and driving core is given in output after realization grid negative pressure VGL first exports source electrode negative pressure VSN
The timing of piece 20.
The second adjustment unit 42 includes second transistor Q2 and second resistance R2；Wherein, the second transistor Q2
Control electrode be connected with third signal input part；The first pole of second transistor Q2 passes through second resistance R2 and second crystal
The control electrode of pipe Q2 connects；Node and fourth signal input terminal phase between the first pole of second transistor Q2 and second resistance R2
Even；The control electrode of second transistor Q2 is connected with third signal output end；The second pole of second transistor Q2 and fourth signal are defeated
Outlet is connected.
Wherein, the third signal input part is connected with source electrode positive pressure VSP, the fourth signal input terminal and grid positive pressure
VGH is connected.
In the present embodiment, second transistor Q2 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, and have cut-in voltage UGS(th), wherein UGS(th)<0.Work as UGS<UGS(th)When, at second transistor Q2
In on state, i.e. variable resistance area；Work as UGS>UGS(th)When, second transistor Q2 is in off state.
When power supply chip 30 exports VGH, the grid voltage of second transistor Q2 is equal with source voltage, second transistor
In off state, it is input to the VGH=0 of driving chip 20, when source electrode positive pressure VSP is exported, second transistor Q2 is in
On state, grid positive pressure VGH is exported from fourth signal output end at this time, i.e., only after source electrode positive pressure VSP is exported, grid
Positive pressure VGH can just be exported to driving chip 20, and driving core is given in output after realization source electrode positive pressure VSP first exports grid positive pressure VGH
The timing of piece 20.
Second time sequence adjusting circuit 50 is used for according to the first control signal GPIO of driving chip 20 and the first power supply electricity
VCC1 is pressed to generate second control signal EN.
In the present embodiment, the driving chip 20 generates first control signal according to second source voltage VCC2, described
First control signal is universal input/output interface (General-Purpose Input/Output Ports, GPIO) signal.
Fig. 6 shows the circuit diagram of the second time sequence adjusting circuit of display device according to an embodiment of the present invention.Such as Fig. 6 institute
Show, second time sequence adjusting circuit 50 includes third transistor Q3 and 3rd resistor R3, wherein the third transistor Q3's
Control electrode is connected with the first control signal GPIO；The first pole of third transistor Q3 passes through 3rd resistor R3 and the third
The control electrode of transistor Q3 connects；Node and second source voltage between the first pole and 3rd resistor R3 of third transistor Q3
VCC2 signal is connected；The second pole of third transistor Q3 is connected with power supply chip 30, for exporting second control signal EN.Its
In, the second control signal EN is for making power supply chip 30 work and generating first group of clock signal.
In the present embodiment, third transistor Q3 is P-channel enhancement type MOS transistor, and control extremely grid, first are extremely
Source electrode, second extremely drain, and have cut-in voltage UGS(th), wherein UGS(th)<0.Work as UGS<UGS(th)When, at third transistor Q3
In on state, i.e. variable resistance area；Work as UGS>UGS(th)When, third transistor Q3 is in off state.
After first supply voltage VCC1 is supplied to driving chip 20, driving chip 20 starts to be initialized, and has initialized
GPIO signal is exported by GPIO interface at rear.When second source voltage VCC2 is provided, the grid electricity of third transistor Q3
Pressure is equal with source voltage, and third transistor Q3 is in off state, the VGH=0 of driving chip 20 is input to, when source electrode positive pressure
When VSP is exported, third transistor Q3 is in the conductive state, and second source voltage VCC2 is provided to power supply chip 30 and makes at this time
Power supply chip 30 is started to work.I.e. only after the completion of driving chip 20 initializes, power supply chip 30 just starts to work normally, real
Existing first supply voltage VCC1 is first supplied to driving chip 20 and is initialized, second source voltage VCC2 quilt after the completion of initialization
Being supplied to power supply chip 30 makes power supply chip 30 start the timing worked normally.
Display device provided in an embodiment of the present invention, power supply chip is provided by the first time sequence adjusting circuit first group
Clock signal is converted into second group of clock signal needed for driving chip, solves the timing and driving chip of power supply chip offer
The problem of liquid crystal display device caused by required timing mismatches cannot normally be shown.The second time sequence adjusting circuit is utilized simultaneously
Power supply chip works normally after so that driving chip is completed initialization, provides supply voltage to driving chip, keeps display normal, steady
It is fixed, improve the reliability of display device.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The range that the claims in the present invention are defined should be subject to by enclosing.
Claims (9)
1. a kind of display device characterized by comprising
Display panel；
Power supply chip is connect with the display panel, for providing supply voltage, and first group of generation for the display panel
Clock signal；
Driving chip is connect with the display panel, for generating gain selection signals and grayscale according to second group of clock signal
Signal is to drive the display panel to show image；
First time sequence adjusting circuit is connected between the driving chip and power supply chip, for turning first group of clock signal
It is changed to second group of clock signal,
Wherein, the driving chip includes:
Sequence controller, for providing second group of clock signal and display data signal；
Gate drivers, for generating gain selection signals according to the grid voltage and being applied to the gain selection signals
The grid line；
Source electrode driver, for generating gray scale voltage corresponding with the display data signal according to the source voltage, and will
The gray scale voltage is applied to the data line.
2. display device according to claim 1, which is characterized in that the display panel has a plurality of grid intersected with each other
Polar curve and multiple data lines and the multiple pixels formed in the infall of the grid line and the data line；And
The supply voltage includes grid voltage and source voltage.
3. display device according to claim 1, which is characterized in that first group of clock signal includes third timing letter
Number and the 4th clock signal, second group of clock signal include the 5th clock signal and the 6th clock signal.
4. display device according to claim 3, which is characterized in that first time sequence adjusting circuit includes:
First timing adjustment unit, for third clock signal to be converted into the 5th clock signal；
Second timing adjustment unit, for the 4th clock signal to be converted into the 6th clock signal；
Wherein, the third clock signal is the clock signal of grid negative pressure and source electrode negative pressure that power supply chip provides；
4th clock signal is the clock signal of grid positive pressure and source electrode positive pressure that power supply chip provides；
5th clock signal is the clock signal of grid negative pressure and source electrode negative pressure that driving chip provides；
6th clock signal is the clock signal of grid positive pressure and source electrode positive pressure that driving chip provides.
5. display device according to claim 4, which is characterized in that the first timing adjustment unit includes first crystal
Pipe and first resistor,
Wherein, the control electrode of the first transistor is connected with the first signal input part；The first of the first transistor is extremely logical
First resistor is crossed to connect with ground terminal；Second pole of the first transistor is connected with second signal input terminal；
The control electrode of the first transistor is connected with the first signal output end；
Node between the first pole and first resistor of the first transistor is connected with second signal output end；
First signal input part is connected with grid negative pressure；The second signal input terminal is connected with source electrode negative pressure.
6. display device according to claim 4, which is characterized in that the second timing adjustment unit includes the second crystal
Pipe and second resistance；
Wherein, the control electrode of the second transistor is connected with third signal input part；The first of the second transistor is extremely logical
Second resistance is crossed to connect with the control electrode of the second transistor；Between first pole of the second transistor and second resistance
Node is connected with fourth signal input terminal；
The control electrode of the second transistor is connected with third signal output end；
Second pole of the second transistor is connected with fourth signal output end；
The third signal input part is connected with source electrode positive pressure, and the fourth signal input terminal is connected with grid positive pressure.
7. display device according to claim 1-6, which is characterized in that it further include the second time sequence adjusting circuit,
For generating second control signal according to the first control signal of driving chip and the first supply voltage, wherein described second
Control signal is for making power supply chip work and generating first group of clock signal.
8. display device according to claim 7, which is characterized in that the driving chip is generated according to second source voltage
The first control signal, wherein the first control signal is universal input/output interface signal.
9. display device according to claim 8, which is characterized in that second time sequence adjusting circuit includes third crystal
Pipe and 3rd resistor,
Wherein, the control electrode of the third transistor is connected with the first control signal；First pole of the third transistor
It is connect by 3rd resistor with the control electrode of the third transistor；Between first pole of the third transistor and 3rd resistor
Node be connected with second source voltage signal；
Second pole of the third transistor is connected with power supply chip, for exporting second control signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109256075B (en) | 2017-07-13 | 2020-08-25 | 昆山国显光电有限公司 | Display screen power supply control method and device, storage medium and electronic equipment |
| CN108172178B (en) * | 2017-12-13 | 2020-06-09 | 深圳市华星光电技术有限公司 | Power supply circuit of time schedule controller and liquid crystal display device |
| CN108389555B (en) * | 2018-02-06 | 2020-09-04 | 昆山龙腾光电股份有限公司 | Drive circuit and display device |
| CN110544452B (en) * | 2018-05-28 | 2021-08-17 | 京东方科技集团股份有限公司 | Power supply time sequence control circuit and control method, display driving circuit and display device |
| CN109192177B (en) * | 2018-11-14 | 2023-03-17 | 维沃移动通信有限公司 | Control circuit, liquid crystal display driving module and liquid crystal display device |
| CN115019740B (en) * | 2022-04-19 | 2024-08-30 | 京东方科技集团股份有限公司 | Time sequence control circuit, display module and display device |
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