CN105355180B - Display panel and control circuit - Google Patents
Display panel and control circuit Download PDFInfo
- Publication number
- CN105355180B CN105355180B CN201510875269.9A CN201510875269A CN105355180B CN 105355180 B CN105355180 B CN 105355180B CN 201510875269 A CN201510875269 A CN 201510875269A CN 105355180 B CN105355180 B CN 105355180B
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- transistor
- grid line
- grid
- gate driving
- driving circuit
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Abstract
The invention discloses a kind of display panels, the grid of several gate driving circuits is exported in the fanout area of the display panel is connected to grid line via a control circuit, the control circuit includes a first transistor, and a control signal is received at a grid of the first transistor；And a second transistor, the control signal is received at a grid of the second transistor, a source electrode of the second transistor is connected to a drain electrode of the first transistor；The wherein described the first transistor has opposite polarity with the second transistor.
Description
Technical field
This case is related to a kind of display panel and control circuit, is especially used for Thin Film Transistor-LCD (Thin
Film Transistor Liquid Crystal Display, TFT-LCD) display panel and control circuit.
Background technology
Using GOA, (Gate On Array, grid grade driving chip are integrated in several bases to traditional TFT-LCD display panels
Plate) basic framework as shown in Figure 1, in display panel 1 comprising viewing area 10, fanout area 11, source electrode chip-on-film
(Source-Chip On Film, S-COF) 12, printed circuit board (Printed Circuit Board, PCB) 13, several grid
Pole driving circuit can be arranged between viewing area and non-display area.
In actual operation, it is the sequence diagram of adjacent two grids output, and transmission such as G_OUT1, G_OUT2 in Fig. 2
The sequence diagram of data-signal DATA_END1, DATA_END2 when to grid line end, because the capacitance of panel itself, resistance are to letter
Number influence, cause distorted signals that signal is overlapped, i.e., adjacent transistor gate simultaneously turns on, and the charging of pixel electrode is wrong
Accidentally.
It is, therefore, desirable to provide new display panel and control circuit, avoid signal from overlapping and are distorted, pixel electrode is prevented to charge
Mistake.
Invention content
Conducting and pass of the present invention by a control signal according to specific timing control gold oxygen field-effect transistor (MOS)
It is disconnected, it realizes output enable (Output Enable) function, to avoid the mistake of pixel electrode from filling, solves above-mentioned signal overlapping and lose
Genuine problem.
One embodiment of the invention proposes that a kind of display panel includes a viewing area, has a plurality of grid line；One fanout area,
Adjacent to the viewing area；Multiple gate driving circuits, are arranged at the edge of the viewing area, each gate driving circuit with
Wherein one connection of a plurality of grid line, each gate driving circuit exports a gate output signal in a grid, in institute
It states grid line one grid line of output and outputs signal to connected grid line；And a control circuit, it is located in the fanout area,
It is connected between each grid output of several gate driving circuits in the fanout area of the display panel and each grid line, packet
A first transistor is included, is used to receive the control signal from the display panel with a grid；And one second crystal
Pipe has a grid for receiving the control signal, and a source electrode of the second transistor is connected to the first transistor
A drain electrode；The wherein described the first transistor has opposite polarity with the second transistor.
Preferably, the gate output signal for controlling adjacent two gate driving circuit of Signal Regulation and being exported, with
Prevent the grid line output signal that the grid line that corresponding two gate driving circuit is connected is exported from interfering with each other.
Preferably, when the control signal is a low voltage level, the first transistor can be connected, and described second is brilliant
Body pipe can turn off, and the gate output signal is equal to the grid line output signal.
Preferably, when the control signal is a high voltage level, the first transistor can turn off, and described second is brilliant
Body pipe can be connected, and the grid line output is turned off.
Preferably, the first transistor and the second transistor are all golden oxygen field-effect transistors.
The present invention can realize the fanout area design of the function of output enable under several gate driver circuitry topologies, can solve
The problems such as certainly pixel electrode mistake is filled, Improving The Quality of Products promote product competitiveness.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly simultaneously coordinates
Attached drawing elaborates.
Description of the drawings
Fig. 1 is the configuration diagram of conventional gate driving panel；
Fig. 2 is the sequence diagram of the grid output and grid line output of conventional gate driving panel；
Fig. 3 is the circuit diagram of the control circuit of one embodiment of the invention；And
Fig. 4 is the control circuit of the embodiment of the present invention.
Specific implementation mode
The explanation of following embodiment is to refer to additional schema, to illustrate the particular implementation that the present invention can be used to implement
Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be illustrate and understand the present invention, rather than to
The limitation present invention.
Display panel framework as shown in Figure 1, one embodiment of the invention discloses a display panel 1, in the display
The grid output of several gate driving circuits (no icon) between the viewing area 10 and fanout area 11 of panel 1 is via a control electricity
Road 14 is connected to grid line.Wherein, the viewing area 10 has a plurality of grid line, and the fanout area 11 is adjacent to the viewing area
10；The multiple gate driving circuit is arranged at the edge of the viewing area 10, each gate driving circuit with it is described a plurality of
Wherein one connection of grid line, each gate driving circuit export the grid line that a gate output signal is extremely connected, and institute
It states grid line and exports a grid line output signal.
Fig. 3 is please referred to, as shown in figure 3, the control circuit 14 is located at for controlling the multiple gate driving circuit
In the fanout area 11, it is connected to each grid output of several gate driving circuits in the fanout area 11 of the display panel 1
Between each grid line, including a first transistor A1 in the first transistor A1 there is a grid to be come from for receiving
One control signal S_OE of the display panel 1；And a second transistor A2 has a grid in the second transistor A2
For receiving the control signal S_OE, a source electrode of the second transistor A2 is connected to the one of the first transistor A1 for pole
Drain electrode；The wherein described the first transistor A1 and second transistor A2 has opposite polarity.
Wherein, the control signal S_OE adjusts the gate output signal G_ that adjacent two gate driving circuit is exported
OUT1 and G_OUT2, with grid line exported GL_OUT1, the GL_OUT2 connected to corresponding two gate driving circuit, with number
It is believed that number DATA_END1, DATA_END2 are into between-line spacing.When the control signal S_OE is a low voltage level (example herein
For 0V, but do not limit) when, the first transistor A1 can be connected, and the second transistor A2 can be turned off, the grid output letter
Number G_OUT1, G_OUT2 are equal to corresponding grid line output signal GL_OUT1, GL_OUT2.As the control signal S_OE
For a high voltage level (example herein is 3.3V, but is not limited) when, the first transistor A1 can be turned off, and described second is brilliant
Body pipe A2 can be connected, and grid line output GL_OUT1 (or GL_OUT2) is turned off, GL_OUT1 as shown in the figure (or GL_
OUT2) it is equal to a shutdown voltage VGL.In the present embodiment of the present invention, the first transistor and the second transistor are all
Golden oxygen field-effect transistor, this is one and illustrates, and the limitation of non-present invention.
In actual use, control signal S_OE is adjusted to the section area of signal G_OUT1 and G_OUT2 interfered with each other,
Because different panel situations is different, specific location is adjusted according to actual use situation, does not do particular determination, then can be achieved to two
Grid line output signal GL_OUT1, GL_OUT2 is into between-line spacing so that data-signal DATA_END1, DATA_END2 are dry without overlapping
It disturbs, eliminates mistake and fill phenomenon, as shown in the timing diagram of figure 4.
The present invention can realize the fanout area design of the function of output enable under several gate driver circuitry topologies, can solve
The problems such as certainly pixel electrode mistake is filled, Improving The Quality of Products promote product competitiveness.
In conclusion although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention is subject to the range that claim defines.
Claims (4)
1. a kind of display panel, which is characterized in that including：
One viewing area has a plurality of grid line；
One fanout area, adjacent to the viewing area；
Multiple gate driving circuits are arranged at the edge of the viewing area, each gate driving circuit and a plurality of grid
Wherein one connection of line, each gate driving circuit export the grid line that a gate output signal is extremely connected, and the grid
Polar curve exports a grid line output signal；And
One control circuit is located in the fanout area for controlling the multiple gate driving circuit, is connected to the display surface
In the fanout area of plate between the output of each grid and each grid line of several gate driving circuits, the control circuit includes：
One the first transistor is used to receive the control signal from the display panel with a grid；And
One second transistor has a grid for receiving the control signal, and a source electrode of the second transistor is connected to
One drain electrode of the first transistor；
The wherein described the first transistor has opposite polarity with the second transistor；
The gate output signal for controlling adjacent two gate driving circuit of Signal Regulation and being exported, to prevent corresponding two
The grid line output signal that the grid line that gate driving circuit is connected is exported interferes with each other；
When the control signal is a low voltage level, the first transistor can be connected, and the second transistor can turn off,
The gate output signal is equal to the grid line output signal；
When the control signal is a high voltage level, the first transistor can turn off, and the second transistor can be connected,
The grid line output is turned off.
2. display panel as described in claim 1, which is characterized in that the first transistor and the second transistor are all
Golden oxygen field-effect transistor.
3. a kind of control circuit is located in a display panel for controlling multiple gate driving circuits, is connected to several grids and drives
Between grid output in dynamic circuit and grid line output, which is characterized in that including：
One the first transistor is used to receive the control signal from the display panel with a grid；And
One second transistor has a grid for receiving the control signal, and a source electrode of the second transistor is connected to
One drain electrode of the first transistor；
The wherein described the first transistor has opposite polarity with the second transistor, and the display panel has a display
Area has a plurality of grid line；One fanout area, adjacent to the viewing area；The multiple gate driving circuit is arranged at described
Wherein one of the edge of viewing area, each gate driving circuit and a plurality of grid line connect, each gate driving circuit
A gate output signal is exported to the grid line connected, and the grid line exports a grid line output signal；
The grid output letter that adjacent two gate driving circuit is exported in control one gate driving circuit of Signal Regulation
Number, it is interfered with each other with the grid line output signal that the grid line for preventing corresponding two gate driving circuit from being connected is exported；
When the control signal is a low voltage level, the first transistor can be connected, and the second transistor can turn off,
The gate output signal is equal to the grid line output signal；
When the control signal is a high voltage level, the first transistor can turn off, and the second transistor can be connected,
The grid line output is turned off.
4. control circuit as claimed in claim 3, which is characterized in that the first transistor and the second transistor are all
Golden oxygen field-effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510875269.9A CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510875269.9A CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN105355180A CN105355180A (en) | 2016-02-24 |
| CN105355180B true CN105355180B (en) | 2018-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510875269.9A Active CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105761704A (en) * | 2016-05-20 | 2016-07-13 | 深圳市华星光电技术有限公司 | Display panel and driving circuit and driving method thereof |
| CN107967903A (en) * | 2017-12-26 | 2018-04-27 | 惠科股份有限公司 | Cut-off signals generation circuit and display device |
| CN209388677U (en) * | 2018-09-11 | 2019-09-13 | 重庆惠科金渝光电科技有限公司 | A kind of driving circuit and display panel |
| CN108877729B (en) * | 2018-09-11 | 2021-02-09 | 惠科股份有限公司 | Driving circuit and display device thereof |
| CN109545164B (en) * | 2019-01-02 | 2021-04-09 | 合肥京东方显示技术有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| TWI690912B (en) * | 2019-02-13 | 2020-04-11 | 友達光電股份有限公司 | Display panel and driving method |
| US11688339B2 (en) * | 2020-04-10 | 2023-06-27 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and manufacturing method thereof, display device |
| CN114067759B (en) * | 2020-07-31 | 2022-12-23 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
| CN113380168B (en) * | 2021-05-20 | 2022-09-27 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
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| TW200947403A (en) * | 2008-05-12 | 2009-11-16 | Chi Mei Optoelectronics Corp | Timing controller, display and driving method thereof |
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| CN105355180A (en) | 2016-02-24 |
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