CN105355180A - Display panel and control circuit - Google Patents
Display panel and control circuit Download PDFInfo
- Publication number
- CN105355180A CN105355180A CN201510875269.9A CN201510875269A CN105355180A CN 105355180 A CN105355180 A CN 105355180A CN 201510875269 A CN201510875269 A CN 201510875269A CN 105355180 A CN105355180 A CN 105355180A
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- gate
- transistor
- gate line
- driver circuit
- output signal
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Abstract
The invention discloses a display panel. The gates of a plurality of gate driving circuit at the fan-out area of the display panel are connected with gate lines through a control circuit; the control circuit comprises a first transistor and a second transistor; a gate of the first transistor receives a control signal; a gate of the second transistor receives the control signal; the source of the second transistor is connected with the drain of the first transistor; and the polarity of the first transistor is opposite to the polarity of the second transistor.
Description
Technical field
This case relates to a kind of display panel and control circuit, especially for display panel and the control circuit of Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay, TFT-LCD).
Background technology
Traditional TFT-LCD display panel uses GOA (GateOnArray, grid level driving chip is integrated in several substrate) basic framework as shown in Figure 1, viewing area 10, fanout area 11, source electrode chip-on-film (Source-ChipOnFilm is comprised in display panel 1, S-COF) 12, printed circuit board (PCB) (PrintedCircuitBoard, PCB) 13, several gate driver circuit can be arranged between viewing area and non-display area.
In actual motion, as G_OUT1, G_OUT2 in Fig. 2, it is the sequential chart that adjacent two grids export, and the sequential chart of data-signal DATA_END1, DATA_END2 when transferring to grid line end, because the electric capacity of panel itself, resistance are on the impact of signal, cause distorted signals that signal is overlapped, the conducting simultaneously of namely adjacent transistor gate, the charging mistake of pixel electrode.
Therefore, need to propose new display panel and control circuit, avoid signal overlapping distortion, prevent pixel electrode charging mistake.
Summary of the invention
The present invention is by the turn-on and turn-off of a control signal according to specific sequential control gold oxygen field-effect transistor (MOS), realize an output enable (OutputEnable) function, avoid the mistake of pixel electrode to fill, solve the problem of above-mentioned signal overlapping distortion.
One embodiment of the invention propose a kind of display panel and comprise a viewing area, have many gate lines; One fanout area, adjacent to described viewing area; Multiple gate driver circuit, be arranged at the edge of described viewing area, each gate driver circuit and described many gate lines wherein one be connected, each gate driver circuit exports a gate output signal at a grid, exports a gate line output signal to connected gate line at described gate line; And a control circuit, be arranged in described fanout area, each grid being connected to several gate driver circuit in the fanout area of described display panel exports between each gate line, comprising a first transistor, having a grid for receiving the control signal from described display panel; And a transistor seconds, have a grid for receiving described control signal, the one source pole of described transistor seconds is connected to a drain electrode of described the first transistor; Wherein said the first transistor and described transistor seconds have opposite polarity.
Preferably, described control signal regulates the gate output signal that described in adjacent two, gate driver circuit exports, the interference mutually of the gate line exported with the gate line preventing corresponding two gate driver circuits from connecting output signal.
Preferably, when described control signal is a low voltage level, described the first transistor meeting conducting, described transistor seconds can turn off, and described gate output signal equals described gate line output signal.
Preferably, when described control signal is a high voltage level, described the first transistor can turn off, and described transistor seconds meeting conducting, described gate line exports and is turned off.
Preferably, described the first transistor and described transistor seconds are all golden oxygen field-effect transistors.
The present invention can realize the fanout area design of the function of output enable under several gate driver circuit framework, can solve pixel electrode mistake and the problem, Improving The Quality of Products, improving product competitive power such as fill.
For making above-mentioned purpose of the present invention, feature and advantage become apparent, preferred embodiment cited below particularly also coordinates accompanying drawing to elaborate.
Accompanying drawing explanation
Fig. 1 is the configuration diagram that conventional gate drives panel;
Fig. 2 is that conventional gate drives the grid of panel to export the sequential chart exported with gate line;
Fig. 3 is the circuit diagram of the control circuit of one embodiment of the invention; And
Fig. 4 is the control circuit of described embodiment of the present invention.
Embodiment
The explanation of following embodiment is graphic with reference to what add, can in order to the specific embodiment implemented in order to illustrate the present invention.The direction term that the present invention mentions, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, and is not used to limit the present invention.
Display panel framework as shown in Figure 1, one embodiment of the invention disclose a display panel 1, and the grid of the several gate driver circuits (without icon) between the viewing area 10 and fanout area 11 of described display panel 1 exports and is connected to gate line via a control circuit 14.Wherein, described viewing area 10 has many gate lines, and described fanout area 11 is adjacent to described viewing area 10; Described multiple gate driver circuit is arranged at the edge of described viewing area 10, each gate driver circuit and described many gate lines wherein one be connected, each gate driver circuit exports a gate output signal to the gate line connected, and described gate line exports a gate line output signal.
Please refer to Fig. 3, as shown in Figure 3, described control circuit 14, for controlling described multiple gate driver circuit, be arranged in described fanout area 11, each grid being connected to several gate driver circuit in the fanout area 11 of described display panel 1 exports between each gate line, comprises a first transistor A1, at described the first transistor A1, there is a grid for receiving the control signal S_OE from described display panel 1; And a transistor seconds A2, at described transistor seconds A2, have a grid for receiving described control signal S_OE, the one source pole of described transistor seconds A2 is connected to a drain electrode of described the first transistor A1; Wherein said the first transistor A1 and described transistor seconds A2 has opposite polarity.
Wherein, described control signal S_OE regulates gate output signal G_OUT1 and the G_OUT2 that described in adjacent two, gate driver circuit exports, with gate line exports GL_OUT1, GL_OUT2 of connecting corresponding two gate driver circuits, and data-signal DATA_END1, DATA_END2 carry out interval.When described control signal S_OE is that (example is herein 0V to a low voltage level, but do not limit) time, described the first transistor A1 meeting conducting, described transistor seconds A2 can turn off, and described gate output signal G_OUT1, G_OUT2 equal corresponding described gate line output signal GL_OUT1, GL_OUT2.When described control signal S_OE is that (example is herein 3.3V to a high voltage level, but do not limit) time, described the first transistor A1 can turn off, described transistor seconds A2 meeting conducting, described gate line exports GL_OUT1 (or GL_OUT2) and is turned off, and GL_OUT1 (or GL_OUT2) equals a shutoff voltage VGL as shown in FIG..In the present embodiment of the present invention, described the first transistor and described transistor seconds are all golden oxygen field-effect transistors, and this is a citing, not restriction of the present invention.
During actual use, control signal S_OE is adjusted to the section district of the mutual interference of signal G_OUT1 and G_OUT2, because different panel situations is different, particular location regulates according to actual behaviour in service, do not do particular determination, then can realize carrying out interval to two gate line output signal GL_OUT1, GL_OUT2, make data-signal DATA_END1, DATA_END2 without overlapping interference, eliminate mistake and fill phenomenon, as shown in the timing diagram of figure 4.
The present invention can realize the fanout area design of the function of output enable under several gate driver circuit framework, can solve pixel electrode mistake and the problem, Improving The Quality of Products, improving product competitive power such as fill.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. a display panel, is characterized in that, comprising:
One viewing area, has many gate lines;
One fanout area, adjacent to described viewing area;
Multiple gate driver circuit, be arranged at the edge of described viewing area, each gate driver circuit and described many gate lines wherein one be connected, each gate driver circuit exports a gate output signal to the gate line connected, and described gate line exports a gate line output signal; And
One control circuit, for controlling described multiple gate driver circuit, is arranged in described fanout area, and each grid being connected to several gate driver circuit in the fanout area of described display panel exports between each gate line, and described control circuit comprises:
One the first transistor, has a grid for receiving the control signal from described display panel; And
One transistor seconds, has a grid for receiving described control signal, and the one source pole of described transistor seconds is connected to a drain electrode of described the first transistor;
Wherein said the first transistor and described transistor seconds have opposite polarity.
2. display panel as claimed in claim 1, it is characterized in that, described control signal regulates the gate output signal that described in adjacent two, gate driver circuit exports, the interference mutually of the gate line exported with the gate line preventing corresponding two gate driver circuits from connecting output signal.
3. display panel as claimed in claim 1, is characterized in that, when described control signal is a low voltage level, described the first transistor meeting conducting, described transistor seconds can turn off, and described gate output signal equals described gate line output signal.
4. display panel as claimed in claim 1, it is characterized in that, when described control signal is a high voltage level, described the first transistor can turn off, and described transistor seconds meeting conducting, described gate line exports and is turned off.
5. display panel as claimed in claim 1, it is characterized in that, described the first transistor and described transistor seconds are all golden oxygen field-effect transistors.
6. a control circuit, for controlling multiple gate driver circuit, is arranged in a display panel, is connected to grid in several gate driver circuit and exports and between gate line exports, it is characterized in that, comprising:
One the first transistor, has a grid for receiving the control signal from described display panel; And
One transistor seconds, has a grid for receiving described control signal, described transistor seconds
One source pole be connected to a drain electrode of described the first transistor;
Wherein said the first transistor and described transistor seconds have opposite polarity, and described display board has a viewing area, have many gate lines; One fanout area, adjacent to described viewing area; Described multiple gate driver circuit is arranged at the edge of described viewing area, each gate driver circuit and described many gate lines wherein one be connected, each gate driver circuit exports a gate output signal to the gate line connected, and described gate line exports a gate line output signal.
7. control circuit as claimed in claim 6, it is characterized in that, described control signal regulates the gate output signal that in a gate driver circuit, described in adjacent two, gate driver circuit exports, the gate line output signal interference mutually exported with the gate line preventing corresponding two gate driver circuits from connecting.
8. control circuit as claimed in claim 6, is characterized in that, when described control signal is a low voltage level, described the first transistor meeting conducting, described transistor seconds can turn off, and described gate output signal equals described gate line output signal.
9. control circuit as claimed in claim 6, it is characterized in that, when described control signal is a high voltage level, described the first transistor can turn off, and described transistor seconds meeting conducting, described gate line exports and is turned off.
10. control circuit as claimed in claim 6, it is characterized in that, described the first transistor and described transistor seconds are all golden oxygen field-effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510875269.9A CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510875269.9A CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
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| Publication Number | Publication Date |
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| CN105355180A true CN105355180A (en) | 2016-02-24 |
| CN105355180B CN105355180B (en) | 2018-09-04 |
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| CN201510875269.9A Active CN105355180B (en) | 2015-12-01 | 2015-12-01 | Display panel and control circuit |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105761704A (en) * | 2016-05-20 | 2016-07-13 | 深圳市华星光电技术有限公司 | Display panel and driving circuit and driving method thereof |
| CN107967903A (en) * | 2017-12-26 | 2018-04-27 | 惠科股份有限公司 | Cut-off signals generation circuit and display device |
| CN108877729A (en) * | 2018-09-11 | 2018-11-23 | 惠科股份有限公司 | Driving circuit and its display device |
| CN109545164A (en) * | 2019-01-02 | 2019-03-29 | 合肥京东方显示技术有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN110459160A (en) * | 2019-02-13 | 2019-11-15 | 友达光电股份有限公司 | Display panel and driving method |
| WO2020051995A1 (en) * | 2018-09-11 | 2020-03-19 | 重庆惠科金渝光电科技有限公司 | Driver circuit and display device |
| CN113380168A (en) * | 2021-05-20 | 2021-09-10 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
| WO2021203423A1 (en) * | 2020-04-10 | 2021-10-14 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor, and display apparatus |
| CN114067759A (en) * | 2020-07-31 | 2022-02-18 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
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| CN109545164A (en) * | 2019-01-02 | 2019-03-29 | 合肥京东方显示技术有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
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| CN110459160A (en) * | 2019-02-13 | 2019-11-15 | 友达光电股份有限公司 | Display panel and driving method |
| CN110459160B (en) * | 2019-02-13 | 2022-09-06 | 友达光电股份有限公司 | Display panel and driving method |
| WO2021203423A1 (en) * | 2020-04-10 | 2021-10-14 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor, and display apparatus |
| CN114067759A (en) * | 2020-07-31 | 2022-02-18 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
| CN114067759B (en) * | 2020-07-31 | 2022-12-23 | 滁州惠科光电科技有限公司 | Grid driving circuit of display panel, driving method thereof and display device |
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| CN105355180B (en) | 2018-09-04 |
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