CN106647084A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN106647084A CN106647084A CN201710108266.1A CN201710108266A CN106647084A CN 106647084 A CN106647084 A CN 106647084A CN 201710108266 A CN201710108266 A CN 201710108266A CN 106647084 A CN106647084 A CN 106647084A
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- Prior art keywords
- array base
- scan line
- base palte
- switch pipe
- lines
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The invention discloses an array substrate and a display panel. The array substrate includes a plurality of scanning lines, a plurality of data lines, and low voltage lines; the plurality of scanning lines and the plurality of data lines are arranged orthogonally so as to form a plurality of pixel units; each pixel unit includes a first switch tube, and at least one pixel unit includes a second switch tube; the second switch tube includes a first end, a second end, and a control end, wherein the first end is connected to a control end of the first switch tube, and the control end is connected to a following scanning line; the following scanning is started after a scanning line corresponding to a pixel unit where the second switch tube is located. The array substrate and the display panel can prolong the charging time of pixels, and can improve the charging rate of the pixels.
Description
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of array base palte and display floater.
Background technology
Liquid crystal display (LCD, Liquid Crystal Display) has that frivolous, colour gamut is high, power consumption is low excellent with it
Point is widely used in TV, Monitor, Note book, App etc. and shows product.
As the resolution more and more higher of liquid crystal display, size are increasing, the charge rate of liquid crystal display is increasingly
It is low, it is impossible to meet the demand of high-res, large-sized monitor.
The content of the invention
The present invention provides a kind of array base palte and display floater, by increasing capacitance it is possible to increase the charging interval of pixel, lifts filling for pixel
Electric rate, the wrong charging risk of reduction, and then lift the display quality of liquid crystal display.
One aspect of the present invention is：A kind of array base palte is provided, the array base palte includes：Multi-strip scanning
Line, a plurality of data lines and low voltage lines；Multi-strip scanning line setting orthogonal with a plurality of data lines, to form multiple pixels
Unit；Wherein, each pixel cell includes a first switch pipe, and pixel cell further includes one described at least one
Second switch pipe；The second switch pipe includes：First end, the second end and control end, the first end connection described first
The control end of switching tube, the control end connects a successive scan lines, and the opening sequence of the successive scan lines is described second
Switching tube be located corresponding level scan line of the pixel cell after, the trailing edge of described level scan line scanning signal with
The rising edge correspondence of the successive scan lines scanning signal, second end connects the low voltage lines.
Wherein, second switch pipe described in is included in each pixel cell.
Wherein, the successive scan lines are adjacent with described level scan line.
Wherein, the scan line that the successive scan lines are at least spaced one-level with described level scan line is connected, described
The quantity of the scan line between successive scan lines and described level scan line is equal to the described of second switch pipe place
The ratio in the precharge time of pixel cell and formal charging interval.
Wherein, the pixel cell of the same color filter of correspondence includes second switch pipe described in.
Wherein, the successive scan lines are adjacent with described level scan line.
Wherein, the scan line that the successive scan lines are at least spaced one-level with described level scan line is connected, described
The quantity of the scan line between successive scan lines and described level scan line is equal to the described of second switch pipe place
The ratio in the precharge time of pixel cell and formal charging interval.
Wherein, the array base palte also includes scan drive circuit, and the scan drive circuit is to provide scanning signal
To the scan line.
Wherein, the array base palte also includes data drive circuit, and the data drive circuit is to provide grayscale signal
To the data wire.
To solve above-mentioned technical problem, another technical scheme that the present invention is adopted is：A kind of display floater is provided, it is described
Display floater includes any of the above-described described array base palte, the opposite substrate being oppositely arranged with the array base palte and is held on
Liquid crystal layer between the array base palte and the opposite substrate.
The invention has the beneficial effects as follows：A kind of array base palte and display floater are provided, by setting up in pixel cell
Two switching tubes, and the control end of control second switch pipe is connected to successive scan lines, within a scan period, scanning signal
Pulse width is fixed, and in the case that other conditions are constant, the time of trailing edge shortens and means scanning signal high level
Time is elongated, that is to say, that the opening time of first switch pipe is elongated so that the charging interval of pixel electrode is elongated, lifts pixel
Charge rate, reduce wrong charging risk, lift the display quality of liquid crystal display.
Description of the drawings
Fig. 1 is the structural representation of array base palte first embodiment of the present invention；
Fig. 2 is the sequential chart of array base palte first embodiment of the present invention；
Fig. 3 is the structural representation of array base palte second embodiment of the present invention；
Fig. 4 is the sequential chart of array base palte second embodiment of the present invention；
Fig. 5 is the structural representation of the embodiment of array base palte of the present invention 3rd；
Fig. 6 is the structural representation of the embodiment of array base palte of the present invention 4th；
Fig. 7 is the contrast schematic diagram of the present invention and prior art type of drive charge waveforms；
Fig. 8 is the structural representation of the embodiment of display floater of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, level is entered to the technical scheme in the embodiment of the present invention clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Fig. 1 is referred to, Fig. 1 is the structural representation of array base palte first embodiment of the present invention.As shown in figure 1, the battle array
Row substrate 10 includes：Multi-strip scanning line 11, a plurality of data lines 12 and low voltage lines Vgl.Wherein, multi-strip scanning line 11 and a plurality of number
According to the orthogonal setting of line 12, to form multiple pixel cells 13.
Wherein, each pixel cell 13 includes that a first switch pipe T1, first switch pipe T1 are used to control array base palte
The voltage of pixel electrode in 10.And at least one pixel cell 13 further include a second switch pipe T2, the second switch pipe
T2 includes：First end a, the second end b and control end c, and first end a connects the control end of first switch pipe T1, the control
End c connects a successive scan lines, and the opening sequence of successive scan lines is corresponding in the pixel cell 13 that second switch pipe T2 is located
After this grade of scan line, the second end b connection low voltage lines Vgl, for when successive scan lines are opened, so that this grade of scan line
Drop quickly to electronegative potential.
The array base palte 10 also includes scan drive circuit 14 and data drive circuit 15.Wherein, scan drive circuit 14
To provide scanning signal to scan line, data drive circuit 15 is to provide grayscale signal to data wire.
With reference to Fig. 1, in an application scenarios of the invention, a second switch pipe T2 is included in each pixel cell 13, and
The opening sequence of successive scan lines after 13 corresponding level scan lines of pixel cell that second switch pipe T2 is located, and after this
Continuous scan line is adjacent with this grade of scan line.By taking N level pixel cells as an example, the pixel cell 13 is in two adjacent low voltage lines
Vgl and two adjacent data line area defined, and the first switch pipe T1 and pixel electrode of the pixel cell 13 is positioned at adjacent
Two data wires, the scan line of the N levels pixel cell 13 and next stage low voltage lines Vgl area defined.The pixel list
The second switch pipe T2 of unit 13 is located at adjacent two data wire, the scan line of the N levels pixel cell 13 and this grade of low voltage lines
Vgl area defined.
Wherein, the first switch pipe T1 of the N levels pixel cell 13 also includes control end d, first end e and the second end f,
Control end d connects this grade of scan line, the first end e connection data wire, the second end f connection pixel electrodes.The N level pixel lists
First end a of the second switch pipe T2 of unit 13 connects control end d of first switch pipe T1, and the second end b connects this grade of low voltage lines
Vgl, the 3rd end c connect next stage scan line.
Further referring to Fig. 2, Fig. 2 is the sequential chart of array base palte first embodiment of the present invention.With reference to Fig. 1, with N
As a example by level pixel cell 13, the trailing edge of this grade of scan line scanning signal and the rising edge pair of N+1 level scan line scanning signals
Should.
Specifically have, when scan drive circuit 14 provides scanning signal into scan line, i.e. Fig. 2 when scanning signal is high level
When, control end d of first switch pipe T1 is opened, and now data drive circuit 15 provides grayscale signal to data wire, by first
Switch transistor T 1 charges to pixel electrode, and the pixel electrode can be red pixel electrode, green pixel electrode, blue pixel electrode
And the one kind in white pixel electrode.After this grade of pixel electrode charging complete, scan drive circuit 14 gives N+1 level scan lines
High level, so that N+1 levels pixel cell is while opening, the second switch pipe T2 of N level pixel cells is also opened therewith
Open, the second end b connection low voltage lines Vgl of second switch pipe T2 can cause the scanning letter of the scan line of N level pixel cells
Number drop quickly to electronegative potential.
Above-mentioned embodiment, by setting up second switch pipe in pixel cell, and controls the control end of second switch pipe
Successive scan lines are connected to, within a scan period, the pulse width of scanning signal is fixed, the constant feelings of other conditions
Under condition, the time of trailing edge shortens and means that the time of scanning signal high level is elongated, that is to say, that the unlatching of first switch pipe
Time is elongated so that the charging interval of pixel electrode is elongated, lifts the charge rate of pixel, reduces wrong charging risk, lifts liquid crystal
The display quality of display.
Refer to Fig. 3, Fig. 3 is the structural representation of array base palte second embodiment of the present invention, the embodiment and
One embodiment difference is that the successive scan lines in first embodiment are adjacent with this grade of scan line, i.e. N levels pixel list
The control end of the second switch pipe T2 of unit connects the scan line of N+1 level pixel cells.Successive scan lines in second embodiment
The scan line for being at least spaced one-level with the scan line of N level pixel cells is connected, and the successive scan lines and this grade of scan line it
Between the quantity of scan line be equal to the precharge time and formal charging interval of the pixel cell that this grade of second switch pipe T2 is located
Ratio.In the present embodiment, the control end of the second switch pipe T2 of N level pixel cells connects the scanning of N+2 level pixel cells
Line.It is described in detail below：
Such as Fig. 3, the array base palte 20 includes：Multi-strip scanning line 21, a plurality of data lines 22 and low voltage lines Vgl.Wherein, it is many
Bar scan line 21 and the orthogonal setting of a plurality of data lines 22, to form multiple pixel cells 23.The array base palte 20 also includes scanning
Drive circuit 24 and data drive circuit 25.Wherein, scan drive circuit to provide scanning signal to scan line 21, drive by data
Dynamic circuit is to provide grayscale signal to data wire 22.
By taking N levels pixel cell 23 as an example, each pixel cell 23 includes a first switch pipe T1, first switch pipe T1
The voltage of pixel electrode in for controlling array base palte 20.And each pixel cell 23 further includes one in the permutation substrate 20
Second switch pipe T2, second switch pipe T2 includes：First end a, the second end b and control end c, and first end a connection first
Control end d of switch transistor T 1, in the scan line of the control end c connection N+2 level pixel cells, the second end b connection low-voltages
Line Vgl, for when the scan line of N+2 level pixel cells is opened, so that this grade of scan line drops quickly to electronegative potential.
Please further combined with Fig. 4, Fig. 4 is the sequential chart of array base palte second embodiment of the present invention.In the same manner, with N levels
As a example by pixel cell 23, in the present embodiment, the trailing edge of this grade of scan line scanning signal and N+2 level scan line scanning signals
Rising edge correspondence.
Specifically have, when the rise time of the scanning signal of scan line 21 is long, it usually needs using precharge (Pre-
Charge type of drive) is charged to pixel electrode.So-called precharge be exactly this grade of scan line it is real drive address before, sweep
Drive circuit 24 is retouched to this grade of scan line high level, first switch pipe T1 is opened, line precharge is entered to the pixel of this grade.Such as Fig. 5
Shown in the front half section time t1 of dotted portion be then the precharge time of this grade of pixel electrode, dotted line latter half is formally to fill
Electric time t2, and by taking second embodiment of the invention as an example, when the precharge time t1 of this grade of pixel cell and its formal charging
Between t2 it is equal, and can also be obtained by Fig. 5, when this grade of pixel cell enters the formal charging interval, N+1 level pixel cells are opened
Open first switch pipe T1 and enter line precharge.
When N level pixel cell charging completes, then scan drive circuit 24 is high to the scan line of N+2 level pixel cells
Level, so that N+2 levels pixel cell is while opening, the second switch pipe T2 of N level pixel cells is also opened therewith,
Second end b connection low voltage lines Vgl of second switch pipe T2, can cause the scanning signal of N level pixel cell scan lines fast
Speed drops to electronegative potential.In other embodiments, control end c of the second switch pipe T2 in N levels pixel cell is not limited to connect
The scan line of N+2 level pixel cells is connected to, and its concrete link position needs to be come by the precharge time of N level pixel cells
Determine, specifically have when the precharge time of N level pixel cells being the integral multiple in formal charging interval, i.e., as t1=(m+1) *
During t2, m is positive integer, and the control end of the second switch pipe T2 of the N level pixel cells should be connected to N+m row pixel cells
Scan line on.
Above-mentioned embodiment, by setting up second switch pipe in pixel cell, and controls the control end of second switch pipe
Successive scan lines are connected to, within a scan period, the pulse width of scanning signal is fixed, the constant feelings of other conditions
Under condition, the time of trailing edge shortens and means that the time of scanning signal high level is elongated, that is to say, that the unlatching of first switch pipe
Time is elongated so that the charging interval of pixel electrode is elongated, lifts the charge rate of pixel, reduces wrong charging risk, lifts liquid crystal
The display quality of display.
Fig. 5 is referred to, Fig. 5 is the structural representation of the embodiment of array base palte of the present invention 3rd, with first embodiment
Difference is that each pixel cell includes a second switch pipe T2 in first embodiment, and in 3rd embodiment, correspondence
The pixel cell of same color filter includes a second switch pipe T2, i.e., in N levels pixel cell, second switch pipe T2 can be with
One kind in the corresponding sub-pixel of Red lightscreening plate, green color filter and blue color filter.It is described in detail below：
As shown in figure 5, the array base palte 30 includes：Multi-strip scanning line 31, a plurality of data lines 32 and low voltage lines Vgl.Its
In, multi-strip scanning line 31 and the orthogonal setting of a plurality of data lines 32, to form multiple pixel cells 33.
The array base palte 30 also includes scan drive circuit 34 and data drive circuit 35.Wherein, scan drive circuit 34
To provide scanning signal to scan line 31, data drive circuit 35 is to provide grayscale signal to data wire 32.
By taking N levels pixel cell 33 as an example, each pixel cell 33 includes a first switch pipe T1, first switch pipe T1
The voltage of pixel electrode in for controlling array base palte 30.It is with the corresponding sub-pixel of blue color filter in this grade of pixel cell
Example, i.e. second switch pipe T2 is only located in the pixel cell 33.And the pixel cell 33 is in two adjacent low voltage lines Vgl and two
Adjacent data line area defined, the first switch pipe T1 of the pixel cell 33 and pixel electrode be located at adjacent two data wire,
The scan line and next stage low voltage lines Vgl area defined of the N levels pixel cell 33.The second of the pixel cell 33
Switch transistor T 2 is located at what adjacent two data wire, the scan line of the N levels pixel cell 33 and this grade of low voltage lines Vgl were surrounded
Region.
Wherein, control end d of the first switch pipe T1 of the N levels pixel cell 33 connects this grade of scan line, and first end e connects
Connect data wire, the second end f connection pixel electrodes.First end a of second switch pipe T2 connects control end d of first switch pipe T1,
Second end b connects this grade of low voltage lines Vgl, the 3rd end c connection next stage scan lines.
In can be with further reference to Fig. 2 while its operation principle is described, the sequential chart of array base palte of the present invention schemes
In 2 when the scanning signal of N level pixel cells is high level, control end d of first switch pipe T1 is opened, now data-driven
Circuit 35 provides grayscale signal to data wire, is charged to pixel electrode by first switch pipe T1.When the N level pixel electrodes fill
After the completion of electricity, scan drive circuit 34 closes it to this grade of scan line low level, while next stage scan line high level is given, with
So that N+1 levels pixel cell is while opening, the second switch pipe T2 of N level pixel cells is also opened therewith, and second opens
The second end b connection low voltage lines Vgl of pipe T2 are closed, the scan line that can cause N level pixel cells drops quickly to electronegative potential.
Certainly in other embodiments, second switch pipe T2 may be located in the corresponding pixel cell of redness, green color filter, its point
Analysis principle is the same, and here is omitted.
Above-mentioned embodiment, by setting up second switch pipe in pixel cell, and controls the control end of second switch pipe
Successive scan lines are connected to, within a scan period, the pulse width of scanning signal is fixed, the constant feelings of other conditions
Under condition, the time of trailing edge shortens and means that the time of scanning signal high level is elongated, that is to say, that the unlatching of first switch pipe
Time is elongated so that the charging interval of pixel electrode is elongated, lifts the charge rate of pixel, reduces wrong charging risk, lifts liquid crystal
The display quality of display.
Fig. 6 is referred to, Fig. 6 is the structural representation of the embodiment of array base palte of the present invention 4th, with the 3rd embodiment
Difference is that the successive scan lines in 3rd embodiment are adjacent with this grade of scan line, i.e., the second of N levels pixel cell opens
The control end for closing pipe T2 connects the scan line of N+1 level pixel cells.Successive scan lines in 3rd embodiment and N level pixels
The scan line of unit is at least spaced the scan line connection of one-level, the quantity of the scan line between successive scan lines and this grade of scan line
The precharge time of the pixel cell being located equal to this grade of pixel cell second switch pipe T2 and the ratio in formal charging interval.At this
In embodiment, the control end of the second switch pipe T2 of N level pixel cells connects the scan line of N+2 level pixel cells.Specifically
It is described as follows：
Such as Fig. 6, the array base palte 40 includes：Multi-strip scanning line 41, a plurality of data lines 42 and low voltage lines Vgl.Wherein, it is many
Bar scan line 41 and the orthogonal setting of a plurality of data lines 42, to form multiple pixel cells 43.The array base palte 40 also includes scanning
Drive circuit 44 and data drive circuit 45.Wherein, scan drive circuit to provide scanning signal to scan line 41, drive by data
Dynamic circuit is to provide grayscale signal to data wire 42.
By taking N levels pixel cell 43 as an example, each pixel cell 43 includes a first switch pipe T1, first switch pipe T1
The voltage of pixel electrode in for controlling array base palte 40.And each pixel cell 43 further includes one in the permutation substrate 40
Second switch pipe T2, second switch pipe T2 includes：First end a, the second end b and control end c, and first end a connection first
Control end d of switch transistor T 1, in scan line Gn+2 of the control end c connection N+2 level pixel cells, the second end b connections are low
Pressure-wire Vgl, for when the scan line of N+2 level pixel cells is opened, so that this grade of scan line drops quickly to low electricity
Position.Can be with reference to the sequential chart of Fig. 4 second embodiments when its specific embodiment is described, and its analysis principle and second is in fact
Apply mode to be similar to, may refer to be described above, here is omitted.
Fig. 7 is referred to, Fig. 7 is the contrast schematic diagram of the present invention and prior art type of drive charge waveforms.Such as Fig. 7 institutes
Show, the fall time using the charge waveforms of type of drive A of the present invention is shorter, and the decrease speed of its trailing edge is faster, one
In the individual cycle, the pulse width of scanning signal is fixed, and in the case that other conditions are constant, the time of trailing edge shortens meaning
The time for scanning signal high level is elongated, that is to say, that the opening time of first switch pipe is elongated so that pixel electrode fills
The electric time is elongated, lifts the charge rate of pixel, reduces wrong charging risk, lifts the display quality of liquid crystal display.
Fig. 8 is referred to, Fig. 8 is the structural representation of the embodiment of display floater of the present invention.One kind that the present invention is provided
Display floater 50, the display panels 50 include that the array base palte B in any of the above-described embodiment is relative with array base palte B and set
The public substrate 51 put and the liquid crystal layer 52 being held between array base palte B and public substrate 51, particular content is referred to
Text description, here is omitted.
In sum, it is above-mentioned it should be readily apparent to one skilled in the art that the present invention provides a kind of array base palte and display floater
Embodiment, is subsequently swept by second switch pipe being set up in pixel cell, and controlling the control end of second switch pipe to be connected to
Line is retouched, within a scan period, the pulse width of scanning signal is fixed, in the case that other conditions are constant, trailing edge
Time shorten mean that the time of scanning signal high level is elongated, that is to say, that the opening time of first switch pipe is elongated, makes
The charging interval for obtaining pixel electrode is elongated, lifts the charge rate of pixel, reduces wrong charging risk, lifts the display of liquid crystal display
Quality.
Embodiments of the present invention are the foregoing is only, the scope of the claims of the present invention is not thereby limited, it is every using this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (10)
1. a kind of array base palte, it is characterised in that the array base palte includes：
Multi-strip scanning line, a plurality of data lines and low voltage lines；
Multi-strip scanning line setting orthogonal with a plurality of data lines, to form multiple pixel cells；Wherein, each picture
Plain unit includes a first switch pipe, and pixel cell described at least one further includes a second switch pipe；
The second switch pipe includes：First end, the second end and control end, the first end connects the first switch pipe
Control end, the control end connects a successive scan lines, and the opening sequence of the successive scan lines is in the second switch pipe institute
Corresponding level scan line of the pixel cell after, the trailing edge of described level scan line scanning signal is follow-up with described
The rising edge correspondence of scan line scanning signal, second end connects the low voltage lines.
2. array base palte according to claim 1, it is characterised in that comprising described in one second in each pixel cell
Switching tube.
3. array base palte according to claim 2, it is characterised in that the successive scan lines and described level scan line phase
It is adjacent.
4. array base palte according to claim 2, it is characterised in that the successive scan lines are with described level scan line extremely
The scan line connection of one-level, the number of the scan line between the successive scan lines and described level scan line are spaced less
Amount is equal to the precharge time of the pixel cell that the second switch pipe is located and the ratio in formal charging interval.
5. array base palte according to claim 1, it is characterised in that the pixel cell of the same color filter of correspondence
Include second switch pipe described in.
6. array base palte according to claim 5, it is characterised in that the successive scan lines and described level scan line phase
It is adjacent.
7. array base palte according to claim 5, it is characterised in that the successive scan lines are with described level scan line extremely
The scan line connection of one-level, the number of the scan line between the successive scan lines and described level scan line are spaced less
Amount is equal to the precharge time of the pixel cell that the second switch pipe is located and the ratio in formal charging interval.
8. array base palte according to claim 1, it is characterised in that the array base palte also includes scan drive circuit,
The scan drive circuit is to provide scanning signal to the scan line.
9. array base palte according to claim 1, it is characterised in that the array base palte also includes data drive circuit,
The data drive circuit is to provide grayscale signal to the data wire.
10. a kind of display floater, it is characterised in that the display floater includes the array base as described in claim 1-9 is arbitrary
Plate, the opposite substrate being oppositely arranged with the array base palte and is held between the array base palte and the opposite substrate
Liquid crystal layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710108266.1A CN106647084A (en) | 2017-02-27 | 2017-02-27 | Array substrate and display panel |
| US15/518,809 US10345662B2 (en) | 2017-02-27 | 2017-04-06 | Array substrates and display panels |
| PCT/CN2017/079548 WO2018152936A1 (en) | 2017-02-27 | 2017-04-06 | Array substrate and display panel |
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| CN201710108266.1A CN106647084A (en) | 2017-02-27 | 2017-02-27 | Array substrate and display panel |
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| CN106647084A true CN106647084A (en) | 2017-05-10 |
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| CN201710108266.1A Pending CN106647084A (en) | 2017-02-27 | 2017-02-27 | Array substrate and display panel |
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| Country | Link |
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| US (1) | US10345662B2 (en) |
| CN (1) | CN106647084A (en) |
| WO (1) | WO2018152936A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106935221A (en) * | 2017-05-18 | 2017-07-07 | 京东方科技集团股份有限公司 | Pixel-driving circuit, array base palte and display device |
| CN106959563A (en) * | 2017-05-26 | 2017-07-18 | 上海天马微电子有限公司 | A kind of array base palte and its driving method, display panel, display device |
| CN113380168A (en) * | 2021-05-20 | 2021-09-10 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
| CN114005394A (en) * | 2021-09-30 | 2022-02-01 | 惠科股份有限公司 | Array substrate, array substrate driving method, display panel and display |
| WO2024031760A1 (en) * | 2022-08-12 | 2024-02-15 | 武汉华星光电技术有限公司 | Display panel and display apparatus |
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| US20040041153A1 (en) * | 2002-09-04 | 2004-03-04 | Ju-Young Lee | Array substrate for liquid crystal display device |
| CN101097321A (en) * | 2006-06-29 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of driving the same |
| CN101963724A (en) * | 2009-07-22 | 2011-02-02 | 北京京东方光电科技有限公司 | Liquid crystal display driving device |
| US20130278572A1 (en) * | 2012-04-20 | 2013-10-24 | Samsung Display Co., Ltd. | Display Panel and Display Device Having the Same |
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| CN102402960A (en) * | 2011-12-02 | 2012-04-04 | 深圳市华星光电技术有限公司 | Drive circuit, liquid crystal panel module, liquid crystal display device and drive method |
| US20130141417A1 (en) | 2011-12-02 | 2013-06-06 | Chenghung Chen | Drive Circuit, LCD Panel Module, LCD Device, and Driving Method |
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2017
- 2017-02-27 CN CN201710108266.1A patent/CN106647084A/en active Pending
- 2017-04-06 US US15/518,809 patent/US10345662B2/en active Active
- 2017-04-06 WO PCT/CN2017/079548 patent/WO2018152936A1/en active Application Filing
Patent Citations (5)
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| CN1336568A (en) * | 2000-07-28 | 2002-02-20 | 夏普株式会社 | Image display device |
| US20040041153A1 (en) * | 2002-09-04 | 2004-03-04 | Ju-Young Lee | Array substrate for liquid crystal display device |
| CN101097321A (en) * | 2006-06-29 | 2008-01-02 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of driving the same |
| CN101963724A (en) * | 2009-07-22 | 2011-02-02 | 北京京东方光电科技有限公司 | Liquid crystal display driving device |
| US20130278572A1 (en) * | 2012-04-20 | 2013-10-24 | Samsung Display Co., Ltd. | Display Panel and Display Device Having the Same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106935221A (en) * | 2017-05-18 | 2017-07-07 | 京东方科技集团股份有限公司 | Pixel-driving circuit, array base palte and display device |
| CN106959563A (en) * | 2017-05-26 | 2017-07-18 | 上海天马微电子有限公司 | A kind of array base palte and its driving method, display panel, display device |
| CN106959563B (en) * | 2017-05-26 | 2020-08-18 | 上海天马微电子有限公司 | Array substrate, driving method thereof, display panel and display device |
| CN113380168A (en) * | 2021-05-20 | 2021-09-10 | 北海惠科光电技术有限公司 | Shift register, gate drive circuit and display panel |
| CN114005394A (en) * | 2021-09-30 | 2022-02-01 | 惠科股份有限公司 | Array substrate, array substrate driving method, display panel and display |
| CN114005394B (en) * | 2021-09-30 | 2022-07-22 | 惠科股份有限公司 | Array substrate, array substrate driving method, display panel and display |
| WO2024031760A1 (en) * | 2022-08-12 | 2024-02-15 | 武汉华星光电技术有限公司 | Display panel and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180299720A1 (en) | 2018-10-18 |
| WO2018152936A1 (en) | 2018-08-30 |
| US10345662B2 (en) | 2019-07-09 |
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Application publication date: 20170510 |
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