CN110930923B - Display panel driving circuit - Google Patents
Display panel driving circuit Download PDFInfo
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- CN110930923B CN110930923B CN201911180496.4A CN201911180496A CN110930923B CN 110930923 B CN110930923 B CN 110930923B CN 201911180496 A CN201911180496 A CN 201911180496A CN 110930923 B CN110930923 B CN 110930923B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The present invention provides a display panel driving circuit, including: a timing controller for outputting a first timing signal of a plurality of first channels; a panel including a plurality of second channels for inputting a second timing signal; a level shifter for converting the first timing signal outputted from the timing controller into the second timing signal corresponding to a level required for driving the panel; a multiplexer for controlling the correspondence between the first timing signal and the second timing signal when the plurality of channels between the timing controller and the panel are transmitted.
Description
Technical Field
The invention relates to the technical field of display panel driving, in particular to a Gate Array (GOA) display panel driving circuit.
Background
Display panels that are thin and have high resolution and high color saturation have become the mainstream components in the current consumer market, for example: liquid crystal panel displays, Active Matrix Organic Light Emitting Diode (AMOLED) displays, etc., wherein these display panels require Gate Array (GOA) display panel driving circuits to drive the display screen. As shown in fig. 1, in the conventional multi-CK (e.g. 12CK) GOA panel driving circuit, a scheme of 1 Level Shifter (e.g. CS703) is adopted, the TCON needs to provide at least more than 16 output ports (output pins) (12 CK output ports, 1 ST output port, 2 LC output ports, and 1 VSS output port), and the Level Shifter needs more than 16 input ports (input pins), more than 16 output ports, and more than 16 panel input ports (panel input pins). Such a driving circuit often causes a problem of insufficient input/output pins (I/O pins) of a Timing Controller (TCON) in an actual design process, and also causes a large amount of input/output waste for a level shifter chip.
However, the number of input/output ports of the TCON in the existing driving system is often not sufficient, and a large number of input/output ports of the level shifter chip are wasted. Therefore, the design structure of the driving circuit of the display panel is still to be improved.
Disclosure of Invention
The invention provides a display panel driving circuit which is used for solving the problem that a large number of input/output ports of a level shifter chip are wasted.
The technical scheme provided by the invention is as follows:
an embodiment of the present invention provides a display panel driving circuit, including: a timing controller for outputting a first timing signal of a plurality of first channels;
a panel including a plurality of second channels for inputting a second timing signal;
a level shifter for converting the first timing signal outputted from the timing controller into the second timing signal in conformity with a level required for driving the panel;
a multiplexer for controlling the correspondence between the first timing signal and the second timing signal when the plurality of channels between the timing controller and the panel are transmitted.
In an embodiment of the invention, the timing controller includes a plurality of first transistors corresponding to a plurality of first channels, gates of the first transistors are respectively connected to a plurality of corresponding first control signal voltages, and the plurality of first control signal voltages respectively control turning on and off of the first transistors correspondingly.
In an embodiment of the invention, the panel includes a plurality of second transistors corresponding to the plurality of second channels, gates of the second transistors are respectively connected to a plurality of corresponding second control signal voltages, and the plurality of second control signal voltages respectively control on and off of the second transistors correspondingly.
In an embodiment of the invention, the first transistor and the second transistor are metal oxide semiconductor transistors.
In an embodiment of the invention, the first transistor and the second transistor are nmos transistors.
In an embodiment of the invention, the first transistor and the second transistor are pmos transistors.
In an embodiment of the invention, the first channels and the second channels have the same number and are respectively corresponding to each other to transmit the corresponding first timing signal and the second timing signal.
In an embodiment of the invention, the multiplexer includes a first multiplexer disposed in the timing controller, and is configured to control a correspondence between a plurality of first timing signals of a plurality of first channels of the timing controller and a plurality of second timing signals of a plurality of second channels of the timing controller when the plurality of first timing signals are transmitted.
In an embodiment of the invention, the multiplexer includes a second multiplexer disposed in the panel for controlling a correspondence between a plurality of the first timing signals of a plurality of the first channels and a plurality of the second timing signals of a plurality of the second channels of the panel when the second timing signals are transmitted.
In an embodiment of the present invention, the level shifter converts the first timing signal output by the timing controller into the second timing signal of a higher level required by the panel.
The embodiment of the invention has the following beneficial effects: in the display panel driving circuit provided by the embodiment of the invention, because the multiplexers are arranged at the time sequence controller and the panel driving end, the time sequence signal output port of the time sequence controller and the time sequence signal input port of the panel driving end are integrated, so that the time sequence signals of a plurality of channels can be correspondingly transmitted by using the same output and input ports, the problem of insufficient input/output ports of the time sequence controller can be solved, the number of the input/output ports of the level converter chip can be reduced, the manufacturing cost is reduced, and the efficiency of the driving circuit is improved.
Drawings
In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, the drawings in the following description are only some embodiments of the invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a prior art display panel driving circuit.
Fig. 2 is a schematic diagram of a display panel driving circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a display panel driving circuit according to an embodiment of the invention.
Detailed Description
Reference in the detailed description to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the same phrases in various places in the specification are not necessarily limited to the same embodiment, but are to be construed as independent or alternative embodiments to other embodiments. In light of the disclosure of the embodiments provided by the present invention, it should be understood by those skilled in the art that the embodiments described in the present invention can have other combinations or variations consistent with the concept of the present invention.
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Directional phrases referred to herein, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], [ vertical ], [ horizontal ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding and is in no way limiting.
The turn-On voltage of a Thin Film Transistor (TFT) of a Gate Array (GOA) generally needs 20V or more, and the turn-off voltage needs-5V or less, while the voltage from a TCON timing control circuit generally is a logic voltage of 0V or 3.3V, and thus Level Shifter is required to realize Level shifting.
Fig. 2 is a schematic diagram of a display panel driving circuit according to an embodiment of the invention. As shown in fig. 2, the Timing Controller (TCON) with 12 Timing signal channels is taken as an example for the embodiment, and the number of Timing signal channels is not limited in practical application. The timing controller TCON includes 12 transistors M301, M302, M303, M304, M305, M306, M307, M308, M309, M310, M311, M312, gates (gates) of the transistors M301-M312 are respectively connected to 12 control signal voltages S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211, S212, and the 12 control signal voltages S201-S212 respectively correspond to on and off of the transistors M301-M312. If the transistors M301-M312 are Metal Oxide Semiconductor (MOS) transistors, the drains (drain) of the transistors M301-M312 are respectively connected to the 12 timing signals CK101, CK102, CK103, CK104, CK105, CK106, CK107, CK108, CK109, CK110, CK111, CK112, and when the transistors M301-M312 are respectively controlled to be turned on by the control signal voltages S201-S212, the sources (source) of the transistors M301-M312 respectively correspond to the output timing signals CK101-CK 112; if the transistors M301-M312 are P-type MOS transistors, the sources of the transistors M301-M312 are respectively connected to 12 clock signals CK101, CK102, CK103, CK104, CK105, CK106, CK107, CK108, CK109, CK110, CK111, and CK112, and when the transistors M301-M312 are respectively controlled to be turned on by the control signal voltages S201-S212, the drains of the transistors M301-M312 respectively correspond to the output clock signals CK101-CK 112.
The timing signals CK101 to CK112 output from the transistors M301 to M312 in the timing controller are merged to a timing signal output port CKa through a first multiplexer MTa (not shown), and are input to a Level Shifter LS (Level Shifter, LS) from the output port CKa. The level shifter LS may convert a timing signal of a higher level (VGH) to a timing signal of a lower level (VGL) or convert a timing signal of a lower level (VGL) to a timing signal of a higher level (VGH) as needed. The timing signals CK101-CK112 are converted into timing signals CK401-CK412 for driving the Panel, and the timing signals CK401-CK412 are coupled to a timing signal input port CKb through a second multiplexer MTb (not shown) and are respectively input to the transistors M601-M612 of the Panel Panel. If the transistors M601-M612 are N-type MOS transistors, the drains (drain) of the transistors M601-M612 are respectively connected to the 12 clock signals CK401-CK412, and when the transistors M601-M612 are respectively controlled to be turned on by the control signal voltages S501-S512, the sources (source) of the transistors M601-M612 respectively correspond to the output clock signals CK401-CK 412; if the transistors M601-M612 are P-type MOS transistors, the sources of the transistors M601-M612 are respectively connected to the 12 clock signals CK401-CK412, and when the transistors M601-M612 are respectively controlled by the control signal voltages S501-S512 to be turned on, the drains of the transistors M601-M612 respectively correspond to the output clock signals CK401-CK 412.
The first multiplexer MTa sequentially connects the timing signals CK101-CK112 in the timing controller TCON to the level shifter LS through the timing signal output port CKa, and after the timing signals CK101-CK112 are converted into the timing signals CK401-CK412 corresponding to the level required by the driving Panel through the level shifter LS, the corresponding timing signals CK401-CK412 are sequentially input to the corresponding transistors M601-M612 through the second multiplexer MTb via the timing signal input port CKb. The first multiplexer MTa and the second multiplexer MTb synchronously control the timing signals which are subjected to level conversion at the present time, so as to ensure that the timing signals CK401-CK412 accessed by the transistors M601-M612 of the Panel correspond to the timing signals CK101-CK112 in the timing controller TCON, respectively.
Fig. 3 is a schematic diagram of a display panel driving circuit according to an embodiment of the present invention, and fig. 3 illustrates a display panel driving circuit of a level shifter LS architecture with a reduced number of input/output ports. This embodiment does not limit the number of timing signal channels within the timing controller TCON. The timing controller TCON generates a first timing signal of a plurality of channels, and the plurality of timing signals generated in the timing controller are converged to a timing signal output port CKa through a first multiplexer MTa and input to the level shifter LS through the output port CKa. The level shifter LS may convert a timing signal of a higher level (VGH) into a timing signal of a lower level (VGL) or convert a timing signal of a lower level (VGL) into a timing signal of a higher level (VGH) as needed. The first timing signal is converted into a second timing signal for driving the Panel, and the second timing signal is converged to a timing signal input port CKb through a second multiplexer MTb and respectively input to a plurality of corresponding second timing signal channels in the Panel for driving the Panel.
The first multiplexer MTa sequentially accesses a plurality of first timing signals in the timing controller TCON to the level shifter LS through the timing signal output port CKa, and the first timing signals are converted into second timing signals in accordance with the level required by the driving Panel through the level shifter LS, and then sequentially input to the corresponding second timing signal channels through the timing signal input port CKb through the second multiplexer MTb. The first multiplexer MTa and the second multiplexer MTb synchronously control the timing signals for performing the level conversion at the next time, so as to ensure that the second timing signals accessed by the plurality of second timing signal channels of the Panel correspond to the first timing signals in the timing controller TCON, respectively.
In the embodiment of the invention, because the multiplexers are arranged at the time sequence controller and the panel driving end, and the time sequence signal output port of the time sequence controller and the time sequence signal input port of the panel driving end are integrated, so that the time sequence signals of a plurality of channels can be correspondingly transmitted by using the same output and input ports, the problem of insufficient input/output ports of the time sequence controller can be solved, the number of the input/output ports of the level converter chip can be reduced, the manufacturing cost is reduced, and the efficiency of the driving circuit is improved.
In summary, although the present invention has been disclosed with reference to the preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present invention, which is defined by the appended claims.
Claims (9)
1. A display panel driving circuit, comprising:
a timing controller for outputting a first timing signal of a plurality of first channels;
a panel including a plurality of second channels for inputting a second timing signal;
a level shifter for converting the first timing signal outputted from the timing controller into the second timing signal corresponding to a level required for driving the panel;
a multiplexer for controlling the correspondence between the first timing signal and the second timing signal when the plurality of channels between the timing controller and the panel are transmitted;
the multiplexer includes a first multiplexer disposed in the timing controller for controlling a correspondence between a plurality of first timing signals of a plurality of first channels of the timing controller and a plurality of second timing signals of a plurality of second channels of the timing controller when the plurality of first timing signals are transmitted.
2. The display panel driving circuit according to claim 1, wherein the timing controller comprises a plurality of first transistors corresponding to a plurality of first channels, gates of the first transistors are respectively connected to a plurality of first control signal voltages, and the plurality of first control signal voltages respectively control on and off of the first transistors.
3. The display panel driving circuit according to claim 1, wherein the panel comprises a plurality of second transistors corresponding to a plurality of second channels, gates of the second transistors are respectively connected to a plurality of second control signal voltages, and the plurality of second control signal voltages respectively control turning on and off of the second transistors.
4. The display panel driving circuit according to claim 2 or 3, wherein the first transistor and the second transistor are metal oxide semiconductor transistors.
5. The display panel driving circuit according to claim 2 or 3, wherein the first transistor and the second transistor are NMOS transistors.
6. The display panel driving circuit according to claim 2 or 3, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors.
7. The display panel driving circuit according to claim 1, wherein the first channels and the second channels are equal in number and are respectively corresponding to each other to transmit the corresponding first timing signal and the second timing signal.
8. The display panel driving circuit according to claim 1, wherein the multiplexer comprises a second multiplexer disposed in the panel for controlling a correspondence between a plurality of the second timing signals of a plurality of the second channels of the panel and a plurality of the first timing signals of a plurality of the first channels when the second timing signals are transmitted.
9. The display panel driving circuit according to claim 1, wherein the level shifter shifts the first timing signal output from the timing controller to the second timing signal of a higher level required for the panel.
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| CN201911180496.4A CN110930923B (en) | 2019-11-27 | 2019-11-27 | Display panel driving circuit |
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| CN201911180496.4A CN110930923B (en) | 2019-11-27 | 2019-11-27 | Display panel driving circuit |
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| CN111063316A (en) * | 2020-01-17 | 2020-04-24 | Tcl华星光电技术有限公司 | Driving circuit and display panel applying same |
| US11043175B1 (en) | 2020-01-17 | 2021-06-22 | Tcl China Star Optoelectronics Technology Co., Ltd. | Driving circuit and display panel used therefor |
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