CN205984242U - Shifting register unit, gate driving circuit and display device - Google Patents

Abstract

The utility model discloses a shifting register unit, gate driving circuit and display device, include: an input module, the 2nd input module, the first module that restores to the throne, second restore to the throne module, node control module, an output module and the 2nd output module, wherein, through mutually supporting of seven above -mentioned modules, can make every shift register unit output have two scanning signal of certain phase difference through sharing node control module to correspond two lines of grid lines among the display panel, with two shift register's realizing having now function, thereby compare simple structure with two current shift register, thereby reduce the occupation space of gate drive circuit, more be suitable for the design of narrow frame.

Description

Shift register cell, gate driver circuit and display device

Technical field

This utility model is related to display technology field, particularly to a kind of shift register cell, gate driver circuit and Display device.

Background technology

In TFT thin film transistor monitor, generally pass through gate driver circuit each thin film transistor (TFT) to pixel region The grid of (TFT, Thin Film Transistor) provides gate drive signal.Gate driver circuit can pass through array processes It is formed on the array base palte of liquid crystal display, i.e. array base palte row cutting (Gate Driver on Array, GOA) technique, This integrated technique not only saves cost, and can accomplish the symmetrical design for aesthetic in liquid crystal panel (Panel) both sides, with When, also eliminate binding (Bonding) region and the fan-out of grid integrated circuits (IC, Integrated Circuit) (Fan-out) wiring space, such that it is able to realize the design of narrow frame；And, this integrated technique may be omitted with grid The Bonding technique of scan-line direction, thus improve production capacity and yield.

Existing gate driver circuit is generally made up of the shift register of multiple cascades, and shift registers at different levels are right respectively Answer a grid line, gate driver circuit passes through shift registers at different levels successively to each grid line of scanning.But, drive in existing grid In galvanic electricity road, shift registers at different levels all include multiple switch transistor, and area occupied is larger, thus being unfavorable for narrow frame Design.Therefore, a kind of gate driver circuit being conducive to narrow frame design how is provided to be those skilled in the art's urgent need to resolve Technical problem.

Utility model content

This utility model embodiment provides a kind of shift register cell, gate driver circuit and display device, is used for carrying For a kind of gate driver circuit being conducive to narrow frame design.

This utility model embodiment provides a kind of shift register cell, including：First input module, the second input mould Block, the first reseting module, the second reseting module, node control module, the first output module and the second output module；Wherein,

Described first input module respectively with the first input signal end, the first direct current signal end and the first pull-up node phase Even；Described first input module is used for the signal at described first direct current signal end under the control at described first input signal end It is supplied to described first pull-up node；

Described first reseting module is saved with the first reset signal end, the second direct current signal end and described first pull-up respectively Point is connected；Described first reseting module is used for described second direct current signal end under the control at described first reset signal end Signal is supplied to described first pull-up node；

Described second input module is saved with the second input signal end, described first direct current signal end and the second pull-up respectively Point is connected；Described second input module is used for described first direct current signal end under the control at described second input signal end Signal is supplied to described second pull-up node；

Described second reseting module respectively with the second reset signal end, described second direct current signal end and described second on Node is drawn to be connected；Described second reseting module is used for described second direct current signal under the control at described second reset signal end The signal at end is supplied to described second pull-up node；

Described node control module respectively with the first clock signal terminal, second clock signal end, described first pull-up node, Described second pull-up node, the first pull-down node, the second pull-down node are connected；Described node control module is used for described first Under the control of clock signal terminal, the signal of described first clock signal terminal is supplied to described first pull-down node, described second Under the control of clock signal terminal, the signal of described second clock signal end is supplied to described second pull-down node, described first The current potential of the current potential of described first pull-down node and described second pull-down node and described the is made respectively under the control of pull-up node The current potential of one pull-up node is contrary, make respectively under the control of described second pull-up node described first pull-down node current potential and The current potential of described second pull-down node is contrary with the current potential of described second pull-up node, under the control of described first pull-down node Make the current potential of the current potential of described first pull-up node and the current potential of described second pull-up node and described first pull-down node respectively On the contrary, the current potential of described first pull-up node and described second pull-up and are made under the control of described second pull-down node respectively The current potential of node is contrary with the current potential of described second pull-down node；

Described first output module respectively with described first clock signal terminal, described second clock signal end, reference signal End, described first pull-up node, described first pull-down node, described second pull-down node and described shift register cell First drive signal outfan is connected；Described first output module is used for described the under the control of described first pull-up node The signal of one clock signal terminal is supplied to described first drive signal outfan, respectively in described first pull-down node and described Under the control of two pull-down node, the signal at described reference signal end is supplied to described first drive signal outfan, described Under the control of two clock signal terminals, the signal at described reference signal end is supplied to described first drive signal outfan, Yi Ji Described first pull-up node be in during floating keep described first pull-up node and described first drive signal outfan it Between voltage difference stable；

Described second output module respectively with described first clock signal terminal, described second clock signal end, described reference Signal end, described second pull-up node, described first pull-down node, described second pull-down node and described shift register list Second drive signal outfan of unit is connected；Described second output module is used for institute under the control of described second pull-up node The signal stating second clock signal end is supplied to described second drive signal outfan, respectively in described first pull-down node and institute State, under the control of the second pull-down node, the signal at described reference signal end is supplied to described second drive signal outfan, in institute State under the control of the first clock signal terminal by the signal at described reference signal end be supplied to described second drive signal outfan with And described second pull-up node and described second drive signal output is kept when described second pull-up node is in floating Voltage difference between end is stable.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described node control module includes：First pull-up node control module, the second pull-up node control module, the first pull-down node control Molding block and the second pull-down node control module；Wherein,

Described first pull-up node control module respectively with described reference signal end, described first pull-up node, described One pull-down node, described second pull-down node are connected；Described first pull-up node control module is used for respectively under described first Draw, under node and the control of described second pull-down node, the signal at described reference signal end is supplied to described first pull-up node；

Described second pull-up node control module respectively with described reference signal end, described second pull-up node, described One pull-down node, described second pull-down node are connected；Described second pull-up node control module is used for respectively under described first Draw, under node and the control of described second pull-down node, the signal at described reference signal end is supplied to described second pull-up node；

Described first pull-down node control module respectively with described first clock signal terminal, described reference signal end, described First pull-down node, described first pull-up node, described second pull-up node are connected；Described first pull-down node control module is used Under the control in described first clock signal terminal, the signal of described first clock signal terminal is supplied under described first Draw node, and respectively under the control of described first pull-up node and described second pull-up node by described reference signal end Signal is supplied to described first pull-down node；

Described second pull-down node control module respectively with described second clock signal end, described reference signal end, described Second pull-down node, described first pull-up node, described second pull-up node are connected；Described second pull-down node control module is used Under the control in described second clock signal end, the signal of described second clock signal end is supplied under described second Draw node, and respectively under the control of described first pull-up node and described second pull-up node by described reference signal end Signal is supplied to described second pull-down node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first pull-up node control module includes：First switch transistor and second switch transistor；Wherein,

The grid of described first switch transistor is connected with described first pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described first pull-up node；

The grid of described second switch transistor is connected with described second pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described first pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described second pull-up node control module includes：3rd switching transistor and the 4th switching transistor；Wherein,

The grid of described 3rd switching transistor is connected with described second pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described second pull-up node；

The grid of described 4th switching transistor is connected with described first pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described second pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first pull-down node control module includes：5th switching transistor, the 6th switching transistor and the 7th switching transistor；Its In,

The grid of described 5th switching transistor is all connected with described first clock signal terminal with source electrode, drain electrode and described the One pull-down node is connected；

The grid of described 6th switching transistor is connected with described first pull-up node, source electrode and described reference signal end phase Even, drain electrode is connected with described first pull-down node；

The grid of described 7th switching transistor is connected with described second pull-up node, source electrode and described reference signal end phase Even, drain electrode is connected with described first pull-down node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described second pull-down node control module includes：8th switching transistor, the 9th switching transistor and the tenth switching transistor；Its In,

The grid of described 8th switching transistor is all connected with described second clock signal end with source electrode, drain electrode and described the Two pull-down node are connected；

The grid of described 9th switching transistor is connected with described first pull-up node, source electrode and described reference signal end phase Even, drain electrode is connected with described second pull-down node；

The grid of described tenth switching transistor is connected with described second pull-up node, source electrode and described reference signal end phase Even, drain electrode is connected with described second pull-down node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first input module includes：11st switching transistor；Wherein,

The grid of described 11st switching transistor is connected with described first input signal end, source electrode and described first direct current Signal end is connected, and drain electrode is connected with described first pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first reseting module includes：Twelvemo closes transistor；Wherein,

The grid that described twelvemo closes transistor is connected with described first reset signal end, source electrode and described second direct current Signal end is connected, and drain electrode is connected with described first pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described second input module includes：13rd switching transistor；Wherein,

The grid of described 13rd switching transistor is connected with described second input signal end, source electrode and described first direct current Signal end is connected, and drain electrode is connected with described second pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described second reseting module includes：14th switching transistor；Wherein,

The grid of described 14th switching transistor is connected with described second reset signal end, source electrode and described second direct current Signal end is connected, and drain electrode is connected with described second pull-up node.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first output module includes：15th switching transistor, sixteenmo close transistor, the 17th switching transistor, the tenth Eight switching transistors and the first electric capacity；Wherein,

The grid of described 15th switching transistor is connected with described first pull-up node, and source electrode is believed with described first clock Number end be connected, drain electrode be connected with described first drive signal outfan；

The grid that described sixteenmo closes transistor is connected with described first pull-down node, source electrode and described reference signal end It is connected, drain electrode is connected with described first drive signal outfan；

The grid of described 17th switching transistor is connected with described second pull-down node, source electrode and described reference signal end It is connected, drain electrode is connected with described first drive signal outfan；

The grid that described eighteenmo closes transistor is connected with described second clock signal end, source electrode and described reference signal End is connected, and drain electrode is connected with described first drive signal outfan；

The first end of described first electric capacity is connected with described first pull-up node, and the second end is defeated with described first drive signal Go out end to be connected.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described second output module includes：19th switching transistor, the 20th switching transistor, the 21st switching transistor, Two twelvemos close transistor AND gate second electric capacity；Wherein,

The grid of described 19th switching transistor is connected with described second pull-up node, and source electrode is believed with described second clock Number end be connected, drain electrode be connected with described second drive signal outfan；

The grid of described 20th switching transistor is connected with described second pull-down node, source electrode and described reference signal end It is connected, drain electrode is connected with described second drive signal outfan；

The grid of described 21st switching transistor is connected with described first pull-down node, source electrode and described reference signal End is connected, and drain electrode is connected with described second drive signal outfan；

The grid that described second twelvemo closes transistor is connected with described first clock signal terminal, and source electrode is with described with reference to letter Number end be connected, drain electrode be connected with described second drive signal outfan；

The first end of described second electric capacity is connected with described second pull-up node, and the second end is defeated with described second drive signal Go out end to be connected.

In a kind of possible embodiment, in the above-mentioned shift register cell that this utility model embodiment provides, Described first reset signal end is connected with described second drive signal outfan；And/or,

Described second input signal end is connected with described first drive signal outfan.

Correspondingly, this utility model embodiment additionally provides a kind of gate driver circuit, including multiple practicalities of cascade Any of the above-described kind of shift register cell that new embodiment provides；Wherein,

First input signal end of first order shift register cell is connected with frame trigger end；

In addition to first order shift register cell, the first input signal end of remaining shift register cell at different levels is respectively It is connected with the second drive signal outfan of upper level shift register cell；

In addition to afterbody shift register cell, the second reset signal end of remaining shift register cell at different levels is divided It is not connected with the first drive signal outfan of next stage shift register cell.

Correspondingly, this utility model embodiment additionally provides a kind of display floater, provides including this utility model embodiment Above-mentioned gate driver circuit.

Shift register cell, gate driver circuit and display device that this utility model embodiment provides, including：First Input module, the second input module, the first reseting module, the second reseting module, node control module, the first output module and Two output modules；Wherein, cooperating by above-mentioned seven modules, can make each displacement by common points control module Register cell output has two scanning signals of certain phase contrast, to correspond to two row grid lines in display floater, to realize The function of existing two shift registers is simple with existing two shift register structure compared, thus reduce grid driving The taking up room, more suitable for narrow frame design of galvanic electricity road..

Brief description

One of structural representation of shift register cell that Fig. 1 a provides for this utility model embodiment；

The two of the structural representation of the shift register cell that Fig. 1 b provides for this utility model embodiment；

One of concrete structure schematic diagram of shift register cell that Fig. 2 a provides for this utility model embodiment；

The two of the concrete structure schematic diagram of the shift register cell that Fig. 2 b provides for this utility model embodiment；

Fig. 3 a is the circuit timing diagram of the shift register cell shown in Fig. 2 a；

Fig. 3 b is the circuit timing diagram of the shift register cell shown in Fig. 2 b；

The flow chart of the driving method that Fig. 4 provides for this utility model embodiment；

The structural representation of the gate driver circuit that Fig. 5 provides for this utility model embodiment..

Specific embodiment

In order that the purpose of this utility model, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, new to this practicality The specific embodiment of shift register cell, gate driver circuit and display device that type embodiment provides is carried out in detail Bright.

A kind of shift register cell that this utility model embodiment provides, as shown in Figure 1a, including：First input module 1st, the second input module 2, the first reseting module 3, the second reseting module 4, node control module 5, the first output module 6 and second Output module 7；Wherein,

First input module 1 is pulled up with the first input signal end Input1, the first direct current signal end VG1 and first respectively Node PU1 is connected；First input module 1 is used for the first direct current signal end under the control of the first input signal end Input1 The signal of VG1 is supplied to the first pull-up node PU1；

First reseting module 3 is pulled up with the first reset signal end Reset1, the second direct current signal end VG2 and first respectively Node PU1 is connected；First reseting module 3 is used for the second direct current signal end under the control of the first reset signal end Reset1 The signal of VG2 is supplied to the first pull-up node PU1；

Second input module 2 is pulled up with the second input signal end Input2, the first direct current signal end VG1 and second respectively Node PU2 is connected；Second input module 2 is used for the first direct current signal end under the control of the second input signal end Input2 The signal of VG1 is supplied to the second pull-up node PU2；

Second reseting module 4 is pulled up with the second reset signal end Reset2, the second direct current signal end VG2 and second respectively Node PU2 is connected；Second reseting module 4 is used for the second direct current signal end under the control of the second reset signal end Reset2 The signal of VG2 is supplied to the second pull-up node PU2；

Node control module 5 respectively with the first clock signal terminal CK1, second clock signal end CK2, the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, the second pull-down node PD2 are connected；Node control module 5 is used for the Under the control of one clock signal terminal CK1, the signal of the first clock signal terminal CK1 is supplied to the first pull-down node PD1, second Under the control of clock signal terminal CK2, the signal of second clock signal end CK2 is supplied to the second pull-down node PD2, on first Draw and under the control of node PU2, make the current potential of the first pull-down node PD1 and the current potential of the second pull-down node PD2 and the first pull-up respectively The current potential of node PU1 is contrary, makes the current potential and second of the first pull-down node PD1 under the control of the second pull-up node PU2 respectively The current potential of pull-down node PD2 is contrary with the current potential of the second pull-up node PU2, makes respectively under the control of the first pull-down node PD1 The current potential of the current potential of the first pull-up node PU1 and the second pull-up node PU2 is contrary with the current potential of the first pull-down node PD1, and Make respectively under the control of the second pull-down node PD2 the current potential of the current potential of the first pull-up node PU1 and the second pull-up node PU2 with The current potential of the second pull-down node PD2 is contrary；

First output module 6 respectively with the first clock signal terminal CK1, second clock signal end CK2, reference signal end Ref, First driving letter of the first pull-up node PU1, the first pull-down node PD1, the second pull-down node PD2 and shift register cell Number outfan Output1 is connected；First output module 6 is used for the first clock signal under the control of the first pull-up node PU1 The signal of end CK2 is supplied to the first drive signal outfan Output1, respectively in the first pull-down node PD1 and the second drop-down section Under the control of point PD2, the signal of reference signal end Ref is supplied to the first drive signal outfan Output1, described second Under the control of clock signal terminal CK2, the signal of described reference signal end Ref is supplied to described first drive signal outfan Output1, and the first pull-up node PU1 and the first drive signal is kept when the first pull-up node PU1 is in floating Voltage difference between outfan Output1 is stable；

Second output module 7 respectively with the first clock signal terminal CK1, second clock signal end CK2, reference signal end Ref, Second driving letter of the second pull-up node PU2, the first pull-down node PD1, the second pull-down node PD2 and shift register cell Number outfan Output2 is connected；Second output module 7 is used for second clock signal under the control of the second pull-up node PU2 The signal of end CK2 is supplied to the second drive signal outfan Output2, respectively in the first pull-down node PD1 and the second drop-down section Under the control of point PD2, the signal of reference signal end Ref is supplied to the second drive signal outfan Output2, described first Under the control of clock signal terminal CK1, the signal of described reference signal end Ref is supplied to described second drive signal outfan Output2 and keep the second pull-up node PU2 defeated with the second drive signal when the second pull-up node PU2 is in floating Go out to hold the voltage difference between Output2 stable.

The above-mentioned shift register cell that this utility model embodiment provides, including：First input module, the second input mould Block, the first reseting module, the second reseting module, node control module, the first output module and the second output module；Wherein, lead to Cross cooperating of above-mentioned seven modules, the output of each shift register cell can be made to have by common points control module Two scanning signals of certain phase contrast, to correspond to two row grid lines in display floater, to realize existing two shift LDs The function of device.Thus simple with existing two shift register structure compared, thus the occupancy reducing gate driver circuit is empty Between, more suitable for narrow frame design.

It should be noted that in the above-mentioned shift register cell that this utility model embodiment provides, with forward scan As a example, when the effective impulse signal at the first input signal end is high potential, the current potential at the first direct current signal end is high potential, the The current potential at two direct current signal ends is electronegative potential, and the current potential at reference signal end is electronegative potential；Effective arteries and veins when the first input signal end When rushing signal for electronegative potential, the current potential at the first direct current signal end is electronegative potential, and the current potential at the second direct current signal end is high potential, ginseng The current potential examining signal end is high potential.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 1b, node control module 5 specifically can include：First pull-up node control module 51, the second pull-up node control module 52nd, the first pull-down node control module 53 and the second pull-down node control module 54；Wherein,

First pull-up node control module 51 respectively with reference signal end Ref, the first pull-up node PU1, the first drop-down section Point PD1, the second pull-down node PD2 are connected；First pull-up node control module 51 is used for respectively in the first pull-down node PD1 and the Under the control of two pull-down node PD2, the signal of reference signal end Ref is supplied to the first pull-up node PU1；

Second pull-up node control module 52 respectively with reference signal end Ref, the second pull-up node PU2, the first drop-down section Point PD1, the second pull-down node PD2 are connected；Second pull-up node control module 52 is used for respectively in the first pull-down node PD1 and the Under the control of two pull-down node PD2, the signal of reference signal end Ref is supplied to the second pull-up node PU2；

First pull-down node control module 53 respectively with the first clock signal terminal CK1, reference signal end Ref, first drop-down Node PD1, the first pull-up node PU1, the second pull-up node PU2 are connected；First pull-down node control module 53 is used for first Under the control of clock signal terminal CK1, the signal of the first clock signal terminal CK1 is supplied to the first pull-down node PD1, and respectively Under the control of the first pull-up node PU1 and the second pull-up node PU2, the signal of reference signal end Ref is supplied to first drop-down Node PD1；

Second pull-down node control module 54 respectively with second clock signal end CK2, reference signal end Ref, second drop-down Node PD2, the first pull-up node PU1, the second pull-up node PU2 are connected；Second pull-down node control module 54 is used for second Under the control of clock signal terminal CK2, the signal of second clock signal end CK2 is supplied to the second pull-down node PD2, and respectively Under the control of the first pull-up node PU1 and the second pull-up node PU2, the signal of reference signal end Ref is supplied to second drop-down Node PD2.

With reference to specific embodiment, this utility model is described in detail.It should be noted that in the present embodiment being In order to preferably explain this utility model, but do not limit this utility model.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the first pull-up node control module 51 specifically can include：First switch transistor M1 and second switch crystal Pipe M2；Wherein,

The grid of described first switch transistor M1 is connected with described first pull-down node PD1, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described first pull-up node PU1；

The grid of described second switch transistor M2 is connected with described second pull-down node P2, source electrode and described reference signal End Ref is connected, and drain electrode is connected with described first pull-up node PU1.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, first switch transistor M1 and second switch are brilliant Body pipe M2 can be N-type switching transistor；Or, when the effective impulse signal of the first input signal end Input1 is electronegative potential When, as shown in Figure 2 b, first switch transistor M1 and second switch transistor M2 can be p-type switching transistor, and here is not made Limit.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, work as first switch When transistor is in the conduction state under the control of the first pull-down node, the signal at reference signal end is supplied to drawknot on first Point；When second switch transistor is in the conduction state under the control of the second pull-down node, the signal at reference signal end is carried Drawknot node in supply first.

The above is only the concrete structure illustrating the first pull-up node control module in shift register cell, concrete During enforcement, the concrete structure of the first pull-up node control module is not limited to the said structure of this utility model embodiment offer, also Can be skilled person will appreciate that other structures, here do not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the second pull-up node control module 52 specifically can include：3rd switching transistor M3 and the 4th switch crystal Pipe M4；Wherein,

The grid of described 3rd switching transistor M3 is connected with described second pull-down node PD2, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described second pull-up node PU2；

The grid of described 4th switching transistor M4 is connected with described first pull-down node PD1, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described second pull-up node PU2.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 3rd switching transistor M3 and the 4th switch are brilliant Body pipe M4 can be N-type switching transistor；Or, when the effective impulse signal of the first input signal end Input1 is electronegative potential When, as shown in Figure 2 b, the 3rd switching transistor M3 and the 4th switching transistor M4 can be p-type switching transistor, and here is not made Limit.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 3rd switch When transistor is in the conduction state under the control of the second pull-down node, the signal at reference signal end is supplied to the second pull-up section Point；When the 4th switching transistor is in the conduction state under the control of the first pull-down node, the signal at reference signal end is carried Supply the second pull-up node.

The above is only the concrete structure illustrating the second pull-up node control module in shift register cell, concrete During enforcement, the concrete structure of the second pull-up node control module is not limited to the said structure of this utility model embodiment offer, also Can be skilled person will appreciate that other structures, here do not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the first pull-down node control module 53 specifically can include：5th switching transistor M5, the 6th switching transistor M6 and the 7th switching transistor M7；Wherein,

The grid of described 5th switching transistor M5 is all connected with described first clock signal terminal CK1 with source electrode, drain electrode with Described first pull-down node PD1 is connected；

The grid of described 6th switching transistor M6 is connected with described first pull-up node PU1, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described first pull-down node PD1；

The grid of described 7th switching transistor M7 is connected with described second pull-up node PU2, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described first pull-down node PD1.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 5th switching transistor M5, the 6th switch crystal Pipe M6 and the 7th switching transistor M7 can be N-type switching transistor；Or, when effective arteries and veins of the first input signal end Input1 When rushing signal for electronegative potential, as shown in Figure 2 b, the 5th switching transistor M5, the 6th switching transistor M6 and the 7th switching transistor M7 can be p-type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 5th switch When transistor is in the conduction state under the control of the first clock signal terminal, the signal of the first clock signal terminal is supplied to first Pull-down node；When the 6th switching transistor is in the conduction state under the control of the first pull-up node, by reference signal end Signal is supplied to the first pull-down node；When the 7th switching transistor is in the conduction state under the control of the second pull-up node, The signal at reference signal end is supplied to the first pull-down node.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, in technique preparation When typically by the chi of ratio the 5th switching transistor of the size of the size of the 6th switching transistor and the 7th switching transistor setting Very little big, so when the signal of the first pull-up node is effective impulse signal, the 6th switching transistor can be made in the first pull-up The speed under the control of node, the signal at reference signal end being supplied to the first pull-down node is more than the 5th switching transistor the Under the control of one clock signal terminal, the signal of the first clock signal terminal is supplied to the speed of the first pull-down node, such that it is able to protect The current potential demonstrate,proving the first pull-down node is contrary with the current potential of the first pull-up node；In the same manner, when the signal of the second pull-up node is effective During pulse signal, the 7th switching transistor can be made to be supplied to the signal at reference signal end under the control of the second pull-up node The speed of the first pull-down node is more than the 5th switching transistor under the control of the first clock signal terminal by the first clock signal terminal Signal be supplied to the speed of the first pull-down node, thereby may be ensured that the current potential of the first pull-down node and the second pull-up node Current potential is contrary.

The above is only the concrete structure illustrating the first pull-down node control module in shift register cell, concrete During enforcement, the concrete structure of the first pull-down node control module is not limited to the said structure of this utility model embodiment offer, also Can be skilled person will appreciate that other structures, here do not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the second pull-down node control module 54 specifically can include：8th switching transistor M8, the 9th switching transistor M9 and the tenth switching transistor M10；Wherein,

The grid of described 8th switching transistor M8 is all connected with described second clock signal end CK2 with source electrode, drain electrode with Described second pull-down node PD2 is connected；

The grid of described 9th switching transistor M9 is connected with described first pull-up node PU1, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described second pull-down node PD2；

The grid of described tenth switching transistor M10 is connected with described second pull-up node PU2, and source electrode is with described with reference to letter Number end Ref be connected, drain electrode be connected with described second pull-down node PD2.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 8th switching transistor M8, the 9th switch crystal Pipe M9 and the tenth switching transistor M10 can be N-type switching transistor；Or, effective as the first input signal end Input1 When pulse signal is electronegative potential, as shown in Figure 2 b, the 8th switching transistor M8, the 9th switching transistor M9 and the tenth switch crystal Pipe M10 can be p-type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 8th switch When transistor is in the conduction state under the control of second clock signal end, the signal of second clock signal end is supplied to second Pull-down node；When the 9th switching transistor is in the conduction state under the control of the first pull-up node, by reference signal end Signal is supplied to the second pull-down node；When the tenth switching transistor is in the conduction state under the control of the second pull-up node, The signal at reference signal end is supplied to the second pull-down node.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, in technique preparation When typically by the chi of ratio the 8th switching transistor of the size of the size of the 9th switching transistor and the tenth switching transistor setting Very little big, so when the signal of the first pull-up node is effective impulse signal, the 9th switching transistor can be made in the first pull-up The speed under the control of node, the signal at reference signal end being supplied to the second pull-down node is more than the 8th switching transistor the Under the control of two clock signal terminals, the signal of second clock signal end is supplied to the speed of the second pull-down node, such that it is able to protect The current potential demonstrate,proving the second pull-down node is contrary with the current potential of the first pull-up node；In the same manner, when the signal of the second pull-up node is effective During pulse signal, the tenth switching transistor can be made to be supplied to the signal at reference signal end under the control of the second pull-up node The speed of the second pull-down node is more than the 8th switching transistor under the control of second clock signal end by second clock signal end Signal be supplied to the speed of the second pull-down node, thereby may be ensured that the current potential of the second pull-down node and the second pull-up node Current potential is contrary.

The above is only the concrete structure illustrating the second pull-down node control module in shift register cell, concrete During enforcement, the concrete structure of the second pull-down node control module is not limited to the said structure of this utility model embodiment offer, also Can be skilled person will appreciate that other structures, here do not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the first input module 1 specifically can include：11st switching transistor M11；Wherein,

The grid of described 11st switching transistor M11 is connected with described first input signal end Input1, source electrode and institute State the first direct current signal end VG1 to be connected, drain electrode is connected with described first pull-up node PU1.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 11st switching transistor M11 can be N-type Switching transistor；Or, when the effective impulse signal of the first input signal end Input1 is electronegative potential, as shown in Figure 2 b, the 11 switching transistors M11 can be p-type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, the 11st switch When transistor is in the conduction state under the control at the first input signal end, the signal at the first direct current signal end is supplied to first Pull-up node.

The above is only the concrete structure illustrating the first input module in shift register cell, in the specific implementation, The concrete structure of the first input module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the first reseting module 3 specifically can include：Twelvemo closes transistor M12；Wherein,

The grid that described twelvemo closes transistor M12 is connected with described first reset signal end Reset1, source electrode and institute State the second direct current signal end VG2 to be connected, drain electrode is connected with described first pull-up node PU1.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first reset When the effective impulse signal of signal end Reset1 is high potential, as shown in Figure 2 a, twelvemo closes transistor M12 can be N-type Switching transistor；Or, when the effective impulse signal of the first reset signal end Reset1 is electronegative potential, as shown in Figure 2 b, the It can also be p-type switching transistor that twelvemo closes transistor M12, be not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when twelvemo Close transistor in the conduction state under the control at the first reset signal end when, the signal at the second direct current signal end is supplied to the One pull-up node.

The above is only the concrete structure illustrating the first reseting module in shift register cell, in the specific implementation, The concrete structure of the first reseting module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the second input module 2 specifically can include：13rd switching transistor M13；Wherein,

The grid of described 13rd switching transistor M13 is connected with described second input signal end Input2, source electrode and institute State the first direct current signal end Ref to be connected, drain electrode is connected with described second pull-up node PU2.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 13rd switching transistor M13 can be N-type Switching transistor；Or, when the effective impulse signal of the first input signal end Input1 is electronegative potential, as shown in Figure 2 b, the 13 switching transistors M13 can also be p-type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, the 13rd switch When transistor is in the conduction state under the control at the second input signal end, the signal at the first direct current signal end is supplied to second Pull-up node.

The above is only the concrete structure illustrating the second input module in shift register cell, in the specific implementation, The concrete structure of the second input module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the second reseting module 4 specifically can include：14th switching transistor M14；Wherein,

The grid of described 14th switching transistor M14 is connected with described second reset signal end Reset2, source electrode and institute State the second direct current signal end VG2 to be connected, drain electrode is connected with described second pull-up node PU2.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the second reset When the effective impulse signal of signal end Reset2 is high potential, as shown in Figure 2 a, the 14th switching transistor M14 can be N-type Switching transistor；Or, when the second reset signal end Reset2 is electronegative potential, as shown in Figure 2 b, the 14th switching transistor M14 can also be p-type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 14th opens Close transistor in the conduction state under the control at the second reset signal end when, the signal at the second direct current signal end is supplied to the Two pull-up nodes.

The above is only the concrete structure illustrating the second reseting module in shift register cell, in the specific implementation, The concrete structure of the second reseting module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the first output module 6 specifically can include：15th switching transistor M15, sixteenmo close transistor M16, 17th switching transistor M17, eighteenmo close transistor M18 and the first electric capacity C1；Wherein,

The grid of described 15th switching transistor M15 is connected with described first pull-up node PU1, source electrode and described first Clock signal terminal CK1 is connected, and drain electrode is connected with described first drive signal outfan Output1；

The grid that described sixteenmo closes transistor M16 is connected with described first pull-down node PD1, source electrode and described reference Signal end Ref is connected, and drain electrode is connected with described first drive signal outfan Output1；

The grid of described 17th switching transistor M17 is connected with described second pull-down node PD2, source electrode and described reference Signal end Ref is connected, and drain electrode is connected with described first drive signal outfan Output1；

The grid that eighteenmo closes transistor M18 is connected with second clock signal end CK2, source electrode and reference signal end Ref It is connected, drain electrode is connected with the first drive signal outfan Output1；

The first end of described first electric capacity C1 is connected with described first pull-up node PU1, and the second end drives with described first Signal output part Output1 is connected.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 15th switching transistor M15, sixteenmo Closing transistor M16, the 17th switching transistor M17 and eighteenmo and close transistor M18 can be N-type switching transistor；Or Person, when the effective impulse signal of the first input signal end Input1 is electronegative potential, as shown in Figure 2 b, the 15th switching transistor M15, sixteenmo close transistor M16, the 17th switching transistor M17 and eighteenmo and close transistor M18 can also be p-type Switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 15th opens When pass transistor is in the conduction state under the control of the first pull-up node, the signal of the first clock signal terminal is supplied to first Drive signal outfan；When sixteenmo pass transistor is in the conduction state under the control of the first pull-down node, by reference The signal of signal end is supplied to the first drive signal outfan；When the 17th switching transistor is under the control of the second pull-down node When in the conduction state, the signal at reference signal end is supplied to the first drive signal outfan；When eighteenmo closes transistor Under the control of second clock signal end in the conduction state when, the signal at reference signal end is supplied to the first drive signal defeated Go out end；When the first pull-up node is in floating, due to the boot strap of the first electric capacity, the voltage at its two ends can be kept Difference is stable, and that is, the voltage difference between the first pull-up node and the first drive signal outfan is stable.

The above is only the concrete structure illustrating the first output module in shift register cell, in the specific implementation, The concrete structure of the first output module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Specifically, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, such as scheme Shown in 2a and 2b, the second output module 7 specifically can include：19th switching transistor M19, the 20th switching transistor M20, 21st switching transistor M21, the second twelvemo close transistor M22 and the second electric capacity C2；Wherein,

The grid of described 19th switching transistor M19 is connected with described second pull-up node PU2, source electrode and described second Clock signal terminal CK2 is connected, and drain electrode is connected with described second drive signal outfan Output2；

The grid of described 20th switching transistor M20 is connected with described second pull-down node PD2, source electrode and described reference Signal end Ref is connected, and drain electrode is connected with described second drive signal outfan Output2；

The grid of described 21st switching transistor M21 is connected with described first pull-down node PD1, source electrode and described ginseng Examine signal end Ref to be connected, drain electrode is connected with described second drive signal outfan Output2；

The grid that second twelvemo closes transistor M22 is connected with the first clock signal terminal CK1, source electrode and described reference signal End Ref is connected, and drain electrode is connected with described second drive signal outfan Output2；

The first end of described second electric capacity C2 is connected with described second pull-up node PU2, and the second end drives with described second Signal output part Output2 is connected.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the first input When the effective impulse signal of signal end Input1 is high potential, as shown in Figure 2 a, the 19th switching transistor M19, the 20th open It can be N-type switching transistor that pass transistor M20, the 21st switching transistor M21, the second twelvemo close transistor M22；Or Person, when the effective impulse signal of the first input signal end Input1 is electronegative potential, as shown in Figure 2 b, the 19th switching transistor It can also be P that M19, the 20th switching transistor M20, the 21st switching transistor M21, the second twelvemo close transistor M22 Type switching transistor, is not limited thereto.

In the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, when the 19th opens When pass transistor is in the conduction state under the control of the second pull-up node, the signal of second clock signal end is supplied to second Drive signal outfan；When the 20th switching transistor is in the conduction state under the control of the second pull-down node, by reference The signal of signal end is supplied to the second drive signal outfan；When the 21st switching transistor is in the control of the first pull-down node Under in the conduction state when, the signal at reference signal end is supplied to the second drive signal outfan；When the second twelvemo closes crystalline substance When body pipe is in the conduction state under the control of the first clock signal terminal, the signal at reference signal end is supplied to the second driving letter Number outfan；When the second pull-up node is in floating, due to the boot strap of the second electric capacity, its two ends can be kept Voltage difference is stable, that is, keep the voltage difference between the second pull-up node and the second drive signal outfan to be in steady statue.

The above is only the concrete structure illustrating the second output module in shift register cell, in the specific implementation, The concrete structure of the second output module is not limited to the said structure of this utility model embodiment offer, can also be art technology Other structures knowable to personnel, here does not limit.

Further, in order to reduce the quantity of holding wire, in the specific implementation, upper in the offer of this utility model embodiment State in shift register cell, the first reset signal end is connected with described second drive signal outfan.

Or, in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, described the Two input signal ends are connected with described first drive signal outfan.

It is preferred that in the specific implementation, in the above-mentioned shift register cell that this utility model embodiment provides, first Reset signal end is connected with described second drive signal outfan；And described second input signal end and described first drive signal Outfan is connected.

It is preferred that in the above-mentioned shift register cell that this utility model embodiment provides, switching transistor is generally individually Using the transistor of phase same material, in the specific implementation, when the effective impulse signal of input signal is high potential, as Fig. 2 a institute Show, all switching transistors are N-type transistor；When the effective impulse signal of input signal is electronegative potential, as shown in Figure 2 b, All switching transistors are P-type transistor.

Further, in the specific implementation, N-type switching transistor turns under high potential effect, under electronegative potential effect Cut-off；P-type switching transistor is ended under high potential effect, turns under electronegative potential effect.

It should be noted that the switching transistor mentioned in this utility model above-described embodiment can be thin film transistor (TFT) (TFT, Thin Film Transistor) or metal oxide semiconductor field effect tube (MOS, Metal Oxide Scmiconductor), it is not limited thereto.In being embodied as, the source electrode of these switching transistors and drain electrode can be according to opening Close the type of transistor and the difference of input signal, its function can be exchanged, here does not do concrete differentiation.

Further, because, in the above-mentioned shift register cell that this utility model embodiment provides, first inputs mould Block and the first reseting module are symmetric design, and the second input module and the second reseting module are symmetric design, it is possible to achieve function Exchange, the above-mentioned shift register cell that therefore this utility model embodiment provides can realize bilateral scanning.In reverse scan When, the first input module of shift register cell and the function of the second reseting module are interchangeable, by the first reseting module Be interchangeable with the function of the second input module, that is, with respect to forward scan, the second reseting module as the first input module, Two reset signal ends are as the first input signal；Second input module is as the first reseting module, the second input signal end conduct First reset signal end；, as the second input module, the second reset signal end is as the second input signal end for first reseting module； , as the second reseting module, the first input signal end is as the second reset signal end for first input module.When the second reset signal When the effective impulse signal at end is high potential, the current potential at the first direct current signal end is electronegative potential, the current potential at the second direct current signal end For high potential, the current potential at reference signal end is electronegative potential；When the effective impulse signal at the second reset signal end is electronegative potential, the The current potential of one direct current signal end is high potential, and the current potential at the second direct current signal end is electronegative potential, and the current potential of the first reference signal is High potential.

Combined circuit sequential chart separately below, the above-mentioned displacement taking forward scan as a example this utility model embodiment being provided The work process of register cell is described.High potential signal is represented with 1 in described below, 0 expression low-potential signal, its In, 1 and 0 represents its logic level, merely to preferably explaining the above-mentioned shift register that this utility model embodiment provides The work process of unit, rather than it is applied to the concrete current potential on the grid of each switching transistor in the specific implementation.

Embodiment one

As a example the structure of the shift register cell shown in by Fig. 2 a, its work process is described, wherein in Fig. 2 a institute In the shift register cell showing, all switching transistors are N-type switching transistor；The current potential of the first direct current signal end VG1 For high potential, the current potential of the second direct current signal end VG2 is electronegative potential；The current potential of reference signal end Ref is electronegative potential；Corresponding defeated Enter output timing diagram as shown in Figure 3 a.Specifically, choose first stage T1 in input and output sequential chart as shown in Figure 3 a, the Two-stage T2, phase III T3, fourth stage T4, the 5th stage T5 and six stages of the 6th stage T6.

T1 in the first stage, Input1=1, Input2=0, Reset1=0, Reset2=0, CK1=0, CK2=1.

Due to Input1=1, the therefore the 11st switching transistor M11 conducting；Due to Reset1=0, therefore twelvemo Close transistor M12 cut-off；Due to Input2=0, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=0, therefore 14th switching transistor M14 cut-off.Due to the 11st switching transistor M11 conducting the letter by the first direct current signal end VG1 Number it is supplied to the first pull-up node PU1, the current potential of the therefore first pull-up node PU1 is high potential.Due to the first pull-up node PU1 Current potential be high potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are equal Conducting.It is supplied to the first pull-down node PD1 due to the 6th switching transistor M6 conducting and by the signal of reference signal end Ref, because The current potential of this first pull-down node PD1 is electronegative potential；Current potential due to the first pull-down node PD1 is electronegative potential, and therefore first opens Close transistor M1, the 4th switching transistor M4, sixteenmo closes transistor M16 and the 21st switching transistor M21 is all cut Only.It is supplied to the second pull-down node PD2 due to the 9th switching transistor M9 conducting and by the signal of reference signal end Ref, therefore The current potential of the second pull-down node PD2 is electronegative potential；Because the current potential of the second pull-down node PD2 is electronegative potential, therefore second switch Transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 are turned off.By It is supplied to the first drive signal in the 15th switching transistor M15 conducting and by the low-potential signal of the first clock signal terminal CK1 Outfan Output1, the first electric capacity C1 charges, and the therefore first drive signal outfan Output1 exports the signal of electronegative potential, by In CK2=1, therefore eighteenmo closes transistor M18 conducting and the signal of the electronegative potential of reference signal end Ref is supplied to first Drive signal outfan Output1, makes the first drive signal outfan Output1 export the signal of electronegative potential further.

In second stage T2, Input1=0, Input2=1, Reset1=0, Reset2=0, CK1=1, CK2=0.

Due to Input1=0, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=0, therefore twelvemo Close transistor M12 cut-off；Due to Input2=1, the therefore the 13rd switching transistor M13 conducting；Due to Reset2=0, therefore 14th switching transistor M14 cut-off.Close transistor M12 due to the 11st switching transistor M11 and twelvemo to be turned off, because This first pull-up node PU1 is in floating, due to the effect of the first electric capacity C1, keeps the current potential of the first pull-up node PU1 For high potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are both turned on. It is supplied to the first driving letter due to the 15th switching transistor M15 conducting and by the high potential signal of the first clock signal terminal CK1 Number outfan Output1, the therefore first drive signal outfan Output1 exports the signal of high potential.Due to the first electric capacity C1 Boot strap the voltage difference between the first pull-up node PU1 and the first drive signal outfan Output1 can be maintained to be in Steady statue, the current potential of the therefore first pull-up node PU1 is further pulled up, can make further the 6th switching transistor M6, 9th switching transistor M9 and the conducting of the 15th switching transistor M15.Due to the 6th switching transistor M6 conducting and by reference The signal of signal end Ref is supplied to the first pull-down node PD1, and the current potential of the therefore first pull-down node PD1 is electronegative potential；Due to The signal of reference signal end Ref is simultaneously supplied to the second pull-down node PD2, the therefore second drop-down section by nine switching transistor M9 conductings The current potential of point PD2 is electronegative potential.Carry due to the 13rd switching transistor M13 conducting and by the signal of the first direct current signal end VG1 Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is high potential.Electricity due to the second pull-up node PU2 Position is high potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all led Logical.It is supplied to the second driving due to the 19th switching transistor M19 conducting and by the low-potential signal of second clock signal end CK2 Signal output part Output2, the second electric capacity C2 charges, and the therefore second drive signal outfan Output2 exports the letter of electronegative potential Number.Due to CK1=1, the therefore second twelvemo is closed transistor M22 conducting and is carried the signal of the electronegative potential of reference signal end Ref Supply the second drive signal outfan Output2, make the second drive signal outfan Output2 export the letter of electronegative potential further Number.It is supplied to the first pull-down node PD1 due to the 7th switching transistor M7 conducting and by the signal of reference signal end Ref, therefore The current potential making the first pull-down node PD1 further is electronegative potential；Due to the tenth switching transistor M10 conducting and by reference signal end The signal of Ref is supplied to the second pull-down node PD2, and the current potential therefore making the second pull-down node PD2 further is electronegative potential.Due to The current potential of the first pull-down node PD1 is electronegative potential, therefore first switch transistor M1, the 4th switching transistor M4, sixteenmo Close transistor M16 and the 21st switching transistor M21 is turned off；Because the current potential of the second pull-down node PD2 is electronegative potential, Therefore second switch transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 is turned off.

In phase III T3, Input1=0, Input2=0, Reset1=1, Reset2=0, CK1=0, CK2=1.

Due to Input1=0, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=1, therefore twelvemo Close transistor M12 conducting；Due to Input2=0, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=0, therefore 14th switching transistor M14 cut-off.Because twelvemo closes transistor M12 conducting the letter by the second direct current signal end VG1 Number it is supplied to the first pull-up node PU1, the current potential of the therefore first pull-up node PU1 is electronegative potential.Due to the first pull-up node PU1 Current potential be electronegative potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are equal Cut-off.Due to CK2=1, therefore eighteenmo closes transistor M18 conducting and provides the low-potential signal of reference signal end Ref To the first drive signal outfan Output1, the therefore first drive signal outfan Output1 exports the signal of electronegative potential.By It is turned off in the 13rd switching transistor M13 and the 14th switching transistor M14, the therefore second pull-up node PU2 is in suspension joint State, due to the effect of the second electric capacity C2, the current potential keeping the second pull-up node PU2 is high potential, the therefore the 7th switch crystal Pipe M7, the tenth switching transistor M10 and the 19th switching transistor M19 are both turned on.Because the 19th switching transistor M19 is led Logical and the signal of the high potential of second clock signal end CK2 is supplied to the second drive signal outfan Output2, therefore second Drive signal outfan Output2 exports the signal of high potential.Boot strap due to the second electric capacity C2 can maintain on second The voltage difference between node PU2 and the second drive signal outfan Output2 is drawn to be in steady statue, the therefore second pull-up node The current potential of PU2 is further pulled up, and can make the 7th switching transistor M7, the tenth switching transistor M10 and the tenth further Nine switching transistor M19 conductings.It is supplied to first due to the 7th switching transistor M7 conducting and by the signal of reference signal end Ref Pull-down node PD1, the current potential of the therefore first pull-down node PD1 is electronegative potential；Because the current potential of the first pull-down node PD1 is low electricity Position, therefore first switch transistor M1, the 4th switching transistor M4, sixteenmo close transistor M16 and the 21st switch Transistor M21 is turned off.It is supplied under second due to the tenth switching transistor M10 conducting and by the signal of reference signal end Ref Draw node PD2, the current potential of the therefore second pull-down node PD2 is electronegative potential；Because the current potential of the second pull-down node PD2 is low electricity Position, therefore second switch transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switch are brilliant Body pipe M20 is turned off.

In fourth stage T4, Input1=0, Input2=0, Reset1=0, Reset2=1, CK1=1, CK2=0.

Due to Input1=0, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=0, therefore twelvemo Close transistor M12 cut-off；Due to Input2=0, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=1, therefore 14th switching transistor M14 conducting.Carry due to the 14th switching transistor M14 conducting and by the signal of reference signal end Ref Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is electronegative potential；Electricity due to the second pull-up node PU2 Position is electronegative potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all cut Only.Due to CK1=1, the therefore the 5th switching transistor M5 and the second twelvemo are closed transistor and are both turned on；Due to the 5th switch crystal Pipe M5 turns on and the signal of the first clock signal terminal CK1 is supplied to the first pull-down node PD1, the therefore first pull-down node PD1 Current potential be high potential；Because the current potential of the first pull-down node PD1 is high potential, therefore first switch transistor M1, the 4th open Close transistor M4, sixteenmo closes transistor M16 and the 21st switching transistor M21 is both turned on.Because first switch is brilliant Body pipe M1 turns on and the signal of reference signal end Ref is supplied to the first pull-up node PU1, the therefore first pull-up node PU1 Current potential is electronegative potential, and the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are all cut Only.It is supplied to the first drive signal due to the transistor M16 conducting of sixteenmo pass and by the low-potential signal of reference signal end Ref Outfan Output1, the therefore first drive signal outfan Output1 exports the signal of electronegative potential.Due to the 4th switch crystal Pipe M4 turns on and the signal of reference signal end Ref is supplied to the second pull-up node PU2, is further ensured that the second pull-up node The current potential of PU2 is electronegative potential, the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 is turned off.It is supplied to the due to the 21st switching transistor M21 conducting and by the low-potential signal of reference signal end Ref Two driving signal outfan Output2, the therefore second drive signal outfan Output2 exports the signal of electronegative potential.Due to Two twelvemos are closed transistor M22 conducting and the low-potential signal of reference signal end Ref are supplied to the second drive signal outfan Output2, is further ensured that the second drive signal outfan Output2 exports the signal of electronegative potential.

In the 5th stage T5, Input1=0, Input2=0, Reset1=0, Reset2=0, CK1=0, CK2=1.

Due to Input1=0, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=0, therefore twelvemo Close transistor M12 cut-off；Due to Input2=0, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=0, therefore 14th switching transistor M14 cut-off.Due to CK2=1, the therefore the 8th switching transistor M8 and eighteenmo close transistor M18 It is both turned on；It is supplied to the second pull-down node PD2 due to the 8th switching transistor M8 conducting and by the signal of second clock signal end, The current potential of the therefore second pull-down node PD2 is high potential；Because the current potential of the second pull-down node PD2 is high potential, therefore second Switching transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 are all led Logical.It is supplied to the first pull-up node PU1 due to second switch transistor M2 conducting and by the signal of reference signal end Ref, therefore The current potential of the first pull-up node PU1 is electronegative potential；Because the current potential of the first pull-up node PU1 is electronegative potential, the therefore the 6th switch Transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are turned off.Due to the 17th switching transistor The low-potential signal of reference signal end Ref is simultaneously supplied to the first drive signal outfan Output1 by M17 conducting, and therefore first Drive signal outfan Output1 exports the signal of electronegative potential.Because eighteenmo closes transistor M18 conducting and by reference signal The low-potential signal of end Ref is supplied to the first drive signal outfan Output1, may further ensure that the first drive signal is defeated Go out to hold Output1 to export the signal of electronegative potential.Carry due to the 3rd switching transistor M3 conducting and by the signal of reference signal end Ref Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is electronegative potential；Electricity due to the second pull-up node PU2 Position is electronegative potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all cut Only；It is supplied to the second drive signal due to the 20th switching transistor M20 conducting and by the low-potential signal of reference signal end Ref Outfan Output2, the therefore second drive signal outfan Output2 exports the signal of electronegative potential.

In the 6th stage T6, Input1=0, Input2=0, Reset1=0, Reset2=0, CK1=1, CK2=0.

Due to Input1=0, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=0, therefore twelvemo Close transistor M12 cut-off；Due to Input2=0, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=0, therefore 14th switching transistor M14 cut-off.Due to CK1=1, the therefore the 5th switching transistor M5 and the second twelvemo close transistor M22 is both turned on；It is supplied to the first pull-down node due to the 5th switching transistor M5 conducting and by the signal of the first clock signal terminal PD1, the current potential of the therefore first pull-down node PD1 is high potential；Because the current potential of the first pull-down node PD1 is high potential, therefore First switch transistor M1, the 4th switching transistor M4, sixteenmo close transistor M16 and the 21st switching transistor M21 is both turned on.It is supplied to the first pull-up node due to first switch transistor M1 conducting and by the signal of reference signal end Ref PU1, the current potential of the therefore first pull-up node PU1 is electronegative potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 with And the 15th switching transistor M15 be turned off.Turn on and reference signal end Ref is low because sixteenmo closes transistor M16 Electric potential signal is supplied to the first drive signal outfan Output1, and the therefore first drive signal outfan Output1 exports low electricity The signal of position.It is supplied to the second pull-up node due to the 4th switching transistor M4 conducting and by the signal of reference signal end Ref PU2, the current potential of the therefore second pull-up node PU2 is electronegative potential, the therefore the 7th switching transistor M7, the tenth switching transistor M10 And the 19th switching transistor M19 be turned off.Due to the 21st switching transistor M21 conducting and by reference signal end Ref Low-potential signal be supplied to the second drive signal outfan Output2, the therefore second drive signal outfan Output2 output The signal of electronegative potential.It is supplied to due to the second twelvemo pass transistor M22 conducting and by the low-potential signal of reference signal end Ref Second drive signal outfan Output2, is further ensured that the second drive signal outfan Output2 exports the letter of electronegative potential Number.

In the above-mentioned shift register cell that this utility model embodiment provides, after the 6th stage T6, weigh always Execute the work process of the 5th stage T5 and the 6th stage T6 again, until the current potential of the first input signal end Input1 is changed into again High potential.

Embodiment two

As a example the structure of the shift register cell shown in by Fig. 2 b, its work process is described, wherein in Fig. 2 b institute In the shift register cell showing, all switching transistors are p-type switching transistor；The current potential of the first direct current signal end VG1 For electronegative potential, the current potential of the second direct current signal end VG2 is high potential；The current potential of reference signal end Ref is high potential；Corresponding defeated Enter output timing diagram as shown in Figure 3 b.Specifically, choose first stage T1 in input and output sequential chart as shown in Figure 3 b, the Two-stage T2, phase III T3, fourth stage T4, the 5th stage T5 and six stages of the 6th stage T6.

T1 in the first stage, Input1=0, Input2=1, Reset1=1, Reset2=1, CK1=1, CK2=0.

Due to Input1=0, the therefore the 11st switching transistor M11 conducting；Due to Reset1=1, therefore twelvemo Close transistor M12 cut-off；Due to Input2=1, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=1, therefore 14th switching transistor M14 cut-off.Due to the 11st switching transistor M11 conducting the letter by the first direct current signal end VG1 Number it is supplied to the first pull-up node PU1, the current potential of the therefore first pull-up node PU1 is electronegative potential.Due to the first pull-up node PU1 Current potential be electronegative potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are equal Conducting.It is supplied to the first pull-down node PD1 due to the 6th switching transistor M6 conducting and by the signal of reference signal end Ref, because The current potential of this first pull-down node PD1 is high potential；Current potential due to the first pull-down node PD1 is high potential, and therefore first opens Close transistor M1, the 4th switching transistor M4, sixteenmo closes transistor M16 and the 21st switching transistor M21 is all cut Only.It is supplied to the second pull-down node PD2 due to the 9th switching transistor M9 conducting and by the signal of reference signal end Ref, therefore The current potential of the second pull-down node PD2 is high potential；Because the current potential of the second pull-down node PD2 is high potential, therefore second switch Transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 are turned off.By It is supplied to the first drive signal in the 15th switching transistor M15 conducting and by the high potential signal of the first clock signal terminal CK1 Outfan Output1, the first electric capacity C1 charges, and the therefore first drive signal outfan Output1 exports the signal of high potential, by In CK2=0, therefore eighteenmo closes transistor M18 conducting and the signal of the high potential of reference signal end Ref is supplied to first Drive signal outfan Output1, makes the first drive signal outfan Output1 export the signal of high potential further.

In second stage T2, Input1=1, Input2=0, Reset1=1, Reset2=1, CK1=0, CK2=1.

Due to Input1=1, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=1, therefore twelvemo Close transistor M12 cut-off；Due to Input2=0, the therefore the 13rd switching transistor M13 conducting；Due to Reset2=1, therefore 14th switching transistor M14 cut-off.Close transistor M12 due to the 11st switching transistor M11 and twelvemo to be turned off, because This first pull-up node PU1 is in floating, due to the effect of the first electric capacity C1, keeps the current potential of the first pull-up node PU1 For electronegative potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are both turned on. It is supplied to the first driving letter due to the 15th switching transistor M15 conducting and by the low-potential signal of the first clock signal terminal CK1 Number outfan Output1, the therefore first drive signal outfan Output1 exports the signal of electronegative potential.Due to the first electric capacity C1 Boot strap the voltage difference between the first pull-up node PU1 and the first drive signal outfan Output1 can be maintained to be in Steady statue, the current potential of the therefore first pull-up node PU1 is dragged down further, can make further the 6th switching transistor M6, 9th switching transistor M9 and the conducting of the 15th switching transistor M15.Due to the 6th switching transistor M6 conducting and by reference The signal of signal end Ref is supplied to the first pull-down node PD1, and the current potential of the therefore first pull-down node PD1 is high potential；Due to The signal of reference signal end Ref is simultaneously supplied to the second pull-down node PD2, the therefore second drop-down section by nine switching transistor M9 conductings The current potential of point PD2 is high potential.Carry due to the 13rd switching transistor M13 conducting and by the signal of the first direct current signal end VG1 Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is electronegative potential.Electricity due to the second pull-up node PU2 Position is electronegative potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all led Logical.It is supplied to the second driving due to the 19th switching transistor M19 conducting and by the high potential signal of second clock signal end CK2 Signal output part Output2, the second electric capacity C2 charges, and the therefore second drive signal outfan Output2 exports the letter of high potential Number.Due to CK1=0, the therefore second twelvemo is closed transistor M22 conducting and is carried the signal of the high potential of reference signal end Ref Supply the second drive signal outfan Output2, make the second drive signal outfan Output2 export the letter of high potential further Number.It is supplied to the first pull-down node PD1 due to the 7th switching transistor M7 conducting and by the signal of reference signal end Ref, therefore The current potential making the first pull-down node PD1 further is high potential；Due to the tenth switching transistor M10 conducting and by reference signal end The signal of Ref is supplied to the second pull-down node PD2, and the current potential therefore making the second pull-down node PD2 further is high potential.Due to The current potential of the first pull-down node PD1 is high potential, therefore first switch transistor M1, the 4th switching transistor M4, sixteenmo Close transistor M16 and the 21st switching transistor M21 is turned off；Because the current potential of the second pull-down node PD2 is high potential, Therefore second switch transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 is turned off.

In phase III T3, Input1=1, Input2=1, Reset1=0, Reset2=1, CK1=1, CK2=0.

Due to Input1=1, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=0, therefore twelvemo Close transistor M12 conducting；Due to Input2=1, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=1, therefore 14th switching transistor M14 cut-off.Because twelvemo closes transistor M12 conducting the letter by the second direct current signal end VG1 Number it is supplied to the first pull-up node PU1, the current potential of the therefore first pull-up node PU1 is high potential.Due to the first pull-up node PU1 Current potential be high potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are equal Cut-off.Due to CK2=0, therefore eighteenmo closes transistor M18 conducting and provides the high potential signal of reference signal end Ref To the first drive signal outfan Output1, the therefore first drive signal outfan Output1 exports the signal of high potential.By It is turned off in the 13rd switching transistor M13 and the 14th switching transistor M14, the therefore second pull-up node PU2 is in suspension joint State, due to the effect of the second electric capacity C2, the current potential keeping the second pull-up node PU2 is electronegative potential, the therefore the 7th switch crystal Pipe M7, the tenth switching transistor M10 and the 19th switching transistor M19 are both turned on.Because the 19th switching transistor M19 is led Logical and the signal of the electronegative potential of second clock signal end CK2 is supplied to the second drive signal outfan Output2, therefore second Drive signal outfan Output2 exports the signal of electronegative potential.Boot strap due to the second electric capacity C2 can maintain on second The voltage difference between node PU2 and the second drive signal outfan Output2 is drawn to be in steady statue, the therefore second pull-up node The current potential of PU2 is dragged down further, can make the 7th switching transistor M7, the tenth switching transistor M10 and the tenth further Nine switching transistor M19 conductings.It is supplied to first due to the 7th switching transistor M7 conducting and by the signal of reference signal end Ref Pull-down node PD1, the current potential of the therefore first pull-down node PD1 is high potential；Because the current potential of the first pull-down node PD1 is high electricity Position, therefore first switch transistor M1, the 4th switching transistor M4, sixteenmo close transistor M16 and the 21st switch Transistor M21 is turned off.It is supplied under second due to the tenth switching transistor M10 conducting and by the signal of reference signal end Ref Draw node PD2, the current potential of the therefore second pull-down node PD2 is high potential；Because the current potential of the second pull-down node PD2 is high electricity Position, therefore second switch transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switch are brilliant Body pipe M20 is turned off.

In fourth stage T4, Input1=1, Input2=1, Reset1=1, Reset2=0, CK1=0, CK2=1.

Due to Input1=1, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=1, therefore twelvemo Close transistor M12 cut-off；Due to Input2=1, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=0, therefore 14th switching transistor M14 conducting.Carry due to the 14th switching transistor M14 conducting and by the signal of reference signal end Ref Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is high potential；Electricity due to the second pull-up node PU2 Position is high potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all cut Only.Due to CK1=0, the therefore the 5th switching transistor M5 and the second twelvemo are closed transistor and are both turned on；Due to the 5th switch crystal Pipe M5 turns on and the signal of the first clock signal terminal CK1 is supplied to the first pull-down node PD1, the therefore first pull-down node PD1 Current potential be electronegative potential；Because the current potential of the first pull-down node PD1 is electronegative potential, therefore first switch transistor M1, the 4th open Close transistor M4, sixteenmo closes transistor M16 and the 21st switching transistor M21 is both turned on.Because first switch is brilliant Body pipe M1 turns on and the signal of reference signal end Ref is supplied to the first pull-up node PU1, the therefore first pull-up node PU1 Current potential is high potential, and the therefore the 6th switching transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are all cut Only.It is supplied to the first drive signal due to the transistor M16 conducting of sixteenmo pass and by the high potential signal of reference signal end Ref Outfan Output1, the therefore first drive signal outfan Output1 exports the signal of high potential.Due to the 4th switch crystal Pipe M4 turns on and the signal of reference signal end Ref is supplied to the second pull-up node PU2, is further ensured that the second pull-up node The current potential of PU2 is high potential, the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 is turned off.It is supplied to the due to the 21st switching transistor M21 conducting and by the high potential signal of reference signal end Ref Two driving signal outfan Output2, the therefore second drive signal outfan Output2 exports the signal of high potential.Due to Two twelvemos are closed transistor M22 conducting and the high potential signal of reference signal end Ref are supplied to the second drive signal outfan Output2, is further ensured that the second drive signal outfan Output2 exports the signal of high potential.

In the 5th stage T5, Input1=1, Input2=1, Reset1=1, Reset2=1, CK1=1, CK2=0.

Due to Input1=1, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=1, therefore twelvemo Close transistor M12 cut-off；Due to Input2=1, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=1, therefore 14th switching transistor M14 cut-off.Due to CK2=0, the therefore the 8th switching transistor M8 and eighteenmo close transistor M18 It is both turned on；It is supplied to the second pull-down node PD2 due to the 8th switching transistor M8 conducting and by the signal of second clock signal end, The current potential of the therefore second pull-down node PD2 is electronegative potential；Because the current potential of the second pull-down node PD2 is electronegative potential, therefore second Switching transistor M2, the 3rd switching transistor M3, the 17th switching transistor M17 and the 20th switching transistor M20 are all led Logical.It is supplied to the first pull-up node PU1 due to second switch transistor M2 conducting and by the signal of reference signal end Ref, therefore The current potential of the first pull-up node PU1 is high potential；Because the current potential of the first pull-up node PU1 is high potential, the therefore the 6th switch Transistor M6, the 9th switching transistor M9 and the 15th switching transistor M15 are turned off.Due to the 17th switching transistor The high potential signal of reference signal end Ref is simultaneously supplied to the first drive signal outfan Output1 by M17 conducting, and therefore first Drive signal outfan Output1 exports the signal of high potential.Because eighteenmo closes transistor M18 conducting and by reference signal The high potential signal of end Ref is supplied to the first drive signal outfan Output1, may further ensure that the first drive signal is defeated Go out to hold Output1 to export the signal of high potential.Carry due to the 3rd switching transistor M3 conducting and by the signal of reference signal end Ref Supply the second pull-up node PU2, the current potential of the therefore second pull-up node PU2 is high potential；Electricity due to the second pull-up node PU2 Position is high potential, and the therefore the 7th switching transistor M7, the tenth switching transistor M10 and the 19th switching transistor M19 are all cut Only；It is supplied to the second drive signal due to the 20th switching transistor M20 conducting and by the high potential signal of reference signal end Ref Outfan Output2, the therefore second drive signal outfan Output2 exports the signal of high potential.

In the 6th stage T6, Input1=1, Input2=1, Reset1=1, Reset2=1, CK1=0, CK2=1.

Due to Input1=1, the therefore the 11st switching transistor M11 cut-off；Due to Reset1=1, therefore twelvemo Close transistor M12 cut-off；Due to Input2=1, the therefore the 13rd switching transistor M13 cut-off；Due to Reset2=1, therefore 14th switching transistor M14 cut-off.Due to CK1=0, the therefore the 5th switching transistor M5 and the second twelvemo close transistor M22 is both turned on；It is supplied to the first pull-down node due to the 5th switching transistor M5 conducting and by the signal of the first clock signal terminal PD1, the current potential of the therefore first pull-down node PD1 is electronegative potential；Because the current potential of the first pull-down node PD1 is electronegative potential, therefore First switch transistor M1, the 4th switching transistor M4, sixteenmo close transistor M16 and the 21st switching transistor M21 is both turned on.It is supplied to the first pull-up node due to first switch transistor M1 conducting and by the signal of reference signal end Ref PU1, the current potential of the therefore first pull-up node PU1 is high potential, the therefore the 6th switching transistor M6, the 9th switching transistor M9 with And the 15th switching transistor M15 be turned off.Because sixteenmo closes transistor M16 conducting the height by reference signal end Ref Electric potential signal is supplied to the first drive signal outfan Output1, the high electricity of the therefore first drive signal outfan Output1 output The signal of position.It is supplied to the second pull-up node due to the 4th switching transistor M4 conducting and by the signal of reference signal end Ref PU2, the current potential of the therefore second pull-up node PU2 is high potential, the therefore the 7th switching transistor M7, the tenth switching transistor M10 And the 19th switching transistor M19 be turned off.Due to the 21st switching transistor M21 conducting and by reference signal end Ref High potential signal be supplied to the second drive signal outfan Output2, the therefore second drive signal outfan Output2 output The signal of high potential.It is supplied to due to the second twelvemo pass transistor M22 conducting and by the high potential signal of reference signal end Ref Second drive signal outfan Output2, is further ensured that the second drive signal outfan Output2 exports the letter of high potential Number.

In the above-mentioned shift register cell that this utility model embodiment provides, after the 6th stage T6, weigh always Execute the work process of the 5th stage T5 and the 6th stage T6 again, until the current potential of the first input signal end Input1 is changed into again Electronegative potential.

The above-mentioned shift register list that this utility model embodiment provides is can be seen that from embodiment one and embodiment two Unit, by public first pull-down node and the second pull-down node, can make the output of each shift register cell have a phase bit Two scanning signals of difference, and reduce the quantity of switching transistor, it is simple with existing two shift register structure compared, And taking up room of gate driver circuit can be reduced, more suitable for narrow frame design.

As can be seen that the sequential of the signal of the first drive signal outfan output meets from embodiment one and embodiment two The timing requirements of the signal at the second input signal end, the sequential of the signal of the second drive signal outfan output meets the first reset The timing requirements of the signal of signal end, therefore, it can the first drive signal outfan is connected with the second input signal end and think Second input signal end provide signal, and the second drive signal outfan is connected with the first reset signal end think first answer Position signal end provides signal, so can reduce the quantity of control signal wire further, simplifies preparation technology.

Based on the design of same utility model, this utility model embodiment provides a kind of the upper of this utility model embodiment offer State the driving method of any one shift register cell, as shown in figure 4, including：：First stage, second stage, the phase III, Fourth stage, the 5th stage and the 6th stage；Wherein,

S401, in the first stage, the first input module is under the control at the first input signal end by the first direct current signal end Signal be supplied to the first pull-up node；Node control module makes the first pull-down node under the control of the first pull-up node respectively Current potential and the second pull-down node current potential contrary with the current potential of the first pull-up node；First output module is in the first pull-up node Control under the signal of the first clock signal terminal is supplied to the first drive signal outfan and in second clock signal end Under control, the signal at reference signal end is supplied to the first drive signal outfan；

S402, in second stage, the first output module keep when the first pull-up node is in floating first pull-up Voltage difference between node and the first drive signal outfan is stable, and by the first clock under the control of the first pull-up node The signal of signal end is supplied to the first drive signal outfan；Second input module is under the control at the second input signal end by The signal of one direct current signal end is supplied to the second pull-up node；Node control module makes under the control of the first pull-up node respectively The current potential of the current potential of the first pull-down node and the second pull-down node is contrary with the current potential of the first pull-up node, and in the second pull-up The current potential of the first pull-down node and the current potential of the current potential of the second pull-down node and the second pull-up node is made respectively under the control of node On the contrary；The signal of second clock signal end is supplied to the second driving letter under the control of the second pull-up node by the second output module Number outfan and under the control of the first clock signal terminal, the signal at reference signal end is supplied to the second drive signal output End；

S403, in the phase III, the first reseting module is under the control at the first reset signal end by the second direct current signal end Signal be supplied to the first pull-up node；First output module is under the control of second clock signal end by the letter at reference signal end Number it is supplied to the first drive signal outfan；Second output module keeps on second when the second pull-up node is in floating Draw voltage difference between node and the second drive signal outfan stable, and under the control of the second pull-up node by second when The signal of clock signal end is supplied to the second drive signal outfan；Node control module difference under the control of the second pull-up node Make the current potential of the current potential of the first pull-down node and the second pull-down node contrary with the current potential of the second pull-up node；

S404, in fourth stage, the second reseting module is under the control at the second reset signal end by the second direct current signal end Signal be supplied to the second pull-up node；Node control module is under the control of the first clock signal terminal by the first clock signal terminal Signal be supplied to the first pull-down node, and make respectively under the control of the first pull-down node the first pull-up node current potential and The current potential of the second pull-up node is contrary with the current potential of the first pull-down node；First output module is under the control of the first pull-down node The signal at reference signal end is supplied to the first drive signal outfan；Second output module is under the control of the first pull-down node The signal at reference signal end is supplied to the second drive signal outfan and by reference under the control of the first clock signal terminal The signal of signal end is supplied to the second drive signal outfan；

S405, in the 5th stage, node control module is under the control of second clock signal end by second clock signal end Signal be supplied to the second pull-down node, make the current potential and second of the first pull-up node under the control of the second pull-down node respectively The current potential of pull-up node is contrary with the current potential of the second pull-down node；First output module will be joined under the control of the second pull-down node The signal examining signal end is supplied to the first drive signal outfan, and by reference signal under the control of second clock signal end The signal at end is supplied to the first drive signal outfan；Second output module is under the control of the second pull-down node by reference signal The signal at end is supplied to the second drive signal outfan；

S406, in the 6th stage, node control module is under the control of the first clock signal terminal by the first clock signal terminal Signal be supplied to the first pull-down node, make the current potential and second of the first pull-up node under the control of the first pull-down node respectively The current potential of pull-up node is contrary with the current potential of the first pull-down node；First output module will be joined under the control of the first pull-down node The signal examining signal end is supplied to the first drive signal outfan；Second output module will be joined under the control of the first pull-down node The signal examining signal end is supplied to the second drive signal outfan and by reference signal under the control of the first clock signal terminal The signal at end is supplied to the second drive signal outfan.

Based on the design of same utility model, this utility model embodiment provides a kind of gate driver circuit, such as Fig. 5 (Fig. 5 with In each shift register cell, the second reset signal end is connected with the second drive signal outfan, the second input signal end and first As a example drive signal outfan is connected) shown in, including the above-mentioned shift LD of multiple this utility model embodiments offers of cascade Device cell S R (1), SR (2) ... SR (n-1), SR (n), SR (n+1) ... SR (N-1), SR (N) (altogether N number of shift register cell, 1 ≤n≤N)；Wherein,

First input signal end Input1 of first order shift register cell SR (1) is connected with frame trigger end STV；

In addition to first order shift register cell SR (1), the first input of remaining shift register cell SR (n) at different levels Signal end Input1_n the second drive signal outfan Output2_n- with upper level shift register cell SR (n-1) respectively 1 is connected；

In addition to afterbody shift register cell SR (N), the second of remaining shift register cell SR (n) at different levels is multiple Position signal end Reset2_2 the first drive signal outfan Output1_ with next stage shift register cell SR (n+1) respectively N+1 is connected.

Specifically, on the concrete structure of each shift register cell in above-mentioned gate driver circuit and this utility model State shift register cell all same in function and structure, repeat no more in place of repetition.

In the specific implementation, in the above-mentioned gate driver circuit that this utility model provides, as shown in figure 5,2k-1 level The second clock signal end CK2 of the first clock signal terminal CK1 of shift register cell and 2k level shift register cell is equal It is that the first clock end ck1 is connected with same clock end；The second clock signal end CK2 of 2k-1 level shift register cell and First clock signal terminal CK1 of 2k level shift register cell is all that second clock end ck2 is connected with same clock end；Wherein, k It is the positive integer more than 0.

Further, in the specific implementation, in the above-mentioned gate driver circuit that this utility model provides, as shown in figure 5, The reference signal end Ref of shift register cells SR (n) at different levels is all that reference edge ref is connected with same signal end；Displacements at different levels First direct current signal end VG1 of register cell SR (n) is all that the first DC terminal vg1 is connected with same signal end；Displacements at different levels Second direct current signal end VG2 of register cell SR (n) is all that the second DC terminal vg2 is connected with same signal end.

Above-mentioned gate driver circuit, when realizing grid line bilateral scanning, makes the first of each shift register cell to input Module is interchangeable with the function of the second reseting module, and the first reseting module is interchangeable with the function of the second input module, that is, With respect to forward scan, in reverse scan the second reseting module of each shift register cell as the first input module, As the first input signal end, the second input module of each shift register cell is as the first reset at the second reset signal end Module, as the first reset signal end, the first reseting module of each shift register cell is as at the second input signal end Two input modules, the first reset signal end is made as the second input module, the first input module of each shift register cell For the second reseting module, the first input signal end does not change as the second reset signal end, the now annexation of circuit, Simply circuit function there occurs transformation.

Based on the design of same utility model, this utility model embodiment additionally provides a kind of display device, including this practicality The above-mentioned gate driver circuit that new embodiment provides.There is provided for each grid line in display device by this gate driver circuit and sweep Retouch signal, it is embodied as can be found in the description of above-mentioned gate driver circuit, and something in common repeats no more.This display device is permissible For：Mobile phone, panel computer, television set, display, notebook computer, DPF, navigator etc. be any to have display function Product or part.For this display device the requisite ingredient of other be those of ordinary skill in the art should Understanding has, and will not be described here, also should not be used as to restriction of the present utility model.

Shift register cell, gate driver circuit and display device that this utility model embodiment provides, including：First Input module, the second input module, the first reseting module, the second reseting module, node control module, the first output module and Two output modules；Wherein, cooperating by above-mentioned seven modules, can make each displacement by common points control module Register cell output has two scanning signals of certain phase contrast, to correspond to two row grid lines in display floater, to realize The function of existing two shift registers is simple with existing two shift register structure compared, thus reduce grid driving The taking up room, more suitable for narrow frame design of galvanic electricity road.

Obviously, those skilled in the art can carry out various changes and modification without deviating from this practicality to this utility model New spirit and scope.So, if of the present utility model these modification and modification belong to this utility model claim and Within the scope of its equivalent technologies, then this utility model is also intended to comprise these changes and modification.

Claims (15)

1. a kind of shift register cell is it is characterised in that include：First input module, the second input module, the first reset mould Block, the second reseting module, node control module, the first output module and the second output module；Wherein,

Described first input module is connected with the first input signal end, the first direct current signal end and the first pull-up node respectively； Described first input module is used for carrying the signal at described first direct current signal end under the control at described first input signal end Supply described first pull-up node；

Described first reseting module respectively with the first reset signal end, the second direct current signal end and described first pull-up node phase Even；Described first reseting module is used for the signal at described second direct current signal end under the control at described first reset signal end It is supplied to described first pull-up node；

Described second input module respectively with the second input signal end, described first direct current signal end and the second pull-up node phase Even；Described second input module is used for the signal at described first direct current signal end under the control at described second input signal end It is supplied to described second pull-up node；

Described second reseting module is saved with the second reset signal end, described second direct current signal end and described second pull-up respectively Point is connected；Described second reseting module is used for described second direct current signal end under the control at described second reset signal end Signal is supplied to described second pull-up node；

Described node control module respectively with the first clock signal terminal, second clock signal end, described first pull-up node, described Second pull-up node, the first pull-down node, the second pull-down node are connected；Described node control module is used in described first clock Under the control of signal end, the signal of described first clock signal terminal is supplied to described first pull-down node, in described second clock Under the control of signal end, the signal of described second clock signal end is supplied to described second pull-down node, in the described first pull-up Make respectively under the control of node on the current potential of described first pull-down node and the current potential and described first of described second pull-down node Draw the current potential of node contrary, make the current potential of described first pull-down node and described under the control of described second pull-up node respectively The current potential of the second pull-down node is contrary with the current potential of described second pull-up node, under the control of described first pull-down node respectively Make the current potential of the current potential of described first pull-up node and described second pull-up node contrary with the current potential of described first pull-down node, And make the current potential of described first pull-up node and described second pull-up node under the control of described second pull-down node respectively Current potential contrary with the current potential of described second pull-down node；

Described first output module respectively with described first clock signal terminal, described second clock signal end, reference signal end, institute State the first of the first pull-up node, described first pull-down node, described second pull-down node and described shift register cell Drive signal outfan is connected；Described first output module is for when under the control of described first pull-up node by described first The signal of clock signal end is supplied to described first drive signal outfan, respectively under described first pull-down node and described second Draw, under the control of node, the signal at described reference signal end is supplied to described first drive signal outfan, when described second Under the control of clock signal end, the signal at described reference signal end is supplied to described first drive signal outfan, and described First pull-up node is in during floating and keeps between described first pull-up node and described first drive signal outfan Voltage difference is stable；

Described second output module respectively with described first clock signal terminal, described second clock signal end, described reference signal End, described second pull-up node, described first pull-down node, described second pull-down node and described shift register cell Second drive signal outfan is connected；Described second output module is used for described the under the control of described second pull-up node The signal of two clock signal terminals is supplied to described second drive signal outfan, respectively in described first pull-down node and described Under the control of two pull-down node, the signal at described reference signal end is supplied to described second drive signal outfan, described Under the control of one clock signal terminal by the signal at described reference signal end be supplied to described second drive signal outfan and Described second pull-up node be in during floating keep described second pull-up node and described second drive signal outfan it Between voltage difference stable.

2. shift register cell as claimed in claim 1 is it is characterised in that described node control module includes：On first Node control module, the second pull-up node control module, the first pull-down node control module is drawn to control mould with the second pull-down node Block；Wherein,

Described first pull-up node control module respectively with described reference signal end, described first pull-up node, described first under Node, described second pull-down node is drawn to be connected；Described first pull-up node control module is used for respectively in the described first drop-down section Under the control of point and described second pull-down node, the signal at described reference signal end is supplied to described first pull-up node；

Described second pull-up node control module respectively with described reference signal end, described second pull-up node, described first under Node, described second pull-down node is drawn to be connected；Described second pull-up node control module is used for respectively in the described first drop-down section Under the control of point and described second pull-down node, the signal at described reference signal end is supplied to described second pull-up node；

Described first pull-down node control module respectively with described first clock signal terminal, described reference signal end, described first Pull-down node, described first pull-up node, described second pull-up node are connected；Described first pull-down node control module is used for Under the control of described first clock signal terminal, the signal of described first clock signal terminal is supplied to described first pull-down node, with And under the control of described first pull-up node and described second pull-up node, the signal at described reference signal end is provided respectively To described first pull-down node；

Described second pull-down node control module respectively with described second clock signal end, described reference signal end, described second Pull-down node, described first pull-up node, described second pull-up node are connected；Described second pull-down node control module is used for Under the control of described second clock signal end, the signal of described second clock signal end is supplied to described second pull-down node, with And under the control of described first pull-up node and described second pull-up node, the signal at described reference signal end is provided respectively To described second pull-down node.

3. shift register cell as claimed in claim 2 is it is characterised in that described first pull-up node control module bag Include：First switch transistor and second switch transistor；Wherein,

The grid of described first switch transistor is connected with described first pull-down node, and source electrode is connected with described reference signal end, Drain electrode is connected with described first pull-up node；

The grid of described second switch transistor is connected with described second pull-down node, and source electrode is connected with described reference signal end, Drain electrode is connected with described first pull-up node.

4. shift register cell as claimed in claim 2 is it is characterised in that described second pull-up node control module bag Include：3rd switching transistor and the 4th switching transistor；Wherein,

The grid of described 3rd switching transistor is connected with described second pull-down node, and source electrode is connected with described reference signal end, Drain electrode is connected with described second pull-up node；

The grid of described 4th switching transistor is connected with described first pull-down node, and source electrode is connected with described reference signal end, Drain electrode is connected with described second pull-up node.

5. shift register cell as claimed in claim 2 is it is characterised in that described first pull-down node control module bag Include：5th switching transistor, the 6th switching transistor and the 7th switching transistor；Wherein,

The grid of described 5th switching transistor is all connected with described first clock signal terminal with source electrode, under drain electrode and described first Node is drawn to be connected；

The grid of described 6th switching transistor is connected with described first pull-up node, and source electrode is connected with described reference signal end, Drain electrode is connected with described first pull-down node；

The grid of described 7th switching transistor is connected with described second pull-up node, and source electrode is connected with described reference signal end, Drain electrode is connected with described first pull-down node.

6. shift register cell as claimed in claim 2 is it is characterised in that described second pull-down node control module bag Include：8th switching transistor, the 9th switching transistor and the tenth switching transistor；Wherein,

The grid of described 8th switching transistor is all connected with described second clock signal end with source electrode, under drain electrode and described second Node is drawn to be connected；

The grid of described 9th switching transistor is connected with described first pull-up node, and source electrode is connected with described reference signal end, Drain electrode is connected with described second pull-down node；

The grid of described tenth switching transistor is connected with described second pull-up node, and source electrode is connected with described reference signal end, Drain electrode is connected with described second pull-down node.

7. the shift register cell as described in any one of claim 1-6 is it is characterised in that described first input module bag Include：11st switching transistor；Wherein,

The grid of described 11st switching transistor is connected with described first input signal end, source electrode and described first direct current signal End is connected, and drain electrode is connected with described first pull-up node.

8. the shift register cell as described in any one of claim 1-6 is it is characterised in that described first reseting module bag Include：Twelvemo closes transistor；Wherein,

The grid that described twelvemo closes transistor is connected with described first reset signal end, source electrode and described second direct current signal End is connected, and drain electrode is connected with described first pull-up node.

9. the shift register cell as described in any one of claim 1-6 is it is characterised in that described second input module bag Include：13rd switching transistor；Wherein,

The grid of described 13rd switching transistor is connected with described second input signal end, source electrode and described first direct current signal End is connected, and drain electrode is connected with described second pull-up node.

10. the shift register cell as described in any one of claim 1-6 is it is characterised in that described second reseting module bag Include：14th switching transistor；Wherein,

The grid of described 14th switching transistor is connected with described second reset signal end, source electrode and described second direct current signal End is connected, and drain electrode is connected with described second pull-up node.

11. shift register cells as described in any one of claim 1-6 are it is characterised in that described first output module bag Include：15th switching transistor, sixteenmo close transistor, the 17th switching transistor, eighteenmo pass transistor AND gate first Electric capacity；Wherein,

The grid of described 15th switching transistor is connected with described first pull-up node, source electrode and described first clock signal terminal It is connected, drain electrode is connected with described first drive signal outfan；

The grid that described sixteenmo closes transistor is connected with described first pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described first drive signal outfan；

The grid of described 17th switching transistor is connected with described second pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described first drive signal outfan；

The grid that described eighteenmo closes transistor is connected with described second clock signal end, source electrode and described reference signal end phase Even, drain electrode is connected with described first drive signal outfan；

The first end of described first electric capacity is connected with described first pull-up node, the second end and described first drive signal outfan It is connected.

12. shift register cells as described in any one of claim 1-6 are it is characterised in that described second output module bag Include：19th switching transistor, the 20th switching transistor, the 21st switching transistor, the second twelvemo close transistor AND gate Second electric capacity；Wherein,

The grid of described 19th switching transistor is connected with described second pull-up node, source electrode and described second clock signal end It is connected, drain electrode is connected with described second drive signal outfan；

The grid of described 20th switching transistor is connected with described second pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described second drive signal outfan；

The grid of described 21st switching transistor is connected with described first pull-down node, source electrode and described reference signal end phase Even, drain electrode is connected with described second drive signal outfan；

The grid that described second twelvemo closes transistor is connected with described first clock signal terminal, source electrode and described reference signal end It is connected, drain electrode is connected with described second drive signal outfan；

The first end of described second electric capacity is connected with described second pull-up node, the second end and described second drive signal outfan It is connected.

13. shift register cells as described in any one of claim 1-6 are it is characterised in that described first reset signal end It is connected with described second drive signal outfan；And/or,

Described second input signal end is connected with described first drive signal outfan.

A kind of 14. gate driver circuits are it is characterised in that include the shifting as described in multiple any one as claim 1-13 of cascade Bit register unit；Wherein,

First input signal end of first order shift register cell is connected with frame trigger end；

In addition to first order shift register cell, the first input signal end of remaining shift register cell at different levels respectively with upper Second drive signal outfan of one-level shift register cell is connected；

In addition to afterbody shift register cell, the second reset signal end of remaining shift register cell at different levels respectively with First drive signal outfan of next stage shift register cell is connected.

A kind of 15. display floaters are it is characterised in that include gate driver circuit as claimed in claim 14.