CN104732950B - Shift register cell and driving method, gate driver circuit and display device - Google Patents

Shift register cell and driving method, gate driver circuit and display device Download PDF

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Publication number
CN104732950B
CN104732950B CN201510187978.8A CN201510187978A CN104732950B CN 104732950 B CN104732950 B CN 104732950B CN 201510187978 A CN201510187978 A CN 201510187978A CN 104732950 B CN104732950 B CN 104732950B
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China
Prior art keywords
nodal point
clock signal
signal
shift register
terminal
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CN201510187978.8A
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Chinese (zh)
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CN104732950A (en
Inventor
王峥
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to CN201510187978.8A priority Critical patent/CN104732950B/en
Publication of CN104732950A publication Critical patent/CN104732950A/en
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Abstract

A kind of shift register cell and driving method, gate driver circuit and display device are embodiments provided, for reducing the volume of display floater, while reducing the power consumption of display floater.The shift register cell includes input module and reseting module, also includes:For responding the voltage signal of primary nodal point, second clock signal and the 3rd clock signal are supplied to into the output module of lead-out terminal;For responding the first clock signal, second clock signal and reset signal, the first clock signal is supplied to into secondary nodal point, and in response to the voltage signal of primary nodal point, low level voltage signal is supplied to into the drop-down control module of secondary nodal point;And for responding the voltage signal and the first clock signal of secondary nodal point, low level voltage signal is supplied to into the drop-down module of primary nodal point and lead-out terminal;Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.

Description

Shift register cell and driving method, gate driver circuit and display device

Technical field

The present invention relates to communication technical field, more particularly to a kind of shift register cell and driving method, raster data model Circuit and display device.

Background technology

Thin Film Transistor-LCD (TFT-LCD) driver mainly includes gate driver circuit and data-driven electricity Road, wherein, the clock signal of input is added in display panels after shift register cell conversion by gate driver circuit Grid line on, gate driver circuit can be formed with same process and is simultaneously formed together on the lcd panel with TFT with TFT. Gate driver circuit includes that with multistage shift register cell per grade is all connected to corresponding gate line to export grid drive Dynamic signal.The at different levels of gate driver circuit are connected with each other, and initial signal is input into grid to the first order order at different levels Drive signal is exported to gate line, wherein when the input of prime is connected to the outfan of upper level, and the output of next stage End is connected to the control end when prime.

The gate driver circuit of said structure is set in LCD, which includes such as Fig. 1 institutes per one-level shift register cell The structure shown.Shift register cell shown in Fig. 1, including 10 thin film transistor (TFT)s and 1 electric capacity, for realizing shift LD The output of device unit and reset function;Eliminated because of doing for producing of the change of each exchange clock signal in gate driver circuit simultaneously Noise is disturbed, the output of signal and the stability of shift register cell is improved;But, more thin film transistor (TFT) needs larger Wiring space so that the size of whole shift register cell is larger, and due to each shift register cell correspondence a line The output of grid line scanning signal, therefore, gate driver circuit needs to take larger space, and then causes the body of liquid crystal display Product is larger, is unfavorable for realizing the narrow frame design of display floater;Also, the thin film transistor (TFT) of greater number also results in displacement and posts The power consumption of storage is larger, and then causes the power consumption of whole display floater higher.

The content of the invention

Embodiments provide a kind of shift register cell and driving method, gate driver circuit and show dress Put, for reducing the volume of display floater, while reducing the power consumption of display floater.

A kind of shift register cell provided in an embodiment of the present invention, the shift register cell include input module, Output module, reseting module, drop-down control module and drop-down module, wherein,

The input module, for responding input signal and the first clock signal, using input signal by as described defeated The primary nodal point for entering module outfan is supplied to output module;

Low level voltage signal, for responding reset signal, is supplied to primary nodal point by the reseting module;

The output module, for responding the voltage signal of primary nodal point, by second clock signal and the 3rd clock signal It is supplied to lead-out terminal;

The drop-down control module, for responding the voltage signal of the first clock signal, second clock signal, primary nodal point And reset signal, the first clock signal is supplied to the secondary nodal point of the outfan as the drop-down control module;And, ring Low level voltage signal should be supplied to into secondary nodal point in the voltage signal of primary nodal point;

The drop-down module, for responding the voltage signal and the first clock signal of secondary nodal point, low level voltage is believed Number it is supplied to primary nodal point and lead-out terminal;

Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.

Shift register cell provided in an embodiment of the present invention, including:For responding input signal and the first clock signal, Input signal is supplied to into the input module of output module by the primary nodal point as the input module outfan;For ringing Reset signal is answered, low level voltage signal is supplied to into the reseting module of primary nodal point;Voltage for responding primary nodal point is believed Number, second clock signal and the 3rd clock signal are supplied to into the output module of lead-out terminal;For respond the first clock signal, Second clock signal and reset signal, the first clock signal is supplied to second of the outfan as the drop-down control module Node, and in response to the voltage signal of primary nodal point, low level voltage signal is supplied to into the drop-down control mould of secondary nodal point Block;And for responding the voltage signal and the first clock signal of secondary nodal point, low level voltage signal is supplied to into first segment The drop-down module of point and lead-out terminal;Wherein, the duty of first clock signal, second clock signal and the 3rd clock signal Than being 1/3.In due to the shift register cell, 1/3 clock signal is using 3 its dutycycles, believed using clock Number timing skew, same trigger triggering under, using a shift register cell within the time of two rows respectively to N Row and N+1 rows export grid line scanning signal, so as to realize the defeated of a shift register cell two row gate drive signals of correspondence Go out, significantly reduce to the space needed for gate driver circuit designing wiring, be conducive to reducing the volume of display floater, realize Manifest the narrow frame design of panel;The power consumption of display floater can also be reduced simultaneously.

Preferably, the input module includes:

First film transistor M1, its grid and drain electrode connection input signal end, source electrode connection primary nodal point;

Second thin film transistor (TFT), its grid connect first clock signal terminal, drain electrode connection input signal end, source electrode connection the One node.

In the input module, the grid of first film transistor M1 is connected the defeated of the shift register cell simultaneously with source electrode Enter signal end, drain electrode connection primary nodal point, therefore when the input signal at the input signal end is to high level, described first is thin Film transistor M1 is turned on, and the input signal is supplied to primary nodal point;And due to the grid connection the of the second thin film transistor (TFT) One clock signal input terminal, drain electrode connection input signal end, source electrode connection primary nodal point, therefore when the first clock signal is high electricity At ordinary times, input signal is supplied to primary nodal point by second thin film transistor (TFT) by the second thin film transistor (TFT) conducting.

Preferably, the reseting module includes:

3rd thin film transistor (TFT), its grid connection reset signal end, drain electrode connection primary nodal point, source electrode connection low level electricity Pressure signal.

Due to the grid connection reset signal end of the 3rd thin film transistor (TFT), drain electrode connection primary nodal point, source electrode connection Low level voltage signal, therefore reset signal is when being high level, the 3rd thin film transistor (TFT) conducting, by the low level signal It is supplied to primary nodal point.

Preferably, the output module includes:

Second clock signal, for responding the voltage signal of primary nodal point, is supplied to the first output by the first output module Terminal;

3rd clock signal, for responding the voltage signal of primary nodal point, is supplied to the second output by the second output module Terminal.

In the output module, when the voltage signal of primary nodal point is high level, by first output module and the Second clock signal and the 3rd clock signal are supplied to first lead-out terminal and the second lead-out terminal by two output modules respectively.

Preferably, first output module includes:

4th thin film transistor (TFT), its grid connect primary nodal point, drain electrode connection second clock signal end, source electrode connection first Lead-out terminal;

Electric capacity, is connected between primary nodal point and first lead-out terminal.

In first output module, when primary nodal point is high level, the 4th thin film transistor (TFT) conducting, by described the Two clock signals are supplied to first lead-out terminal;The electric capacity, then for keeping the current potential of primary nodal point so that the 4th thin film is brilliant Body pipe is tended to remain within a certain period of time.

Second output module includes:

5th thin film transistor (TFT), its grid connect primary nodal point, drain electrode the 3rd clock signal terminal of connection, source electrode connection second Lead-out terminal.

In second output module, when primary nodal point is high level, the 5th thin film transistor (TFT) conducting, by described the Three clock signals are supplied to the second lead-out terminal.

Preferably, the drop-down control module includes:

First drop-down control module, for responding the voltage letter of the first clock signal, second clock signal and primary nodal point Number, the first clock signal is supplied to into secondary nodal point;

First clock signal, for responding reset signal, is supplied to secondary nodal point by the second drop-down control module;

Low level voltage signal, for responding the voltage signal of primary nodal point, is supplied to by the 3rd drop-down control module Two nodes.

In the drop-down control module, when the first clock signal or second clock signal are high level, and the electricity of primary nodal point When pressure signal is low level, the first clock signal is supplied to by secondary nodal point by the described first drop-down control module;When described When reset signal is high level, the first clock signal is supplied to by secondary nodal point by the described second drop-down control module;When When the voltage signal of one node is high level, low level voltage signal is supplied to into second by the 3rd drop-down control module Node.

Preferably, the first drop-down control module includes:

6th thin film transistor (TFT), its grid and drain electrode connect the first clock signal terminal simultaneously, and source electrode connects the 3rd node;

7th thin film transistor (TFT), its grid connect the 3rd node, drain electrode the first clock signal terminal of connection, source electrode connection second Node;

8th thin film transistor (TFT), its grid connect second clock signal end, and drain electrode the first clock signal terminal of connection, source electrode connect Connect the 3rd node;

9th thin film transistor (TFT), its grid connect primary nodal point, drain electrode connection low level voltage signal, source electrode connection the 3rd Node.

In the first drop-down control module, when the first clock signal is high level, and the voltage signal of primary nodal point is low During level, the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT) are turned on, and the first clock is believed by the cut-off of the 9th thin film transistor (TFT) Number it is supplied to secondary nodal point;When second clock signal is high level, and the voltage signal of primary nodal point is when being low level, described the First clock signal is supplied to second by eight thin film transistor (TFT)s and the conducting of the 7th thin film transistor (TFT), the cut-off of the 9th thin film transistor (TFT) Node.

Preferably, the second drop-down control module includes:

Tenth thin film transistor (TFT), its grid connection reset signal end, drain electrode the first clock signal terminal of connection, source electrode connection the Two nodes.

In the second drop-down control module, when reset signal end is high level, the tenth thin film transistor (TFT) conducting will First clock signal is supplied to secondary nodal point.

Preferably, the 3rd drop-down control module includes:

11st thin film transistor (TFT), its grid connect primary nodal point, drain electrode connection low level voltage signal, source electrode connection the Two nodes.

When the voltage signal of primary nodal point is high level, the 11st thin film transistor (TFT) conducting, by the low level Voltage signal is supplied to secondary nodal point.

Preferably, the drop-down module includes:

Low level voltage signal, for responding the voltage signal of secondary nodal point, is supplied to first segment by the first drop-down module Point;

Second drop-down module, for responding the voltage signal of secondary nodal point, low level voltage signal is supplied to first defeated Go out terminal and the second lead-out terminal;

Low level voltage signal, for responding the first clock signal, is supplied to first lead-out terminal by the 3rd drop-down module With the second lead-out terminal.

In the drop-down module, when the voltage signal of secondary nodal point is high level signal, will be low by the first drop-down module Level voltage signal is supplied to primary nodal point, and primary nodal point is discharged, while low level is electric by the second drop-down module Pressure signal is supplied to first lead-out terminal and the second lead-out terminal, and first lead-out terminal and the second lead-out terminal are discharged; Also, when the first clock signal is high level, low level voltage signal is supplied to by the first outfan by the 3rd drop-down module Son and the second lead-out terminal, discharge to first lead-out terminal and the second lead-out terminal.

Preferably, the first drop-down module includes:

12nd thin film transistor (TFT), its grid connect secondary nodal point, drain electrode connection primary nodal point, source electrode connection low level electricity Pressure signal.

In the first drop-down module, when the voltage signal of secondary nodal point is high level, the 12nd thin film transistor (TFT) Conducting, discharges to primary nodal point.

Preferably, the second drop-down module includes:

13rd thin film transistor (TFT), its grid connect secondary nodal point, drain electrode connection first lead-out terminal and the second outfan Son, source electrode connection low level voltage signal.

In the second drop-down module, when the voltage signal of secondary nodal point is high level, the 13rd thin film transistor (TFT) Conducting, discharges to first lead-out terminal and the second lead-out terminal.

Preferably, the 3rd drop-down module includes:

14th thin film transistor (TFT), its grid connect first clock signal, drain electrode connection first lead-out terminal and second defeated Go out terminal, source electrode connection low level voltage signal.

In the 3rd drop-down module, when the first clock signal is high level, the 14th thin film transistor (TFT) conducting, First lead-out terminal and the second lead-out terminal are discharged.

Preferably, all thin film transistor (TFT)s are N-type or P-type TFT.

Preferably, all thin film transistor (TFT)s are polycrystalline SiTFT, or amorphous silicon film transistor is, or Person is oxide thin film transistor.

Embodiments provide a kind of gate driver circuit, including the shift register cells at different levels of cascade;Wherein, The input signal end connection initial signal end of first order shift register cell, the reset signal of first order shift register cell The lead-out terminal of end connection next stage shift register cell;In the input signal end connection of afterbody shift register cell The lead-out terminal of one-level shift register cell, the reset signal end connection initial signal of afterbody shift register cell End;

In addition to the first order and afterbody shift register cell, the input signal end of remaining shift register cell at different levels The lead-out terminal of connection upper level shift register cell, reset signal end connects the outfan of next stage shift register cell Son;And the shift register cell of all cascades is above-mentioned shift register cell.

The gate driver circuit is formed by the cascade of above-mentioned shift register cell, due to the shift register cell In, 1/3 clock signal is using 3 its dutycycles, using the timing skew of clock signal, trigger in same trigger Under, grid line scanning signal is exported to n rows and n+1 rows respectively using a shift register cell within the time of two rows, so as to The output of a shift register cell two row gate drive signals of correspondence is realized, is significantly reduced and gate driver circuit is set Space needed for meter wiring, is conducive to reducing the volume of display floater, and realization manifests the narrow frame design of panel;Simultaneously can be with Reduce the power consumption of display floater.

A kind of display device is embodiments provided, the display device includes above-mentioned gate driver circuit.

A kind of driving method of above-mentioned shift register cell is embodiments provided, methods described includes:

Input signal is supplied to primary nodal point in response to input signal and the first clock signal by input module;

Second clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;

3rd clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;

Low level voltage signal is supplied to primary nodal point in response to reset signal by reseting module, and primary nodal point is discharged; Drop-down control module is in response to the first clock signal, and first clock signal is supplied to secondary nodal point, to secondary nodal point Charge;Low level voltage signal is supplied to by voltage signal and first clock signal of the drop-down module in response to secondary nodal point One node and lead-out terminal;

Low level voltage signal is supplied to primary nodal point and outfan in response to second clock signal by drop-down control module Son;

Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.

In driving method provided in an embodiment of the present invention, as the shift register cell adopts 3 its dutycycles equal For 1/3 clock signal, using the timing skew of clock signal, under the triggering of same trigger, by a shift LD Device unit exports grid line scanning signal to n rows and n+1 rows within the time of two rows respectively, so as to realize a shift register list The output of unit's two row gate drive signals of correspondence, reduces the number of the shift register cell needed for composition gate driver circuit Mesh, so as to significantly reduce to the space needed for gate driver circuit designing wiring, is conducive to reducing the volume of display floater, Realization manifests the narrow frame design of panel;The power consumption of display floater can also be reduced simultaneously.

Description of the drawings

Fig. 1 is shift register cell structural representation in prior art;

Fig. 2 is a kind of structural representation of shift register cell provided in an embodiment of the present invention;

Fig. 3 is a kind of structural representation of gate driver circuit provided in an embodiment of the present invention;

Fig. 4 is a kind of clock signal figure of each signal end of shift register cell provided in an embodiment of the present invention.

Specific embodiment

Embodiments provide a kind of shift register cell, gate driver circuit and driving method and show dress Put, for reducing the volume of display floater, while reducing the power consumption of display floater.

Below in conjunction with the accompanying drawings, the present invention will be described.

Embodiments provide a kind of shift register cell, its structure as shown in Fig. 2 from figure 2 it can be seen that The register cell includes:Input module 201, reseting module 202, output module 203, drop-down control module 204 and drop-down Module 205;

The input module 201, for responding input signal and the first clock signal, using input signal by as described The primary nodal point of input module outfan is supplied to output module;

The reseting module 202, connection reset signal end, for responding reset signal, low level voltage signal is provided To primary nodal point;

The output module 203, for responding the voltage signal of primary nodal point, second clock signal and the 3rd clock is believed Number it is supplied to lead-out terminal;

The drop-down control module 204, for responding the voltage of the first clock signal, second clock signal, primary nodal point Signal and reset signal, the first clock signal is supplied to the secondary nodal point of the outfan as the drop-down control module;With And, in response to the voltage signal of primary nodal point, low level voltage signal is supplied to into secondary nodal point;

The drop-down module 205, for responding the voltage signal and the first clock signal of secondary nodal point, by low level voltage Signal is supplied to primary nodal point and lead-out terminal;

Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.

Shift register cell provided in an embodiment of the present invention, including:For responding input signal and the first clock signal, Input signal is supplied to into the input module of output module by the primary nodal point as the input module outfan;For ringing Reset signal is answered, low level voltage signal is supplied to into the reseting module of primary nodal point;Voltage for responding primary nodal point is believed Number, second clock signal and the 3rd clock signal are supplied to into the output module of lead-out terminal;For respond the first clock signal, Second clock signal and reset signal, the first clock signal is supplied to second of the outfan as the drop-down control module Node, and in response to the voltage signal of primary nodal point, low level voltage signal is supplied to into the drop-down control mould of secondary nodal point Block;And for responding the voltage signal and the first clock signal of secondary nodal point, low level voltage signal is supplied to into first segment The drop-down module of point and lead-out terminal;Wherein, the duty of first clock signal, second clock signal and the 3rd clock signal Than being 1/3.In due to the shift register cell, 1/3 clock signal is using 3 its dutycycles, believed using clock Number timing skew, same trigger triggering under, using a shift register cell within the time of two rows respectively to n Row and n+1 rows export grid line scanning signal, so as to realize the defeated of a shift register cell two row gate drive signals of correspondence Go out, the number of the shift register cell needed for reducing significantly is reduced to needed for gate driver circuit designing wiring Space, is conducive to reducing the volume of display floater, and realization manifests the narrow frame design of panel;Display floater can also be reduced simultaneously Power consumption.

Further, the output module 203 includes:

Second clock signal, for responding the voltage signal of primary nodal point, is supplied to first by the first output module 2031 Lead-out terminal;

3rd clock signal, for responding the voltage signal of primary nodal point, is supplied to second by the second output module 2032 Lead-out terminal.

In the output module, when the voltage signal of primary nodal point is high level, by first output module and the Second clock signal and the 3rd clock signal are supplied to first lead-out terminal and the second lead-out terminal by two output modules respectively

Further, the drop-down control module 204 includes:

First drop-down control module 2041, for responding the electricity of the first clock signal, second clock signal and primary nodal point First clock signal is supplied to secondary nodal point by pressure signal;

First clock signal, for responding reset signal, is supplied to secondary nodal point by the second drop-down control module 2042;

3rd drop-down control module 2043, for responding the voltage signal of primary nodal point, low level voltage signal is provided To secondary nodal point.

In the drop-down control module, when the first clock signal or second clock signal are high level, and the electricity of primary nodal point When pressure signal is low level, first clock signal is supplied to by the second section by the described first drop-down control module Point;When the reset signal is high level, the first clock signal is supplied to into second by the described second drop-down control module Node;When the voltage signal of the primary nodal point is high level, by the 3rd drop-down control module by low level voltage Signal is supplied to secondary nodal point.

With reference to specific embodiment, the present invention is described in detail.It should be noted that in the present embodiment be in order to The present invention is preferably explained, but does not limit the present invention.

Shift register cell as shown in Figure 2, including:Input module 201, reseting module 202, output module 203, Drop-down control module 204 and drop-down module 205;

Specifically, the input module 201, including:

First film transistor M1, its grid and drain electrode connection input signal end INPUT, source electrode connection primary nodal point P1;

Second thin film transistor (TFT) M2, its grid connect the first clock signal terminal CLK1, drain electrode connection input signal end INPUT, source electrode connection primary nodal point P1.

In the input module, the grid of first film transistor M1 is connected the defeated of the shift register cell simultaneously with source electrode Enter signal end INPUT, drain electrode connection primary nodal point P1, therefore when the input signal of the input signal end INPUT is to high level When, the input signal is supplied to the primary nodal point P1 by the first film transistor M1 conducting;And due to the second thin film Grid connection 1 input of the first clock signal clk of transistor M2, drain electrode connection input signal end INPUT, source electrode connection first Node P1, therefore when the first clock signal clk 1 is high level, the second thin film transistor (TFT) M2 conductings, by described second Input signal is supplied to primary nodal point P1 by thin film transistor (TFT) M2.

The reseting module 202, including:

3rd thin film transistor (TFT) M3, its grid connect reset signal end RESET, and drain electrode connection primary nodal point P1, source electrode connect Meet low level voltage signal VSS.

In the reseting module, due to the grid connection reset signal end RESET of the 3rd thin film transistor (TFT) M3, leakage Pole connect primary nodal point P1, source electrode connection low level voltage signal VSS, therefore reset signal be high level when, the described 3rd is thin Film transistor M3 is turned on, and the low level signal VSS is supplied to primary nodal point P1.

The output module 203, including:For respond primary nodal point P1 voltage signal and by second clock signal provide To the first output module 2031 of first lead-out terminal, and for respond primary nodal point P1 voltage signal and by the 3rd clock believe Number CLK3 is supplied to the second output module 2032 of the second lead-out terminal.

Wherein, first output module 2031 includes:

4th thin film transistor (TFT) M4, its grid connect primary nodal point P1, drain electrode connection second clock signal end CLK2, source electrode Connection first lead-out terminal OUTPUT1;

Electric capacity C, is connected between primary nodal point P1 and first lead-out terminal OUTPUT1.

In first output module, when primary nodal point P1 is high level, the 4th thin film transistor (TFT) M4 conductings, by institute State second clock signal CLK2 and be supplied to first lead-out terminal OUTPUT1;The electric capacity C, then for keeping primary nodal point P1's Current potential so that the 4th thin film transistor (TFT) M4 is tended to remain within a certain period of time.

Second output module 2032 includes:

5th thin film transistor (TFT) M5, its grid connect primary nodal point P1, drain electrode the 3rd clock signal terminal CLK3 of connection, source electrode Connect the second lead-out terminal OUTPUT2.

In second output module, when primary nodal point P1 is high level, the 5th thin film transistor (TFT) M5 conductings, by institute State the 3rd clock signal clk 3 and be supplied to the second lead-out terminal OUTPUT2.

The drop-down control module 204, including:For respond the first clock signal clk 1, second clock signal CLK2 and First clock signal clk 1 is supplied to the first drop-down control module of secondary nodal point P2 by the voltage signal of primary nodal point P1 2041;For responding reset signal, the first clock signal clk 1 is supplied to into the second drop-down control module of secondary nodal point P2 2042;And, for responding the voltage signal of primary nodal point P1, low level voltage signal is supplied to into the 3rd of secondary nodal point P2 the Drop-down control module 2043.

Wherein, the described first drop-down control module 2041 includes:

6th thin film transistor (TFT) M6, its grid and drain electrode connect the first clock signal terminal CLK1, source electrode connection the 3rd simultaneously Node P3;

7th thin film transistor (TFT) M7, its grid connect the 3rd node, and drain electrode the first clock signal terminal CLK1 of connection, source electrode connect Meet secondary nodal point P2;

8th thin film transistor (TFT) M8, its grid connect second clock signal end CLK2, drain electrode the first clock signal terminal of connection CLK1, source electrode connect the 3rd node P3;

9th thin film transistor (TFT) M9, its grid connect primary nodal point P1, drain electrode connection low level voltage signal VSS, source electrode Connect the 3rd node P3.

In the first drop-down control module, when the first clock signal clk 1 is high level, and the voltage letter of primary nodal point P1 Number for low level when, the 6th thin film transistor (TFT) M6 and the 7th thin film transistor (TFT) M7 conducting, the 9th thin film transistor (TFT) M9 cut-off, First clock signal clk 1 is supplied to into secondary nodal point P2;When second clock signal CLK2 is high level, and primary nodal point P1 When voltage signal is low level, the 8th thin film transistor (TFT) M8 and the 7th thin film transistor (TFT) M7 conductings, the 9th thin film transistor (TFT) M9 ends, and the first clock signal clk 1 is supplied to secondary nodal point P2.

The second drop-down control module 2042 includes:

Tenth thin film transistor (TFT) M10, its grid connect reset signal end RESET, drain electrode the first clock signal terminal of connection CLK1, source electrode connection secondary nodal point P2.

In the second drop-down control module, when reset signal end is high level, the tenth thin film transistor (TFT) M10 leads It is logical, the first clock signal clk 1 is supplied to into secondary nodal point P2.

The 3rd drop-down control module 2043 includes:

11st thin film transistor (TFT) M11, its grid connect primary nodal point P1, drain electrode connection low level voltage signal VSS, source Pole connects secondary nodal point P2.

When the voltage signal of primary nodal point P1 is high level, the 11st thin film transistor (TFT) M11 conductings will be described low Level voltage signal VSS is supplied to secondary nodal point P2.

The drop-down module 205 includes:For responding the voltage signal of secondary nodal point P2, by low level voltage signal VSS It is supplied to the first drop-down module 2051 of primary nodal point P1;For responding the voltage signal of secondary nodal point P2, by low level voltage Signal is supplied to the second drop-down module 2052 of first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2;And be used for The first clock signal clk 1 is responded, low level voltage signal is supplied to into first lead-out terminal OUTPUT1 and the second lead-out terminal The 3rd drop-down module 2053 of OUTPUT2.

In the drop-down module, when the voltage signal of secondary nodal point P2 is high level signal, will by the first drop-down module Low level voltage signal is supplied to primary nodal point P1, and primary nodal point P1 is discharged, while will be low by the second drop-down module Level voltage signal is supplied to first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2, to first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2 are discharged;Also, when the first clock signal clk 1 is high level, by the 3rd Low level voltage signal is supplied to first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2 by drop-down module, to first Lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2 are discharged.

Further, the described first drop-down module 2051 includes:

12nd thin film transistor (TFT) M12, its grid connect secondary nodal point P2, drain electrode connection primary nodal point P1, source electrode connection Low level voltage signal VSS.

In the first drop-down module, when the voltage signal of secondary nodal point P2 is high level, the 12nd film crystal Pipe M12 is turned on, and primary nodal point P1 is discharged.

Preferably, the second drop-down module 2052 includes:

13rd thin film transistor (TFT) M13, its grid connect secondary nodal point P2, drain electrode connection first lead-out terminal and second defeated Go out terminal, source electrode connection low level voltage signal VSS.

In the second drop-down module, when the voltage signal of secondary nodal point P2 is high level, the 13rd film crystal Pipe M13 is turned on, and first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2 are discharged.

Preferably, the 3rd drop-down module 2053 includes:

14th thin film transistor (TFT) M14, its grid connect first clock signal clk 1, drain electrode connection first lead-out terminal and Second lead-out terminal, source electrode connection low level voltage signal VSS.

In the 3rd drop-down module, when the first clock signal clk 1 is high level, the 14th thin film transistor (TFT) M14 is turned on, and first lead-out terminal OUTPUT1 and the second lead-out terminal OUTPUT2 are discharged.

Further, all thin film transistor (TFT)s are N-type or P-type TFT.

Further, all thin film transistor (TFT)s are polycrystalline SiTFT, or are amorphous silicon film transistor, Or it is oxide thin film transistor.

The embodiment of the present invention two provides a kind of gate driver circuit, including the shift register cells at different levels of cascade;Its In, the input signal end connection initial signal end of first order shift register cell, the reset of first order shift register cell Signal end connects the lead-out terminal of next stage shift register cell;The input signal end of afterbody shift register cell connects Connect the lead-out terminal of one-level shift register cell, the reset signal end connection starting letter of afterbody shift register cell Number end;

In addition to the first order and afterbody shift register cell, the input signal end of remaining shift register cell at different levels The lead-out terminal of connection upper level shift register cell, reset signal end connects the outfan of next stage shift register cell Son;And the shift register cell of all cascades is the shift register cell shown in Fig. 2.

The gate driver circuit is formed by the cascade of above-mentioned shift register cell, due to the shift register cell In, 1/3 clock signal is using 3 its dutycycles, using the timing skew of clock signal, trigger in same trigger Under, grid line scanning signal is exported to n rows and m+1 rows respectively using a shift register cell within the time of two rows, so as to The output of a shift register cell two row gate drive signals of correspondence is realized, is significantly reduced and gate driver circuit is set Space needed for meter wiring, is conducive to reducing the volume of display floater, and realization manifests the narrow frame design of panel;Simultaneously can be with Reduce the power consumption of display floater.

Specifically, the array base palte gate driver circuit includes N levels, and N is grid line quantity, referring to Fig. 3, initial signal STV It is input to first order shift register cell as input signal, and order exports gate drive signal to gate line, N-th grade of input signal is provided by (n-1)th grade of output signal, wherein n<N.

The sequential chart of each signal end that Fig. 4 is, drives to array base palte grid provided in an embodiment of the present invention with reference to Fig. 4 The n-th (n in galvanic electricity road<The series of N, N for array base palte grid circuit) method of work of level shift register cell said It is bright, wherein, all shift register cells are above-mentioned shift register cell, and all thin film transistor (TFT) TFT are high electricity Flat conducting, low level cut-off.

When the gate driver circuit is scanned, VSS is low level signal:

First stage S1, the first clock signal clk 1 is high level, and second clock signal CLK2 is low level, the 3rd clock Signal CLK3 is low level, is high level as prime output signal OUTPUT (n-1) of input signal, reset signal OUTPUT (n+2) it is low level.Input signal OUTPUT (n-1) of high level causes the conducting of first film transistor M1T1, input signal OUTPUT (n-1) charges to electric capacity C so that primary nodal point P1 is high level;Now, in response to the voltage signal of primary nodal point P1 The 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5 conductings, but, due to now the first clock signal clk 1 and the 3rd Clock signal clk 3 is low level, therefore, first lead-out terminal OUTPUT1 (n) and the second lead-out terminal in the time period The output of OUTPUT2 (n+1) is low level.

Additionally, the first clock signal clk 1 of high level causes the 6th thin film transistor (TFT) M6 conductings, but due in response to 9th thin film transistor (TFT) M9 of the voltage signal of primary nodal point P1 discharges to the source electrode of the 6th thin film transistor (TFT) M6, enters And end the 7th thin film transistor (TFT) M7, it is impossible to it is charged for secondary nodal point P2, and in response to the tenth of primary nodal point P1 the One thin film transistor (TFT) M11 is also at conducting state, and secondary nodal point P2 is discharged, and makes the secondary nodal point P2 be in low electricity It is flat, now, in response to the 12nd thin film transistor (TFT) M12 and the 13rd thin film transistor (TFT) M13 of the voltage signal of secondary nodal point P2 Cut-off, turns in response to the 14th thin film transistor (TFT) M14 of the first clock signal clk 1, to first lead-out terminal and the second output Terminal carries out continuous discharge.

Second stage S2:First clock signal clk 1 is low level, and second clock signal CLK2 is high level, the 3rd clock Signal CLK3 is low level, and input signal OUTPUT (n-1) is low level, and reset signal OUTPUT (n+2) is low level;First Node P1 is high level, in response to the 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5 of the voltage signal of primary nodal point P1 Conducting, due to the boot strap of electric capacity C, the voltage of primary nodal point P1 continues rising, the 4th thin film transistor (TFT) M4 and the 5th thin film Transistor M5 is held on, and the current potential of primary nodal point P1 is further pulled up;It is thin in response to the 14th of the first clock signal clk 1 the Film transistor M14 ends;Now first lead-out terminal OUTPUT1 (n) is output as high level, the second lead-out terminal OUTPUT2 (n+ 1) it is output as low level.

Meanwhile, turn in response to the 8th thin film transistor (TFT) M8 of second clock signal CLK2, and pass through the 8th thin film Transistor M8 provides second clock signal CLK2 for the 7th thin film transistor (TFT) M7 and makes the 7th thin film transistor (TFT) M7 conductings, First clock signal clk 1 is provided for secondary nodal point P2 by the 7th thin film transistor (TFT) M7, and in response to primary nodal point P1 The 9th thin film transistor (TFT) M9 and the 11st thin film transistor (TFT) M11 of voltage signal be held on, therefore at secondary nodal point P2 after Low level is held in continuation of insurance, in response to the 12nd thin film transistor (TFT) M12 and the 13rd film crystal of the voltage signal of secondary nodal point P2 Pipe M13 keeps cut-off state.

Phase III S3, the first clock signal clk 1 is low level, and second clock signal CLK2 is low level, the 3rd clock Signal CLK3 is high level, and input signal OUTPUT (n-1) is low level, and reset signal OUTPUT (n+2) is low level;First Node P1 is high potential, in response to the 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5 of the voltage signal of primary nodal point P1 Conducting, and the 3rd clock signal clk 3 is high level, due to the boot strap of electric capacity C, the voltage of primary nodal point P1 is raised again, 4th thin film transistor (TFT) M4 and the 5th thin film transistor (TFT) M5 are held on, and the current potential of primary nodal point P1 is further pulled up, by institute State the 5th thin film transistor (TFT) M5 the 3rd clock signal clk 3 is provided for the second lead-out terminal OUTPUT2 (n+1);Now, first is defeated Go out to hold OUTPUT1 (n) to be output as low level, the second outfan OUTPUT2 (n+1) is output as high level.

Meanwhile, end in response to the thin film transistor (TFT) of the first clock signal clk 1 and second clock signal CLK2, and ring Should be held in the 9th thin film transistor (TFT) M9 of the voltage signal of primary nodal point P1 and the 11st thin film transistor (TFT) M11, therefore At secondary nodal point P2 continue keep low level, in response to secondary nodal point P2 voltage signal the 12nd thin film transistor (TFT) M12 and 13rd thin film transistor (TFT) M13 keeps cut-off state, in response to the 14th thin film transistor (TFT) M14 of the first clock signal clk 1 Keep cut-off state.

Fourth stage S4, the first clock signal clk 1 is high level, and second clock signal CLK2 is low level, the 3rd clock Signal CLK3 is low level, and input signal OUTPUT (n-1) is low level, and reset signal OUTPUT (n+2) is high level;First Clock signal clk 1 is high level, is turned in response to the 14th thin film transistor (TFT) M14 of the first clock signal clk 1, and to first Lead-out terminal and the second lead-out terminal provide second voltage signal VSS so that first lead-out terminal and the second lead-out terminal are rapid It is reduced to low level;Therefore, first lead-out terminal OUTPUT1 (n) and the second lead-out terminal OUTPUT2 (n+1) in the time period Output is low level.

Meanwhile, the high level of reset signal input causes the 3rd thin film transistor (TFT) M3 to turn on, and carries to primary nodal point P1 For low level voltage signal VSS so that low level is reduced to rapidly at primary nodal point P1;In response to the voltage signal of primary nodal point P1 The 9th thin film transistor (TFT) M9 and the 11st thin film transistor (TFT) M11 cut-offs, the first clock signal clk 1 passes through the 6th film crystal Pipe M6 and the 7th thin film transistor (TFT) M7 to secondary nodal point P2 charge, now in response to secondary nodal point P2 voltage signal the 12nd Thin film transistor (TFT) M12 and the 13rd thin film transistor (TFT) M13 conductings, it is low level is electric by the 12nd thin film transistor (TFT) M12 Pressure is supplied to primary nodal point P1, and the primary nodal point P1 is discharged, and passes through the 13rd thin film transistor (TFT) by low electricity Flat voltage signal is supplied to first lead-out terminal OUTPUT1 (n) and the second lead-out terminal OUTPUT2 (n+1), defeated to described first Go out terminal OUTPUT1 (n) and the second lead-out terminal OUTPUT2 (n+1) is discharged, eliminate the change due to exchanging clock signal Caused interference noise, it is ensured that the stability of output signal.

5th stage S5, the first clock signal clk 1 is low level, and second clock signal CLK2 is high level, the 3rd clock Signal CLK3 is low level, and input signal OUTPUT (n-1) is low level, and reset signal OUTPUT (n+2) is low level;Due to Second clock signal CLK2 is high level, is turned in response to the 8th thin film transistor (TFT) M8 of second clock signal CLK2, by first Clock signal clk 1 is supplied to the grid of the 7th thin film transistor (TFT) M7 for low level so that the 7th thin film transistor (TFT) M7 ends, the Two node P2 keep high level, thin in response to the 12nd thin film transistor (TFT) M12 and the 13rd of the voltage signal of secondary nodal point P2 Film transistor M13 is tended to remain on, the two ends of electric capacity C are connected with low level voltage signal, and holding circuit is stablized, eliminate by The interference noise caused by the change of exchange clock signal, the impact caused by noise jamming is minimized, it is ensured that output letter Number stability.

Other times circuit maintains steady statue, the two ends of holding capacitor C to be connected with low level voltage signal, until next The arrival of frame OUTPUT (n-1) repeats said process.

In the gate driver circuit that the embodiment of the present invention two is provided, 1/3 clock signal is using 3 its dutycycles, Using the timing skew of clock signal, under the triggering of same trigger, using a shift register cell two rows when It is interior that grid line scanning signal is exported to n rows and n+1 rows respectively, so as to realize that a shift register cell two row grids of correspondence drive The output of dynamic signal, significantly reduces to the space needed for gate driver circuit designing wiring, is conducive to reducing display floater Volume, realization manifests the narrow frame design of panel;The power consumption of display floater can also be reduced simultaneously.

The embodiment of the present invention three provides a kind of display device, and the display device includes above-mentioned gate driver circuit.

The embodiment of the present invention four provides a kind of driving method of shift register cell, is provided with the embodiment of the present invention two Shift register cell as a example by, methods described includes:

Input signal is supplied to primary nodal point in response to input signal and the first clock signal by input module;

Second clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;

3rd clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;

Low level voltage signal is supplied to primary nodal point in response to reset signal by reseting module, and primary nodal point is discharged; Drop-down control module is in response to the first clock signal, and first clock signal is supplied to secondary nodal point, to secondary nodal point Charge;Low level voltage signal is supplied to by voltage signal and first clock signal of the drop-down module in response to secondary nodal point One node and lead-out terminal;

Low level voltage signal is supplied to primary nodal point and outfan in response to second clock signal by drop-down control module Son;

Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.

In the driving method that the embodiment of the present invention four is provided, as the shift register cell adopts 3 its dutycycles 1/3 clock signal is, using the timing skew of clock signal, under the triggering of same trigger, is posted by a displacement Storage unit exports grid line scanning signal to n rows and n+1 rows within the time of two rows respectively, so as to realize a shift register The output of unit two row gate drive signals of correspondence, reduces the number of the shift register cell needed for composition gate driver circuit Mesh, so as to significantly reduce to the space needed for gate driver circuit designing wiring, is conducive to reducing the volume of display floater, Realization manifests the narrow frame design of panel;The power consumption of display floater can also be reduced simultaneously.

In sum, a kind of shift register cell provided in an embodiment of the present invention, gate driver circuit and display device; Wherein, the shift register cell includes:For responding input signal and the first clock signal, using input signal by as The primary nodal point of the input module outfan is supplied to the input module of output module;For responding reset signal, by low electricity Flat voltage signal is supplied to the reseting module of primary nodal point;For responding the voltage signal of primary nodal point, by second clock signal The output module of lead-out terminal is supplied to the 3rd clock signal;For responding the first clock signal, second clock signal and answering Position signal, the first clock signal is supplied to the secondary nodal point of the outfan as the drop-down control module, and in response to Low level voltage signal is supplied to the drop-down control module of secondary nodal point by the voltage signal of primary nodal point;And for responding The voltage signal of secondary nodal point and the first clock signal, low level voltage signal is supplied under primary nodal point and lead-out terminal Drawing-die block;Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.Due to this In shift register cell, 1/3 clock signal is using 3 its dutycycles, using the timing skew of clock signal, same Under the triggering of one trigger, grid line is exported to n rows and n+1 rows respectively using a shift register cell within the time of two rows Scanning signal, so as to realize the output of a shift register cell two row gate drive signals of correspondence, the shifting needed for reducing The number of bit register unit, significantly reduces to the space needed for gate driver circuit designing wiring, is conducive to reduction aobvious Show the volume of panel, realization manifests the narrow frame design of panel;The power consumption of display floater can also be reduced simultaneously.

Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising these changes and modification.

Claims (18)

1. a kind of shift register cell, it is characterised in that the shift register cell include input module, output module, Reseting module, drop-down control module and drop-down module, wherein,
The input module, for responding input signal and the first clock signal, using input signal by as the input mould The primary nodal point of block outfan is supplied to output module;
Low level voltage signal, for responding reset signal, is supplied to primary nodal point by the reseting module;
The output module, for responding the voltage signal of primary nodal point, second clock signal and the 3rd clock signal is provided To lead-out terminal;
The drop-down control module, for responding the first clock signal, second clock signal, the voltage signal of primary nodal point and answering Position signal, the first clock signal is supplied to the secondary nodal point of the outfan as the drop-down control module;And, in response to Low level voltage signal is supplied to secondary nodal point by the voltage signal of primary nodal point;
The drop-down module, for responding the voltage signal and the first clock signal of secondary nodal point, low level voltage signal is carried Supply primary nodal point and lead-out terminal;
Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3;
The output module includes:First output module, for responding the voltage signal of primary nodal point, second clock signal is carried Supply first lead-out terminal;Second output module, for responding the voltage signal of primary nodal point, the 3rd clock signal is supplied to Second lead-out terminal.
2. shift register cell as claimed in claim 1, it is characterised in that the input module includes:
First film transistor, its grid and drain electrode connection input signal end, source electrode connection primary nodal point;
Second thin film transistor (TFT), its grid connect the first clock signal terminal, drain electrode connection input signal end, source electrode connection first segment Point.
3. shift register cell as claimed in claim 1, it is characterised in that the reseting module includes:
3rd thin film transistor (TFT), its grid connection reset signal end, drain electrode connection primary nodal point, source electrode connection low level voltage letter Number.
4. shift register cell as claimed in claim 1, it is characterised in that first output module includes:
4th thin film transistor (TFT), its grid connect primary nodal point, and drain electrode connection second clock signal end, source electrode connection first are exported Terminal;
Electric capacity, is connected between primary nodal point and first lead-out terminal.
5. shift register cell as claimed in claim 1, it is characterised in that second output module includes:
5th thin film transistor (TFT), its grid connect primary nodal point, and drain electrode the 3rd clock signal terminal of connection, source electrode connection second are exported Terminal.
6. shift register cell as claimed in claim 1, it is characterised in that the drop-down control module includes:
First drop-down control module, for responding the voltage signal of the first clock signal, second clock signal and primary nodal point, will First clock signal is supplied to secondary nodal point;
First clock signal, for responding reset signal, is supplied to secondary nodal point by the second drop-down control module;
Low level voltage signal, for responding the voltage signal of primary nodal point, is supplied to second section by the 3rd drop-down control module Point.
7. shift register cell as claimed in claim 6, it is characterised in that the first drop-down control module includes:
6th thin film transistor (TFT), its grid and drain electrode connect the first clock signal terminal simultaneously, and source electrode connects the 3rd node;
7th thin film transistor (TFT), its grid connect the 3rd node, drain electrode the first clock signal terminal of connection, source electrode connection second section Point;
8th thin film transistor (TFT), its grid connect second clock signal end, drain electrode the first clock signal terminal of connection, source electrode connection the Three nodes;
9th thin film transistor (TFT), its grid connect primary nodal point, and drain electrode connection low level voltage signal, source electrode connect Section three Point.
8. shift register cell as claimed in claim 6, it is characterised in that the second drop-down control module includes:
Tenth thin film transistor (TFT), its grid connection reset signal end, drain electrode the first clock signal terminal of connection, source electrode connection second section Point.
9. shift register cell as claimed in claim 6, it is characterised in that the 3rd drop-down control module includes:
11st thin film transistor (TFT), its grid connect primary nodal point, drain electrode connection low level voltage signal, source electrode connection second section Point.
10. shift register cell as claimed in claim 1, it is characterised in that the drop-down module includes:
Low level voltage signal, for responding the voltage signal of secondary nodal point, is supplied to primary nodal point by the first drop-down module;
Low level voltage signal, for responding the voltage signal of secondary nodal point, is supplied to the first outfan by the second drop-down module Son and the second lead-out terminal;
Low level voltage signal, for responding the first clock signal, is supplied to first lead-out terminal and by the 3rd drop-down module Two lead-out terminals.
11. shift register cells as claimed in claim 10, it is characterised in that the first drop-down module includes:
12nd thin film transistor (TFT), its grid connect secondary nodal point, drain electrode connection primary nodal point, source electrode connection low level voltage letter Number.
12. shift register cells as claimed in claim 10, it is characterised in that the second drop-down module includes:
13rd thin film transistor (TFT), its grid connect secondary nodal point, drain electrode connection first lead-out terminal and the second lead-out terminal, source Pole connects low level voltage signal.
13. shift register cells as claimed in claim 10, it is characterised in that the 3rd drop-down module includes:
14th thin film transistor (TFT), its grid connect the first clock signal, drain electrode connection first lead-out terminal and the second outfan Son, source electrode connection low level voltage signal.
14. as described in claim 1~13 any claim shift register cell, it is characterised in that all film crystals Pipe is N-type or P-type TFT.
15. shift register cells as claimed in claim 14, it is characterised in that all thin film transistor (TFT)s are polysilicon membrane Transistor, or amorphous silicon film transistor is, or it is oxide thin film transistor.
A kind of 16. gate driver circuits, including the shift register cells at different levels of cascade;Wherein, first order shift register list The input signal end connection initial signal end of unit, the reset signal end connection next stage displacement of first order shift register cell are posted The lead-out terminal of storage unit;The input signal end connection upper level shift register cell of afterbody shift register cell Lead-out terminal, the reset signal end connection initial signal end of afterbody shift register cell;
In addition to the first order and afterbody shift register cell, the input signal end connection of remaining shift register cell at different levels The lead-out terminal of upper level shift register cell, reset signal end connect the lead-out terminal of next stage shift register cell;
Characterized in that, the shift register cell of all cascades is as described in claim 1~15 any claim Shift register cell.
17. a kind of display devices, it is characterised in that including gate driver circuit as claimed in claim 16.
A kind of 18. driving methods of the shift register cell as described in claim 1~15 any claim, its feature exist In methods described includes:
Input signal is supplied to primary nodal point in response to input signal and the first clock signal by input module;
Second clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;
3rd clock signal is supplied to lead-out terminal by voltage signal of the output module in response to primary nodal point;
Low level voltage signal is supplied to primary nodal point in response to reset signal by reseting module, and primary nodal point is discharged;It is drop-down Control module is in response to the first clock signal, and first clock signal is supplied to secondary nodal point, and secondary nodal point is charged; Low level voltage signal is supplied to primary nodal point in response to the voltage signal and the first clock signal of secondary nodal point by drop-down module And lead-out terminal;
Low level voltage signal is supplied to primary nodal point and lead-out terminal in response to second clock signal by drop-down control module;
Wherein, the dutycycle of first clock signal, second clock signal and the 3rd clock signal is 1/3.
CN201510187978.8A 2015-04-20 2015-04-20 Shift register cell and driving method, gate driver circuit and display device CN104732950B (en)

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CN105679248B (en) 2016-01-04 2017-12-08 京东方科技集团股份有限公司 Shift register cell and its driving method, gate driving circuit, display device
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CN107610736A (en) * 2017-09-27 2018-01-19 京东方科技集团股份有限公司 A kind of shift register, gate driving circuit and display device
CN107507598A (en) * 2017-09-28 2017-12-22 京东方科技集团股份有限公司 A kind of shift register, gate driving circuit and display device
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CN102968950B (en) * 2012-11-08 2015-06-24 京东方科技集团股份有限公司 Shifting register unit and array substrate gate drive device
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