CN111179797A

CN111179797A - Shifting register unit and driving method thereof, grid driving circuit and related device

Info

Publication number: CN111179797A
Application number: CN201811345137.5A
Authority: CN
Inventors: 袁志东; 李永谦; 袁粲; 谢恩明
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2018-11-13
Filing date: 2018-11-13
Publication date: 2020-05-19
Anticipated expiration: 2038-11-13
Also published as: US20200394960A1; CN111179797B; US11037502B2; WO2020098309A1; EP3882902A1; EP3882902A4

Abstract

The invention discloses a shift register unit and a driving method thereof, a grid driving circuit and a related device. Therefore, each shift register unit can output a plurality of scanning signals to correspond to different grid lines in the array substrate. Compared with the prior shift register unit which can only output one scanning signal, the shift register unit can reduce the number of shift registers in the grid driving circuit, reduce the occupied space of the grid driving circuit and realize the design of an ultra-narrow frame. In addition, because the signals of different output control nodes have no influence on each other, the stability of the waveform of the output scanning signal can be improved, and the waveform difference of the scanning signal is avoided.

Description

Shifting register unit and driving method thereof, grid driving circuit and related device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof, a gate driving circuit, an array substrate and a display device.

Background

With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. In the Gate Driver on Array (GOA) technology, a Thin Film Transistor (TFT) Gate Driver Circuit is Integrated on an Array substrate of a display panel to form a scan Driver for the display panel, so that a wiring space of a Bonding area and a Fan-out area of the Gate Integrated Circuit (IC) can be omitted. The general gate driving circuit is composed of a plurality of cascaded shift register units, each shift register unit is correspondingly connected with a gate line, so that scanning signals are sequentially input to the gate lines on the display panel through the shift register units. However, since the gate lines of each row are correspondingly connected to one shift register unit, the structure design of the gate driving circuit is complicated, and the space occupied by the gate driving circuit is large, which is not favorable for the narrow frame design.

Disclosure of Invention

The embodiment of the invention provides a shift register unit, a driving method thereof, a gate driving circuit, an array substrate and a display device, which can reduce the number of shift register units in the gate driving circuit, thereby reducing the structural design complexity and the occupied space of the gate driving circuit and further realizing narrow frame design.

An embodiment of the present invention provides a shift register unit, including: the circuit comprises a signal control circuit, a branch control circuit, a cascade signal output circuit and a plurality of scanning signal output circuits;

the signal control circuit is configured to control a signal of the first node and a signal of the second node in response to an input signal and a reset signal;

the branch control circuit is configured to control signals of output control nodes in one-to-one correspondence with the respective scan signal output circuits in response to a signal of the first node;

the cascade signal output circuit is configured to output a cascade signal in response to signals of the first node and the second node;

each of the scan signal output circuits is configured to output a different scan signal in response to a signal of the corresponding output control node and a signal of the second node.

Optionally, in an embodiment of the present invention, there are two scan signal output circuits, and the branch control circuit includes: a first transistor and a second transistor;

a gate and a first pole of the first transistor are both coupled to the first node, and a second pole of the first transistor is coupled to an output control node corresponding to a first scanning signal output circuit of the two scanning signal output circuits; a gate and a first pole of the second transistor are both coupled to the first node, and a second pole of the second transistor is coupled to an output control node corresponding to a second scanning signal output circuit of the two scanning signal output circuits; or,

a gate of the first transistor is configured to receive a first reference signal, a first pole of the first transistor is coupled to the first node, and a second pole of the first transistor is coupled to an output control node corresponding to the first scan signal output circuit; the gate of the second transistor is used for receiving the first reference signal, the first poles of the second transistors are coupled to the first node, and the second poles of the second transistors are coupled to the output control node corresponding to the second scanning signal output circuit.

Optionally, in an embodiment of the present invention, the number of the scan signal output circuits is two, and a first scan signal output circuit of the two scan signal output circuits includes: at least 1 first sub-scanning signal output circuit; each of the first sub-scanning signal output circuits corresponds to one first clock signal one by one, and each of the first sub-scanning signal output circuits corresponds to one first sub-scanning signal output end one by one;

the first sub-scanning signal output circuit is configured to provide the corresponding first clock signal to the corresponding first sub-scanning signal output terminal in response to a signal of the same output control node; and providing a second reference signal to the corresponding first sub-scan signal output terminal in response to the signal of the second node.

Optionally, in an embodiment of the present invention, the first sub-scanning signal output circuit includes: a third transistor, a fourth transistor and a first capacitor;

a gate of the third transistor is coupled to the corresponding output control node, a first pole of the third transistor is used for receiving the corresponding first clock signal, and a second pole of the third transistor is coupled to the corresponding first sub-scan signal output terminal;

a gate of the fourth transistor is coupled to the second node, a first pole of the fourth transistor is configured to receive the second reference signal, and a second pole of the fourth transistor is coupled to the corresponding first sub-scan signal output terminal;

the first capacitor is coupled between the corresponding output control node and the first sub-scanning signal output end.

Optionally, in an embodiment of the present invention, there are two scan signal output circuits, and a second scan signal output circuit of the two scan signal output circuits includes: at least 1 second sub-scanning signal output circuit; each second sub-scanning signal output circuit corresponds to a second clock signal one by one, and each second sub-scanning signal output circuit corresponds to a second sub-scanning signal output end one by one;

the second sub-scanning signal output circuit is configured to provide the corresponding second clock signal to the corresponding second sub-scanning signal output terminal in response to a signal of the same output control node; and providing a second reference signal to a corresponding second sub-scan signal output terminal in response to the signal of the second node.

Optionally, in an embodiment of the present invention, the second sub-scanning signal output circuit includes: a fifth transistor, a sixth transistor, and a second capacitor;

a gate of the fifth transistor is coupled to the corresponding output control node, a first pole of the fifth transistor is configured to receive the corresponding second clock signal, and a second pole of the fifth transistor is coupled to the corresponding second sub-scan signal output terminal;

a gate of the sixth transistor is coupled to the second node, a first pole of the sixth transistor is configured to receive the second reference signal, and a second pole of the sixth transistor is coupled to the corresponding second sub-scan signal output terminal;

the second capacitor is coupled between the corresponding output control node and the second sub-scanning signal output end.

Optionally, in an embodiment of the present invention, the cascade signal output circuit is configured to provide a third clock signal to the cascade signal output terminal in response to the signal of the first node; and providing a third reference signal to the cascade signal output in response to the signal of the second node.

Optionally, in an embodiment of the present invention, the cascade signal output circuit includes: a seventh transistor, an eighth transistor, and a third capacitor;

a gate of the seventh transistor is coupled to the first node, a first pole of the seventh transistor is configured to receive the third clock signal, and a second pole of the seventh transistor is coupled to the cascade signal output terminal;

a gate of the eighth transistor is coupled to the second node, a first pole of the eighth transistor is configured to receive the third reference signal, and a second pole of the eighth transistor is coupled to the cascade signal output terminal;

the third capacitor is coupled between the first node and the cascade signal output end.

Optionally, in an embodiment of the present invention, the signal control circuit includes: an input circuit, a reset circuit, a node control circuit;

the input circuit is configured to provide a first reference signal to the first node in response to the input signal;

the reset circuit is configured to provide a third reference signal to an output control node corresponding to each of the scan signal output circuits in response to a reset signal;

the node control circuit is configured to control a signal of the first node and a signal of each of the output control nodes to be opposite in level to a signal of the second node, respectively.

Optionally, in an embodiment of the present invention, there are two scan signal output circuits, and the input circuit includes: a ninth transistor; wherein a gate of the ninth transistor is configured to receive the input signal, a first pole of the ninth transistor is configured to receive the first reference signal, and a second pole of the ninth transistor is coupled to the first node;

the reset circuit includes: a tenth transistor and an eleventh transistor; wherein a gate of the tenth transistor is configured to receive the reset signal, a first pole of the tenth transistor is configured to receive the third reference signal, and a second pole of the tenth transistor is coupled to an output control node; a gate of the eleventh transistor is configured to receive the reset signal, a first pole of the eleventh transistor is configured to receive the third reference signal, and a second pole of the eleventh transistor is coupled to another output control node;

the node control circuit includes: a twelfth transistor, a thirteenth transistor, and an inverter; wherein a gate of the twelfth transistor is coupled to the second node, a first pole of the twelfth transistor is configured to receive the third reference signal, and a second pole of the twelfth transistor is coupled to an output control node; a gate of the thirteenth transistor is coupled to the second node, a first pole of the thirteenth transistor is configured to receive the third reference signal, and a second pole of the thirteenth transistor is coupled to another output control node; an input of the inverter is coupled to the first node and an output of the inverter is coupled to the second node.

Optionally, in an embodiment of the present invention, the reset circuit further includes: a fourteenth transistor; wherein a first pole of the tenth transistor and a first pole of the eleventh transistor receive the third reference signal through the fourteenth transistor, respectively; a gate of the fourteenth transistor is configured to receive the reset signal;

the node control circuit further includes: a fifteenth transistor; wherein a first pole of the twelfth transistor and a first pole of the thirteenth transistor each receive the third reference signal through the fifteenth transistor; a gate of the fifteenth transistor is coupled to the second node.

Optionally, in an embodiment of the present invention, the shift register unit further includes: a detection circuit; the detection circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a fourth capacitor;

a gate of the sixteenth transistor is configured to receive a first detection control signal, a first pole of the sixteenth transistor is configured to receive the input signal, and a second pole of the sixteenth transistor is coupled to a first pole of the eighteenth transistor;

a gate of the seventeenth transistor is configured to receive the first detection control signal, a first pole of the seventeenth transistor is coupled to the gate of the nineteenth transistor, and a second pole of the seventeenth transistor is coupled to the first pole of the eighteenth transistor;

a gate of the eighteenth transistor is coupled to a gate of the nineteenth transistor, a second pole of the eighteenth transistor is configured to receive a fourth reference signal;

a first pole of the nineteenth transistor to receive the fourth reference signal, a second pole of the nineteenth transistor coupled to the first pole of the twentieth transistor;

a gate of the twentieth transistor is configured to receive a second detection control signal, a second pole of the twentieth transistor is coupled to the first node;

the fourth capacitor is coupled between the first pole of the nineteenth transistor and the gate of the nineteenth transistor.

Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift register units provided by the embodiment of the invention;

the input signal of the first stage shift register unit is input from a frame start signal end;

in each adjacent four-stage shift register unit, the input signal of the fourth-stage shift register unit is input by the cascade signal of the first-stage shift register unit;

in each adjacent five-stage shift register unit, the reset signal of the first-stage shift register unit is input by the cascade signal of the fifth-stage shift register unit.

Correspondingly, the embodiment of the invention also provides an array substrate which comprises the gate drive circuit provided by the embodiment of the invention.

Correspondingly, the embodiment of the invention also provides a display device which comprises the array substrate provided by the embodiment of the invention.

Correspondingly, an embodiment of the present invention further provides a driving method for a shift register unit, including: a display scanning stage; wherein the display scan phase comprises: an input stage, an output stage and a reset stage;

in the input stage, the signal control circuit controls a signal of a first node and a signal of a second node in response to an input signal; the branch control circuit controls signals of output control nodes corresponding to the scanning signal output circuits one to one in response to the signals of the first nodes; the cascade signal output circuit outputs a cascade signal in response to a signal of the first node; each of the scan signal output circuits outputs a different scan signal in response to a signal of a corresponding output control node;

in the output stage, the branch control circuit responds to the signal of the first node and controls the signal of an output control node corresponding to each scanning signal output circuit one by one; the cascade signal output circuit outputs a cascade signal in response to a signal of the first node; each of the scan signal output circuits outputs a different scan signal in response to a signal of a corresponding output control node;

in the reset phase, the signal control circuit controls a signal of the first node and a signal of the second node in response to a reset signal; the cascade signal output circuit outputs a cascade signal in response to a signal of the first node; each of the scan signal output circuits outputs a different scan signal in response to a signal of a corresponding output control node.

Optionally, in an embodiment of the present invention, the number of the scan signal output circuits is two, and a first scan signal output circuit of the two scan signal output circuits includes: a plurality of first sub-scanning signal output circuits; the second scan signal output circuit includes: a plurality of second sub-scanning signal output circuits;

each of the first sub-scanning signal output circuits supplies the corresponding first clock signal to the corresponding first sub-scanning signal output terminal in response to a signal of the corresponding output control node in the input stage and the output stage; each second sub-scanning signal output circuit responds to the signal of the corresponding output control node and provides the corresponding second clock signal to the corresponding second sub-scanning signal output end; the cascade signal output circuit provides a third clock signal to a cascade signal output end in response to the signal of the first node;

in the reset phase, each first sub-scanning signal output circuit responds to the signal of the second node and provides a second reference signal to a corresponding first sub-scanning signal output end; each second sub-scanning signal output circuit responds to the signal of the second node and provides the second reference signal to a corresponding second sub-scanning signal output end; the cascade signal output circuit provides a third reference signal to the cascade signal output terminal in response to the signal of the second node.

Optionally, in the embodiment of the present invention, in the display scanning stage, the timings of the first clock signals are the same, the timings of the second clock signals are the same, and the timings of the first clock signals and the timings of the second clock signals are different.

Optionally, in this embodiment of the present invention, the periods of the first clock signal, the second clock signal, and the third clock signal are the same;

in the same cycle, a rising edge of the third clock signal occurs before a rising edge of the first clock signal, and a falling edge of the third clock signal occurs after a falling edge of the second clock signal.

The invention has the following beneficial effects:

according to the shift register unit, the driving method thereof, the gate driving circuit, the array substrate and the display device provided by the embodiment of the invention, the signal control circuit responds to the input signal and the reset signal to control the signal of the first node and the signal of the second node. By the branch control circuit being configured to control the signals of the output control nodes in one-to-one correspondence with the respective scanning signal output circuits in response to the signal of the first node, different output control nodes can be divided so that the signals of the other output control nodes may not be affected when the signal of the output control node changes. And outputting the cascade signal by the cascade signal output circuit in response to the signals of the first node and the second node to provide an input signal for the shift register unit of the next stage. By providing a plurality of scan signal output circuits to output different scan signals in response to the signal of the corresponding output control node and the signal of the second node through each scan signal output circuit. Therefore, each shift register unit can output a plurality of scanning signals to correspond to different grid lines in the array substrate. Compared with the prior shift register unit which can only output one scanning signal, the shift register unit can reduce the number of shift registers in the grid driving circuit, reduce the occupied space of the grid driving circuit and realize the design of an ultra-narrow frame. In addition, because the signals of different output control nodes have no influence on each other, the stability of the waveform of the output scanning signal can be improved, and the waveform difference of the scanning signal is avoided.

Drawings

FIG. 1 is a schematic diagram of a shift register unit according to the related art;

FIG. 2 is a signal simulation diagram of the shift register unit shown in FIG. 1;

FIG. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of a circuit according to an embodiment of the present invention;

FIG. 6 is a simulation timing diagram after simulation of the shift register unit shown in FIG. 4;

fig. 7 is a second schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 8 is a second timing diagram of the circuit according to the second embodiment of the present invention;

fig. 9 is a third schematic structural diagram of a shift register unit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention;

FIG. 11 is a third timing diagram of the circuit according to the embodiment of the present invention;

FIG. 12 is a fourth exemplary diagram illustrating a shift register unit according to an embodiment of the present invention;

fig. 13 is a flowchart of a driving method according to an embodiment of the present invention;

fig. 14a is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 14b is a second schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register unit, a driving method thereof, a gate driving circuit and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict. It should be noted that the shapes of the drawings are not to scale and are merely intended to illustrate the invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, in order to realize outputting a plurality of scan signals, a shift register unit may be provided with a plurality of scan signal output circuits 01, for example, two scan signal output circuits 01 are provided in fig. 1; one of the scan signal output circuits 01 outputs a scan signal G1, and the other scan signal output circuit 01 outputs a scan signal G2. Specifically, the signal of the pull-up node a and the signal of the pull-down node B are controlled by the signal control circuit. The scan signal output circuit 01 that outputs the scan signal G1 includes: transistors M01 and M02 and a capacitor C01; the gate of the transistor M01 is coupled to the pull-up node a, the first pole of the transistor M01 is used for receiving the clock signal CK1, and the second pole of the transistor M01 is used for outputting the scan signal G1. The gate of transistor M02 is coupled to the pull-down node B, a first pole of transistor M02 is configured to receive the signal VGL, and a second pole of transistor M02 is coupled to the second pole of transistor 01. The capacitor C01 is coupled between the pull-up node a and the second pole of the transistor 01. The scan signal output circuit 01 that outputs the scan signal G2 includes: transistors M03 and M04 and a capacitor C02; the gate of the transistor M03 is coupled to the pull-up node a, the first pole of the transistor M03 is used for receiving the clock signal CK2, and the second pole of the transistor M03 is used for outputting the scan signal G2. The gate of the transistor M04 is coupled to the pull-down node B, the first pole of the transistor M04 is for receiving the signal VGL, and the second pole of the transistor M04 is coupled to the second pole of the transistor 03. The capacitor C02 is coupled between the pull-up node a and the second pole of the transistor 03. The transistor M01 can provide the clock signal CK1 to the second terminal thereof under the control of the signal of the pull-up node a to output as the scan signal G1. The transistor 03 may supply a signal of the clock signal CK2 to a second terminal thereof under the control of the signal of the pull-up node a to output as the scan signal G2. The analog timing diagram can be obtained by simulation of the clock signals CK1, CK2, the signal a of the pull-up node a, the signal B of the pull-down node B, and the scan signals G1 and G2, as shown in fig. 2. Since the high level of the clock signal CK1 occurs earlier than the high level of the clock signal CK2, the transistor 01 will pull up the level of the pull-up node a when it is turned on under the control of the signal of the pull-up node a to output the signal of the high level of the clock signal CK1 as the scan signal G1. When the transistor 02 is turned on under the control of the signal of the pull-up node a to output the high-level signal of the clock signal CK2 as the scan signal G2, the level of the pull-up node a is further pulled up. Since the transistor 01 and the transistor 03 are both controlled by the signal a at the same pull-up node a, and the high level of the clock signal CK1 is preferentially transited to the low level, the falling Time RFT (12us) of the scan signal G1 from the high level to the low level is shorter than the falling Time RFT (14us) of the scan signal G2 from the high level to the low level, so that the waveforms of the output scan signals G1 and G2 are different.

Based on this, an embodiment of the present invention provides a shift register unit, as shown in fig. 3, which may include: the signal control circuit 10, the branch control circuit 20, the cascade signal output circuit 30, and the plurality of scanning signal output circuits 40_ M (1 ≦ M, where M represents the total number of scanning signal output circuits, and M ≦ 2 is taken as an example in fig. 3); wherein,

the signal control circuit 10 is configured to control the signal of the first node PU and the signal of the second node PD in response to the INPUT signal INPUT and the reset signal RE;

the branch control circuit 20 is configured to control the signals of the output control nodes PO _ m in one-to-one correspondence with the respective scan signal output circuits 40_ m in response to the signal of the first node PU;

the cascade signal output circuit 30 is configured to output the cascade signal CR in response to the signals of the first node PU and the second node PD;

each scan signal output circuit 40_ m is configured to output a different scan signal goutm in response to the signal of the corresponding output control node PO _ m and the signal of the second node PD.

The shift register unit provided in the embodiment of the present invention responds to an input signal and a reset signal through a signal control circuit to control a signal of a first node and a signal of a second node. By the branch control circuit being configured to control the signals of the output control nodes in one-to-one correspondence with the respective scanning signal output circuits in response to the signal of the first node, different output control nodes can be divided so that the signals of the other output control nodes may not be affected when the signal of the output control node changes. And outputting the cascade signal by the cascade signal output circuit in response to the signals of the first node and the second node to provide an input signal for the shift register unit of the next stage. By providing a plurality of scan signal output circuits to output different scan signals in response to the signal of the corresponding output control node and the signal of the second node through each scan signal output circuit. Therefore, each shift register unit can output a plurality of scanning signals to correspond to different grid lines in the array substrate. Compared with the prior shift register unit which can only output one scanning signal, the shift register unit can reduce the number of shift registers in the grid driving circuit, reduce the occupied space of the grid driving circuit and realize the design of an ultra-narrow frame. In addition, because the signals of different output control nodes have no influence on each other, the stability of the waveform of the output scanning signal can be improved, and the waveform difference of the scanning signal is avoided.

In practical implementation, in the embodiment of the present invention, the first node PU may be a pull-up node, and the second node PD may be a pull-down node.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the signal control circuit 10 may include: the input circuit 11, the reset circuit 12, and the node control circuit 13 control the levels of the signals of the first node PU, the output control node PO _ m, and the second node PD by the cooperation of the input circuit 11, the reset circuit 12, and the node control circuit 13. Wherein the INPUT circuit 11 is configured to provide a signal of a first reference signal VREF1 to the first node PU in response to the INPUT signal INPUT. The reset circuit 12 is configured to supply the signal of the third reference signal terminal VREF3 to the output control node PO _ m corresponding to each scan signal output circuit 40_ m in response to the reset signal RE. The node control circuit 13 is configured to control the signal of the first node PU and the signal of each output control node PO _ m to be opposite in level to the signal of the second node PD, respectively.

In particular implementation, in an embodiment of the present invention, as shown in fig. 4, the cascade signal output circuit 30 is configured to provide the third clock signal CLK3 to the cascade signal output terminal CROUT in response to the signal of the first node PD; and providing the signal of the third reference signal terminal VREF3 to the cascade signal output terminal CROUT in response to the signal of the second node PD.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.

The first embodiment,

In practical implementation, in the embodiment of the present invention, as shown in fig. 3 and 4, the number of the scan signal output circuits may be two. Alternatively, the number of the scanning signal output circuits may be three, four, five, or the like. Of course, in practical applications, the number of the scan signal output circuits may be determined according to practical application environments, and is not limited herein. The following description will be made by taking an example in which the number of scanning signal output circuits is two.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the first scan signal output circuit 40_1 of the two scan signal output circuits may include: at least 1 first sub-scanning signal output circuits 41 — N (1 ≦ N, where N represents the total number of first sub-scanning signal output circuits, and fig. 4 takes N ≦ 1 as an example); each of the first sub-scan signal output circuits 41_ n corresponds to one first clock signal CLK1_ n, and each of the first sub-scan signal output circuits 41_ n corresponds to one first sub-scan signal output terminal GOUT1_ n. Also, the first sub scanning signal output circuits 41_ n are configured to provide the corresponding first clock signal CLK1_ n to the corresponding first sub scanning signal output terminals GOUT1_ n in response to a signal of the same output control node, i.e., the first sub scanning signal output circuits 41_ n are configured to provide the corresponding first clock signal CLK1_ n to the corresponding first sub scanning signal output terminals GOUT1_ n in response to a signal of the output control node PO _ 1; and providing a second reference signal VREF2 to the corresponding first sub-scanning signal output terminal GOUT1_ n in response to the signal of the second node PD. The first sub-scanning signal output terminals GOUT1_ n respectively output scanning signals GOUT1_ n.

Further, in implementation, as shown in fig. 4, 1 first sub-scanning signal output circuit may be provided; or 2 first sub-scanning signal output circuits may be provided. In practical applications, the specific number of the first sub-scanning signal output circuits may be determined according to practical application environments, and is not limited herein. The following description will be given taking an example in which 1 first sub-scanning signal output circuit is provided.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the second scan signal output circuit 40_2 of the two scan signal output circuits may include: at least 1 second sub-scanning signal output circuits 42_ K (1 ≦ K, where K represents the total number of second sub-scanning signal output circuits, and K ≦ 1 is taken as an example in fig. 4); each of the second sub-scan signal output circuits 42_ k corresponds to one second clock signal CLK2_ k, and each of the second sub-scan signal output circuits 42_ k corresponds to one second sub-scan signal output terminal GOUT2_ k. Also, the second sub-scan signal output circuits 42_ k are configured to provide the corresponding second clock signal CLK2_ k to the corresponding second sub-scan signal output terminals GOUT2_ k in response to a signal of the same output control node, i.e., the second sub-scan signal output circuits 42_ k are configured to provide the corresponding second clock signal CLK2_ k to the corresponding second sub-scan signal output terminals GOUT2_ k in response to a signal of the output control node PO _ 2; and providing a second reference signal VREF2 to the corresponding second sub-scanning signal output terminal GOUT2_ k in response to the signal of the second node PD. The second sub-scanning signal output terminals GOUT2_ k output scanning signals GOUT2_ k, respectively.

Further, in implementation, as shown in fig. 4, 1 second sub-scanning signal output circuit may be provided; or 2 second sub-scanning signal output circuits may be provided. In practical applications, the specific number of the second sub-scanning signal output circuits may be determined according to practical application environments, and is not limited herein. The following description will be given taking an example in which 1 second sub-scanning signal output circuit is provided.

Further, in practical implementation, in the embodiment of the present invention, N may be K.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the branch control circuit 20 may include: a first transistor M1 and a second transistor M2; the gate and the first pole of the first transistor M1 are both coupled to the first node PU, and the second pole of the first transistor M1 is coupled to the output control node PO _1 corresponding to the first scan signal output circuit 40_1 of the two scan signal output circuits; the gate and the first pole of the second transistor M2 are both coupled to the first node PU, and the second pole of the second transistor M2 is coupled to the output control node PO _2 corresponding to the second scan signal output circuit 40_2 of the two scan signal output circuits.

In practical implementation, since the gate of the first transistor M1 is coupled to the first pole, the first transistor M1 forms a diode connection, so that when the voltage of the gate of the first transistor M1 is greater than the voltage of the second pole thereof, the first transistor M1 can form a path to make the first node PU and the output control node PO _1 conduct; when the voltage of the gate of the first transistor M1 is not greater than the voltage of the second pole thereof, the first transistor M1 may form an open circuit to disconnect the first node PU from the output control node PO _ 1. Similarly, when the voltage of the gate of the second transistor M2 is greater than the voltage of the second pole thereof, the second transistor M2 may form a path to turn on the first node PU and the output control node PO _ 2; when the voltage of the gate of the second transistor M2 is not greater than the voltage of the second pole thereof, the second transistor M2 may form an open circuit to disconnect the first node PU from the output control node PO _2.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the first sub scanning signal output circuit 41 — n may include: a third transistor M3, a fourth transistor M4, and a first capacitor C1; the gate of the third transistor M3 is coupled to the corresponding output control node PO _1, the first pole of the third transistor M3 is used for receiving the corresponding first clock signal CLK1_ n, and the second pole of the third transistor M3 is coupled to the corresponding first sub-scan signal output terminal GOUT1_ n. The gate of the fourth transistor M4 is coupled to the second node PD, the first pole of the fourth transistor M4 is used for receiving the second reference signal VREF2, and the second pole of the fourth transistor M4 is coupled to the corresponding first sub-scan signal output terminal GOUT1_ n. The first capacitor C1 is coupled between the corresponding output control node PO _1 and the first sub-scan signal output terminal GOUT1 — n.

In practical implementation, in the embodiment of the invention, the third transistor M3 in each of the first sub-scan signal output circuits 41_ n can be in a conducting state under the control of the signal of the output control node PO _1 to provide the corresponding first clock signal CLK1_ n to the corresponding first sub-scan signal output terminal GOUT1_ n. The fourth transistor M4 in each of the first sub-scanning signal output circuits 41_ n may be in a turned-on state under the control of the signal of the second node PD to provide the second reference signal VREF2 to the corresponding first sub-scanning signal output terminal GOUT1_ n. The first capacitor C1 can maintain the level of the connected output control node PO _1 and the level of the first sub-scanning signal output terminal GOUT1_ n, and can maintain a stable voltage difference between the output control node PO _1 and the first sub-scanning signal output terminal GOUT1_ n when the output control node PO _1 is floated.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the second sub-scanning signal output circuit 42 — k may include: a fifth transistor M5, a sixth transistor M6, and a second capacitor C2; the gate of the fifth transistor M5 is coupled to the corresponding output control node PO _2, the first pole of the fifth transistor M5 is configured to receive the corresponding second clock signal CLK2_ k, and the second pole of the fifth transistor M5 is coupled to the corresponding second sub-scan signal output terminal GOUT2_ k. The gate of the sixth transistor M6 is coupled to the second node PD, the first pole of the sixth transistor M6 is used for receiving the second reference signal VREF2, and the second pole of the sixth transistor M6 is coupled to the corresponding second sub-scan signal output terminal GOUT2_ k. The second capacitor C2 is coupled between the corresponding output control node PO _2 and the second sub-scanning signal output terminal GOUT2 — k.

In practical implementation, in the embodiment of the invention, the fifth transistor M5 in each of the second sub-scan signal output circuits 42_ k may be in a conducting state under the control of the signal of the output control node PO _2 to provide the corresponding second clock signal CLK2_ k to the corresponding second sub-scan signal output terminal GOUT2_ k. The sixth transistor M6 in each of the second sub-scanning signal output circuits 42_ k may be in a turned-on state under the control of the signal of the second node PD to provide the second reference signal VREF2 to the corresponding second sub-scanning signal output terminal GOUT2_ k. The second capacitor C2 can maintain the level of the connected output control node PO _2 and the level of the second sub-scanning signal output terminal GOUT2_ k, and can maintain a stable voltage difference between the output control node PO _2 and the second sub-scanning signal output terminal GOUT2_ k when the output control node PO _2 is floated.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the input circuit 11 may include: a ninth transistor M9; a gate of the ninth transistor M9 is for receiving the INPUT signal INPUT, a first pole of the ninth transistor M9 is for receiving the first reference signal VREF1, and a second pole of the ninth transistor M9 is coupled to the first node PU. Wherein, the ninth transistor M9 may be in a conductive state under the control of the INPUT signal INPUT to provide the first reference signal VREF1 to the first node PU.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the reset circuit 12 may include: a tenth transistor M10 and an eleventh transistor M11; wherein a gate of the tenth transistor M10 is for receiving the reset signal RE, a first pole of the tenth transistor M10 is for receiving the third reference signal VREF3, and a second pole of the tenth transistor M10 is coupled to an output control node, i.e., the output control node PO _ 1. A gate of the eleventh transistor M11 is for receiving the reset signal RE, a first pole of the eleventh transistor M11 is for receiving the third reference signal VREF3, and a second pole of the eleventh transistor M11 is coupled to another output control node, i.e., the output control node PO _2. Wherein, the tenth transistor M10 may be in a turn-on state under the control of the active pulse signal of the reset signal RE to provide the third reference signal VREF3 to the output control node PO _ 1. The eleventh transistor M11 may be in a turn-on state under the control of the reset signal RE to provide the third reference signal VREF3 to the output control node PO _2.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the node control circuit 13 may include: a twelfth transistor M12, a thirteenth transistor M13, and an inverter ND; wherein a gate of the twelfth transistor M12 is coupled to the second node PD, a first pole of the twelfth transistor M12 is configured to receive the third reference signal VREF3, and a second pole of the twelfth transistor M12 is coupled to an output control node, i.e., the output control node PO _ 1; a gate of the thirteenth transistor M3 is coupled to the second node PD, a first pole of the thirteenth transistor M13 is for receiving a third reference signal VREF3, and a second pole of the thirteenth transistor M13 is coupled to another output control node, i.e., the output control node PO _2. An input terminal of the inverter ND is coupled to the first node PU, and an output terminal of the inverter ND is coupled to the second node PD. Wherein, the twelfth transistor M12 may be in a turn-on state under the control of the signal of the second node PD to provide the third reference signal VREF3 to the output control node PO _ 1. The thirteenth transistor M13 may be in a turn-on state under the control of the signal of the second node PD to provide the third reference signal VREF3 to the output control node PO _2. An inverter may have its input terminal opposite in level to its output terminal.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the cascade signal output circuit 30 may include: a seventh transistor M7, an eighth transistor M8, and a third capacitor C3; wherein a gate of the seventh transistor M7 is coupled to the first node PU, a first pole of the seventh transistor M7 is configured to receive the third clock signal CLK3, and a second pole of the seventh transistor M7 is coupled to the cascade signal output terminal CROUT. The gate of the eighth transistor M8 is coupled to the second node PD, the first pole of the eighth transistor M8 is configured to receive the third reference signal VREF3, and the second pole of the eighth transistor M8 is coupled to the cascade signal output terminal CROUT. The third capacitor C3 is coupled between the first node PU and the cascade signal output terminal CROUT. Wherein the seventh transistor M7 may be in a conductive state under the control of the signal of the first node PU to provide the third clock signal CLK3 to the cascade signal output terminal CROUT. The eighth transistor M8 may be in a turn-on state under the control of the signal of the second node PD to provide the third reference signal VREF3 to the cascade signal output terminal CROUT. The third capacitor C3 may maintain the level of the first node PU and the level of the cascade signal output terminal CROUT, and may maintain a stable voltage difference between the first node PU and the cascade signal output terminal CROUT when the first node PU is floating.

The specific structure of each circuit in the shift register unit is only illustrated, and in the specific implementation, the specific structure of each circuit is not limited to the structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In specific implementation, in order to make the manufacturing process uniform, in the embodiment of the present invention, as shown in fig. 4, all the switch transistors may be N-type transistors. It should be noted that the embodiment of the present invention is only described by taking the transistor in the shift register unit as an N-type transistor as an example, and the design principle of the case where the transistor is a P-type transistor is the same as that of the present invention, and also falls within the protection scope of the present invention.

It should be noted that, in the embodiment of the present invention, when all the transistors are N-type transistors, the first reference signal is a high level signal, and the second reference signal and the third reference signal are low level signals. When all the transistors are P-type transistors, the first reference signal is a low level signal, and the second reference signal and the third reference signal are high level signals. It should be noted that the levels of the signals mentioned in the embodiments of the present invention only represent the logic levels, and not the actual applied voltage values of the signals in the specific implementation.

A frame time in general at the time of display driving may include a display scan phase and a blank time (blanking) phase. In a specific implementation, in the display scanning stage, the timings of the first clock signals are the same, the timings of the second clock signals are the same, and the timings of the first clock signals and the second clock signals are different. For example, as shown in FIG. 5, the first clock signal CLK1_1 is clocked differently than the second clock signal CLK2_ 1. It should be noted that, in the embodiments of the present invention, the voltage values of the high-level signals are the same, for example, the voltage value of the high level of the INPUT signal INPUT, the voltage value of the high level of the first clock signal CLK1_1, the voltage value of the high level of the second clock signal CLK2_1, and the voltage value of the first reference signal VREF1 are the same. Further, the voltage values of the low-level signals mentioned in the embodiments of the present invention may also be the same, for example, the voltage value of the low level of the INPUT signal INPUT, the voltage value of the low level of the first clock signal CLK1_1, the voltage value of the low level of the second clock signal CLK2_1, the voltage value of the second reference signal VREF2, and the voltage value of the third reference signal VREF3 are the same. In order to reduce the number of signal terminals and the occupied space of signal lines, the second reference signal VREF2 and the third reference signal VREF3 may be set to be the same signal, i.e., the second reference signal VREF2 and the third reference signal VREF3 are provided by using the same reference signal terminal.

In one implementation, as shown in fig. 5, the periods of the first clock signal CLK1_ n, the second clock signal CLK2_ k, and the third clock signal CLK3 are the same. For example, in one cycle, the duration of the high level signal of the first clock signal CLK1_ n may be 4a, the duration of the low level signal may be 6a, and the duration of one cycle of the first clock signal CLK1_ n may be 10 a. In one period, the duration of the high level signal of the second clock signal CLK2_ n may be 4a, the duration of the low level signal may be 6a, and the duration of one period of the second clock signal CLK2_ n may be 10 a. In one period, the duration of the high level signal of the third clock signal CLK3 may be 5a, the duration of the low level signal may be 5a, and the duration of one period of the third clock signal CLK3 may also be 10 a. Further, in the same cycle, the rising edge of the third clock signal CLK3 occurs before the rising edge of the first clock signal CLK1_ n, and the falling edge of the third clock signal CLK3 occurs after the falling edge of the second clock signal CLK2_ n. For example, as shown in fig. 5, in the same cycle, the rising edge of the third clock signal CLK3 is aligned with the rising edge of the first clock signal CLK1_1, and the falling edge of the third clock signal CLK3 is aligned with the falling edge of the second clock signal CLK2_ 1.

In specific implementation, in the shift register unit provided in the embodiment of the present invention, the N-type transistor is turned on under the action of a high level signal and turned off under the action of a low level signal; the P-type transistor is turned on under the action of a low-level signal and turned off under the action of a high-level signal. In a specific implementation, the first pole of the transistor may serve as a source and the second pole as a drain, or the first pole of the transistor may serve as a drain and the second pole as a source, which are not specifically distinguished herein.

The following describes the operation process of the shift register unit provided in the embodiment of the present invention with reference to a circuit timing diagram, that is, fig. 5, by taking the structure of the shift register unit shown in fig. 4 as an example. In the following description, a high level signal is denoted by 1, and a low level signal is denoted by 0, where 1 and 0 represent logic levels thereof, which are provided only for better explaining the operation process of the shift register unit provided by the embodiment of the present invention, and are not voltage values applied to the gates of the transistors in specific implementation.

Specifically, the input phase T1, the output phase T2, and the reset phase T3 in the circuit timing diagram shown in fig. 5 are selected.

In the INPUT phase T1, INPUT is 1, CLK1_1 is 0, CLK2_1 is 0, CLK3 is 0, and RE is 0.

Since INPUT is equal to 1, the ninth transistor M9 is turned on to provide the first reference signal VREF1 of high level to the first node PU, so that the signal of the first node PU is a high level signal. Since the signal of the first node PU is a high level signal, the seventh transistor M7 is turned on, and acts through the inverter ND, so that the signal of the second node PD is a low level signal. Thereby controlling the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 to be turned off. The turned-on seventh transistor M7 supplies the third clock signal CLK3 of a low level to the cascade signal output terminal CROUT to output the cascade signal CR of a low level. Since the first transistor M1 and the second transistor M2 form a diode-connected structure, signals of the output control nodes PO _1 and PO _2 are also high level signals. Since the signal of the output control node PO _1 is a high level signal, the third transistor M3 is turned on to provide the first clock signal CLK1_1 of a low level to the first sub scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 of a low level, and the first capacitor C1 is charged. Since the signal of the output control node PO _2 is a high level signal, the fifth transistor M5 is turned on to supply the second clock signal CLK2_1 of a low level to the second sub scan signal output terminal GOUT2_1 to output the scan signal GOUT2_1 of a low level, and the second capacitor C2 is charged. Since RE is 0, both the tenth transistor M10 and the eleventh transistor M11 are turned off.

In the output phase T2, INPUT is 0, CLK1_1 is 1, CLK2_1 is 0, CLK3 is 1, and RE is 0.

Since INPUT is equal to 1, the ninth transistor M9 is turned off, and the first node PU is floated. The signal at the first node PU is kept at a high level by the third capacitor C3, the seventh transistor M7 is turned on, and the signal at the second node PD is turned off by the inverter ND, so that the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all controlled to be turned off. The turned-on seventh transistor M7 provides the high-level third clock signal CLK3 to the cascade signal output terminal CROUT, and due to the floating of the first node PU and the third capacitor C3, the level of the first node PU may be pulled high, so that the seventh transistor M7 provides the high-level third clock signal CLK3 to the cascade signal output terminal CROUT, and outputs the high-level cascade signal CR. Also, since the level of the first node PU is pulled high, the levels of the output control nodes PO _1 and PO _2 are also pulled high. Since the level of the output control node PO _1 is pulled high, the third transistor M3 is turned on to provide the first clock signal CLK1_1 of a low level to the first sub scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 of a low level. Due to the first capacitor C1, the level of the output control node PO _1 can be further pulled high to provide the first clock signal CLK1_1 of high level to the first sub-scanning signal output terminal GOUT1_1 through the third transistor M3, outputting the scanning signal GOUT1_1 of high level. When the first node PU is pulled high and the level of the output control node PO _1 is further pulled high, the first transistor M1 forms a diode connection mode, so that the first node PU and the output control node PO _1 can be disconnected, thereby preventing the signal of the output control node PO _2 from being affected when the output control node PO _1 is further pulled high. Since the level of the output control node PO _2 is pulled high, the fifth transistor M5 is turned on to supply the second clock signal CLK2_1 of a low level to the second sub scan signal output terminal GOUT2_1 to output the scan signal GOUT2_1 of a low level. Since RE is 0, both the tenth transistor M10 and the eleventh transistor M11 are turned off.

Thereafter, the second clock signal CLK2_1 is converted from a low level signal to a high level signal, i.e., from CLK2_ 1-0 to CLK2_ 1-1, and the rest of the signals are unchanged. At this time, since the fifth transistor M5 supplies the second clock signal CLK2_1 of a high level to the second sub scanning signal output terminal GOUT2_1, the level of the output control node PO _2 may be further pulled high due to the second capacitor C2 to supply the second clock signal CLK2_1 of a high level to the second sub scanning signal output terminal GOUT2_1 through the fifth transistor M5 to output the scanning signal GOUT2_1 of a high level. When the first node PU is pulled high and the level of the output control node PO _2 is further pulled high, the second transistor M2 forms a diode connection mode, so that the first node PU and the output control node PO _2 can be disconnected, thereby preventing the signal of the output control node PO _1 from being affected when the output control node PO _2 is further pulled high.

Thereafter, the first clock signal CLK1_1 is converted from a high level signal to a low level signal, i.e., from CLK1_ 1-1 to CLK1_ 1-0, and the rest of the signals are unchanged. Thus, the third transistor M3 provides the first clock signal CLK1_1 of a low level to the first sub scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 of a low level.

In the reset phase T3, INPUT is 0 and RE is 1.

Since INPUT is equal to 0, the ninth transistor M9 is turned off, and since RE is equal to 1, both the tenth transistor M10 and the eleventh transistor M11 are turned on. The turned-on tenth transistor M10 provides the third reference signal VREF3 of a low level to the output control node PO _1 so that the signal of the output control node PO _1 is a low level signal, and the turned-on eleventh transistor M11 provides the third reference signal VREF3 of a low level to the output control node PO _2 so that the signal of the output control node PO _2 is a low level signal, so that the first node PU can be discharged as a low level signal. Thus, the second node PD can be set to a high level signal by the action of the inverter ND. Since the signal of the second node PD is a high level signal, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12 and the thirteenth transistor M13 are all controlled to be turned on. The turned-on fourth transistor M4 provides the second reference signal VREF2 of a low level to the first sub-scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 of a low level. The turned-on sixth transistor M6 provides the second reference signal VREF2 of a low level to the second sub-scan signal output terminal GOUT2_1 to output the scan signal GOUT2_1 of a low level. The turned-on eighth transistor M8 provides the third reference signal VREF3 of a low level to the cascade signal output terminal CROUT to output the cascade signal CR of a low level. The turned-on twelfth transistor M12 provides the low level third reference signal VREF3 to the output control node PO _1, and further outputs the signal of the control node PO _1 as a low level. The turned-on thirteenth transistor M13 provides the low level of the third reference signal VREF3 to the output control node PO _2, further making the signal of the output control node PO _2 low.

After the reset phase T3, since INPUT is 0 and RE is 0, the signal of the output control node PO _1 is maintained as a low level signal by the first capacitor C1, the signal of the output control node PO _2 is maintained as a low level signal by the second capacitor C2, the signal of the first node PU is maintained as a low level signal by the third capacitor C3, the signal of the second node PD is a high level signal, and the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 are all controlled to be turned on. The turned-on fourth transistor M4 provides the second reference signal VREF2 of a low level to the first sub-scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 of a low level. The turned-on sixth transistor M6 provides the second reference signal VREF2 of a low level to the second sub-scan signal output terminal GOUT2_1 to output the scan signal GOUT2_1 of a low level. The turned-on eighth transistor M8 provides the third reference signal VREF3 of a low level to the cascade signal output terminal CROUT to output the cascade signal CR of a low level. The turned-on twelfth transistor M12 provides the low level third reference signal VREF3 to the output control node PO _1, and further outputs the signal of the control node PO _1 as a low level. The turned-on thirteenth transistor M13 provides the low level of the third reference signal VREF3 to the output control node PO _2, further making the signal of the output control node PO _2 low.

In addition, the shift register unit provided by the invention can enable signals of different output control nodes to have no influence on each other, thereby improving the stability of the waveform of the output scanning signals and avoiding the waveform difference of the scanning signals. By performing simulation on the shift register unit in the first embodiment, a simulation diagram as shown in fig. 6 is obtained. As can be seen from fig. 6, the time duration for converting the scan signal gout1_1 and the scan signal gout2_1 from the high level signal to the low level signal is 12us, so that the waveforms of the scan signal gout1_1 and the scan signal gout2_1 have high similarity and small difference.

In practical applications, when the shift register unit in the first embodiment is applied to an array substrate of a display device, since the array substrate includes a plurality of gate lines, a scan signal with a phase difference is output to two gate lines through the shift register unit in the first embodiment. The Display device may be an Organic Light-Emitting Diode (OLED) Display device or a Liquid Crystal Display (LCD), and is not limited herein.

Also, in the output phase, since the first node PU is pulled high by the third capacitor, the levels of the output control nodes PO _1 and PO _2 can be further pulled high in the case of pulling high, thereby improving the driving capability of the third transistor M3 and the fifth transistor M5.

Example II,

The parts of the shift register unit provided in the second embodiment of the present invention that are the same as the parts of the shift register unit provided in the first embodiment of the present invention are not described herein again, and only different parts are described below.

In concrete implementation, in the embodiment of the present invention, as shown in fig. 7, 2 first sub-scanning signal output circuits 41_1 and 41_2 are provided in the shift register unit, and 2 second sub-scanning signal output circuits 42_1 and 42_2 are provided. The first sub-scan signal output circuit 41_1 corresponds to the first clock signal CLK1_1 and the first sub-scan signal output terminal GOUT1_ 1. The first sub-scan signal output circuit 41_2 corresponds to the first clock signal CLK1_2 and the first sub-scan signal output GOUT1_2. The second sub-scanning signal output circuit 42_1 corresponds to the second clock signal CLK2_1 and the second sub-scanning signal output terminal GOUT2_ 1. The second sub-scanning signal output circuit 42_2 corresponds to the second clock signal CLK2_2 and the second sub-scanning signal output terminal GOUT2_ 2.

The operation of the shift register unit provided in this embodiment will be described with reference to the timing chart of the circuit shown in fig. 8. Specifically, the input phase T1, the output phase T2, and the reset phase T3 in the circuit timing diagram shown in fig. 8 are selected.

In the INPUT phase T1, INPUT is 1, CLK1_1 is 0, CLK1_2 is 0, CLK2_1 is 0, CLK2_2 is 0, CLK3 is 0, and RE is 0. The following description is made only with respect to the third transistor M3, the fourth transistor M4, and the first capacitor C1 in the first sub-scan signal output circuit 41_2, and the fifth transistor M5, the sixth transistor M6, and the second capacitor C2 in the second sub-scan signal output circuit 42_ 2. The remaining operation of this stage may be substantially the same as the operation of the input stage T1 in the first embodiment, and is not described herein again. Specifically, since the signal of the output control node PO _1 is a high level signal, the third transistor M3 is turned on to supply the first clock signal CLK1_2 of a low level to the first sub scan signal output terminal GOUT1_2 to output the scan signal GOUT1_2 of a low level, and the first capacitor C1 is charged. Since the signal of the output control node PO _2 is a high level signal, the fifth transistor M5 is turned on to supply the second clock signal CLK2_2 of a low level to the second sub scan signal output terminal GOUT2_2 to output the scan signal GOUT2_2 of a low level, and the second capacitor C2 is charged.

In the output phase T2, INPUT is 0, CLK1_1 is 1, CLK1_2 is 1, CLK2_1 is 0, CLK2_2 is 0, CLK3 is 1, and RE is 0. The following description is made only with respect to the third transistor M3, the fourth transistor M4, and the first capacitor C1 in the first sub-scan signal output circuit 41_2, and the fifth transistor M5, the sixth transistor M6, and the second capacitor C2 in the second sub-scan signal output circuit 42_ 2. The remaining operation process of this stage may be substantially the same as the operation process of the output stage T2 in the first embodiment, and is not described herein again. Since the level of the output control node PO _1 is further pulled high to supply the first clock signal CLK1_2 of a high level to the first sub scan signal output terminal GOUT1_2 through the third transistor M3, the scan signal GOUT1_2 of a high level is output. Thereafter, the second clock signal CLK2_2 is converted from a low level signal to a high level signal, and since the level of the output control node PO _2 is further pulled high, the second clock signal CLK2_2 of a high level is supplied to the second sub scanning signal output terminal GOUT2_2 through the fifth transistor M5, and the scanning signal GOUT2_2 of a high level is output. Thereafter, the first clock signal CLK1_2 is converted from a high level signal to a low level signal, i.e., from CLK1_ 2-1 to CLK1_ 2-0, and the rest of the signals are unchanged. Thus, the third transistor M3 provides the first clock signal CLK1_2 of a low level to the first sub scan signal output terminal GOUT1_2 to output the scan signal GOUT1_2 of a low level.

In the reset phase T3, INPUT is 0 and RE is 1. The following description is made only with respect to the third transistor M3, the fourth transistor M4, and the first capacitor C1 in the first sub-scan signal output circuit 41_2, and the fifth transistor M5, the sixth transistor M6, and the second capacitor C2 in the second sub-scan signal output circuit 42_ 2. The rest of the operation process of this stage may be substantially the same as the operation process of the reset stage T3 in the first embodiment, and is not described herein again. The third transistor M3 and the fifth transistor M5 are both turned off, and the fourth transistor M4 and the sixth transistor M6 are both turned on. The turned-on fourth transistor M4 provides the second reference signal VREF2 of a low level to the first sub-scan signal output terminal GOUT1_2 to output the scan signal GOUT1_2 of a low level. The turned-on sixth transistor M6 provides the second reference signal VREF2 of a low level to the second sub-scan signal output terminal GOUT2_2 to output the scan signal GOUT2_2 of a low level.

After the reset phase T3, since INPUT is 0 and RE is 0. The following description is made only with respect to the third transistor M3, the fourth transistor M4, and the first capacitor C1 in the first sub-scan signal output circuit 41_2, and the fifth transistor M5, the sixth transistor M6, and the second capacitor C2 in the second sub-scan signal output circuit 42_ 2. The third transistor M3 and the fifth transistor M5 are both turned off, and the fourth transistor M4 and the sixth transistor M6 are both turned on. The turned-on fourth transistor M4 provides the second reference signal VREF2 of a low level to the first sub-scan signal output terminal GOUT1_2 to output the scan signal GOUT1_2 of a low level. The turned-on sixth transistor M6 provides the second reference signal VREF2 of a low level to the second sub-scan signal output terminal GOUT2_2 to output the scan signal GOUT2_2 of a low level.

In this way, the first sub-scanning signal output circuit 41_1 and the first sub-scanning signal output circuit 41_2 can output scanning signals with the same timing and waveform, and the two scanning signals can be input to the same gate line in one row to improve the driving capability. Similarly, the second sub-scanning signal output circuit 42_1 and the second sub-scanning signal output circuit 42_2 can output scanning signals with the same timing and waveform, and the two scanning signals can be input to the same gate line of the next row to improve the driving capability.

Example III,

The parts of the shift register unit provided in the third embodiment of the present invention that are the same as the parts of the shift register unit provided in the second embodiment of the present invention are not described herein again, and only different parts are described below.

In practical implementation, there are two scan signal output circuits, and in the embodiment of the present invention, as shown in fig. 9, the reset circuit 12 may further include: a fourteenth transistor M14; a first pole of the tenth transistor M10 and a first pole of the eleventh transistor M11 respectively receive the third reference signal VREF3 through the fourteenth transistor M14. A gate of the fourteenth transistor M14 is for receiving the reset signal RE, a first pole of the fourteenth transistor M14 is for receiving the third reference signal VREF3, and a second pole of the fourteenth transistor M14 is coupled to a first pole of the tenth transistor M10 and a first pole of the eleventh transistor M11, respectively. Wherein, the fourteenth transistor M14 may supply the third reference signal VREF3 to the first pole of the tenth transistor M10 and the first pole of the eleventh transistor M11, respectively, when being in a turn-on state under the control of a high-level signal of the reset signal RE. Therefore, the influence of the change of the third reference signal VREF3 on the tenth transistor M10 and the eleventh transistor M11 can be avoided, and the circuit stability is improved.

In specific implementation, in the embodiment of the present invention, as shown in fig. 9, the node control circuit 13 further includes: a fifteenth transistor M15; wherein, the first pole of the twelfth transistor M12 and the first pole of the thirteenth transistor M13 respectively receive the third reference signal VREF3 through the fifteenth transistor M15. A gate of the fifteenth transistor M15 is coupled to the second node PD, a first pole of the fifteenth transistor M15 is configured to receive the third reference signal VREF3, and a second pole of the fifteenth transistor M15 is coupled to a first pole of the twelfth transistor M12 and a first pole of the thirteenth transistor M13, respectively. Wherein, when the fifteenth transistor M15 is in a turn-on state under the control of the high-level signal of the second node PD, the third reference signal VREF3 may be provided to the first pole of the twelfth transistor M12 and the first pole of the thirteenth transistor M13, respectively. Therefore, the influence of the change of the third reference signal VREF3 on the twelfth transistor M12 and the thirteenth transistor M13 can be avoided, and the circuit stability is improved.

The pixel circuit in the form of 3T1C shown in fig. 10 is used in a typical OLED display device to drive the OLED to emit light and to perform external threshold compensation for the OLED. The pixel circuit includes: a driving transistor T01, transistors T02 to T03, and a storage capacitor Cst. The pixel circuit controls the driving transistor T01 to generate an operating current to drive the organic light emitting diode L to emit light by controlling the transistor T02 to be turned on to write the Data voltage of the Data signal terminal Data into the gate of the driving transistor T01. The signal carrying the threshold voltage information of the driving transistor T01 is output through the detection line SL via the transistor T03. This makes it necessary for one row of pixel circuits to correspond to two gate lines to input signals G01 and G02, respectively. In order to realize control of the pixel circuit, in a specific implementation, in the embodiment of the present invention, as shown in fig. 9, the shift register unit may further include: a detection circuit 50. The detection circuit 50 may include: a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a fourth capacitor C4; the gate of the sixteenth transistor M16 is for receiving the first detection control signal VC1, the first pole of the sixteenth transistor M16 is for receiving the INPUT signal INPUT, and the second pole of the sixteenth transistor M16 is coupled to the first pole of the eighteenth transistor M18. A gate of the seventeenth transistor M17 is configured to receive the first detection control signal VC1, a first pole of the seventeenth transistor M17 is coupled to the gate of the nineteenth transistor M19, and a second pole of the seventeenth transistor M17 is coupled to the first pole of the eighteenth transistor M18. A gate of the eighteenth transistor M18 is coupled to a gate of the nineteenth transistor M19, and a second pole of the eighteenth transistor M18 is for receiving the fourth reference signal VREF 4. A first pole of the nineteenth transistor M19 is for receiving a fourth reference signal VREF4, and a second pole of the nineteenth transistor M19 is coupled to a first pole of the twentieth transistor M20. A gate of the twentieth transistor M20 is for receiving the second detection control signal VC2, and a second pole of the twentieth transistor M20 is coupled to the first node PU. The fourth capacitor C4 is coupled between the first pole of the nineteenth transistor M19 and the gate of the nineteenth transistor M19. Specifically, the sixteenth transistor M16 may be in a turn-on state under the control of the first detection control signal VC1 to provide the INPUT signal INPUT to the first pole of the eighteenth transistor M18 and the second pole of the seventeenth transistor M17. The seventeenth transistor M17 may be in a turn-on state under the control of the first detection control signal VC1 to supply a signal of a second pole thereof to the gate of the nineteenth transistor M19 and the gate of the eighteenth transistor M18. The eighteenth transistor M18 may be in a conductive state under the control of a signal of its gate. The nineteenth transistor M19 may be in a conductive state under control of a signal of its gate to provide the fourth reference signal VREF4 to the first pole of the twentieth transistor M20. The twentieth transistor M20 may be in a turn-on state under the control of the second detection control signal VC2 to provide a signal of a first pole thereof to the first node PU.

In one embodiment, the fourth reference signal may be a high level signal. Further, the voltage value of the fourth reference signal may be the same as the voltage value of the first reference signal. In order to reduce the number of signal terminals and reduce the occupied space of the signal lines, the fourth reference signal and the first reference signal may be set to be the same signal, that is, the same reference signal terminal is used to provide the fourth reference signal and the first reference signal.

The operation of the shift register unit provided in this embodiment will be described with reference to the timing chart of the circuit shown in fig. 11. Specifically, one frame time is divided into a display scan phase DP and a blank time phase BT. The timing of the first clock signals CLK1_ n during the display scan period DP is the same, and the timing of the first clock signals CLK1_ n during the blank time period BT is different. Similarly, the timing of the second clock signals CLK2_ n in the display scan phase DP is the same, and the timing of the second clock signals CLK2_ n in the blank time phase BT is different.

Specifically, the display scan phase DP includes: an input phase T1, an output phase T2, and a reset phase T3. In the INPUT stage T1, INPUT is 1, CLK1_1 is 0, CLK1_2 is 0, CLK2_1 is 0, CLK2_2 is 0, CLK3 is 0, RE is 0, VC1 is 1, and VC2 is 0. Since RE is 0, the fourteenth transistor M14 is turned off. Since the signal of the second node PD is a low level signal, the fifteenth transistor M15 is turned off. Since VC1 is equal to 1, both the sixteenth transistor M16 and the seventeenth transistor M17 are turned on to supply a high-level signal of the INPUT signal INPUT to the gate of the nineteenth transistor M19 and held by the fourth capacitor C4, and the nineteenth transistor M19 is controlled to be turned on to supply a high-level fourth reference signal VREF4 to the twentieth transistor M20. However, since VC2 is equal to 0, the twentieth transistor M20 is turned off, and thus does not affect the signal of the first node PU. The remaining operation process of this stage may be substantially the same as the operation process of the input stage T1 in the second embodiment, and is not described herein again. Moreover, the working processes of the output stage T2 and the reset stage T3 in the third embodiment may be substantially the same as the working processes of the output stage T2 and the reset stage T3 in the second embodiment, and are not described herein again.

The blank time period BT may include: a test input stage T4, a test output stage T5, and a test reset stage T6. In the blank time period BT, the INPUT signal INPUT, the reset signal RE, the second clock signals CLK2_ 1-CLK 2_2, the third clock signal CLK3, and the first to fourth reference signals VREF4 are all low level signals.

In the detection input stage T4, VC1 is 0, VC2 is 1, CLK1_1 is 0, and CLK1_2 is 0. Since VC1 is 0, both the sixteenth transistor M16 and the seventeenth transistor M17 are turned off. The gate of the nineteenth transistor M19 is a high level signal due to the action of the fourth capacitor C4 to control the nineteenth transistor M19 to be turned on, and the twentieth transistor M20 is turned on to supply the fourth reference signal VREF4 of a high level to the first node PU since VC2 is 1. Since the signal of the first node PU is a high level signal, the seventh transistor M7 is turned on, and acts through the inverter ND, so that the signal of the second node PD is a low level signal. Thereby controlling the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the thirteenth transistor M13 to be turned off. The turned-on seventh transistor M7 supplies the third clock signal CLK3 of a low level to the cascade signal output terminal CROUT to output the cascade signal CR of a low level. Since the first transistor M1 and the second transistor M2 form a diode-connected structure, signals of the output control nodes PO _1 and PO _2 are also high level signals. Since the signal of the output control node PO _1 is a high level signal, both the third transistors M3 are turned on. The third transistor M3 of the first sub-scan signal output circuit 41_1 provides the first clock signal CLK1_1 to the first sub-scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 at a low level. The third transistor M3 in the first sub scanning signal output circuit 41_2 provides the first clock signal CLK1_2 to the first sub scanning signal output terminal GOUT1_2 to output the scanning signal GOUT1_2 of low level. Since the signal of the output control node PO _2 is a high level signal, the two fifth transistors M5 are turned on. The fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the second clock signal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the scanning signal GOUT2_1 at a low level. The fifth transistor M5 in the second sub scanning signal output circuit 42_2 provides the second clock signal CLK2_2 to the second sub scanning signal output terminal GOUT2_2 to output the scanning signal GOUT2_2 of a low level.

In the detection output stage T5, VC1 and VC2 are 0, the first clock signal CLK1_1 has two high level pulses, and the first clock signal CLK1_2 has one high level pulse. Specifically, due to the first capacitor C1, the signal of the output control node PO _1 is maintained to be a high level signal, and thus both the third transistors M3 are turned on. The third transistor M3 in the first sub-scan signal output circuit 41_1 provides the first clock signal CLK1_1 to the first sub-scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 having two high level pulses. The third transistor M3 in the first sub scanning signal output circuit 41_2 provides the first clock signal CLK1_2 to the first sub scanning signal output terminal GOUT1_2 to output the scanning signal GOUT1_2 having a high level pulse. Due to the second capacitor C2, the signal at the output control node PO _2 is kept high, and thus the two fifth transistors M5 are turned on. The fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the second clock signal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the scanning signal GOUT2_1 at a low level. The fifth transistor M5 in the second sub scanning signal output circuit 42_2 provides the second clock signal CLK2_2 to the second sub scanning signal output terminal GOUT2_2 to output the scanning signal GOUT2_2 of a low level.

In the detection reset phase T6, VC1 is 1, VC2 is 0, CLK1_1 is 0, and CLK1_2 is 0.

Since VC2 is 0, the twentieth transistor M20 is turned off. Since VC1 is equal to 1, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on to provide the INPUT signal INPUT of low level to the gate of the nineteenth transistor M19, and control the nineteenth transistor M19 to be turned off. Due to the function of the first capacitor C1, the signal of the output control node PO _1 is kept at a high level, and thus both the third transistors M3 are turned on. The third transistor M3 of the first sub-scan signal output circuit 41_1 provides the first clock signal CLK1_1 with a low level to the first sub-scan signal output terminal GOUT1_1 to output the scan signal GOUT1_1 with a low level. The third transistor M3 in the first sub scanning signal output circuit 41_2 provides the first clock signal CLK1_2 of low level to the first sub scanning signal output terminal GOUT1_2 to output the scanning signal GOUT1_2 of low level. Due to the second capacitor C2, the signal at the output control node PO _2 is kept high, and thus the two fifth transistors M5 are turned on. The fifth transistor M5 in the second sub-scanning signal output circuit 42_1 provides the second clock signal CLK2_1 to the second sub-scanning signal output terminal GOUT2_1 to output the scanning signal GOUT2_1 at a low level. The fifth transistor M5 in the second sub scanning signal output circuit 42_2 provides the second clock signal CLK2_2 to the second sub scanning signal output terminal GOUT2_2 to output the scanning signal GOUT2_2 of a low level.

Generally, the OLED is detected by external compensation during the blank time period, so that the scanning signals gout1_1 and gout1_2 output by the shift register unit in the third embodiment input signals G01 and G02 to two gate lines in one row respectively, so as to control the OLED in the row to realize the display function during the display scanning period DP in one frame, and control the OLED in the row to realize the detection function of external compensation during the blank time period BT. And inputting signals G01 and G02 to two grid lines in the next row respectively through scanning signals gout2_1 and gout2_2 so as to meet the requirements of OLED display.

Example four,

The parts of the shift register unit provided in the fourth embodiment of the present invention that are the same as the parts of the shift register unit provided in the third embodiment of the present invention are not described herein again, and only different parts are described below.

In practical implementation, there are two scan signal output circuits, and in the embodiment of the present invention, as shown in fig. 12, the branch control circuit 20 may include: a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is used for receiving a first reference signal VREF1, the first pole of the first transistor M1 is coupled to the first node PU, and the second pole of the first transistor M1 is coupled to the output control node PO _1 corresponding to the first scan signal output circuit. The gate of the second transistor M2 is used for receiving a first reference signal VREF1, the first poles of the second transistors M2 are coupled to the first node PU, and the second pole of the second transistor M2 is coupled to the output control node PO _2 corresponding to the second scan signal output circuit.

In specific implementation, the first reference signal is a high level signal during the display scan period DP and the blank time period BT. The voltage value of the first reference signal is the same as the voltage value of the first clock signal and the voltage value of the second clock signal. In this way, in the input stage T1, when the first node PU is a high-level signal, the voltage value of the gate of the first transistor M1 is the same as the first electrode thereof, which corresponds to the formation of a diode-connected structure, and the voltage value of the gate of the second transistor M2 is the same as the first electrode thereof, which corresponds to the formation of a diode-connected structure. The remaining operation process of this stage may be substantially the same as the operation process of the input stage T1 in the third embodiment, and is not described herein again.

In the output stage T2, since the output control signals PO _1 to PO _1 are further pulled high, the gate-source voltages of the first transistor M1 and the second transistor M2 are large, which causes the first transistor M1 and the second transistor M2 to be turned off, so that the signals of the further pulled output control signals PO _1 to PO _1 cannot influence each other through the first node PU, thereby improving the circuit stability. The remaining operation process of this stage may be substantially the same as the operation process of the output stage T2 in the third embodiment, and is not described herein again.

In the reset period T3, the first transistor M1 and the second transistor M2 are always turned on. The rest of the working process in this stage may be substantially the same as the working process in the reset stage T3 in the third embodiment, and is not described herein again.

The detection input stage T4, the detection output stage T5 and the detection reset stage T6. The first transistor M1 and the second transistor M2 are always turned on. The remaining working processes of the three stages may be substantially the same as the working processes of the detection input stage T4, the detection output stage T5, and the detection reset stage T6 in the third embodiment, and are not described herein again.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of the shift register unit provided by the embodiment of the present invention, and the shift register unit provided by the embodiment of the present invention can output a plurality of different scanning signals by driving the shift register unit provided by the embodiment of the present invention through the driving method. In addition, the implementation of the driving method can refer to the implementation of the shift register unit, and repeated parts are not described herein again.

In a specific implementation, in an embodiment of the present invention, the display scanning stage may include: an input phase, an output phase and a reset phase. Specifically, as shown in fig. 13, the following steps may be included:

s1301, in an input stage, a signal control circuit responds to an input signal and controls a signal of a first node and a signal of a second node; the branch control circuit responds to the signal of the first node and controls the signals of the output control nodes corresponding to the scanning signal output circuits one by one; a cascade signal output circuit outputting a cascade signal in response to a signal of the first node; each scanning signal output circuit outputs different scanning signals in response to the signal of the corresponding output control node;

s1302, in the output stage, the branch control circuit responds to the signal of the first node and controls the signals of the output control nodes corresponding to the scanning signal output circuits one to one; a cascade signal output circuit outputting a cascade signal in response to a signal of the first node; each scanning signal output circuit outputs different scanning signals in response to the signal of the corresponding output control node;

s1303, in a reset stage, the signal control circuit responds to a reset signal and controls a signal of the first node and a signal of the second node; a cascade signal output circuit outputting a cascade signal in response to a signal of the first node; each of the scanning signal output circuits outputs a different scanning signal in response to a signal of a corresponding output control node.

In a specific implementation, the number of the scan signal output circuits is two, and a first scan signal output circuit of the two scan signal output circuits includes: a plurality of first sub-scanning signal output circuits; the second scan signal output circuit includes: a plurality of second sub-scanning signal output circuits. It should be noted that, the detailed description in this section refers to the first embodiment, and is not repeated herein.

In the embodiment of the invention, in the input stage and the output stage, each first sub-scanning signal output circuit responds to the signal of the corresponding output control node and provides the corresponding first clock signal to the corresponding first sub-scanning signal output end; each second sub-scanning signal output circuit responds to the signal of the corresponding output control node and provides the corresponding second clock signal to the corresponding second sub-scanning signal output end; the cascade signal output circuit responds to the signal of the first node and provides a third clock signal to the cascade signal output end;

in a reset phase, each first sub-scanning signal output circuit responds to a signal of the second node and provides a second reference signal to a corresponding first sub-scanning signal output end; each second sub-scanning signal output circuit responds to the signal of the second node and provides a second reference signal to a corresponding second sub-scanning signal output end; the cascade signal output circuit provides a third reference signal to the cascade signal output terminal in response to the signal of the second node.

In the embodiment of the invention, in the display scanning stage, the time sequences of the first clock signals are the same, the time sequences of the second clock signals are the same, and the time sequences of the first clock signals and the second clock signals are different.

In the embodiment of the invention, the periods of the first clock signal, the second clock signal and the third clock signal are the same; in the same cycle, the rising edge of the third clock signal occurs before the rising edge of the first clock signal, and the falling edge of the third clock signal occurs after the falling edge of the second clock signal. For example, as shown in fig. 5, 8, and 11, the rising edge of the third clock signal CLK3 is aligned with the rising edge of the first clock signal CLK1 — n, and the falling edge of the third clock signal CLK3 is aligned with the falling edge of the second clock signal CLK2 — k.

Further, in practical implementation, the shift register unit further comprises a detection circuit, so that the shift register unit can be applied to an OLED display device. In an embodiment of the present invention, the driving method may further include: a blank time phase; wherein the blank time phase may include: the method comprises a detection input stage, a detection output stage and a detection reset stage. The working process of the detection circuit in these stages is referred to in the third embodiment, and is not described herein.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 14a and 14b, including a plurality of cascaded shift register units provided by the embodiment of the present invention: SR (n-2), SR (n-1), SR (n +1), SR (n + 2); (N is equal to or more than 1 and equal to or less than N and N is an integer) in total N shift register units;

in each adjacent four-stage shift register unit, the INPUT signal INPUT of the fourth-stage shift register unit SR (n +1) is INPUT by the cascade signal CR of the first-stage shift register unit SR (n-2);

in each adjacent five-stage shift register unit, the reset signal RE of the first-stage shift register unit SR (n-2) is input by the cascade signal CR of the fifth-stage shift register unit SR (n + 2).

Fig. 14a illustrates an example of the structure of a shift register unit using the structure shown in fig. 4. Fig. 14b illustrates an example of a shift register unit structure using the structure shown in fig. 9.

In practical implementation, when the structure of the shift register unit adopts the structure shown in fig. 4, the first clock signal CLK1_1 of the 5y-4 th stage shift register unit is provided by the same clock terminal CLK1_1, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_1, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 1. The first clock signal CLK1_1 of the 5y-3 stage shift register unit is provided by the same clock terminal CLK1_2, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_2, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 2. The first clock signal CLK1_1 of the 5y-2 stage shift register unit is provided by the same clock terminal CLK1_3, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_3, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 3. The first clock signal CLK1_1 of the 5y-1 stage shift register unit is provided by the same clock terminal CLK1_4, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_4, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 4. The first clock signal CLK1_1, the second clock signal CLK2_1 and the third clock signal CLK3 of the 5 y-th stage shift register unit are respectively provided by the same clock terminal CLK1_5, the same clock terminal CLK2_5 and the same clock terminal CLK3_5, respectively. Wherein k is a positive integer.

In practical implementation, when the structure of the shift register unit adopts the structure shown in fig. 9, the first clock signal CLK1_1 of the 5y-4 th stage shift register unit is provided by the same clock terminal CLK1_11, the first clock signal CLK1_2 is provided by the same clock terminal CLK1_21, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_11, the second clock signal CLK2_2 is provided by the same clock terminal CLK2_21, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 1. The first clock signal CLK1_1 of the 5y-3 stage shift register unit is provided by the same clock terminal CLK1_12, the first clock signal CLK1_2 is provided by the same clock terminal CLK1_22, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_12, the second clock signal CLK2_2 is provided by the same clock terminal CLK2_22, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 2. The first clock signal CLK1_1 of the 5y-2 stage shift register unit is provided by the same clock terminal CLK1_13, the first clock signal CLK1_2 is provided by the same clock terminal CLK1_23, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_13, the second clock signal CLK2_2 is provided by the same clock terminal CLK2_23, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 3. The first clock signal CLK1_1 of the 5y-1 stage shift register unit is provided by the same clock terminal CLK1_14, the first clock signal CLK1_2 is provided by the same clock terminal CLK1_24, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_14, the second clock signal CLK2_2 is provided by the same clock terminal CLK2_24, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 4. The first clock signal CLK1_1 of the 5 y-th stage shift register unit is provided by the same clock terminal CLK1_15, the first clock signal CLK1_2 is provided by the same clock terminal CLK1_25, the second clock signal CLK2_1 is provided by the same clock terminal CLK2_15, the second clock signal CLK2_2 is provided by the same clock terminal CLK2_25, and the third clock signal CLK3 is provided by the same clock terminal CLK3_ 5. Wherein k is a positive integer.

In specific implementation, the first detection control signals of the shift register units of each stage are the same signal, so as to control the shift register units of each stage within one frame time. The second detection control signals of each stage of shift register unit are different, and only the second detection control signal corresponding to one stage of shift register unit has a high-level pulse signal within one frame time, so that the stage of shift register unit outputs the scan signals gout1_1, gout1_2, gout2_1 and gout2_2 shown in fig. 11 during the blank time period. The rest of the shift register units output low level signals in the blank time period.

Specifically, the specific structure of each shift register unit in the gate driving circuit is the same as that of the shift register unit of the present invention in function and structure, and repeated descriptions are omitted.

Based on the same inventive concept, the embodiment of the invention also provides an array substrate, which comprises the gate driving circuit provided by the embodiment of the invention. The principle of the array substrate for solving the problems is similar to that of the gate driving circuit, so the implementation of the array substrate can be referred to the implementation of the gate driving circuit, and repeated details are not repeated herein.

The array substrate provided by the embodiment of the invention includes the gate driving circuit, and provides scanning signals for each gate line on the array substrate through each shift register unit in the gate driving circuit.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the array substrate provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the present invention. The implementation of the display device can refer to the above embodiments of the array substrate, and repeated descriptions are omitted.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register cell, comprising: the circuit comprises a signal control circuit, a branch control circuit, a cascade signal output circuit and a plurality of scanning signal output circuits;

2. The shift register cell according to claim 1, wherein the scan signal output circuits are two, the branch control circuit includes: a first transistor and a second transistor;

3. The shift register cell according to claim 1, wherein the scan signal output circuits are two, and a first scan signal output circuit of the two scan signal output circuits includes: at least 1 first sub-scanning signal output circuit; each of the first sub-scanning signal output circuits corresponds to one first clock signal one by one, and each of the first sub-scanning signal output circuits corresponds to one first sub-scanning signal output end one by one;

4. The shift register cell of claim 3, wherein the first sub scanning signal output circuit comprises: a third transistor, a fourth transistor and a first capacitor;

5. The shift register cell according to claim 1, wherein the scan signal output circuits are two, and a second scan signal output circuit of the two scan signal output circuits includes: at least 1 second sub-scanning signal output circuit; each second sub-scanning signal output circuit corresponds to a second clock signal one by one, and each second sub-scanning signal output circuit corresponds to a second sub-scanning signal output end one by one;

6. The shift register cell of claim 5, wherein the second sub scanning signal output circuit comprises: a fifth transistor, a sixth transistor, and a second capacitor;

7. The shift register cell of claim 1, wherein the cascade signal output circuit is configured to provide a third clock signal to a cascade signal output terminal in response to the signal of the first node; and providing a third reference signal to the cascade signal output in response to the signal of the second node.

8. The shift register cell of claim 7, wherein the cascade signal output circuit comprises: a seventh transistor, an eighth transistor, and a third capacitor;

9. The shift register cell of claim 1, wherein the signal control circuit comprises: an input circuit, a reset circuit, a node control circuit;

10. The shift register cell of claim 9, wherein the scan signal output circuits are two, the input circuit comprising: a ninth transistor; wherein a gate of the ninth transistor is configured to receive the input signal, a first pole of the ninth transistor is configured to receive the first reference signal, and a second pole of the ninth transistor is coupled to the first node;

11. The shift register cell of claim 10, wherein the reset circuit further comprises: a fourteenth transistor; wherein a first pole of the tenth transistor and a first pole of the eleventh transistor receive the third reference signal through the fourteenth transistor, respectively; a gate of the fourteenth transistor is configured to receive the reset signal;

12. The shift register cell of any one of claims 1-11, further comprising: a detection circuit; the detection circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a fourth capacitor;

13. A gate drive circuit comprising a plurality of shift register cells according to any one of claims 1 to 12 in cascade;

14. An array substrate comprising the gate driver circuit of claim 13.

15. A display device comprising the array substrate according to claim 14.

16. A method of driving a shift register cell according to any one of claims 1 to 12, comprising: a display scanning stage; wherein the display scan phase comprises: an input stage, an output stage and a reset stage;

17. The driving method according to claim 16, wherein the number of the scan signal output circuits is two, and a first scan signal output circuit of the two scan signal output circuits includes: a plurality of first sub-scanning signal output circuits; the second scan signal output circuit includes: a plurality of second sub-scanning signal output circuits;

18. The driving method as claimed in claim 17, wherein in the display scan phase, the timings of the first clock signals are the same, the timings of the second clock signals are the same, and the timings of the first clock signals and the second clock signals are different.

19. The driving method according to claim 18, wherein the periods of the first clock signal, the second clock signal, and the third clock signal are the same;