CN114360430B

CN114360430B - Shift register and driving method, grid driving circuit and display panel

Info

Publication number: CN114360430B
Application number: CN202210096114.5A
Authority: CN
Inventors: 朱磊
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Priority date: 2022-01-26
Filing date: 2022-01-26
Publication date: 2024-01-23
Anticipated expiration: 2042-01-26
Also published as: CN114360430A

Abstract

The invention provides a shift register, a driving method, a grid driving circuit, a display panel and a display device, relates to the technical field of display, and can narrow the frame of the display panel. The shift register comprises a shift register circuit and a signal output circuit; the shift register circuit is configured to output an initial scan signal at an initial scan signal output terminal; the signal output circuit is configured to output a first scanning signal at a first scanning signal output end and output a second scanning signal at a second scanning signal output end; the waveforms of the first scanning signal and the second scanning signal are not identical, the first scanning signal is one signal required by the sub-pixel which is electrically connected with the shift register, and the second scanning signal is the other signal required by the sub-pixel. The shift register can be applied to a gate driving circuit, a display panel and a display device.

Description

Shift register and driving method, grid driving circuit and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method, a gate driving circuit, a display panel, and a display device.

Background

The gate driving circuit (also called a scanning driving circuit) is an important component in the display device, and the gate driving circuit comprises a plurality of stages of cascaded shift registers, and each stage of shift registers is coupled with a gate line in the display screen. The gate driving circuit is capable of sequentially outputting the switching state voltages of the TFT (Thin Film Transistor ) devices row by row, that is, outputting scanning signals (may also be referred to as gate signals) to the gate lines in the display screen row by row, so that a plurality of TFTs coupled to the same gate line in the display screen are turned on row by row, and when a plurality of TFTs coupled to one row of gate lines are turned on, pixel voltages are input to the pixel electrodes of each sub-pixel through the data lines, so that picture display is performed.

Disclosure of Invention

The invention provides a shift register, a driving method, a grid driving circuit, a display panel and a display device, so as to narrow the frame of the display panel.

In order to achieve the above purpose, the invention adopts the following technical scheme:

a first aspect of the present invention provides a shift register including a shift register circuit and a signal output circuit; the shift register circuit is electrically connected to an initial scan signal output end, and is configured to output an initial scan signal at the initial scan signal output end.

The signal output circuit is electrically connected with an initial scanning signal input end, a control signal end, a first clock signal end, a first voltage signal end, a second voltage signal end, a third voltage signal end, a first scanning signal output end and a second scanning signal output end, and the initial scanning signal input end is electrically connected with the initial scanning signal output end; the signal output circuit is configured to output a first scan signal at the first scan signal output terminal, a second scan signal at the second scan signal output terminal in response to a control signal received at the control signal terminal, an initial scan signal received at the initial scan signal input terminal, a first clock signal received at the first clock signal terminal, a first voltage signal received at the first voltage signal terminal, a second voltage signal received at the second voltage signal terminal, and a third voltage signal received at the third voltage signal terminal; the waveforms of the first scanning signals and the second scanning signals are not identical, the first scanning signals are signals required by the sub-pixels electrically connected with the shift register, and the second scanning signals are signals required by the sub-pixels. .

The shift register provided by the embodiment of the invention can provide two scanning signals with different waveforms for one sub-pixel, namely, one shift register can provide two different time sequence signals for the same sub-pixel, so that the number of the shift registers in the display panel can be reduced, the space occupied by the shift registers in the display panel is reduced, and the frame is narrowed.

In some embodiments, the first scan signal is a gate scan signal required for a sub-pixel electrically connected to the shift register, and the second scan signal is a light emission control signal required for the sub-pixel.

In some embodiments, the signal output circuit comprises: a first scanning signal output circuit and a second scanning signal output circuit. The first scanning signal output circuit is electrically connected with the control signal end, the initial scanning signal input end, the first clock signal end and the first scanning signal output end; the first scan signal output circuit is configured to output the initial scan signal received at the initial scan signal input terminal and the first clock signal received at the first clock signal terminal by the first scan signal output terminal at different stages, respectively, in response to the control signal received at the control signal terminal, thereby causing the first scan signal output terminal to output the first scan signal.

The second scanning signal output circuit is electrically connected with the initial scanning signal input end, the first voltage signal end, the second voltage signal end, the third voltage signal end and the second scanning signal output end; the second scan signal output circuit is configured to output the first voltage signal received at the first voltage signal terminal and the second voltage signal received at the second voltage signal terminal by the second scan signal output terminal at different stages, respectively, in response to the initial scan signal received at the initial scan signal input terminal and the third voltage signal received at the third voltage signal terminal, thereby causing the second scan signal output terminal to output the second scan signal.

In some embodiments, the control signal terminals include a second clock signal terminal and a third clock signal terminal; the first scanning signal output circuit includes: a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is electrically connected to the second clock signal terminal, the first clock signal terminal, and the first scan signal output terminal, the first output sub-circuit being configured to transmit the first clock signal received at the first clock signal terminal to the first scan signal output terminal in response to a second clock signal received at the second clock signal terminal. The second output sub-circuit is electrically connected to the third clock signal terminal, the initial scan signal input terminal, and the first scan signal output terminal, the second output sub-circuit being configured to transmit the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to a third clock signal received at the third clock signal terminal.

In some embodiments, the first output sub-circuit includes: a first transistor, wherein a control electrode of the first transistor is electrically connected to the second clock signal terminal, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the first scan signal output terminal; the second output sub-circuit includes: and a control electrode of the second transistor is electrically connected to the third clock signal end, a first electrode of the second transistor is electrically connected to the initial scanning signal input end, and a second electrode of the second transistor is electrically connected to the first scanning signal output end.

In some embodiments, the second scan signal output circuit includes: a third output sub-circuit, a first control sub-circuit, a second control sub-circuit, and a fourth output sub-circuit. The third output sub-circuit is electrically connected to the initial scanning signal input end, the first voltage signal end and the second scanning signal output end; the third output sub-circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal; the first control sub-circuit is electrically connected to the initial scanning signal input end, the first voltage signal end and a first node; the first control sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the first node in response to the initial scan signal received at the initial scan signal input terminal.

The second control sub-circuit is electrically connected to the first node and the third voltage signal terminal, the second control sub-circuit being configured to control the voltage of the first node in conjunction with the first control sub-circuit in accordance with a third voltage signal received at the third voltage signal terminal; the fourth output sub-circuit is electrically connected to the first node, the second voltage signal terminal and the second scanning signal output terminal; the fourth output sub-circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to a voltage of the first node.

In some embodiments, the second control sub-circuit is configured to transmit the third voltage signal at the third voltage signal terminal to the first node to change the voltage of the first node if the first voltage signal is not transmitted to the first node.

In some embodiments, the second control sub-circuit comprises: and the control electrode and the first electrode of the fourth transistor are electrically connected to the third voltage signal end, and the second electrode of the fourth transistor is electrically connected to the first node.

In some embodiments, the second control sub-circuit comprises: a regulation sub-circuit and an energy storage sub-circuit. The regulation and control sub-circuit is electrically connected with a fourth clock signal end, the first node and the third voltage signal end; the regulation sub-circuit is configured to transmit a third voltage signal received at the third voltage signal terminal to the first node in response to a fourth clock signal received at the fourth clock signal terminal; the energy storage sub-circuit is electrically connected with a fifth clock signal end and the first node; the tank sub-circuit is configured to change a voltage of the first node by a coupling action in accordance with a fifth clock signal received at the fifth clock signal terminal, in a case where the first voltage signal and the third voltage signal are not transmitted to the first node.

In some embodiments, the regulation subcircuit includes: and a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the fourth clock signal terminal, a first electrode of the seventh transistor is electrically connected to the third voltage signal terminal, and a second electrode of the seventh transistor is electrically connected to the first node. The tank sub-circuit includes: and a first capacitor, a first end of which is electrically connected to the fifth clock signal end, and a second end of which is electrically connected to the first node.

In some embodiments, the first control sub-circuit comprises: and a third transistor, wherein a control electrode of the third transistor is electrically connected to the initial scan signal input terminal, a first electrode of the third transistor is electrically connected to the first voltage signal terminal, and a second electrode of the third transistor is electrically connected to the first node. And/or, the third output sub-circuit comprises: and a control electrode of the fifth transistor is electrically connected to the initial scanning signal input end, a first electrode of the fifth transistor is electrically connected to the first voltage signal end, and a second electrode of the fifth transistor is electrically connected to the second scanning signal output end. And/or, the fourth output sub-circuit comprises: and a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the sixth transistor is electrically connected to the second scan signal output terminal.

In some embodiments, the shift register circuit includes: an input sub-circuit and an output control sub-circuit. The input sub-circuit is electrically connected to a first signal terminal, a second signal terminal and a second node, and is configured to transmit a second signal received at the second signal terminal to the second node in response to a first signal received at the first signal terminal, wherein the first signal terminal or the second signal terminal is electrically connected to an initial scan signal output terminal of a shift register circuit in a previous stage shift register; the output control sub-circuit is electrically connected to the second node, a sixth clock signal terminal and the initial scan signal output terminal, the output control sub-circuit being configured to transmit a sixth clock signal received at the sixth clock signal terminal to the initial scan signal output terminal in response to a voltage of the second node; wherein the period of the sixth clock signal is at least twice the period of the first clock signal.

A second aspect of the present invention provides a gate driving circuit including a shift register provided by some of the above embodiments of N-stage cascade connection, N being a positive integer greater than or equal to 1; the shift register includes: the shift register circuit comprises an input sub-circuit, wherein the input sub-circuit is electrically connected with a first signal end, a second signal end and a second node, and an initial scanning signal output end of the shift register circuit in the nth shift register is electrically connected with a first signal end or a second signal end of the shift register circuit in the n+1th shift register, and N is more than or equal to 1 and less than or equal to N-1.

A third aspect of the present invention provides a display panel including: some of the embodiments described above provide a gate driving circuit.

In some embodiments, the display panel further includes a plurality of rows of sub-pixels, a plurality of gate scan signal lines, and a plurality of light emission control signal lines. At least one gate scanning signal line is electrically connected with a first scanning signal output end of a shift register in the gate driving circuit and further electrically connected with one row of sub-pixels; at least one light-emitting control signal line is electrically connected with a second scanning signal output end of a shift register in the grid driving circuit, and further electrically connected with one row of sub-pixels.

A fourth aspect of the present invention provides a display device including: the display panel provided in the above embodiment.

A fifth aspect of the present invention provides a driving method of a shift register for a shift register, the shift register including a shift register circuit and a signal output circuit; the shift register circuit is electrically connected to an initial scanning signal output end, and is configured to output an initial scanning signal at the initial scanning signal output end; the signal output circuit is electrically connected to an initial scanning signal input end, a control signal end, a first clock signal end, a first voltage signal end, a second voltage signal end, a third voltage signal end, a first scanning signal output end and a second scanning signal output end, and the initial scanning signal input end is electrically connected with the initial scanning signal output end.

The driving method includes: the shift register circuit outputs an initial scanning signal at the initial scanning signal output end; the signal output circuit outputs a first scan signal at the first scan signal output terminal and a second scan signal at the second scan signal output terminal in response to a control signal received at the control signal terminal, an initial scan signal received at the initial scan signal input terminal, a first clock signal received at the first clock signal terminal, a first voltage signal received at the first voltage signal terminal, a second voltage signal received at the second voltage signal terminal, and a third voltage signal received at the third voltage signal terminal; the waveform of the first scanning signal is not identical to the waveform of the second scanning signal.

In some embodiments, the signal output circuit includes a first scan signal output circuit and a second scan signal output circuit. The driving method of the shift register includes: a charging phase, an output phase and a reset phase, wherein the output phase comprises a pixel initialization phase and a refresh and compensation phase, and the reset phase comprises a first light-emitting phase and a second light-emitting phase.

In the charging stage, the shift register circuit outputs a first level of an initial scan signal to the initial scan signal output terminal.

In the output stage, the shift register circuit outputs a second level of an initial scanning signal to the initial scanning signal output end; in the pixel initialization stage in the output stage, a first scan signal output circuit transmits a first clock signal received at a first clock signal terminal to a first scan signal output terminal in response to a control signal received at a control signal terminal; the second scan signal output circuit transmits the first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal.

In the refresh and compensation stage of the output stages, the first scan signal output circuit transmits the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal; the second scan signal output circuit transmits the first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal.

In the reset stage, the shift register circuit outputs a first level of an initial scanning signal to the initial scanning signal output end; in the first light-emitting stage of the reset stage, the first scan signal output circuit transmits the first clock signal received at the first clock signal terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal; the second scan signal output circuit transmits the second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to the third voltage signal received at the third voltage signal terminal.

In the second light-emitting stage of the reset stage, the first scan signal output circuit transmits the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal; the second scan signal output circuit transmits the second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to the third voltage signal received at the third voltage signal terminal.

It can be understood that the above embodiments of the present invention provide a gate driving circuit, a display panel, a display device and a driving method of a shift register, and the advantages achieved by the gate driving circuit, the display panel, the display device and the driving method of the shift register can refer to the advantages of the shift register described above, and are not repeated herein.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1A is a schematic diagram of a display device according to an embodiment of the present invention;

FIG. 1B is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 1C is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 2A is a block diagram of a shift register according to an embodiment of the present invention;

FIG. 2B is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 3A is a block diagram of a pixel driving circuit according to an embodiment of the present invention;

FIG. 3B is a timing diagram of a pixel driving circuit according to an embodiment of the invention;

fig. 4A to 4C are diagrams illustrating driving processes of the pixel driving circuit according to the embodiment of the invention;

FIG. 5A is a schematic diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 5B is a schematic diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 5C is a schematic diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 5D is a timing diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

fig. 6A to 6D are diagrams illustrating a driving process of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 7A is a schematic diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 7B is a schematic diagram of a signal output circuit in a shift register according to an embodiment of the present invention;

FIG. 7C is a timing diagram illustrating another embodiment of a signal output circuit in a shift register according to the present invention;

fig. 8A to 8F are diagrams illustrating another driving process of the signal output circuit in the shift register according to the embodiment of the present invention;

FIG. 9A is a schematic diagram of a shift register circuit in a shift register according to an embodiment of the present invention;

FIG. 9B is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 9C is a diagram illustrating another embodiment of a shift register according to the present invention;

FIG. 9D is a diagram showing a shift register according to an embodiment of the present invention;

FIG. 9E is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 9F is a diagram showing another configuration of a shift register circuit in a shift register according to an embodiment of the present invention;

fig. 10A to 10C are diagrams illustrating a driving process of a shift register circuit in a shift register according to an embodiment of the present invention;

FIG. 11A is a schematic diagram of a shift register circuit in a shift register according to an embodiment of the present invention;

FIG. 11B is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 11C is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 11D is a diagram illustrating another embodiment of a shift register according to the present invention;

FIG. 11E is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 11F is a schematic diagram of a shift register circuit in a shift register according to an embodiment of the present invention;

fig. 12A to 12D are diagrams illustrating another driving process of the shift register circuit in the shift register according to the embodiment of the present invention;

fig. 13 is a block diagram of a gate driving circuit according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, the following description of the embodiments accompanied with the accompanying drawings will be given in detail. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1A, some embodiments of the present invention provide a display apparatus 100, the display apparatus 100 including a display panel 200, wherein the display apparatus 100 includes a mobile phone, a tablet computer, a personal digital assistant (Personal Digital Assistant, abbreviated as PDA), a vehicle-mounted computer, a wearable display device, and the like. The embodiment of the present invention is not particularly limited to the specific form of the display device 100 described above.

Referring to fig. 1B and 1C, the display panel 200 includes a display area AA and a peripheral area BB located at least one side of the display area AA, wherein a plurality of sub-pixels 21 and a plurality of scan signal lines S are disposed in the display area AA, and the plurality of sub-pixels 21 are disposed in the display area AA according to a specified rule, wherein the sub-pixels 21 are minimum units for performing picture display in the display panel 200, each sub-pixel 21 may display a single color, such as red, green or blue, and by adjusting the brightness of different sub-pixels 21, the color superposition may realize the display of multiple colors. Wherein each sub-pixel 21 comprises a light emitting device OLED and a pixel driving circuit 211 for driving the light emitting device OLED to emit light. The pixel driving circuit 211 is coupled to the scan signal line S, so as to receive the scan signal from the scan signal line S.

Referring to fig. 1C, in some embodiments, the peripheral region BB is provided with a gate driving circuit 300, and the gate driving circuit 300 includes a peripheral signal trace and a multi-stage cascade shift register 400', wherein the peripheral signal trace may provide an operation signal for the shift register 400'. The shift register 400 'mainly comprises a transistor, a capacitor and other devices, and in the working process of the shift register 400', the potential of an internal control node is controlled through the transistor and the capacitor, so that the output of a scanning signal is realized. The output end of the shift register 400 'is coupled to the scan signal line S, and the pixel driving circuit 211 is coupled to the scan signal line S, so that the scan signal outputted from the output end of the shift register 400' can be transmitted to the pixel driving circuit 211 through the scan signal line S.

Referring to fig. 1C, the display panel includes a plurality of sub-pixels arranged in an array, and a plurality of scan signal lines S extending along a row direction of the plurality of sub-pixels, wherein one scan signal line S is electrically connected to one row of sub-pixels 21, i.e. one scan signal line S can provide scan signals for one row of sub-pixels 21, and the plurality of scan signals scan the plurality of rows of sub-pixels row by row, so that the plurality of rows of sub-pixels are opened gradually. As shown in fig. 3A, taking the pixel driving circuit of "7T1C" as an example, the pixel driving circuit 211 includes a first reset transistor T8, a compensation transistor T9, a driving transistor T10, a writing transistor T11, a first light emitting control transistor T12, a second light emitting control transistor T13, a second reset transistor T14, and a second capacitor C2, in the pixel driving circuit 21, the writing transistor T11 is turned on by one scan signal to write a data voltage, the first light emitting control transistor T12 and the second light emitting control transistor T13 are turned on by another scan signal to make the light emitting device emit light, so that one row of pixel driving circuit 211 is electrically connected to at least two gate scan signal lines, one shift register 400 'can output one scan signal, and one row of pixel driving circuit 211 needs at least two shift registers 400' to supply the scan signal thereto.

Illustratively, the shift register 400' in the display panel 200 includes a gate scan shift register 401 and a light emission control shift register 402, the gate scan shift register 401 is capable of outputting a gate scan signal G (n) and transmitting to one row of sub-pixels 21 through one scan signal line S (e.g., the gate scan signal line G), and the light emission control shift register 402 is capable of outputting a light emission control signal Em (n) and transmitting to one row of sub-pixels 21 through one scan signal line S (e.g., the light emission control signal line Em).

At least two shift registers 400' are needed for providing scan signals to one row of sub-pixels 21, which results in a larger number of shift registers 400' being required in the display panel 200, and each shift register 400 includes a plurality of transistors and capacitors, so that the shift registers 400' occupy a larger space, which is disadvantageous for the design of the narrow frame display panel 200.

Based on this, some embodiments of the present invention provide a shift register 400, referring to fig. 2A, the shift register 400 includes a shift register circuit 410 and a signal output circuit 420, the shift register circuit 410 may generate an initial scan signal and transmit the initial scan signal goa (n) to the signal output circuit 420, and the signal output circuit 420 may output a first scan signal and a second scan signal at a first scan signal output terminal G (n) and a second scan signal output terminal EM (n), respectively, according to the initial scan signal goa (n), wherein the first scan signal is, for example, a gate scan signal G (n), and the second scan signal is a light emission control signal EM (n). Therefore, the shift register 400 provided by the present invention can provide two signals, namely the gate scan signal g (n) and the light emission control signal em (n), so as to reduce the number of shift registers 400 in the display panel 200, which is beneficial to narrowing the frame of the display panel 200.

The structure of the shift register 400 is described below. Referring to fig. 2A, the shift register circuit 410 in the shift register 400 is electrically connected to the initial scan signal output terminal GOA (n), and the shift register circuit 410 is configured to output the initial scan signal GOA (n) at the initial scan signal output terminal GOA (n).

Referring to fig. 2A, the signal output circuit 420 in the shift register 400 is electrically connected to an initial scan signal input terminal VIN (n), a control signal terminal CT, a first clock signal terminal CLK1, a first voltage signal terminal V1, a second voltage signal terminal V2, a third voltage signal terminal V3, a first scan signal output terminal G (n) and a second scan signal output terminal EM (n), and the initial scan signal input terminal VIN (n) is electrically connected to the initial scan signal output terminal GOA (n).

The initial scan signal input terminal VIN (n) is electrically connected to the initial scan signal output terminal GOA (n), and the shift register 400 can transmit the initial scan signal GOA (n) output by the initial scan signal output terminal GOA (n) to the signal output circuit 420. The first voltage signal transmitted from the first voltage signal terminal V1 to the signal output circuit 420 is a constant voltage signal, the second voltage signal transmitted from the second voltage signal terminal V2 to the signal output circuit 420 is a constant voltage signal, and the third voltage signal transmitted from the third voltage signal terminal V3 to the signal output circuit 420 is a constant voltage signal. Wherein, there is a voltage difference between the first voltage signal and the second voltage signal, and a voltage difference between the first voltage signal and the third voltage signal.

The signal output circuit 420 is configured to output the first scan signal at the first scan signal output terminal G (n), the second scan signal at the second scan signal output terminal EM (n) in response to the control signal received at the control signal terminal CT, the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n), the first clock signal CLK1 received at the first clock signal terminal CLK1, the first voltage signal received at the first voltage signal terminal V1, the second voltage signal received at the second voltage signal terminal V2, and the third voltage signal received at the third voltage signal terminal V3. The first scan signal and the second scan signal can be respectively transmitted to the pixel driving circuit 211 through two scan signal lines S.

The signal output circuit 420 may form a first scan signal and a second scan signal according to the control signal, the initial scan signal goa (n), the first clock signal clk1, the first voltage signal, the second voltage signal, and the third voltage signal. Optionally, the waveforms of the first scan signal and the second scan signal are not identical. And the first scan signal is one signal required for the sub-pixel electrically connected to the shift register 400, and the second scan signal is another signal required for the sub-pixel.

One shift register 400 may be electrically connected to one row of sub-pixels through at least one scan signal line S, and further transmit a scan signal to the sub-pixels electrically connected to the shift register 400. The first scan signal and the second scan signal generated by one shift register 400 may be transmitted to the same row of sub-pixels through two scan signal lines, respectively, that is, the shift register 400 provided in some embodiments of the present disclosure may provide signals with two waveforms that are not identical to each other for the same row of sub-pixels. Further, the number of shift registers 400 in the display panel 200 is reduced, and the occupied area of the shift registers 400 is reduced, which is beneficial to narrowing the frame of the display panel 200. In some embodiments, the first scan signal is a gate scan signal g (n) required for the sub-pixel 21 electrically connected to the shift register 400, and the second scan signal is a light emission control signal em (n) required for the sub-pixel 21.

Referring to fig. 2B, a plurality of gate scan signal lines G are disposed in the display panel 200, and each of the gate scan signal lines G may be electrically connected to a first scan signal output terminal G (n) in one of the shift registers 400 to receive the gate scan signal G (n). In addition, each gate scan signal line G may be electrically connected to one row of the sub-pixels 21 to transmit the gate scan signal G (n) received at the first scan signal output terminal G (n) to one row of the sub-pixels 21, wherein the gate scan signal line G extends in the X direction.

The display panel 200 is further provided with a plurality of emission control signal lines Em, and each emission control signal line Em may be electrically connected to the second scan signal output terminal Em (n) in one shift register 400 to receive the emission control signal Em (n). In addition, each emission control signal line Em may be electrically connected to one row of sub-pixels 21 to transmit the emission control signal Em (n) received at the second scan signal output terminal Em (n) to one row of sub-pixels 21, wherein the gate scan signal line G extends in the X direction.

In summary, the shift register 400 according to some embodiments of the present invention can provide the gate scan signal g (n) and the light emission control signal em (n), that is, one shift register 400 can provide two different scan signals for the sub-pixel 21, which is equivalent to the shift register 400 realizing the functions of the gate scan shift register 401 and the light emission control shift register 402 in fig. 1C, so that the number of shift registers in the display panel 200 can be reduced, the space occupied by the shift registers in the display panel 200 can be reduced, and the frame can be narrowed.

The gate scan signal G (n) and the emission control signal Em (n) output from the shift register 400 are respectively transmitted to the pixel driving circuit 211 via the gate scan signal line G and the emission control signal line Em, and in some embodiments, the pixel driving circuit 211 may be a circuit including 2T1C, 7T1C or 6T1C, where T represents a transistor, C represents a capacitor, and the pixel driving circuit 211 in 7T1C mode is described as an example.

For example, referring to fig. 3A, the pixel driving circuit 211 may include a first reset transistor T8, a compensation transistor T9, a driving transistor T10, a writing transistor T11, a first light emitting control transistor T12, a second light emitting control transistor T13, a second reset transistor T14, and a second capacitor C2, and the scan signal line S electrically connected to the pixel driving circuit 211 includes a gate scan signal line G, a reset signal line Rst, and a light emitting control signal line Em, and further, the pixel driving circuit 211 is electrically connected to the first high voltage signal line Vdd and the third low voltage signal line Vss.

Wherein, the gate of the first reset transistor T8 is electrically connected to the reset signal line Rst, the first pole of the first reset transistor T8 is electrically connected to the initialization signal line Vt, and the second pole of the first reset transistor T8 is electrically connected to the driving node a; the gate of the compensation transistor T9 is electrically connected to the gate scanning signal line G, the first pole of the compensation transistor T9 is electrically connected to the second pole of the driving transistor T10, and the second pole of the compensation transistor T9 is electrically connected to the driving node A; the gate of the driving transistor T10 is electrically connected to the driving node a; the gate of the writing transistor T11 is electrically connected to the gate scanning signal line G, the first pole of the writing transistor T11 is electrically connected to the data signal line Dt, and the second pole of the writing transistor T11 is electrically connected to the first pole of the driving transistor T10; the grid electrode of the first light-emitting control transistor T12 and the grid electrode of the second light-emitting control transistor T13 are electrically connected to a light-emitting control signal line Em, the first pole of the first light-emitting control transistor T12 is electrically connected with a first high voltage signal line Vdd, the second pole of the first light-emitting control transistor T12 is electrically connected with the first pole of the driving transistor T10, the first pole of the second light-emitting control transistor T13 is electrically connected with the second pole of the driving transistor T10, and the second pole of the second light-emitting control transistor T13 is electrically connected with the anode of the light-emitting device OLED; the gate of the second reset transistor T14 is electrically connected to the gate scan signal line G, the first electrode of the second reset transistor T14 is electrically connected to the initialization signal line Vt, the second electrode of the second reset transistor T14 is electrically connected to the anode of the light emitting device OLED, and the cathode of the light emitting device OLED is electrically connected to the third low voltage signal line Vss.

Alternatively, the voltage at which the first electrode of the second reset transistor T14 is electrically connected to the initialization signal line Vt may be different from the voltage at which the first electrode of the first reset transistor T8 is electrically connected to the initialization signal line Vt.

The gate scan signal line G, the reset signal line Rst, and the emission control signal line Em are electrically connected to the pixel driving circuit 211 in a row of sub-pixels corresponding to the first-stage shift register. The gate scan signal line G is electrically connected to the first scan signal output end G (n) of the shift register stage, so as to receive the gate scan signal G (n) output by the first scan signal output end G (n), and the gate scan signal line G is used for transmitting the gate scan signal G (n); the emission control signal line Em is electrically connected to the second scan signal output end Em (n) of the shift register stage, so as to receive the emission control signal Em (n) output by the second scan signal output end Em (n), and the emission control signal line Em is used for transmitting the emission control signal Em (n). The reset signal line Rst is used for transmitting a reset timing signal Rst, and in some embodiments, the reset signal line Rst is connected to the first scan signal output terminal G (n) in the upper stage shift register 400 to receive the gate scan signal G (n-1) output by the upper stage shift register 400, that is, the gate scan signal G (n-1) output by the upper stage shift register 400 can be used as the reset timing signal Rst required by the sub-pixels 21 of the present row. The initialization signal line Vt is used for transmitting an initialization signal, and the data signal line Dt is used for transmitting a data signal Dt. As shown in fig. 2B, the data signal line Dt and the first high voltage signal line Vdd extend in the Y direction.

In some embodiments, each transistor in the pixel driving circuit 211 may be a P-type transistor that is turned on when the gate receives a low voltage signal. In other embodiments, each transistor in the pixel driving circuit 211 may be an N-type transistor that is turned on when the gate receives a high voltage signal. In addition, in other embodiments, some of the transistors in the pixel driving circuit 211 are N-type transistors, and the rest are P-type transistors, for example: t8 and T9 are N-type tubes, and the rest are P-type tubes. It should be noted that the above-mentioned "high voltage signal" and "low voltage signal" are colloquially referred to, and generally speaking, the on condition of the N-type transistor is that the gate-source voltage difference is greater than the threshold voltage thereof, that is, the gate voltage of the N-type transistor is greater than the sum of the source voltage thereof and the threshold voltage thereof, the threshold voltage of the N-type transistor is positive, that the gate voltage signal for conducting the N-type transistor is a high voltage signal, the on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than the threshold voltage thereof, that the threshold voltage of the P-type transistor is negative, that is, the gate voltage signal for conducting the P-type transistor is less than the sum of the source voltage thereof and the threshold voltage thereof, that the level of the "high voltage signal" and the "low voltage signal" is relative to the reference voltage (e.g. 0V).

The following describes the driving process of the pixel driving circuit 211 with reference to the timing chart of the pixel driving circuit 211 shown in fig. 3B by taking the P-type transistors as examples of the transistors in the pixel driving circuit 211.

The driving process of the pixel driving circuit 211 is as follows: one frame period includes a pixel initialization phase t21, a refresh and compensation phase t22, and a light emission phase t30. In fig. 3B and fig. 4A, in the pixel initializing stage T21, the reset timing signal rst is at a low level, and the first reset transistor T8 is turned on under the control of the reset timing signal rst, so that the initializing signal is written into the driving node a, and the driving node a is reset. The gate scan signal g (n) and the light emission control signal em (n) are both at high level, and the compensation transistor T9, the write transistor T11, and the second reset transistor T14 are in an off state under the control of the gate scan signal g (n). The first light emission control transistor T12 and the second light emission control transistor T13 are in an off state under the control of the light emission control signal em (n). At this time, the driving transistor T10 is turned on, but the light emitting device OLED does not emit light.

Referring to fig. 3B and 4B, in the refresh and compensation stage T22, the reset timing signal rst is high, and the first reset transistor T8 is turned off under the control of the reset timing signal rst. The gate scan signal g (n) is at a low level, and the second reset transistor T14 is turned on under the control of the gate scan signal g (n), so that an initialization signal is written to the anode of the light emitting device OLED, thereby resetting the anode of the light emitting device OLED. The write transistor T11 is turned on under the control of the gate scan signal g (n), the compensation transistor T9 is turned on under the control of the gate scan signal g (n), and the driving transistor T10 maintains the on state of the pixel initialization stage T21, so that the data signal dt can be sequentially transmitted to the driving node a through the write transistor T11, the driving transistor T10 and the compensation transistor T9, so that the voltage of the driving node a is changed until the voltage of the driving node a reaches the sum of the threshold voltage of the driving transistor T10 and the voltage of the data signal dt, so that the driving transistor T10 is turned off. In the refresh and compensation stage T22, the threshold voltage of the driving transistor T10 can be written into the driving node a to compensate the threshold voltage drift of the driving transistor T10, so as to avoid the change of the driving signal generated by the driving transistor T10 and reduce the influence on the light emitting intensity of the light emitting device OLED. At this stage, the light emission control signal em (n) is at a high level, and the first light emission control transistor T12 and the second light emission control transistor T13 are in an off state under the control of the light emission control signal em (n).

Referring to fig. 3B and 4C, in the light emitting period, the gate scan signal g (n) is at a high level, and the second reset transistor T14 is turned off under the control of the gate scan signal g (n). The reset timing signal rst is at a high level, the first reset transistor T8 is turned off under the control of the reset timing signal rst, the compensation transistor T9 is turned off under the control of the gate scan signal g (n), and the write transistor T11 and the second reset transistor T14 are turned off under the control of the gate scan signal g (n). The light emission control signal em (n) is at a low level, the first light emission control transistor T12 and the second light emission control transistor T13 are turned on under the control of the light emission control signal em (n), so that a first voltage signal transmitted in the first high voltage signal line Vdd is written to a first electrode of the driving transistor T10, an anode voltage of the light emitting device OLED can be written to a second electrode of the driving transistor T10, so that the driving transistor T10 is turned on, a path is formed between the first high voltage signal line Vdd and the light emitting device OLED, and the first voltage signal is written to an anode of the light emitting device OLED, so that the light emitting device OLED emits light.

Optionally, in some embodiments the signal output circuit 420 in the shift register 400 is configured to provide the gate scan signal g (n) and the reset timing signal rst to the pixel driving circuit 211 to which the shift register 400 is connected; for example: the shift register 400 provides the gate scan signal g (n) and the reset timing signal rst to the connected T9, T8 of the pixel driving circuit 211, respectively, i.e., the first scan signal g (n) and the second scan signal rst are the gate scan signal g (n) and the reset timing signal rst, respectively.

Optionally, in some embodiments the signal output circuit 420 in the shift register 400 is configured to provide signals to T11 and T9, respectively, of the pixel driving circuit 211 to which the shift register 400 is connected, for example: t11 is a P-type tube and T9 is an N-type tube. It can be understood that at this time, the gates of T11 and T9 are respectively connected to two different signal lines, so as to provide signals with two different waveforms, which are not identical, for T11 and T9.

Optionally, the signal output circuit 420 in the shift register 400 according to some embodiments of the present invention is configured to provide the gate scan signal g (n) and the light emission control signal em (n) to the pixel driving circuit 211 connected to the shift register 400, that is, the first scan signal g (n) and the second scan signal em (n) are respectively.

Some embodiments of the present invention provide a driving method of a shift register, the driving method including: the shift register circuit 410 outputs an initial scan signal GOA (n) at an initial scan signal output terminal GOA (n); the signal output circuit 420 outputs the first scan signal at the first scan signal output terminal G (n) and the second scan signal at the second scan signal output terminal EM (n) in response to the control signal received at the control signal terminal CT, the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n), the first clock signal CLK1 received at the first clock signal terminal CLK1, the first voltage signal received at the first voltage signal terminal V1, the second voltage signal received at the second voltage signal terminal V2, and the third voltage signal received at the third voltage signal terminal V3; the waveform of the first scanning signal is not identical to the waveform of the second scanning signal.

The driving method of the shift register according to some embodiments of the present invention may be used in the shift register 400 according to some embodiments of the present invention, so that the shift register 400 outputs the first scan signal and the second scan signal with different waveforms.

The signal output circuit 420 of the shift register 400 can supply the gate scan signal g (n) and the light emission control signal em (n) to the same row of subpixels. In some embodiments, referring to fig. 5A, 5B, and 5C, the signal output circuit 420 includes: a first scanning signal output circuit 421 and a second scanning signal output circuit 422. The first scan signal output circuit 421 is configured to output a first scan signal, i.e., a gate scan signal g (n), and the second signal output circuit 420 is configured to output a second scan signal, i.e., a light emission control signal em (n). The first scanning signal output circuit 421 and the second scanning signal output circuit 422 will be specifically described below taking the shift register 400 for providing the gate scanning signal g (n) and the emission control signal em (n) to the pixel driving circuit 211 in which each transistor is a P-type transistor.

In some embodiments, referring to fig. 5A, 5B and 5C, the first scan signal output circuit 421 is electrically connected to the control signal terminal CT, the initial scan signal input terminal VIN (n), the first clock signal terminal CLK1 and the first scan signal output terminal G (n). The first scan signal output circuit 421 is configured to output the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) and the first clock signal CLK1 received at the first clock signal terminal CLK1 by the first scan signal output terminal G (n) at different stages, respectively, in response to the control signal received at the control signal terminal CT, thereby causing the first scan signal output terminal G (n) to output the first scan signal, i.e., the gate scan signal G (n).

Referring to fig. 5D, in the pixel initialization stage T21, the first scan signal, i.e., the gate scan signal g (n), is at a high level, in the refresh and compensation stage T22, the gate scan signal g (n) is at a low level, and at this time, the writing transistor T11 and the compensation transistor T9 in the pixel driving circuit 211 are turned on under the control of the gate scan signal g (n). In the light emitting stage, the gate scan signal g (n) is at a high level.

In some embodiments, referring to fig. 5A, 5B and 5C, the second scan signal output circuit 422 is electrically connected to the initial scan signal input terminal VIN (n), the first voltage signal terminal V1, the second voltage signal terminal V2, the third voltage signal terminal V3 and the second scan signal output terminal EM (n); the second scan signal output circuit 422 is configured to output the first voltage signal received at the first voltage signal terminal V1 and the second voltage signal received at the second voltage signal terminal V2 by the second scan signal output terminal EM (n) at different stages, respectively, in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) and the third voltage signal received at the third voltage signal terminal V3, thereby causing the second scan signal output terminal EM (n) to output the second scan signal. The first voltage signal terminal V1 is a first high voltage signal terminal VDD, and the first voltage signal is a high level signal; the second voltage signal terminal V2 is a second low voltage signal terminal VGL, and the second voltage signal is a low level signal; the third voltage signal terminal V3 is the first low voltage signal terminal VSS, the third voltage signal is a low level signal, and a voltage difference exists between the second voltage signal and the third voltage signal. The voltage of the second voltage signal and the voltage of the third voltage signal can be negative, and the voltage of the first voltage signal is positive. In other examples, the voltage of the second voltage signal and the voltage of the third voltage signal may be the same positive value, and at this time, the voltage of the first voltage signal may be a negative value.

In the pixel initialization stage t21, referring to fig. 5D, the second scan signal, i.e., the light emission control signal em (n), is at a high level; in the refresh and compensation stage t22, the light emission control signal em (n) is high level; in the light emitting stage, the light emission control signal em (n) is at a low level, and at this time, the first light emission control transistor T12 and the second light emission control transistor T13 in the pixel driving circuit 211 are turned on under the control of the gate scan signal g (n). The second scan signal output circuit 422 transmits the first voltage signal and the second voltage signal to the second scan signal output terminal EM (n) at different stages under the control of the initial scan signal goa (n) and the third voltage signal. The first voltage signal and the second voltage signal are constant voltage signals, and the second scanning signal has different levels in different stages, so that one of the first voltage signal and the second voltage signal is a high level signal, and the other is a low level signal. Illustratively, the first voltage signal is a high level signal and the second voltage signal is a low level signal.

Some embodiments of the present invention also provide a driving method of the shift register 400, the driving method including: as shown in fig. 5D, one frame period includes: the pixel driving circuit comprises a charging stage t1, an output stage t2 and a reset stage t3, wherein the output stage t2 comprises a pixel initializing stage t21 and a refreshing and compensating stage t22, and the reset stage t3 comprises a first light-emitting stage t31 and a second light-emitting stage t32. The driving method of the shift register 400 is described below taking the example that the gate scan signal g (n) and the light emission control signal em (n) outputted from the shift register 400 are used for the pixel driving circuit 211 of 7T1C, and the transistors in the pixel driving circuit 211 are P-type transistors.

In the charging stage t1, the shift register circuit 410 outputs the first level of the initial scan signal GOA (n) to the initial scan signal output terminal GOA (n). For example, referring to fig. 5D, the first level of the initial scan signal goa (n) is a high level.

In the output stage t2, the shift register circuit 410 outputs the second level of the initial scan signal GOA (n) to the initial scan signal output terminal GOA (n). For example, referring to fig. 5D, the second level of the initial scan signal goa (n) is a low level. The output stage t2 corresponds to a period of the first clock signal clk1, the first clock signal clk1 is at a high level in the pixel initialization stage t21 of the output stage t2, and the first clock signal clk1 is changed to a low level in the refresh and compensation stage t22 of the output stage t 2.

In the pixel initialization stage t21 in the output stage t2, the first scan signal output circuit 421 transmits the first clock signal CLK1 received at the first clock signal terminal CLK1 to the first scan signal output terminal G (n) in response to the control signal received at the control signal terminal CT. The second scan signal output circuit 422 transmits the first voltage signal received at the first voltage signal terminal V1 to the second scan signal output terminal EM (n) in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n).

In the pixel initialization stage t21, the first scan signal output circuit 421 transmits the first clock signal clk1 to the first scan signal output terminal G (n) under the control of the control signal. For example, referring to fig. 5D, the first clock signal clk1 is at a high level, and further, the first scan signal, i.e., the gate scan signal g (n), is at a high level in the pixel initialization stage t 21.

In the pixel initializing period t21, the second scan signal output circuit 422 transmits the first voltage signal to the second scan signal output terminal EM (n) under the control of the initial scan signal goa (n). For example, referring to fig. 5D, the first voltage signal is a high level signal, and the second scan signal, i.e., the light emission control signal em (n), is high level in the pixel initialization stage t 21.

In the refresh and compensation stage t22 in the output stage t2, the first scan signal output circuit 421 transmits the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) to the first scan signal output terminal G (n) in response to the control signal received at the control signal terminal CT. The second scan signal output circuit 422 transmits the first voltage signal received at the first voltage signal terminal V1 to the second scan signal output terminal EM (n) in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n).

In the refresh and compensation stage t22, the first scan signal output circuit 421 transmits the initial scan signal goa (n) to the first scan signal output terminal G (n) under the control of the control signal, and for example, referring to fig. 5D, the initial scan signal goa (n) is at a low level, and the gate scan signal G (n) is at a low level in the refresh and compensation stage t 22.

In the refresh and compensation stage t22, the second scan signal output circuit 422 transmits the first voltage signal to the second scan signal output terminal EM (n) under the control of the initial scan signal goa (n). For example, referring to fig. 5D, the first voltage signal is a high level signal, and the second scan signal is high level in the refresh and compensation phase t 22.

In the reset phase t3, the shift register circuit 410 outputs the first level of the initial scan signal GOA (n) to the initial scan signal output terminal GOA (n). For example, referring to fig. 5D, the initial scan signal goa (n) is at a high level in the reset phase t 3.

In the first light emitting stage t31 of the reset stage t3, the first scan signal output circuit 421 transmits the first clock signal CLK1 received at the first clock signal terminal CLK1 to the first scan signal output terminal G (n) in response to the control signal received at the control signal terminal CT. The second scan signal output circuit 422 transmits the second voltage signal received at the second voltage signal terminal V2 to the second scan signal output terminal EM (n) in response to the third voltage signal received at the third voltage signal terminal V3.

In the first light emitting stage t31, the first scan signal output circuit 421 transmits the first clock signal clk1 to the first scan signal output terminal G (n) under the control of the control signal. For example, referring to fig. 5D, the first clock signal clk1 is at a high level in the first light emitting period t31, and further the first scan signal, i.e., the gate scan signal g (n), is at a high level in the first light emitting period t 31.

In the first light emitting stage t31, the second scan signal output circuit 422 may transmit the second voltage signal to the second scan signal output terminal EM (n) according to the third voltage signal. For example, referring to fig. 5D, the second voltage signal is a low level signal, and thus the second scan signal, i.e., the light emission control signal em (n), is at a low level in the first light emission period t 31.

In the second light emitting period t32 of the reset period t3, the first scan signal output circuit 421 transmits the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) to the first scan signal output terminal G (n) in response to the control signal received at the control signal terminal CT. The second scan signal output circuit 422 transmits the second voltage signal received at the second voltage signal terminal V2 to the second scan signal output terminal EM (n) in response to the third voltage signal received at the third voltage signal terminal V3.

In the second light emitting stage t32, the first scan signal output circuit 421 transmits the initial scan signal goa (n) to the first scan signal output terminal G (n) under the control of the control signal. For example, referring to fig. 5D, the initial scan signal goa (n) is at a high level in the second light-emitting period t32, and thus the first scan signal, i.e., the gate scan signal g (n), is at a high level in the second light-emitting period t 32.

In the second light emitting stage t32, the second scan signal output circuit 422 may transmit the second voltage signal to the second scan signal output terminal EM (n) according to the third voltage signal. For example, referring to fig. 5D, the second voltage signal is a low level signal, and thus the second scan signal, i.e., the light emission control signal em (n), is at a low level in the second light emission period t 32.

In summary, according to the driving method of the shift register 400 provided by some embodiments of the present invention, the first scan signal output circuit 421 can output the first clock signal clk1 in the pixel initialization stage t21, output the initial scan signal goa (n) in the refresh and compensation stage t22, output the first clock signal clk1 in the first light-emitting stage t31, output the initial scan signal goa (n) in the second light-emitting stage t32, and further form the first scan signal, i.e. the gate scan signal g (n) by the first clock signal clk1 and the initial scan signal goa (n) output in different stages. The second scan signal output circuit 422 may output a first voltage signal in the pixel initializing stage t21, a first voltage signal in the refresh and compensation stage t22, a second voltage signal in the first light emitting stage t31, and a second voltage signal in the second light emitting stage t32, so that the first voltage signal and the second voltage signal output in different stages form a second scan signal, i.e., a light emitting control signal em (n).

The first light-emitting stage t31 and the second light-emitting stage t32 both belong to the light-emitting stage t30, and therefore, the light-emitting stage t30 and the reset stage t3 are the same stage.

In some embodiments of the present invention, the first scan signal output circuit 421 is configured to output a first scan signal, and in some embodiments, referring to fig. 5B and 5C, the first scan signal output circuit 421 includes: the first output sub-circuit 4211 and the second output sub-circuit 4212, and the control signal terminal CT includes a second clock signal terminal CLK2 and a third clock signal terminal CLK3. The first output sub-circuit 4211 is electrically connected to the second clock signal terminal CLK2, the first clock signal terminal CLK1, and the first scan signal output terminal G (n), and the first output sub-circuit 4211 is configured to transmit the first clock signal CLK1 received at the first clock signal terminal CLK1 to the first scan signal output terminal G (n) in response to the second clock signal CLK2 received at the second clock signal terminal CLK 2. The second output sub-circuit 4212 is electrically connected to the third clock signal terminal CLK3, the initial scan signal input terminal VIN (n), and the first scan signal output terminal G (n), and the second output sub-circuit 4212 is configured to transmit the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) to the first scan signal output terminal G (n) in response to the third clock signal CLK3 received at the third clock signal terminal CLK3.

The first output sub-circuit 4211 may be controlled by the second clock signal CLK2 to turn on or off the first clock signal terminal CLK1 and the first scan signal output terminal G (n). The second output sub-circuit 4212 may switch on or off the initial scan signal input terminal VIN (n), i.e., the initial scan signal output terminal GOA (n), and the first scan signal output terminal G (n) under the control of the third clock signal clk 3. It should be noted that, when the first clock signal terminal CLK1 is turned on to the first scan signal output terminal G (n), the initial scan signal input terminal VIN (n) is disconnected from the first scan signal output terminal G (n). When the first clock signal terminal CLK1 is disconnected from the first scan signal output terminal G (n), the initial scan signal input terminal VIN (n) is connected to the first scan signal output terminal G (n).

Some embodiments of the present invention provide a driving method of a shift register 400, which further includes: referring to fig. 5D and 6A, in the pixel initialization stage t21, the first output sub-circuit 4211 transmits the first clock signal CLK1 received at the first clock signal terminal CLK1 to the first scan signal output terminal G (n) in response to the second clock signal CLK2 received at the second clock signal terminal CLK 2. The second output sub-circuit 4212 disconnects the initial scan signal input terminal VIN (n) from the first scan signal output terminal G (n) in response to the third clock signal CLK3 received at the third clock signal terminal CLK 3.

Referring to fig. 5D, the period of the second clock signal clk2 is the same as the period of the first clock signal clk1, and the waveform of the second clock signal clk2 is opposite to that of the first clock signal clk1, and the second clock signal clk2 goes through one period in the output phase t2, the second clock signal clk2 is at a low level in the pixel initialization phase t21 of the output phase t2, and the second clock signal clk2 is at a high level in the refresh and compensation phase t22 of the output phase t 2.

Referring to fig. 5D, the period of the third clock signal clk3 is the same as that of the first clock signal clk1, the waveform of the third clock signal clk3 is the same as that of the first clock signal clk1, and the third clock signal clk3 goes through one period in the output phase t2, the third clock signal clk3 is at a high level in the pixel initialization phase t21 of the output phase t2, and the third clock signal clk3 is at a low level in the refresh and compensation phase t22 of the output phase t 2.

In some embodiments, the second clock signal clk2 may be appropriately shifted from the first clock signal clk1 (or the third clock signal clk 3), i.e., the rising edge of the second clock signal clk2 is not at the same time as the falling edge of the first clock signal clk1, and the level of the second clock signal clk2 changes slightly in advance or behind the level of the first clock signal clk 1.

In fig. 6A, in the pixel initialization stage t21, the first output sub-circuit 4211 is in a conductive state under the control of the second clock signal clk 2; under the control of the third clock signal clk3, the second output sub-circuit 4212 is in an off state, and thus the first clock signal clk1 can be transmitted to the first scan signal output terminal G (n), and the initial scan signal goa (n) cannot be transmitted to the first scan signal output terminal G (n).

Referring to fig. 5D and 6B, during the refresh and compensation phase t22, the first output sub-circuit 4211 disconnects the first clock signal terminal CLK1 from the first scan signal output terminal G (n) in response to the second clock signal CLK2 received at the second clock signal terminal CLK 2; the second output sub-circuit 4212 transmits the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) to the first scan signal output terminal G (n) in response to the third clock signal CLK3 received at the third clock signal terminal CLK 3.

Referring to fig. 6B, in the refresh and compensation stage t22, the first output sub-circuit 4211 is in an off state under the control of the second clock signal clk 2; under the control of the third clock signal clk3, the second output sub-circuit 4212 is in a conductive state, so that the first clock signal clk1 cannot be transmitted to the first scan signal output terminal G (n), and the initial scan signal goa (n) can be transmitted to the first scan signal output terminal G (n).

Referring to fig. 5D and 6C, in the first light-emitting stage t31, the first output sub-circuit 4211 transmits the first clock signal CLK1 received at the first clock signal terminal CLK1 to the first scan signal output terminal G (n) in response to the second clock signal CLK2 received at the second clock signal terminal CLK 2; the second output sub-circuit 4212 disconnects the initial scan signal input terminal VIN (n) from the first scan signal output terminal G (n) in response to the third clock signal CLK3 received at the third clock signal terminal CLK 3.

In fig. 6C, in the first light emitting stage t31, the first output sub-circuit 4211 is in a conductive state under the control of the second clock signal clk 2; under the control of the third clock signal clk3, the second output sub-circuit 4212 is in an off state, and thus the first clock signal clk1 can be transmitted to the first scan signal output terminal G (n), and the initial scan signal goa (n) cannot be transmitted to the first scan signal output terminal G (n).

Referring to fig. 5D and 6D, in the second light emitting stage t32, the first output sub-circuit 4211 disconnects the first clock signal terminal CLK1 from the first scan signal output terminal G (n) in response to the second clock signal CLK2 received at the second clock signal terminal CLK 2; the second output sub-circuit 4212 transmits the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n) to the first scan signal output terminal G (n) in response to the third clock signal CLK3 received at the third clock signal terminal CLK 3.

In fig. 6D, in the second light emitting stage t32, the first output sub-circuit 4211 is in an off state under the control of the second clock signal clk 2; under the control of the third clock signal clk3, the second output sub-circuit 4212 is in a conductive state, so that the first clock signal clk1 cannot be transmitted to the first scan signal output terminal G (n), and the initial scan signal goa (n) can be transmitted to the first scan signal output terminal G (n).

In summary, the first output sub-circuit 4211 and the second output sub-circuit 4212 provided in some embodiments of the present invention may be turned on in different stages, so that the first clock signal clk1 and the initial scan signal goa (n) are transmitted to the first scan signal output terminal G (n) in different stages.

In some embodiments, referring to fig. 5C, the first output sub-circuit 4211 comprises a first transistor T1, wherein a control electrode of the first transistor T1 is electrically connected to the second clock signal terminal CLK2, a first electrode of the first transistor T1 is electrically connected to the first clock signal terminal CLK1, and a second electrode of the first transistor T1 is electrically connected to the first scan signal output terminal G (n). The first transistor T1 may be turned on or off between the first pole and the second pole of the first transistor T1 under the control of the second clock signal clk2, and the first clock signal clk1 may be transmitted to the first scan signal output terminal G (n) when the first pole and the second pole of the first transistor T1 are turned on.

In some examples, the first transistor T1 is a P-type transistor, and when the second clock signal clk2 is at a low level, the first transistor T1 is turned on. In other examples, the first transistor T1 is an N-type transistor, and the first transistor T1 is turned on when the second clock signal clk2 is at a high level.

In some embodiments, referring to fig. 5C, the second output sub-circuit 4212 comprises a second transistor T2, a control electrode of the second transistor T2 is electrically connected to the third clock signal terminal CLK3, a first electrode of the second transistor T2 is electrically connected to the initial scan signal input terminal VIN (n), and a second electrode of the second transistor T2 is electrically connected to the first scan signal output terminal G (n). The second transistor T2 may be turned on or off between the first pole and the second pole of the second transistor T2 under the control of the third clock signal clk3, and the initial scan signal goa (n) may be transmitted to the first scan signal output terminal G (n) when the first pole and the second pole of the second transistor T2 are turned on.

In some examples, the second transistor T2 is a P-type transistor, and when the third clock signal clk3 is at a low level, the second transistor T2 is turned on. In other examples, the second transistor T2 is an N-type transistor, and when the third clock signal clk3 is at a high level, the second transistor T2 is turned on.

In some embodiments, the first transistor T1 and the second transistor T2 are P-type transistors, and the shift register 400 and the driving method provided in some embodiments of the invention are specifically described below by taking the first transistor T1 and the second transistor T2 as P-type transistors as examples.

Referring to fig. 5D and 6A, in the pixel initialization stage T21, the second clock signal clk2 is at a low level, and under the control of the second clock signal clk2, the first transistor T1 is turned on, so that the first clock signal clk1 is transmitted to the first scan signal output terminal G (n), at this time, the first clock signal clk1 is at a high level, and then the first scan signal, i.e., the gate scan signal G (n), is at a high level in the pixel initialization stage T21. The third clock signal clk3 is at a high level, and the second transistor T2 is turned off under the control of the third clock signal clk3, so that the initial scan signal input terminal VIN (n) is turned off from the first scan signal output terminal G (n).

Referring to fig. 5D and 6B, in the refresh and compensation stage T22, the second clock signal CLK2 is at a high level, and the first transistor T1 is turned off under the control of the second clock signal CLK2, so that the first clock signal terminal CLK1 is disconnected from the first scan signal output terminal G (n). The third clock signal clk3 is at a low level, and under the control of the third clock signal clk3, the second transistor T2 is turned on, so that the initial scan signal goa (n) is transmitted to the first scan signal output terminal G (n), and at this time, the initial scan signal goa (n) is at a low level, and further the initial scan signal goa (n) is at a low level in the refresh and compensation stage T22.

Referring to fig. 5D and 6C, in the first light emitting stage T31, the second clock signal clk2 is at a low level, the first transistor T1 is turned on under the control of the second clock signal clk2, so that the first clock signal clk1 is transmitted to the first scan signal output terminal G (n), at this time, the first clock signal clk1 is at a high level, and then the first scan signal, i.e., the gate scan signal G (n), is at a high level in the pixel initializing stage T21. The third clock signal clk3 is at a high level, and the second transistor T2 is turned off under the control of the third clock signal clk3, so that the initial scan signal input terminal VIN (n) is turned off from the first scan signal output terminal G (n).

Referring to fig. 5D and 6D, in the second light emitting stage T32, the second clock signal CLK2 is at a high level, and the first transistor T1 is turned off under the control of the second clock signal CLK2, so that the first clock signal terminal CLK1 is disconnected from the first scan signal output terminal G (n). The third clock signal clk3 is at a low level, and under the control of the third clock signal clk3, the second transistor T2 is turned on, so that the initial scan signal goa (n) is transmitted to the first scan signal output terminal G (n), and at this time, the initial scan signal goa (n) is at a high level, and further the initial scan signal goa (n) is at a high level in the second light-emitting stage T32.

In some embodiments, the first transistor T1 and the second transistor T2 are P-type transistors, the first clock signal terminal CLK1 and the third clock signal terminal CLK3 are the same signal terminal, and the first scan signal output circuit 421 can receive the same clock signal at the first clock signal terminal CLK1 and the third clock signal terminal CLK 3.

The first scan signal output circuit 421 is configured to output a first scan signal, and the second scan signal output circuit 422 is configured to output a second scan signal. The second scanning signal output circuit 422 is described below.

In some embodiments, referring to fig. 5B and 5C, the second scan signal output circuit 422 includes: a third output sub-circuit 4221, a first control sub-circuit 4222, a second control sub-circuit 4223, and a fourth output sub-circuit 4224. The third output sub-circuit 4221 can output a first voltage signal under the control of the initial scan signal goa (n), and the fourth output sub-circuit 4224 can output a second voltage signal under the control of the first control sub-circuit 4222 and the second control sub-circuit 4223.

In some embodiments, referring to fig. 5B and 5C, the third output sub-circuit 4221 is electrically connected to the initial scan signal input terminal VIN (n), the first voltage signal terminal V1, and the second scan signal output terminal EM (n). The third output sub-circuit 4221 is configured to transmit the first voltage signal received at the first voltage signal terminal V1 to the second scan signal output terminal EM (n) in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n).

The third output sub-circuit 4221 may be controlled by the initial scan signal goa (n) to make the first voltage signal terminal V1 and the second scan signal output terminal EM (n) be turned on or off, and the second scan signal output terminal EM (n) may be capable of outputting the first voltage signal when the first voltage signal terminal V1 and the second scan signal output terminal EM (n) are turned on.

In some embodiments, referring to fig. 5B and 5C, the first control sub-circuit 4222 is electrically connected to the initial scan signal input terminal VIN (N), the first voltage signal terminal V1, and the first node N1, the first control sub-circuit 4222 being configured to transmit the first voltage signal received at the first voltage signal terminal V1 to the first node N1 in response to the initial scan signal goa (N) received at the initial scan signal input terminal VIN (N).

The first control sub-circuit 4222 may be controlled by the initial scan signal goa (N) to make the first voltage signal terminal V1 be connected to or disconnected from the first node N1, where the voltage of the first node N1 is the same as the voltage of the first voltage signal when the first voltage signal terminal V1 is connected to the first node N1.

In some embodiments, referring to fig. 5B and 5C, the second control sub-circuit 4223 is electrically connected to the first node N1 and the third voltage signal terminal V3, the second control sub-circuit 4223 being configured to control the voltage of the first node N1 in conjunction with the first control sub-circuit 4222 according to the third voltage signal received at the third voltage signal terminal V3.

The second control sub-circuit 4223 and the first control sub-circuit 4222 act on the first node N1 together, so as to control the voltage of the first node N1, and further control the on or off of the fourth output sub-circuit 4224. The first control sub-circuit 4222 may control whether the first voltage signal is transmitted to the first node, when the first control sub-circuit 4222 is turned off under the control of the initial scan signal goa (N), the first voltage signal cannot be transmitted to the first node N1, and at this time, the second control sub-circuit 4223 may change the voltage of the first node N1 according to the third voltage signal. Accordingly, the first control sub-circuit 4222 and the second control sub-circuit 4223 may control the voltage of the first node N1, thereby controlling the on or off of the fourth output sub-circuit 4224.

In some embodiments, referring to fig. 5B and 5C, the fourth output sub-circuit 4224 is electrically connected to the first node N1, the second voltage signal terminal V2, and the second scan signal output terminal EM (N); the fourth output sub-circuit 4224 is configured to transmit the second voltage signal received at the second voltage signal terminal V2 to the second scan signal output terminal EM (N) in response to the voltage of the first node N1.

The fourth output sub-circuit 4224 may be controlled by the voltage of the first node N1 to make the second voltage signal terminal V2 be connected or disconnected with the second scan signal output terminal EM (N), and the second scan signal output terminal EM (N) may output the second voltage signal when the second voltage signal terminal V2 is connected with the second scan signal output terminal EM (N).

Some embodiments of the present invention provide a driving method of a shift register 400, which further includes: in the pixel initializing stage t21 and the refresh and compensation stage t22, referring to fig. 6A and 6B, the third output sub-circuit 4221 transmits the first voltage signal received at the first voltage signal terminal V1 to the second scan signal output terminal EM (n) in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n). For example, referring to fig. 5D, the first voltage signal is a high level signal, and the second scan signal output terminal EM (n) outputs the first voltage signal in the pixel initialization stage t21 and the refresh and compensation stage t22, and further the second scan signal emission control signal is high level in the pixel initialization stage t21 and the refresh and compensation stage t 22.

Referring to fig. 6A and 6B, the first control sub-circuit 4222 transmits the first voltage signal received at the first voltage signal terminal V1 to the first node N1 in response to the initial scan signal goa (N) received at the initial scan signal input terminal VIN (N); the second control sub-circuit 4223 holds the voltage of the first node N1. The first control sub-circuit 4222 and the second control sub-circuit 4223 may make the voltage of the first node N1 substantially the same as the voltage of the first voltage signal terminal V1, and for example, referring to fig. 5D, the first voltage signal is a high level signal, and thus, the voltage of the first node N1 is high level in the pixel initialization phase t21 and the refresh and compensation phase t 22.

The fourth output sub-circuit 4224 is responsive to the voltage of the first node N1 to disconnect the second voltage signal terminal V2 from the second scan signal output terminal EM (N), and thus the second voltage signal cannot be transmitted to the second scan signal output terminal EM (N).

In the first and second light-emitting phases t31 and t32, referring to fig. 6C and 6D, the third output sub-circuit 4221 disconnects the first voltage signal terminal V1 from the second scan signal output terminal EM (n) in response to the initial scan signal goa (n) received at the initial scan signal input terminal VIN (n), and thus the first voltage signal cannot be transmitted to the second scan signal output terminal EM (n).

The first control sub-circuit 4222 disconnects the first voltage signal terminal V1 from the first node N1 in response to the initial scan signal goa (N) received at the initial scan signal input terminal VIN (N); the second control sub-circuit 4223 changes the voltage of the first node N1 according to the third voltage signal received at the third voltage signal terminal V3 in the case where the first voltage signal is not transmitted to the first node N1.

In the first light emitting period t31 and the second light emitting period t32, referring to fig. 6C and 6D, the first voltage signal terminal V1 is disconnected from the first node N1, and thus the first voltage signal cannot be transmitted to the first node N1.

The fourth output sub-circuit 4224 transmits the second voltage signal received at the second voltage signal terminal V2 to the second scan signal output terminal EM (N) in response to the voltage of the first node N1. For example, referring to fig. 5D, the second voltage signal is a low level signal, and the second scan signal, i.e., the light emission control signal em (n), is low level in both the first light emission period t31 and the second light emission period t 32.

In some embodiments, referring to fig. 5C, the third output sub-circuit 4221 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is electrically connected to the initial scan signal input terminal VIN (n), a first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal V1, and a second electrode of the fifth transistor T5 is electrically connected to the second scan signal output terminal EM (n). And/or, the fourth output sub-circuit 4224 comprises a sixth transistor T6, wherein a control electrode of the sixth transistor T6 is electrically connected to the first node N1, a first electrode of the sixth transistor T6 is electrically connected to the second voltage signal terminal V2, and a second electrode of the sixth transistor T6 is electrically connected to the second scan signal output terminal EM (N).

For example, the fifth transistor T5 is a P-type transistor, and in the pixel initialization stage T21 and the refresh and compensation stage T22, referring to fig. 5D, the initial scan signal goa (n) is at a low level, which can control the fifth transistor T5 to be turned on, so that the first voltage signal is transmitted to the second scan signal output end EM (n).

The sixth transistor T6 is a P-type transistor, and the first voltage signal is transmitted to the first node N1 during the pixel initialization stage T21 and the refresh and compensation stage T22, and the voltage of the first node N1 is at a high level, so that the sixth transistor T6 is in an off state, such that the second voltage signal cannot be transmitted thereto. In the first light emitting period T31 and the second light emitting period T32, the first control sub-circuit 4222 and the second control sub-circuit 4223 control the voltage of the first node N1 to be low, so that the sixth transistor T6 is turned on.

It should be noted that, when the sixth transistor T6 is a P-type transistor, the voltage of the third voltage signal is smaller than the voltage of the second voltage signal, so as to ensure that when the third voltage signal is transmitted to the first node N1, the voltage of the first electrode is subtracted from the voltage of the control electrode of the sixth transistor T6, that is, the voltage difference obtained by subtracting the voltage of the second voltage signal from the voltage of the third voltage signal is smaller than the threshold voltage of the sixth transistor T6, so that the sixth transistor T6 is turned on. The voltage of the second voltage signal and the voltage of the third voltage signal are the same as negative values. When the first voltage signal is transmitted to the first node N1, the sixth transistor T6 may be turned off, and thus the voltage of the first voltage signal is a positive value.

The following describes the structures of the two second control sub-circuits 4223 and the driving method of the corresponding shift register 400, respectively.

In some embodiments, the second control sub-circuit 4223 is configured to transmit the third voltage signal at the third voltage signal terminal V3 to the first node N1 to change the voltage of the first node N1 if the first voltage signal is not transmitted to the first node N1.

In this case, the first control sub-circuit 4222 is in an on state, i.e., the first voltage signal can be transmitted to the first node N1, and at this time, the first node N1 maintains the voltage of the first voltage signal. In the off state of the first control sub-circuit 4222, i.e. the first voltage signal cannot be transmitted to the first node N1, at this time, the second control sub-circuit 4223 can change the voltage of the first node N1 according to the third voltage signal.

With respect to the structure of the second control sub-circuit 4223 provided in some embodiments, the driving method of the shift register 400 provided in some embodiments of the present invention further includes: in one frame period, the pixel initialization phase t21, the refresh and compensation phase t22, the first light-emitting phase t31, and the second light-emitting phase t32 are sequentially completed. In the first light emitting period t31 and the second light emitting period t32, the second control sub-circuit 4223 transmits the third voltage signal at the third voltage signal terminal V3 to the first node N1 to change the voltage of the first node N1 in the case that the first voltage signal is not transmitted to the first node N1.

The third voltage signal is illustratively a low level signal. Referring to fig. 6C and 6D, in the first and second light emitting phases t31 and t32, since the first control sub-circuit 4222 is in an off state, the first voltage signal cannot be transmitted to the first node N1, and at this time, the first node N1 is in a floating state, and thus the third voltage signal can be transmitted to the first node N1, thereby changing the voltage of the first node N1 such that the voltage of the first node N1 is at a low level.

In some embodiments, referring to fig. 5C, the first control sub-circuit 4222 comprises a third transistor T3, wherein a control electrode of the third transistor T3 is electrically connected to the initial scan signal input terminal VIN (N), a first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal V1, and a second electrode of the third transistor is electrically connected to the first node N1. The second control sub-circuit 4223 comprises a fourth transistor T4, wherein the control electrode and the first electrode of the fourth transistor T4 are electrically connected to the third voltage signal terminal V3, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1.

In one frame period, referring to fig. 6A to 6D, the fourth transistor T4 is always in an on state. In the pixel initializing stage t21 and the refresh and compensation stage t22, referring to fig. 5D, the initial scan signal goa (n) is low. Referring to fig. 6A and 6B, under the control of the initial scan signal goa (N), the third transistor T3 is in an on state, so that the first voltage signal is transmitted to the first node N1, and even though the fourth transistor T4 is turned on, the control electrode of the fourth transistor T4 is connected to the same signal terminal as the first electrode, so that the fourth transistor T4 corresponds to a resistor, so that the third voltage signal received by the first electrode of the fourth transistor T4 cannot be written to the first node N1, and at this time, the voltage of the first node N1 is at a high level, and the sixth transistor T6 is turned off.

In the first and second light-emitting phases t31 and t32, referring to fig. 5D, the initial scan signal goa (n) is low level. Referring to fig. 6C and 6D, under the control of the initial scan signal goa (N), the third transistor T3 is in an off state, the first voltage signal cannot be transmitted to the first node N1, the first node N1 is in a floating state, and the fourth transistor T4 is in an on state, so that the third voltage signal can be written to the first node N1, and at this time, the voltage of the first node N1 is at a low level, thereby turning on the sixth transistor T6.

The above describes one configuration of the second control sub-circuit 4223 and the driving method of the corresponding shift register 400, and the following describes another configuration of the second control sub-circuit 4223 and the driving method of the corresponding shift register 400.

In some embodiments, referring to fig. 7A, the second control sub-circuit 4223 comprises: a regulator sub-circuit 42231 and a tank sub-circuit 42232. The regulator circuit 42231 is electrically connected to the fourth clock signal terminal CLK4, the first node N1, and the third voltage signal terminal V3; the regulation sub-circuit 42231 is configured to transmit the third voltage signal received at the third voltage signal terminal V3 to the first node N1 in response to the fourth clock signal CLK4 received at the fourth clock signal terminal CLK 4. The tank sub-circuit 42232 is electrically connected to the fifth clock signal terminal CLK5 and the first node N1; the tank sub-circuit 42232 is configured to change the voltage of the first node N1 by a coupling effect in accordance with the fifth clock signal CLK5 received at the fifth clock signal terminal CLK5 in the event that the first and third voltage signals are not transmitted to the first node N1.

Under the control of the fourth clock signal clk4, the regulator circuit 42231 may enable the third voltage signal terminal V3 to be connected to or disconnected from the first node N1, and when the third voltage signal terminal V3 is connected to the first node N1, the third voltage signal can be transmitted to the first node N1. It should be noted that, in the case that the first voltage signal is not transmitted to the first node N1, the third voltage signal can be transmitted to the first node N1.

When the third voltage signal terminal V3 is disconnected from the first node N1, the third voltage signal cannot be transmitted to the first node N1, and at the same time, the first voltage signal cannot be transmitted to the first node N1, and at this time, the first node N1 is in a floating state.

The tank sub-circuit 42232 is electrically connected to the first node N1, the tank sub-circuit 42232 is electrically connected to the fifth clock signal terminal CLK5, the level of the fifth clock signal CLK5 can be changed, and the tank sub-circuit 42232 can change the voltage of the first node N1 according to the change of the level of the fifth clock signal CLK5 when the first node N1 is in the floating state.

With respect to the structure of the second control sub-circuit 4223 provided in some embodiments, the driving method of the shift register 400 provided in some embodiments of the present invention further includes:

The first light-emitting stage t31 includes a first sub-light-emitting stage t301 and a third sub-light-emitting stage t303, the second light-emitting stage includes a second sub-light-emitting stage t302 and a fourth sub-light-emitting stage t304, and the pixel initialization stage t21, the refresh and compensation stage t22, the first sub-light-emitting stage t301, the second sub-light-emitting stage t302, the third sub-light-emitting stage t303 and the fourth sub-light-emitting stage t304 are sequentially completed within one frame period.

Referring to fig. 8A and 8B, in the pixel initialization stage t21 and the refresh and compensation stage t22, the regulator sub-circuit 42231 disconnects the third voltage signal terminal V3 from the first node N1 in response to the fourth clock signal CLK4 received at the fourth clock signal terminal CLK 4; the tank sub-circuit 42232 maintains the voltage of the first node N1. Referring to fig. 7C, in the output stage t2, the fourth clock signal clk4 goes through one half period, in the output stage t2, the fourth clock signal clk4 is at a high level, and in the first sub-emission stage t301, the second sub-emission stage t302, the fourth clock signal clk4 is at a low level, and in the third sub-emission stage t303 and the fourth sub-emission stage t304, the fourth clock signal clk4 is at a high level. Illustratively, the period of the fourth clock signal clk4 is twice that of the first clock signal clk1, and the high-level voltage values of the fourth clock signal clk4 and the first clock signal clk1 are equal, and the low-level voltage values of the fourth clock signal clk and the first clock signal clk are equal.

In the pixel initialization stage t21 and the refresh and compensation stage t22, the first control sub-circuit 4222 transmits the first voltage signal to the first node N1 under the control of the initial scan signal goa (N), and the first voltage signal is illustratively a high level signal, so that the voltage of the first node N1 is high level in the pixel initialization stage t21 and the refresh and compensation stage t 22. The regulation sub-circuit 42231 is controlled by the fourth clock signal clk4 to disconnect the third voltage signal terminal V3 from the first node N1, so that the third voltage signal cannot be transmitted to the first node N1. At this time, the voltage of the first node N1 can be maintained at a high level.

Referring to fig. 8C and 8D, in the first sub-light-emitting stage t301 and the second sub-light-emitting stage t302, the regulation sub-circuit 42231 transmits the third voltage signal received at the third voltage signal terminal V3 to the first node N1 in response to the fourth clock signal CLK4 received at the fourth clock signal terminal CLK 4; the tank sub-circuit 42232 holds the voltage of the first node N1.

In the first sub-emission period t301 and the second sub-emission period t302, the first control sub-circuit 4222 disconnects the first voltage signal terminal V1 from the first node N1 under the control of the initial scan signal goa (N), and the first voltage signal cannot be transmitted to the first node N1. The regulator sub-circuit 42231 transmits a third voltage signal to the first node N1 under the control of the fourth clock signal clk4, wherein the third voltage signal is a low level signal. At this time, the level of the first node N1 is the same as the level of the third voltage signal.

Referring to fig. 8E and 8F, in the third sub-emission period t303 and the fourth sub-emission period t304, the regulator sub-circuit 42231 disconnects the third voltage signal terminal V3 from the first node N1 in response to the fourth clock signal CLK4 received at the fourth clock signal terminal CLK 4; the tank sub-circuit 42232 changes the voltage of the first node N1 by a coupling action in accordance with the fifth clock signal CLK5 received at the fifth clock signal terminal CLK5 in the case where the first and third voltage signals are not transmitted to the first node N1.

Referring to fig. 7C, the periods of the fifth clock signal clk5 and the second clock signal clk2 are the same, the waveforms of the fifth clock signal clk5 and the second clock signal clk2 are the same, and the fifth clock signal clk5 goes through one period in the output phase t2, the fifth clock signal clk5 is at a low level in the pixel initialization phase t21 of the output phase t2, and the fifth clock signal clk5 is at a high level in the refresh and compensation phase t22 of the output phase t 2.

In the third sub-lighting stage t303 and the fourth sub-lighting stage t304, referring to fig. 8E and 8F, the first control sub-circuit 4222 disconnects the first voltage signal terminal V1 from the first node N1 under the control of the initial scan signal goa (N), and the first voltage signal cannot be transmitted to the first node N1. The regulation sub-circuit 42231 is controlled by the fourth clock signal clk4 to disconnect the third voltage signal terminal V3 from the first node N1, so that the third voltage signal cannot be transmitted to the first node N1, and therefore the first node N1 is in a floating state.

The tank sub-circuit 42232 is connected to the fifth clock signal terminal CLK5 and the first node N1, respectively, and the first voltage signal and the third voltage signal cannot be transmitted to the first node N1 during the third sub-emission period t303 and the fourth sub-emission period t304, and the first node N1 is in a floating state, so that the level of the fifth clock signal CLK5 can change to cause the level of the first node N1 to change, thereby controlling the state of the third output sub-circuit 4221, so that the second voltage signal is transmitted to the second scan signal output terminal EM (N).

In some embodiments, referring to fig. 7B, the first control sub-circuit 4222 comprises a third transistor T3, wherein a control electrode of the third transistor T3 is electrically connected to the initial scan signal input terminal VIN (N), a first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal V1, and a second electrode of the third transistor is electrically connected to the first node N1. The regulator sub-circuit 42231 includes a seventh transistor T7, wherein a control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal terminal CLK4, a first electrode of the seventh transistor T7 is electrically connected to the third voltage signal terminal V3, and a second electrode of the seventh transistor T7 is electrically connected to the first node N1. The tank sub-circuit 42232 includes: the first capacitor C1, a first terminal of the first capacitor C1 is electrically connected to the fifth clock signal terminal CLK5, and a second terminal of the first capacitor C1 is electrically connected to the first node N1.

The seventh transistor T7 may be a P-type transistor, and the fourth clock signal clk4 is high in the pixel initializing stage T21 and the refresh and compensation stage T22, and the seventh transistor T7 may be turned off such that the third voltage signal cannot be transmitted to the first node N1.

In the pixel initialization stage t21 and the refresh and compensation stage t22, referring to fig. 8A, the initial scan signal goa (n) is low. Referring to fig. 8A and 8B, the initial scan signal goa (N) is low, and thus the third transistor T3 is turned on, transmitting the first voltage signal to the first node N1, and the first node N1 is high. The fourth clock signal clk4 is high, and thus the seventh transistor T7 is turned off, and thus the third voltage signal cannot be transmitted to the first node N1.

In the first sub-emission period T301 and the second sub-emission period T302, referring to fig. 7C, 8C and 8D, the initial scan signal goa (n) is at a high level, thereby turning off the third transistor T3. The fourth clock signal clk4 is low, and thus the seventh transistor T7 can be controlled to be turned on, so that the third voltage signal is transmitted to the first node N1, and thus the first node N1 is low, and the sixth transistor T6 is controlled to be turned on. The fifth clock signal clk5 is at a low level in the first sub-emission period t301, is at a high level in the second sub-emission period t302, and does not cause the level of the first node N1 to change although the level of the fifth clock signal clk5 changes when the first sub-emission period t301 changes to the second sub-emission period t 302.

In the third sub-emission period T303, referring to fig. 7C and 8E, the initial scan signal goa (n) is at a high level, thereby turning off the third transistor T3. The fourth clock signal clk4 is high, so that the seventh transistor T7 is turned off, resulting in the third voltage signal not being transmitted to the first node N1, and the first voltage signal not being transmitted to the first node N1. The level of the fifth clock signal clk5 is changed from high level to low level, wherein the level of the fifth clock signal clk5 is reduced by Δv, and the first capacitor C1 is further capable of driving the level of the first node N1 to be further reduced, so as to control the sixth transistor T6 to maintain the on state. For convenience of description, the level of the first node N1 in the first sub-light-emitting period t301 and the second sub-light-emitting period t302 may be defined as V1, and thus, the level of the first node N1 in the third sub-light-emitting period t303 is changed to V1- Δv.

In the fourth sub-emission period T304, referring to fig. 7C and 8F, the initial scan signal goa (n) is at a high level, thereby turning off the third transistor T3. The fourth clock signal clk4 is high, so that the seventh transistor T7 is turned off, resulting in the third voltage signal not being transmitted to the first node N1, and the first voltage signal not being transmitted to the first node N1. The level of the fifth clock signal clk5 is changed from low level to high level, so that the level of the first node N1 is increased, wherein the level of the fifth clock signal clk5 is increased by Δv, and thus the level of the first node N1 is increased by Δv from V1- Δv, and at this time, the level of the first node N1 is (V1- Δv) +Δv=v1, that is, in the fourth sub-lighting stage T304, the level of the first node N1 is increased to V1, which is still the low level, so that the sixth transistor T6 is in the on state.

In some embodiments, referring to fig. 7C, the fifth clock signal CLK5 may be the same as the second clock signal CLK2, i.e., the fifth clock signal terminal CLK5 is the same signal terminal as the second clock signal terminal CLK 2.

In some embodiments, referring to fig. 7C, the fourth clock signal clk4 has a period twice that of the first clock signal clk1, and the fourth clock signal clk4 has a period twice that of the second clock signal clk 2. Wherein the period of the first clock signal clk1 is the same as the period of the second clock signal clk 2.

In some embodiments, the first transistor T1, the second transistor T2, … … and the seventh transistor T7 may be P-type transistors.

The signal output circuit 420 corresponding to the pixel driving circuit 211, each of which is a P-type transistor, is specifically described above, and the corresponding shift register circuit 410 is described below.

In some embodiments, referring to fig. 9A, the shift register circuit 410 includes: an input sub-circuit 411 and an output control sub-circuit 412, the input sub-circuit 411 being electrically connected to the first signal terminal, the second signal terminal and the second node N2, the input sub-circuit 411 being configured to transmit the second signal received at the second signal terminal to the second node N2 in response to the first signal received at the first signal terminal, wherein the first signal terminal or the second signal terminal is electrically connected to the initial scan signal output terminal GOA (N-1) of the shift register circuit 410 in the previous stage shift register 400. The output control sub-circuit 412 is electrically connected to the second node N2, the sixth clock signal terminal CLK6 and the initial scan signal output terminal GOA (N), and the output control sub-circuit 412 is configured to transmit the sixth clock signal CLK6 received at the sixth clock signal terminal CLK6 to the initial scan signal output terminal GOA (N) in response to the voltage of the second node N2. Wherein the period of the sixth clock signal clk6 is at least twice the period of the first clock signal clk 1.

The first signal terminal or the second signal terminal is electrically connected to the initial scan signal output terminal GOA (n-1) in the previous stage shift register circuit 410, and the plurality of shift registers 400 in the gate driving circuit 300 are cascaded. For convenience of description, the initial scan signal GOA (n) output by the previous stage shift register circuit 410 may be referred to as a previous stage initial scan signal GOA (n-1), the initial scan signal GOA (n) output by the present stage shift register circuit 410 may be referred to as an initial scan signal GOA (n), the initial scan signal GOA (n) output by the next stage shift register circuit 410 may be referred to as a next stage initial scan signal GOA (n+1), the initial scan signal output terminal GOA (n) in the previous stage shift register circuit 410 may be referred to as a previous stage initial scan signal output terminal GOA (n-1), the initial scan signal output terminal GOA (n) in the present stage shift register circuit 410 may be referred to as an initial scan signal output terminal GOA (n), and the initial scan signal GOA (n) output by the next stage shift register circuit 410 may be referred to as a next stage initial scan signal GOA (n+1).

Under the control of the first signal, the input sub-circuit 411 may be turned on or off between the second signal terminal and the initial scan signal output terminal GOA (n) of the present stage. The sixth clock signal terminal CLK6 may be turned on or off from the initial scan signal output terminal GOA (N) under the control of the level of the second node N2.

In some examples, the first signal terminal is electrically connected to the initial scan signal output terminal GOA (n-1) in the upper stage shift register circuit 410, i.e. the first signal terminal may receive the initial scan signal GOA (n-1) output by the upper stage shift register circuit 410.

In the charging stage t1, the input sub-circuit 411 transmits the second signal to the second node N2 under the control of the first signal, i.e., the previous stage initial scan signal goa (N-1), and for example, referring to fig. 9A, the second signal terminal may be the third voltage signal terminal V3, and further transmits the third voltage signal to the second node N2. Under the control of the level of the second node N2, the output control sub-circuit 412 may transmit the sixth clock signal clk6 to the initial scan signal output terminal GOA (N), for example, referring to fig. 9B, the sixth clock signal clk6 is at a high level during the charging period t1, and further the initial scan signal GOA (N) is at a first level, i.e., at a high level during the charging period t 1.

In the output stage t2, under the control of the first signal, i.e. the previous stage of the initial scan signal GOA (N-1), the input sub-circuit 411 disconnects the third voltage signal terminal V3 from the initial scan signal output terminal GOA (N), and the third voltage signal cannot be transmitted to the second node N2. The output control sub-circuit 412 may transmit the sixth clock signal clk6 to the initial scan signal output terminal GOA (N) under the control of the level of the second node N2. Referring to fig. 9B, the sixth clock signal clk6 is low in the output stage t2, and thus, the initial scan signal goa (n) is low, i.e., the second level in the output stage t 2.

In the reset phase t3, under the control of the first signal, i.e., the previous stage of the initial scan signal GOA (N-1), the input sub-circuit 411 disconnects the third voltage signal terminal V3 from the initial scan signal output terminal GOA (N), and the third voltage signal cannot be transmitted to the second node N2. Under the control of the level of the second node N2, the output control sub-circuit 412 disconnects the sixth clock signal terminal CLK6 from the initial scan signal output terminal GOA (N), and the level of the initial scan signal GOA (N) is the first level.

In some embodiments, referring to fig. 9A, the input sub-circuit 411 includes an eighth transistor M8, wherein a control electrode of the eighth transistor M8 is electrically connected to the previous stage initial scan signal output terminal GOA (N-1), a first electrode is electrically connected to the third voltage signal terminal V3, and a second electrode is electrically connected to the second node N2; the output control sub-circuit 412 includes a tenth transistor M10, wherein a control electrode of the tenth transistor M10 is electrically connected to the second node N2, a first electrode is electrically connected to the sixth clock signal terminal CLK6, and a second electrode is electrically connected to the initial scan signal output terminal GOA (N).

In addition, the shift register circuit 410 further includes a ninth transistor M9, an eleventh transistor M11, a twelfth transistor M12, a twelfth transistor M … …, an eighteenth transistor M18, and a third capacitor C3, wherein a control electrode of the ninth transistor M9 is electrically connected to the next stage initial scan signal output terminal GOA (n+1), and a first electrode thereof is electrically connected to the first voltage signal terminal V1. The control electrode of the eleventh transistor M11 is electrically connected to the fourth voltage signal terminal V4, the first electrode is electrically connected to the fifth voltage signal terminal V5, and the second electrode is electrically connected to the second node N2. The twelfth transistor M12 has a control electrode electrically connected to the third node N3, a first electrode electrically connected to the sixth voltage signal terminal V6, and a second electrode electrically connected to the fourth node N4. The thirteenth transistor M13 has a control electrode electrically connected to the second node N2, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the fourth node N4. The fourteenth transistor M14 has a control electrode electrically connected to the fourth voltage signal terminal V4, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the initial scan signal output terminal GOA (n). The fifteenth transistor M15 has a control electrode electrically connected to the second node N2, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the third node N3. The control electrode and the first electrode of the sixteenth transistor M16 are electrically connected to the sixth voltage signal terminal V6, and the second electrode is electrically connected to the third node N3. The seventeenth transistor M17 has a control electrode electrically connected to the fourth node N4, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the second node N2. The eighteenth transistor M18 has a control electrode electrically connected to the fourth node N4, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the initial scan signal output terminal GOA (N). The first end of the third capacitor C3 is electrically connected to the second node N2, and the second end is electrically connected to the initial scan signal output terminal GOA (N).

In some embodiments, the second control sub-circuit 4223 includes a fourth transistor T4, and the structure of the shift register 400 is shown in fig. 9C, and the corresponding timing diagram is shown in fig. 9B. In other embodiments, the second control sub-circuit 4223 includes a seventh transistor T7 and a first capacitor C1, and the structure of the shift register 400 is shown in fig. 9D, and the corresponding timing diagram is shown in fig. 9E.

In some embodiments, the eighth transistor M8 to the eighteenth transistor M18 are P-type transistors, and the fourth voltage signal to the sixth voltage signal are described below by taking P-type transistors as examples of each transistor in the shift register circuit 410.

For example, referring to fig. 9A, the fourth voltage signal terminal V4 may be a fourth high voltage signal terminal GCH for receiving a high voltage signal, that is, the fourth voltage signal is a high voltage signal, and the high voltage signal received by the fourth high voltage signal terminal GCH may be at a high level when the Display panel 200 is in a Display state and at a low level when it is in a blank state. When the shift register 400 is in the charging stage t1, the outputting stage t2 and the resetting stage t3, the display panel 200 is in the display state.

For example, referring to fig. 9A, the fifth voltage signal terminal V5 is a fifth high voltage signal terminal VGH for receiving a high voltage signal, i.e., the fifth voltage signal is a high voltage signal having a high level.

For example, referring to fig. 9A, the sixth voltage signal terminal V6 is a sixth low voltage signal terminal GCL for receiving a low voltage signal, that is, the sixth voltage signal is a low voltage signal when the Display panel 200 is in the Display state, and is a high level when it is in the Blanking state.

In some embodiments, referring to fig. 9F, the first signal terminal and the second signal terminal may be the initial scan signal output terminal GOA (n-1) of the shift register circuit 410 in the previous stage shift register 400, that is, the control electrode and the first electrode of the eighth transistor M8 in the input sub-circuit 411 are electrically connected to the initial scan signal output terminal GOA (n-1) of the shift register circuit 410 in the previous stage shift register 400.

For the shift register circuit 410, where each transistor is a P-type transistor, the disclosure further provides a driving method of the shift register 400, where the driving method further includes: one frame period includes a charging phase t1, an output phase t2, and a reset phase t3.

In the charging stage t1, referring to fig. 9B, 9E and 10A, the upper stage initial scan signal goa (N-1) output signal is low, thereby controlling the eighth transistor M8 to be turned on, and the eighth transistor M8 transmits the third voltage signal to the second node N2, such that the second node N2 is charged to the low level. The second node N2 is low, and thus the thirteenth transistor M13 and the fifteenth transistor M15 are controlled to be turned on, the thirteenth transistor M13 transmits the fifth voltage signal to the fourth node N4, the fourth node N4 is charged to the high level, and the fifteenth transistor M15 transmits the fifth voltage signal to the third node N3, and thus the third node N3 is charged to the high level. Since the third node N3 is pulled high, the twelfth transistor M12 is turned off. Since the fourth node N4 is at a high level, the seventeenth transistor M17 and the eighteenth transistor M18 are turned off. While the next stage initial scan signal goa (n+1) is high, so the tenth transistor M10 is turned off. Further, since the second node N2 is charged to the low level, the tenth transistor M10 is turned on, the tenth transistor M10 transmits the sixth clock signal clk6 to the initial scan signal output terminal GOA (N), and since the sixth clock signal clk6 is at the high level in the charging stage t1, the initial scan signal GOA (N) is at the high level in the charging stage t 1.

In the output stage t2, referring to fig. 9B, 9E and 10B, the upper stage initial scan signal goa (N-1) becomes high level, so that the eighth transistor M8 is turned off and the lower stage initial scan signal goa (n+1) remains high level, and thus the ninth transistor M9 is turned off, and at this time, the second node N2 is in a floating state, and remains low level. Since the second node N2 maintains the low level of the charging period t1, the thirteenth transistor M13 and the fifteenth transistor M15 remain in the on state. The fifteenth transistor M15 transmits a fifth voltage signal to the third node, the fifth voltage signal being at a high level, and thus the third node N3 maintains a high level of the charging period t1, and thus the twelfth transistor M12 maintains an off state. The thirteenth transistor M13 transmits the fifth voltage signal to the fourth node N4, and the fourth node N4 maintains a high level, thereby turning off the seventeenth and eighteenth transistors M17 and M18. Since the second node N2 is kept at a low level, the tenth transistor M10 is kept in an on state, the tenth transistor M10 transmits the sixth clock signal clk6 to the initial scan signal output terminal GOA (N), and the sixth clock signal clk6 is at a low level in the output stage t2, and thus the initial scan signal GOA (N) is at a low level, i.e., a second level, in the output stage t 2.

In the output stage t2, the level of the signal of the initial scan signal output terminal GOA (N) changes from high level to low level, and due to the coupling effect of the third capacitor C3, the level of the second node N2 can be further reduced, so that the tenth transistor M10 is further turned on, thereby ensuring that the sixth clock signal clk6 is transmitted to the initial scan signal output terminal GOA (N). It should be noted that, in the output stage t2, the pixel driving circuit 211 is in the pixel initializing stage t21 and the refresh and compensation stage t22.

In the reset stage t3, referring to fig. 9B, 9E, and 10C, the upper stage initial scan signal goa (n-1) remains high, and therefore, the eighth transistor M8 is turned off. The next stage of initial scan signal goa (n+1) is low, so that the ninth transistor M9 is turned on to transmit the first voltage signal to the second node N2, charge the second node N2 to high level, and reduce noise of the second node N2. The second node N2 is at a high level, and thus controls the thirteenth transistor M13, the fifteenth transistor M15 and the tenth transistor M10 to be turned off, and the sixth clock signal clk6 cannot be transmitted to the initial scan signal output terminal GOA (N) through the tenth transistor M10 because the tenth transistor M10 is turned off. At this time, since the fifteenth transistor M15 is turned off and the sixteenth transistor M16 is turned on, the sixteenth transistor M16 is capable of transmitting the sixth voltage signal to the third node N3, the third voltage signal is at a low level and charges the third node N3 to a low level, so as to control the twelfth transistor M12 to be turned on, the twelfth transistor M12 is capable of transmitting the sixth voltage signal to the fourth node N4 and charges the fourth node N4 to a low level and further controls the eighteenth transistor M18 and the seventeenth transistor M17 to be turned on, wherein the eighteenth transistor M18 is capable of transmitting the fifth voltage signal to the initial scan signal output terminal GOA (N), and the fifth voltage signal is at a high level, so that the initial scan signal GOA (N) is at a high level, i.e., the first level in the reset phase t 3. And the seventeenth transistor M17 may transmit the fifth voltage signal to the second node N2, and noise-reduce the second node N2. In the reset period t3, the pixel driving circuit 211 is in the light emitting period.

In the charging stage t1, the output stage t2, and the reset stage t3, the fourth voltage signal is at a high level, and the eleventh transistor M11 and the fourteenth transistor M14 are turned off. After the reset period t3 is ended, the fourth voltage signal is changed to a low level, so that the eleventh transistor M11 and the fourteenth transistor M14 are turned on, wherein the eleventh transistor M11 may transmit the fifth voltage signal to the second node N2 to reset the second node N2, and the fourteenth transistor M14 may transmit the fifth voltage signal to the initial scan signal output terminal GOA (N) to reset the initial scan signal output terminal GOA (N).

In some embodiments, as shown in fig. 9B and 9E, the period of the sixth clock signal clk6 is at least twice the period of the first clock signal clk1 and the period of the second clock signal clk2, e.g., the period of the sixth clock signal clk6 is greater than or equal to twice the period of the first clock signal clk1 and the period of the second clock signal clk2, and less than or equal to four times the period of the first clock signal clk1 and the period of the second clock signal clk 2. Taking the example that the period of the sixth clock signal clk6 is twice the period of the first clock signal clk1 and the period of the second clock signal clk2, when the output period T2 of the shift register circuit 410 is the second level (low level) of the output sixth clock signal clk6 in the on state of the tenth transistor M10, the first scan signal output circuit 421 sequentially turns on the first transistor T1 and the second transistor T2 under the control of the second clock signal clk2 and the third clock signal clk3, and then outputs the first level (high level) of the corresponding first clock signal clk1 during the on period of the first transistor T1, and outputs the second level of the corresponding initial scan signal goa (n) during the on period of the second transistor T2 as the first scan signal, so that the second level of the first scan signal is half the duration of the second level of the first scan signal (a). The second scan signal output circuit 422 is capable of transmitting the first voltage signal to the second scan signal output terminal EM (n) according to the second level of the initial scan signal goa (n), even though the second scan signal outputs a high level in the pixel initializing stage t21 and the refresh and compensation stage t22 of the output stage t 2. Illustratively, the sixth clock signal clk6 is high during the charging phase t1 and the sixth clock signal clk6 is low during the output phase t 2.

In addition, the period of the sixth clock signal clk6 is less than or equal to four times of the period of the first clock signal clk1 and the period of the second clock signal clk2, so as to avoid the signal output by each signal terminal from being disordered.

In some embodiments, as shown in fig. 9E, the period of the sixth clock signal clk6 may be equal to or greater than the period of the fourth clock signal clk 4.

The above describes a configuration of the shift register circuit 410, wherein the first signal terminal is electrically connected to the initial scan signal output terminal GOA (n-1) in the shift register circuit 410 of the previous stage. In some other embodiments, the second signal terminal is electrically connected to the initial scan signal output terminal GOA (n-1) in the previous stage of the shift register circuit 410, and the specific structure and driving method of the shift register circuit 410 are described below.

In some embodiments, referring to fig. 11A, the input sub-circuit 411 includes a nineteenth transistor M19, a control electrode of the nineteenth transistor M19 is electrically connected to the seventh clock signal terminal CLK7, a first electrode is electrically connected to the previous stage initial scan signal output terminal GOA (N-1), and a second electrode is electrically connected to the fifth node N5.

The output control sub-circuit 412 includes a thirteenth transistor M23, wherein a gate electrode of the thirteenth transistor M23 is electrically connected to the second node N2, a first electrode thereof is electrically connected to the sixth clock signal terminal CLK6, and a second electrode thereof is electrically connected to the initial scan signal output terminal GOA (N).

In addition, the shift register circuit 410 further includes a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a fourth capacitor C4, and a fifth capacitor C5. Wherein the control electrode of the twentieth transistor M20 is electrically connected to the fifth node N5, the first electrode is electrically connected to the seventh clock signal terminal CLK7, and the second electrode is electrically connected to the sixth node N6. The control electrode of the twenty-first transistor M21 is electrically connected to the seventh clock signal terminal CLK7, the first electrode is electrically connected to the second voltage signal terminal V2, and the second electrode is electrically connected to the sixth node N6. The second transistor M22 has a control electrode electrically connected to the sixth node N6, a first electrode electrically connected to the fifth voltage signal terminal V5, and a second electrode electrically connected to the initial scan signal output terminal GOA (N). The twenty-third transistor M23 has a control electrode electrically connected to the second node N2, a first electrode electrically connected to the sixth clock signal terminal CLK6, and a second electrode electrically connected to the initial scan signal output terminal GOA (N). The control electrode of the twenty-fourth transistor M24 is electrically connected to the sixth node N6, the first electrode is electrically connected to the fifth voltage signal terminal V5, and the second electrode is electrically connected to the eighth node N8. The control electrode of the twenty-fifth transistor M25 is electrically connected to the sixth clock signal terminal CLK6, the first electrode is electrically connected to the fifth node N5, and the second electrode is electrically connected to the eighth node N8. The control electrode of the twenty-sixth transistor M26 is electrically connected to the second voltage signal terminal V2, the first electrode is electrically connected to the fifth node N5, and the second electrode is electrically connected to the second node N2. The first end of the fourth capacitor C4 is connected to the second node N2, and the second end is electrically connected to the initial scan signal output terminal GOA (N). The first end of the fifth capacitor C5 is electrically connected to the sixth node N6, and the second end is electrically connected to the fifth voltage signal terminal V5.

In some embodiments, the second control sub-circuit 4223 includes a fourth transistor T4, and the structure of the shift register 400 is shown in fig. 11B, and the corresponding timing diagram is shown in fig. 11C. In other embodiments, the second control sub-circuit 4223 includes a seventh transistor T7 and a first capacitor C1, and the structure of the shift register 400 is shown in fig. 11D, and the timing diagram corresponding to the structure is shown in fig. 11E.

In some embodiments, referring to fig. 11F, the first signal terminal and the second signal terminal may be the initial scan signal output terminal GOA (n-1) of the shift register circuit 410 in the upper stage shift register 400. Namely, the control electrode and the first electrode of the nineteenth transistor M19 in the input sub-circuit 411 are electrically connected to the initial scan signal output terminal GOA (n-1) of the shift register circuit 410 in the shift register 400 of the previous stage.

In some embodiments, the nineteenth transistor M19 to the twenty-sixth transistor M26 may be P-type transistors. Correspondingly, the second voltage signal end V2 is a second low voltage signal end VGL, and the second voltage signal is a low level signal; the fifth voltage signal terminal is a fifth high voltage signal terminal VGH for receiving a high voltage signal, i.e., the fifth voltage signal is a high voltage signal having a high level.

For the shift register circuit 410, in which the nineteenth transistor M19 to the twenty sixth transistor M26 are P-type transistors, the disclosure further provides a driving method of the shift register 400, where the driving method further includes: one frame period includes a charging phase t1, an output phase t2, and a reset phase t3, wherein the reset phase t3 includes a first pull-up phase t310 and a second pull-up phase t320.

In the charging stage t1, referring to fig. 11C, 11E and 12A, the seventh clock signal CLK7 received at the seventh clock signal terminal CLK7 is at a low level, thereby turning on the nineteenth transistor M19, the nineteenth transistor M19 transmits the upper-stage initial scan signal goa (N-1) to the fifth node N5, and the upper-stage initial scan signal goa (N-1) is at a low level, and thus the fifth node N5 is at a low level. Under the control of the seventh clock signal clk7, the twenty-first transistor M21 is turned on, and the twenty-first transistor M21 transmits the second voltage signal to the sixth node N6. Under the control of the fifth node N5, the twentieth transistor M20 is turned on, and the twentieth transistor M20 transmits the seventh clock signal clk7 to the sixth node N6; the second voltage signal is low, the seventh clock signal terminal CLK7 is low in the charging phase t1, and therefore the sixth node N6 is low.

Under the control of the sixth node N6, the twenty-fourth transistor M24 is turned on, the twenty-fourth transistor M24 transmits the fifth voltage signal to the eighth node N8, and the fifth voltage signal is at a high level, so the eighth node N8 is at a high level. While the sixth clock signal clk6 is at a high level, the twenty-first transistor M21 is turned off under the control of the sixth clock signal clk6, and therefore the high level of the eighth node N8 cannot be written into the fifth node N5.

The second voltage signal is at a low level, and thus the twenty-sixth transistor M26 is controlled to be turned on, and the signal of the fifth node N5 can be written into the second node N2, so that the second node N2 is at a low level.

The sixth node N6 is low, and thus controls the turning-on of the twenty-second transistor M22, and the twenty-second transistor M22 transmits the fifth voltage signal to the initial scan signal output terminal GOA (N). The second node N2 is low, thereby controlling the twenty-third transistor M23 to be turned on, and the twenty-third transistor M23 transmits the sixth clock signal clk6 to the initial scan signal output terminal GOA (N). Since the fifth voltage signal is at a high level and the sixth clock signal clk6 is at a high level in the charging period t1, the initial scan signal goa (n) is at a first level, which is a high level, in the charging period t 1.

In the output stage t2, referring to fig. 11C, 11E and 12B, the seventh clock signal clk7 is at a high level, and thus controls the nineteenth transistor M19 to be turned off, and thus the previous initial scan signal goa (N-1) cannot be transmitted to the fifth node N5, and the fifth node N5 remains at a low level.

The seventh clock signal clk7 is high, and thus controls the twenty-first transistor M21 to be turned off, and the second voltage signal cannot be transmitted to the sixth node N6. The fifth node N5 keeps a low level, and thus controls the twentieth transistor M20 to turn on, the twentieth transistor M20 transmits the seventh clock signal clk7 to the sixth node N6, and the seventh clock signal clk7 is at a high level in the output stage t2, so that the sixth node N6 is at a high level, and thus controls the twenty-second transistor M22 to turn off, such that the fifth voltage signal cannot be transmitted to the initial scan signal output terminal GOA (N).

The sixth node N6 is high, and therefore, the twenty-fourth transistor M24 is turned off, and the fifth voltage signal cannot be transmitted to the eighth node N8. The sixth clock signal clk6 is low, thereby controlling the twenty-fifth transistor M25 to turn on, and the twenty-fifth transistor M25 writes the low level of the fifth node N5 to the eighth node N8.

The fifth node N5 is at a low level, and since the twenty-sixth transistor M26 is turned on, the low level of the fifth node N5 can be written into the second node N2, the second node N2 is at a low level, and the twenty-third transistor M23 is further controlled to be turned on, the twenty-third transistor M23 transmits the sixth clock signal clk6 to the initial scan signal output terminal GOA (N), and the second clock signal clk2 is at a low level in the output stage t2, and therefore the initial scan signal GOA (N) is at a low level, i.e., a second level, in the output stage t 2. Since the level of the initial scan signal output terminal GOA (N) is changed from the high level to the low level, the level of the second node N2 is further lowered under the control of the fourth capacitor C4, thereby further turning on the twenty-third transistor M23.

In the first pull-up stage t310, referring to fig. 11C, 11E and 12C, the seventh clock signal clk7 is at a low level, and thus controls the nineteenth transistor M19 to be turned on, the nineteenth transistor M19 transmits the previous stage initial scan signal goa (N-1) to the fifth node N5, and the previous stage initial scan signal goa (N-1) is at a high level, so that the fifth node N5 is at a high level. The twenty-sixth transistor M26 is turned on, and the low level of the fifth node N5 is written into the second node N2, and the second node N2 is high level, thereby controlling the twenty-third transistor M23 to be turned off.

The fifth node N5 is high, thereby controlling the twentieth transistor M20 to be turned off. The sixth clock signal clk6 is high, thereby controlling the twenty-fifth transistor M25 to turn off. The sixth node N6 is low, and thus the twenty-fourth transistor M24 is controlled to be turned on, and the twenty-fourth transistor M24 transmits the fifth voltage signal to the eighth node N8, and the eighth node N8 is high.

The seventh clock signal clk7 is at a low level to control the turning-on of the twenty-first transistor M21, the twenty-first transistor M21 transmits the second voltage signal to the sixth node N6, and the second voltage signal is at a low level, so that the sixth node N6 is at a low level to control the turning-on of the second transistor M22, the twenty-second transistor M22 transmits the fifth voltage signal to the initial scan signal output terminal GOA (N), and the fifth voltage signal is at a high level, so that the initial scan signal GOA (N) is at a high level, i.e., a first level, in the first pull-up stage t 310.

Note that in the first pull-up stage t310, the pixel driving circuit 211 is in the light-emitting stage.

In the second pull-up stage t320, referring to fig. 11C, 11E and 12D, the seventh clock signal clk7 is at a high level, the nineteenth transistor M19 is turned off, and the previous stage initial scan signal goa (N-1) cannot be transmitted to the fifth node N5. The sixth node N6 is at a low level, so as to control the conduction of the twenty-fourth transistor M24, the sixth clock signal clk6 is at a low level, and the twenty-fifth transistor M25 is on, so that the fifth voltage signal is written into the fifth node N5 through the twenty-fourth transistor M24 and the twenty-fifth transistor M25 in sequence, and the fifth voltage signal is at a high level, so that the fifth node N5 is at a high level. The twenty-sixth transistor M26 is turned on, the level of the fifth node N5 is written into the second node N2, the second node N2 is at a high level, and the twenty-third transistor M23 is controlled to be turned off, so that the sixth clock signal clk6 cannot be written into the initial scan signal output terminal GOA (N).

The seventh clock signal clk7 is high, the twenty-first transistor M21 is turned off, and the second voltage signal cannot be transmitted to the sixth node N6. The fifth node N5 is high, thereby controlling the twentieth transistor M20 to be turned off. The sixth node N6 is kept at a low level, so that the twenty-second transistor M22 is turned on, and the twenty-second transistor M22 transmits the fifth voltage signal to the initial scan signal output terminal GOA (N), and the fifth voltage signal is at a high level, so that the initial scan signal GOA (N) is at a high level, i.e., the first level, in the second pull-up stage t 320. It should be noted that, in the second pull-up stage t320, the pixel driving circuit 211 is in the light emitting stage.

In some embodiments, as shown in fig. 11C and 11E, the period of the seventh clock signal clk7 may be the same as the period of the sixth clock signal clk6, and the period of the sixth clock signal clk6 may be greater than or equal to two times the period of the first clock signal clk1, less than four times the period of the first clock signal clk 1; the period of the sixth clock signal clk6 may be greater than or equal to two times the period of the second clock signal clk2, less than four times the period of the second clock signal clk2, and the period of the fourth clock signal clk4 may be equal to two times the period of the first clock signal clk 1. The first clock signal clk1 is the third clock signal clk3, and the second clock signal clk2 is the fifth clock signal clk5.

For example, referring to fig. 11E, in the charging period t1 and the output period t2, the seventh clock signal clk7 goes through a portion of one cycle, in the front stage of the charging period t1, the seventh clock signal clk7 is low, the seventh clock signal clk7 changes to high level immediately before the output period t2, the seventh clock signal clk7 is high throughout the output period t2, and in the front stage of the first pull-up period t310, the seventh clock signal clk7 remains high. In the front stage of the first pull-up stage t310, the seventh clock signal clk7 changes to a low level; upon entering the second pull-up stage t320, the seventh clock signal clk7 changes to a high level.

In addition to the shift register circuit 410 provided in the above embodiment, in other embodiments, the shift register circuit 410 may further include other modes, such as 10T, 12T, and 13T, which are not described herein.

The shift register 400 required for the pixel driving circuit 211, each of which is a P-type transistor, is described in detail above, in other embodiments, each of the transistors in the pixel driving circuit 211 may be an N-type transistor, and the control electrode of each of the transistors in the pixel driving circuit 211 is turned on when receiving a high level signal, and the timing diagram of the pixel driving circuit 211 may be adaptively adjusted. The initial scan signal goa (n) required by the pixel driving circuit 211 is at a low level, i.e., a first level, in the charging phase t1, at a high level, i.e., a second level, in the output phase t2, and at a low level in the reset phase t 3.

In some embodiments, the plurality of transistors in the shift register 400 may be N-type transistors, and the signals output by the plurality of signal terminals connected to the shift register 400 may be adaptively adjusted. The first voltage signal terminal V1 is a third low voltage signal terminal VSS, the second voltage signal terminal V2 is a fifth high voltage signal terminal VGH, and the third voltage signal terminal V3 is a first high voltage signal terminal VDD. Other clock signals are adaptively adjusted, which is not explicitly recited herein. It should be noted that, at this time, the sixth transistor is an N-type transistor, the voltage of the third voltage signal is greater than the voltage of the second voltage signal, so as to ensure that when the third voltage signal is transmitted to the first node, the voltage difference obtained by subtracting the first electrode voltage from the voltage of the control electrode of the sixth transistor T6, i.e., the voltage of the third voltage signal subtracted from the voltage of the second voltage signal, is greater than the threshold voltage of the sixth transistor T6, and thus the sixth transistor T6 is turned on. At this time, the voltages of the second voltage signal and the third voltage signal may be positive values. When the first voltage signal is transmitted to the first node N1, the sixth transistor T6 may be turned off, and the voltage of the first voltage signal may be negative.

Some embodiments of the present invention further provide a gate driving circuit 300, where the gate driving circuit 300 includes the shift register 400 provided in any of the above embodiments of N-stage cascade connection, N is a positive integer greater than or equal to 1; the shift register 400 includes: the shift register circuit 410 and the signal output circuit 420, wherein the shift register circuit 410 includes an input sub-circuit 411, the input sub-circuit 411 is electrically connected to the first signal terminal, the second signal terminal and the second node N2, and the initial scan signal output terminal GOA (N) of the shift register circuit in the N-th shift register 400 is electrically connected to the first signal terminal or the second signal terminal of the shift register circuit in the n+1-th shift register.

Referring to fig. 13, in the gate driving circuit 300, N shift registers 400 are included, shift register circuits 410 in the shift registers 400 are sequentially cascaded to realize a shift register function, and the signal output circuit 420 only realizes the first scan signal and the second scan signal output, and does not perform the shift register function.

Referring to fig. 13, an initial scan signal output terminal GOA (n) of the shift register circuit in the nth shift register 400 is electrically connected to the first signal terminal or the second signal terminal of the shift register circuit in the n+1th shift register. Illustratively, n is 1, so the initial scan signal output terminal GOA (n) of the first stage shift register 400 (R1) is electrically connected to the first signal terminal or the second signal terminal of the shift register circuit in the second stage shift register 400 (R2). Where N < N, it is understood.

Wherein, the first signal terminal or the second signal terminal of the shift register circuit 410 IN each stage of shift register is electrically connected to the initial scan signal output terminal GOA (N) IN the previous stage of shift register 400 except for the nth stage of shift register 400 (R (N)), wherein the first signal terminal and the second signal terminal may be collectively referred to as a signal input terminal IN. Illustratively, the signal input IN of the shift register circuit 410 IN the first stage shift register 400 (R (1)) may be electrically connected to the start signal line STV.

The gate driving circuit 300 provided in some embodiments of the present invention has all the advantages of the shift register 400 provided in some embodiments above, and is not described herein.

Some embodiments of the present invention also provide a display panel 200, see fig. 2B, the display panel 200 comprising: the gate driving circuit 300 provided in some of the above embodiments. The display panel 200 provided by some embodiments of the present invention has all the advantages of the gate driving circuit 300 provided by some embodiments above, and is not described herein.

In some embodiments, the display panel 200 further includes: a plurality of rows of subpixels 21, a plurality of gate scan signal lines G, and a plurality of emission control signal lines Em. At least one gate scan signal line G is electrically connected to the first scan signal output G (n) of one shift register 400 in the gate driving circuit 300, and further electrically connected to one row of sub-pixels 21. At least one emission control signal line Em is electrically connected to the second scan signal output Em (n) of one shift register 400 in the gate driving circuit 300, and further electrically connected to one row of sub-pixels 21.

For example, the first scan signal output terminal G (n) and the second scan signal output terminal EM (n) in one shift register 400 may be connected to one gate scan signal line G and one emission control signal line EM, respectively. In some embodiments, the first scan signal output terminal G (n) is configured to output the gate scan signal G (n), and the second scan signal output terminal EM (n) is configured to output the light emission control signal EM (n). One gate scan signal line G may be electrically connected to the first scan signal output terminal G (n) and the plurality of sub-pixels 21 in one row of sub-pixels 21, and one emission control signal line Em may be electrically connected to the second scan signal output terminal Em (n) and the plurality of sub-pixels 21 in one row of sub-pixels 21, so that one shift register 400 may provide the gate scan signal G (n) to one row of sub-pixels 21 through one gate scan signal line G and the emission control signal Em (n) to one row of sub-pixels 21 through one emission control signal line Em, i.e., one shift register 400 may provide both the gate scan signal G (n) and the emission control signal Em (n) to the gate scan signal line G and the emission control signal Em, respectively, thereby reducing the number of shift registers 400 in the display panel 200, reducing the occupied area of the shift registers 400, and facilitating narrowing the frame of the display panel 200.

The display panel 200 provided in some embodiments of the present invention may be, for example, an OLED (Organic Light-Emitting Diode) display panel, a Micro-Organic Light-Emitting Diode (Micro Organic Light-Emitting Diode) display panel, a quantum dot Organic Light-Emitting Diode (Quantum Dot Light Emitting Diodes, QLED) display panel, a Mini Light-Emitting Diode (Mini LED) display panel, or a Micro Light-Emitting Diode (Micro LED) display panel.

Some embodiments of the present invention further provide a display device 100, where the display device 100 includes the display panel 200 provided by some embodiments of the present invention, and therefore, the display device 100 provided by some embodiments of the present invention has all the advantages of the display panel 200 provided by the embodiments of the present invention, and detailed descriptions thereof are omitted herein.

It should be noted that, the display device 100 in this embodiment may be any product or component with a display function, such as an electronic paper LCD (liquid crystal display), an OLED (Organic Light-Emitting Diode) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A shift register is characterized by comprising a shift register circuit and a signal output circuit; wherein,

the shift register circuit is electrically connected to an initial scanning signal output end, and is configured to output an initial scanning signal at the initial scanning signal output end;

the signal output circuit is electrically connected with an initial scanning signal input end, a control signal end, a first clock signal end, a first voltage signal end, a second voltage signal end, a third voltage signal end, a first scanning signal output end and a second scanning signal output end, and the initial scanning signal input end is electrically connected with the initial scanning signal output end;

the signal output circuit is configured to output a first scan signal at the first scan signal output terminal and a second scan signal at the second scan signal output terminal in response to a control signal received at the control signal terminal, an initial scan signal received at the initial scan signal input terminal, a first clock signal received at the first clock signal terminal, a first voltage signal received at the first voltage signal terminal, a second voltage signal received at the second voltage signal terminal, and a third voltage signal received at the third voltage signal terminal, wherein a waveform of the first scan signal is not identical to a waveform of the second scan signal, the first scan signal is one signal required for a sub-pixel electrically connected to the shift register, and the second scan signal is another signal required for the sub-pixel.

2. The shift register as claimed in claim 1, wherein,

the first scanning signal is a grid scanning signal required by a sub-pixel electrically connected with the shift register, and the second scanning signal is a light-emitting control signal required by the sub-pixel.

3. The shift register according to claim 1, wherein the signal output circuit includes:

the first scanning signal output circuit is electrically connected with the control signal end, the initial scanning signal input end, the first clock signal end and the first scanning signal output end; the first scan signal output circuit is configured to output the initial scan signal received at the initial scan signal input terminal and the first clock signal received at the first clock signal terminal by the first scan signal output terminal at different stages, respectively, in response to the control signal received at the control signal terminal, thereby causing the first scan signal output terminal to output the first scan signal;

4. The shift register as claimed in claim 3, wherein,

the control signal end comprises a second clock signal end and a third clock signal end;

the first scanning signal output circuit includes:

a first output sub-circuit electrically connected to the second clock signal terminal, the first clock signal terminal, and the first scan signal output terminal, the first output sub-circuit configured to transmit the first clock signal received at the first clock signal terminal to the first scan signal output terminal in response to a second clock signal received at the second clock signal terminal;

and a second output sub-circuit electrically connected to the third clock signal terminal, the initial scan signal input terminal, and the first scan signal output terminal, the second output sub-circuit configured to transmit the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to a third clock signal received at the third clock signal terminal.

5. The shift register as claimed in claim 4, wherein,

The first output sub-circuit includes: a first transistor, wherein a control electrode of the first transistor is electrically connected to the second clock signal terminal, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the first scan signal output terminal;

the second output sub-circuit includes: and a control electrode of the second transistor is electrically connected to the third clock signal end, a first electrode of the second transistor is electrically connected to the initial scanning signal input end, and a second electrode of the second transistor is electrically connected to the first scanning signal output end.

6. A shift register according to claim 3, wherein the second scanning signal output circuit comprises:

the third output sub-circuit is electrically connected with the initial scanning signal input end, the first voltage signal end and the second scanning signal output end; the third output sub-circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal;

The first control sub-circuit is electrically connected with the initial scanning signal input end, the first voltage signal end and a first node; the first control sub-circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the first node in response to the initial scan signal received at the initial scan signal input terminal;

a second control sub-circuit electrically connected to the first node and the third voltage signal terminal, the second control sub-circuit configured to control the voltage of the first node in conjunction with the first control sub-circuit in accordance with a third voltage signal received at the third voltage signal terminal; a fourth output sub-circuit electrically connected to the first node, the second voltage signal terminal, and the second scan signal output terminal; the fourth output sub-circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to a voltage of the first node.

7. The shift register as claimed in claim 6, wherein,

The second control sub-circuit is configured to transmit the third voltage signal at the third voltage signal terminal to the first node to change a voltage of the first node if the first voltage signal is not transmitted to the first node.

8. The shift register as claimed in claim 7, wherein,

the second control sub-circuit includes: and the control electrode and the first electrode of the fourth transistor are electrically connected to the third voltage signal end, and the second electrode of the fourth transistor is electrically connected to the first node.

9. The shift register as claimed in claim 6, wherein,

the second control sub-circuit includes:

the regulation and control sub-circuit is electrically connected with a fourth clock signal end, the first node and the third voltage signal end; the regulation sub-circuit is configured to transmit a third voltage signal received at the third voltage signal terminal to the first node in response to a fourth clock signal received at the fourth clock signal terminal;

the energy storage sub-circuit is electrically connected with the fifth clock signal end and the first node; the tank sub-circuit is configured to change a voltage of the first node by a coupling action in accordance with a fifth clock signal received at the fifth clock signal terminal, in a case where the first voltage signal and the third voltage signal are not transmitted to the first node.

10. The shift register of claim 9, wherein the shift register comprises a plurality of registers,

the regulator sub-circuit includes: a seventh transistor having a control electrode electrically connected to the fourth clock signal terminal, a first electrode electrically connected to the third voltage signal terminal, and a second electrode electrically connected to the first node;

the tank sub-circuit includes: and a first capacitor, a first end of which is electrically connected to the fifth clock signal end, and a second end of which is electrically connected to the first node.

11. Shift register according to any of the claims 6-10, characterized in that,

the first control sub-circuit includes: a third transistor having a control electrode electrically connected to the initial scan signal input terminal, a first electrode electrically connected to the first voltage signal terminal, and a second electrode electrically connected to the first node;

and/or the number of the groups of groups,

the third output sub-circuit includes: a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the initial scan signal input terminal, a first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the fifth transistor is electrically connected to the second scan signal output terminal;

And/or the number of the groups of groups,

the fourth output sub-circuit includes: and a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the sixth transistor is electrically connected to the second scan signal output terminal.

12. The shift register as claimed in claim 1, wherein,

the shift register circuit includes:

an input sub-circuit electrically connected to a first signal terminal, a second signal terminal, and a second node, the input sub-circuit configured to transmit a second signal received at the second signal terminal to the second node in response to a first signal received at the first signal terminal, wherein the first signal terminal or the second signal terminal is electrically connected to an initial scan signal output terminal of a shift register circuit in a previous stage shift register;

an output control sub-circuit electrically connected to the second node, a sixth clock signal terminal, and the initial scan signal output terminal, the output control sub-circuit configured to transmit a sixth clock signal received at the sixth clock signal terminal to the initial scan signal output terminal in response to a voltage of the second node;

Wherein the period of the sixth clock signal is at least twice the period of the first clock signal.

13. A gate driving circuit comprising N-stage cascade of shift registers according to any one of claims 1 to 12, N being a positive integer greater than or equal to 1; the shift register includes: the shift register circuit comprises an input sub-circuit, wherein the input sub-circuit is electrically connected with a first signal end, a second signal end and a second node, and an initial scanning signal output end of the shift register circuit in the nth shift register is electrically connected with a first signal end or a second signal end of the shift register circuit in the n+1th shift register, and N is more than or equal to 1 and less than or equal to N-1.

14. A display panel, comprising:

the gate drive circuit of claim 13.

15. The display panel of claim 14, comprising: a plurality of rows of subpixels;

a plurality of gate scanning signal lines, at least one of which is electrically connected with a first scanning signal output end of one shift register in the gate driving circuit and further electrically connected with a row of sub-pixels;

And the plurality of light-emitting control signal lines are electrically connected with the second scanning signal output end of one shift register in the grid driving circuit, and further electrically connected with one row of sub-pixels.

16. A display device, comprising: the display panel of claim 14 or 15.

17. A shift register driving method is characterized by being used for a shift register, wherein the shift register comprises a shift register circuit and a signal output circuit; the shift register circuit is electrically connected to an initial scanning signal output end, and is configured to output an initial scanning signal at the initial scanning signal output end; the signal output circuit is electrically connected with an initial scanning signal input end, a control signal end, a first clock signal end, a first voltage signal end, a second voltage signal end, a third voltage signal end, a first scanning signal output end and a second scanning signal output end, and the initial scanning signal input end is electrically connected with the initial scanning signal output end;

the driving method includes:

the shift register circuit outputs an initial scanning signal at the initial scanning signal output end;

The signal output circuit outputs a first scan signal at the first scan signal output terminal and a second scan signal at the second scan signal output terminal in response to a control signal received at the control signal terminal, an initial scan signal received at the initial scan signal input terminal, a first clock signal received at the first clock signal terminal, a first voltage signal received at the first voltage signal terminal, a second voltage signal received at the second voltage signal terminal, and a third voltage signal received at the third voltage signal terminal; the waveform of the first scanning signal is not identical to the waveform of the second scanning signal.

18. The method for driving a shift register as claimed in claim 17, wherein,

the signal output circuit comprises a first scanning signal output circuit and a second scanning signal output circuit;

the driving method includes: one frame period includes: a charging phase, an output phase and a reset phase, wherein the output phase comprises a pixel initialization phase and a refresh and compensation phase, and the reset phase comprises a first light-emitting phase and a second light-emitting phase;

In the charging stage, the shift register circuit outputs a first level of an initial scanning signal to the initial scanning signal output end;

in the output stage, the shift register circuit outputs a second level of an initial scanning signal to the initial scanning signal output end;

in the pixel initialization stage in the output stage, a first scan signal output circuit transmits a first clock signal received at a first clock signal terminal to a first scan signal output terminal in response to a control signal received at a control signal terminal;

the second scan signal output circuit transmits the first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal;

in the refresh and compensation stage of the output stages, the first scan signal output circuit transmits the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal;

the second scan signal output circuit transmitting the first voltage signal received at the first voltage signal terminal to the second scan signal output terminal in response to the initial scan signal received at the initial scan signal input terminal;

In the reset stage, the shift register circuit outputs a first level of an initial scanning signal to the initial scanning signal output end;

in the first light-emitting stage of the reset stage, the first scan signal output circuit transmits the first clock signal received at the first clock signal terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal;

the second scan signal output circuit transmitting the second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to the third voltage signal received at the third voltage signal terminal;

in the second light-emitting stage of the reset stage, the first scan signal output circuit transmits the initial scan signal received at the initial scan signal input terminal to the first scan signal output terminal in response to the control signal received at the control signal terminal;

the second scan signal output circuit transmits the second voltage signal received at the second voltage signal terminal to the second scan signal output terminal in response to the third voltage signal received at the third voltage signal terminal.