CN109192154A - Gate driving circuit and display device - Google Patents
Gate driving circuit and display device Download PDFInfo
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- CN109192154A CN109192154A CN201811056150.9A CN201811056150A CN109192154A CN 109192154 A CN109192154 A CN 109192154A CN 201811056150 A CN201811056150 A CN 201811056150A CN 109192154 A CN109192154 A CN 109192154A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Crystallography & Structural Chemistry (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
This application discloses a kind of gate driving circuits, including cascade multiple drive element of the grid, and each drive element of the grid includes: input module, according to the first enabling signal and the second enabling signal, charge to first node；Output module is connected in the first node with the input module, generates multiple gate drive signals according to multiple voltage signals are corresponding, and provide the gate drive signal in output end；Pull-down module is connected with output module, for the gate drive signal to be pulled down to low level signal under the control of second clock signal；And stable module, it is connected with the first node and output end, under the control of first clock signal and the second clock signal, the gate drive signal and described the same level transmitting signal is maintained at the low level signal.The quantity of drive element of the grid can be reduced, realizes narrow frame and low-power consumption display device, and improve the stability of driving circuit.
Description
Technical field
The present invention relates to field of display technology, relate more specifically to gate driving circuit and display device.
Background technique
Liquid crystal display device is change the phenomenon that being changed under the action of electric field using the orientation of liquid crystal molecule
The display device of light source light transmittance.Due to having the advantages that display is high-quality, small in size and low in energy consumption, liquid crystal display device is
It is widely used in the mobile terminal of such as mobile phone and the large scale display panel of such as flat panel TV.Liquid on existing market
Crystal display is largely projection-type liquid crystal display comprising liquid crystal display panel and backlight module (backlight module).
The working principle of liquid crystal display panel is liquid crystal molecule to be placed among the parallel glass substrate of two panels, and apply on two panels glass substrate
Add driving voltage to control the direction of rotation of liquid crystal molecule, generation picture is modulated to the luminous of backlight module.
The development of liquid crystal display device in recent years presents the development trend of high integration, low cost, integrative display
Driving is increasingly becoming the research hotspot of flat panel display.So-called integrative display driving circuit refers to gate driving circuit and source
The peripheral circuits such as pole driving circuit using switching tube (Thin Film Transistor, TFT) realize and with pixel switch pipe one
It rises and is made in TFT substrate.It is compared with traditional circuit (IC) driving method, uses the method for integrated gate driving not only can be with
The quantity and its press seal program of reduction peripheral driver chip reduce cost, and make display periphery more slim, so that aobvious
Show that device mould group is more compact, mechanically and electrically reliability is enhanced.
The basic functional principle of liquid crystal display panel and driving circuit are as follows: gate driving circuit is upper by what is be electrically connected with grid line
Pull transistor sends out gate drive signal to grid line, sequentially opens the TFT of every a line, then simultaneously by source electrode drive circuit
The pixel unit of one full line is charged to respectively required voltage, to show different grayscale.I.e. first by the grid of the first row
Driving circuit, which passes through to pull up transistor, opens the thin film transistor (TFT) of the first row, then by source electrode drive circuit to the picture of the first row
Plain unit charges.When the pixel unit of the first row is charged, gate driving circuit just closes the row thin film transistor (TFT), so
The gate driving circuit of the second row is pulled up transistor by it and opens the thin film transistor (TFT) of the second row afterwards, then by source drive electricity
It charges to the pixel unit of the second row on road.So sequentially go down, when the pixel unit for last line of having substituted the bad for the good, just again
It charges to the pixel unit of the first row.
But for large-sized liquid crystal display device, the load of gate driving circuit driving is very big, and to display
Uniformity requirements it is higher, the gate drive signal for requiring gate driving circuit output voltage values larger and stable in this way is existing
Technology is generally solved the problem above-mentioned using the number and size of the switch element, capacitor that increase in gate driving circuit, but
It is the narrow frame design that the above method is unfavorable for liquid crystal display device, and power consumption is big.
Therefore, it is necessary to provide improved technical solution to overcome the above technical problem existing in the prior art.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of gate driving circuit and display device, it can be in output electricity
While pressure is worth larger and stable gate drive signal, be conducive to narrow frame design, and small power consumption.
A kind of gate driving circuit, including cascade multiple drive element of the grid are disclosed according to an aspect of the present invention,
It is characterized in that, each drive element of the grid includes: input module, it is connected with first node, is believed according to the first starting
Number and the second enabling signal, charge to first node；First output module is connected in described first with the input module
Node generates the same level transmitting signal according to the first clock signal；Second output module is connected in described with the input module
One node generates multiple gate drive signals according to multiple voltage signals are corresponding, and provides the gate driving in output end
Signal；First pull-down module is connected with the first node, will under the control of third enabling signal and the 4th enabling signal
The first node is pulled down to low level signal；Second pull-down module is connected with second output module, at second
The same level gate drive signal is pulled down to low level signal under the control of clock signal；And stable module, with described first
Node is connected with output end, and under the control of first clock signal and the second clock signal, the grid is driven
Dynamic signal and described the same level transmitting signal are maintained at the low level signal.
Preferably, the multiple voltage signal is multiple alternating signals that high level does not overlap, wherein the multiple electricity
It presses the sum of high level time of signal to be equal to a frame and shows the time.
Preferably, the duty ratio of the multiple voltage signal is equal.
Preferably, the voltage signal includes at least first voltage signal and second voltage signal, the second output mould
Root tuber generates first gate driving signal according to the first voltage signal；Second output module is believed according to the second voltage
Number generation second grid driving signal.
Preferably, the input module includes: first switch tube, and control terminal receives first enabling signal, and first is logical
Terminal receives second enabling signal, and alternate path end is connect with the first node.
Preferably, first output module includes: second switch, and control terminal is connect with the first node, and first
Path terminal is for receiving first clock signal, and alternate path end is for generating the same level transmitting signal；First capacitor is connected to
Between the control terminal and alternate path end of the second switch.
Preferably, first pull-down module includes: third switching tube, and control terminal is for receiving the third starting letter
Number, the first path terminal is connect with the first node, and alternate path end is for receiving the 4th enabling signal.
Preferably, the stable module includes: the 6th switching tube, and control terminal is connect with the first node, the first access
End is connected to second node, and alternate path end receives the low level signal；8th switching tube, control terminal is for receiving described the
One clock signal, for the first path terminal for receiving d. c. voltage signal, alternate path end is connected to the second node；5th opens
Guan Guan, control terminal are connected to the second node, and the first path terminal is connected to the first node, and alternate path end is for receiving
The low level signal；7th switching tube, control terminal are connected to the second node, and the first path terminal is connected to described the same level and passes
Delivery signal output end, alternate path end is for receiving the low level signal.
Preferably, the stable module further include: the 4th switching tube, control terminal are used to receive the second clock signal,
First path terminal is connected to the same level transmitting signal output end, and alternate path end is for receiving the low level signal.
Preferably, second output module includes: the 11st switching tube, and control terminal is connected to the first node, the
One path terminal is for receiving the first voltage signal, and alternate path end is for exporting the first gate driving signal；Tenth
Two switching tubes, control terminal are connected to the first node, and the first path terminal is for receiving the second voltage signal, alternate path
End is for exporting the second grid driving signal, wherein when the first voltage signal is high level, the described 11st is opened
Pipe conducting is closed, the effective first gate driving signal is exported；When the second voltage signal is high level, the described tenth
The conducting of two switching tubes exports the effective second grid driving signal.
Preferably, second pull-down module includes: the 9th switching tube, and control terminal receives the second clock signal, the
For one path terminal for receiving the low level signal, alternate path end is connected to the alternate path end of the 11st switching tube；
Tenth switching tube, control terminal receive the second clock signal, and the first path terminal is connected to the second of the 12nd switching tube
Path terminal, alternate path end is for receiving the low level signal, wherein when the second clock signal is effective, the described 9th
Switching tube and the conducting of the tenth switching tube, are provided to the 11st switching tube and the 12nd switching tube for the low level signal respectively
Alternate path end.
According to another aspect of the present invention ,-kind of display device is provided characterized by comprising above-mentioned gate driving
Circuit, for providing multiple gate drive signals；Data drive circuit, for providing multiple luma datas；And display panel,
The display panel includes the multiple pixel units and a plurality of grid line and multiple data lines for being arranged in array, the display surface
Plate receives the multiple gate drive signal via a plurality of grid line, so that the multiple pixel unit is selected by row, with
And the multiple luma data is received by column via the multiple data lines, to be supplied to selected pixel unit to realize figure
As display.
The gate driving circuit of the embodiment of the present invention includes successively cascade multiple drive element of the grid, when one of grid
When pole driving unit carries out pixel charging, only the pixel for being separated by level-one with it is pre-charged, reduces the grid opened simultaneously
The quantity of line reduces the overlapping period of adjacent drive element of the grid output waveform, can avoid band occur in display
Phenomenon promotes the display quality of display device.
In preferred embodiment, the transmitting signal and gate drive signal of drive element of the grid are defeated by different modules
Out, so that the load reduction of transfer unit, to enhance the stability of circuit signal transmitting.
In preferred embodiment, every level-one drive element of the grid of gate driving circuit drives a plurality of grid line, full
It is conducive to reduce the quantity of drive element of the grid under the premise of sufficient gate driving circuit driving capability, reduces corresponding laying out pattern face
Product, so as to realize narrow frame, low-power consumption display device.
Similarly, it can be also effectively reduced using the power consumption of the display device of above-mentioned drive element of the grid.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 shows the structural representation of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.
Fig. 2 shows the circuit diagrams of the drive element of the grid of first embodiment of the invention.
Fig. 3 shows the structural schematic diagram of gate driving circuit according to a second embodiment of the present invention.
Fig. 4 shows the working timing figure of the gate driving circuit of second embodiment of the invention.
Fig. 5 shows the circuit of n-th grade of drive element of the grid in gate driving circuit according to a second embodiment of the present invention
Schematic diagram.
Fig. 6 shows the working timing figure of the drive element of the grid of second embodiment of the invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.In addition, may not show in figure
Certain well known parts out.
Many specific details of the invention, such as structure, material, size, the processing work of component is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Gate driving circuit (also referred to as shift register) of the invention includes that multistage drive element of the grid (also referred to as shifts
Deposit unit), every level-one drive element of the grid is corresponding with every a line grid line on display panel respectively to be electrically connected, thus will
Gate drive signal is sequentially gradually applied on every a line grid line, and the connection relationship between drive element of the grid will hereinafter
It is described in detail.
Fig. 1 shows the structural representation of n-th grade of drive element of the grid in the gate driving circuit of first embodiment of the invention
Figure.As shown in Figure 1, drive element of the grid 100 include input module 110, the first pull-down module 120, the first output module 130,
Second pull-down module 140, the second output module 150 and stable module 160.
The input terminal of input module 110 is for receiving prime transmitting signal Zn-2 and enabling signal V3, output end and first
Node Q connection is pre-charged first node Q for transmitting signal Zn-2 according to prime.First output module 130 and first
Node Q connection transmits signal Zn to export the clock signal clk 1 received according to the control voltage of first node Q for the same level.
Second output module 150 connect with the control voltage according to first node Q that the voltage signal V1 received is defeated with first node Q
It is out the same level gate drive signal Gn.First pull-down module 120 is used for receiving rear class transmitting signal Zn+2 and enabling signal V4
Enabling signal V4 is provided to first node Q to drag down the current potential of first node Q in transmitting signal Zn+2 according to rear class.Under second
Drawing-die block 140 is connect with the second output module 150, for low level signal VGL to be provided to second according to clock signal clk 2
Output module 150 with by the same level gate drive signal Gn down for low level signal VGL.Stable module 160 is used for according to clock
Low level signal VGL is alternately provided to first node Q and the same level transmitting signal output end by signal CLK1 and clock signal clk 2.
Fig. 2 shows the circuit diagrams of the drive element of the grid of first embodiment of the invention.As shown in Fig. 2, input module
110 include first switch tube T1, and the control terminal of first switch tube T1 receives prime and transmits signal Zn-2, and the reception of the first path terminal is opened
Dynamic signal V3, alternate path end is connect with first node Q.
First output module 130 includes second switch T2 and first capacitor C1, the control terminal of second switch T2 and the
One node Q connection, the first path terminal are connect with output end for receiving clock signal clk 1, alternate path end to export the same level biography
Delivery signal Zn, first capacitor C1 are connected between the control terminal of second switch T2 and alternate path end.
Wherein, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2.Certainly,
It will be appreciated by those skilled in the art that can also be arranged between the control terminal and alternate path end of second switch T2
Separate storage capacitor, at this point, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2
The sum of with separate storage capacitor.
Second output module 150 includes the 11st switch transistor T 11, the control terminal and first node Q of the 11st switch transistor T 11
Connection, the first path terminal are connect with output end for receiving voltage signal V1, alternate path end to export the same level gate driving letter
Number Gn.
First pull-down module 120 includes third switch transistor T 3, and the control terminal of third switch transistor T 3 is for receiving rear class transmitting
Signal Zn+2, the first path terminal are connect with first node Q, and alternate path end is for receiving enabling signal V4.It transmits and believes when rear class
When number Zn+2 is high level, third switch transistor T 3 is connected, and enabling signal V4 is provided to first node Q to drag down first node Q
Current potential.It should be noted that the structure of the first pull-down module 120 is not limited only to above-mentioned structure, it is also possible to other multiple open
The structure of pipe combination is closed, those skilled in the art can select as the case may be.
Second pull-down module 140 includes the 9th switch transistor T 9, and the control terminal of the 9th switch transistor T 9 is for receiving clock signal
CLK2, the first path terminal is for receiving low level signal VGL, the alternate path end at alternate path end and the 11st switch transistor T 11
Connection.When clock signal CLK2 is high level, low level signal VGL is provided to the 11st switch by the conducting of the 9th switching tube
The alternate path end of pipe T11.
Stable module 160 includes the 4th to the 8th switch transistor T 4-T8, and the control terminal of the 4th switch transistor T 4 receives clock signal
CLK2, the first path terminal are connected to the same level transmitting signal output end, and alternate path end is for receiving low level signal VGL.At that time
When clock signal CLK2 is high level, low level signal VGL is provided to the same level transmitting signal output by the conducting of the 4th switch transistor T 4
End.The control terminal of 6th switch transistor T 6 is connected to first node Q, and the first path terminal is connected to second node QB, alternate path end
For receiving low level signal VGL.For receiving clock signal clk 1, the first path terminal is used for the control terminal of 8th switch transistor T 8
Direct current signal VDC is received, alternate path end is connect with second node QB.The control terminal of 5th switch transistor T 5 is connected to second node
QB, the first path terminal are connected to first node Q, and alternate path end receives low level signal VGL.The control terminal of 7th switch transistor T 7
It is connected to second node QB, the first path terminal is connected to the same level transmitting signal output end, and alternate path end is for receiving low level
Signal VGL.
In the above-described embodiments, the transmitting signal of drive element of the grid and gate drive signal are defeated by different modules
Out, so that the load reduction of transfer unit, to enhance the stability of circuit signal transmitting.
In preferred embodiment of the present invention, a kind of gate driving circuit, including multistage drive element of the grid are provided, it is each
Grade drive element of the grid is corresponding with the multirow grid line on display panel respectively to be electrically connected, sequentially gradually by gate drive signal
It is applied on every a line grid line.
Fig. 3 shows the structural schematic diagram of the gate driving circuit of second embodiment of the invention.It is according to an embodiment of the present invention
Gate driving circuit is, for example, integrated gate drive circuitry (Gate Driver in Array, be abbreviated as GIA), including successively grade
Multiple drive element of the grid 200 of connection.Multiple drive element of the grid 200 phase corresponding with the grid line on display panel respectively
Even, via grid line by the pixel unit on row selection display panel.Then it is mentioned via data line by column by source electrode drive circuit
For corresponding grayscale signal to realize that image is shown.
In the present embodiment, each drive element of the grid is connected with multiple grid lines on display panel, by row scanning
The multiple grid line.
In a preferred embodiment, the gate driving circuit 20 of the embodiment of the present invention is sided configuration, the multiple grid
Driving unit includes two groups of drive element of the grid, and two groups of drive element of the grid cascade the left and right for being set to display panel respectively
Two sides, including first part 20a and second part 20b.
Every level-one drive element of the grid all includes that the first enabling signal input terminal, the second enabling signal input terminal, third open
Dynamic signal input part, the 4th enabling signal input terminal, the first clock signal input terminal, second clock signal input part, low level
Signal input part, direct current signal input terminal, first voltage signal input part, second voltage signal input part, the same level transmit signal
Output end and the same level gate drive signal output end, the same level gate drive signal output end is for driving display panel 210
Pixel unit.For being located at the drive element of the grid on the left of display panel, the first clock signal input terminal and second clock letter
Number input terminal is connected respectively to receive clock signal clk 1_L and CLK2_L with multiple clock lines；For being located on the right side of display panel
Drive element of the grid, the first clock signal input terminal and second clock signal input part are connected with a plurality of clock letter line respectively
To receive clock signal clk 1_R and CLK2_R.
When drive element of the grid is first order drive element of the grid, the first enabling signal of the drive element of the grid is defeated
Enter end for inputting enabling signal STV1_L.
When pole driving unit is second level drive element of the grid, the first enabling signal input of the drive element of the grid
End is for inputting enabling signal STV1_R.
It is described when drive element of the grid is the third level any drive element of the grid into the n-th -2 grades drive element of the grid
The same level transmitting signal that first enabling signal input terminal of drive element of the grid is electrically connected to the i-th -2 grades drive element of the grid is defeated
Outlet.The third enabling signal input terminal of drive element of the grid is electrically connected to the same level transmitting of the i-th+2 grades drive element of the grid
Signal output end.
When drive element of the grid is n-th grade or (n-1)th grade of drive element of the grid, the first of the drive element of the grid is opened
Dynamic signal input part is electrically connected to the same level transmitting signal output end of the i-th -2 grades drive element of the grid, the gate driving list
The third enabling signal input terminal of member is for inputting enabling signal STV2_L or STV2_R.
Second enabling signal input terminal of every level-one drive element of the grid and the 4th enabling signal input terminal for connecing respectively
Receive enabling signal V3 and enabling signal V4.Low level signal input terminal is for receiving low level signal VGL, direct current signal input terminal
For receiving direct current signal VDC.
Preferably, every level-one drive element of the grid exports multiple gate drive signals, as shown in figure 3, first order grid drives
Moving cell exports gate drive signal G1 and G2, and second level drive element of the grid exports gate drive signal G3 and G4, the third level
Drive element of the grid exports gate drive signal G5 and G6, and so on.
It should be noted that, although in the above-described embodiments by taking every level-one drive element of the grid drives two grid lines as an example
Be illustrated, still, invention is not limited thereto system, those skilled in the art can meet driving load under the premise of,
The quantity of every level-one drive element of the grid driving grid line is selected as the case may be.
The every level-one drive element of the grid of the gate driving circuit of the embodiment of the present invention drives two grid lines, relative to existing
The gate driving circuit of technology reduces the drive element of the grid of half quantity, so as to reduce corresponding laying out pattern face
Product, so as to realize narrow frame, low-power consumption display device.
It should be noted that although describing the gate driving circuit using sided configuration in this embodiment, it is of the invention
It is without being limited thereto.When being applied to the gate driving circuit of one-sided configuration, gate driving circuit of the invention can also reduce grid
The quantity of driving unit obtains the beneficial effect for reducing chip area.
Fig. 4 shows the working timing figure of the gate driving circuit of second embodiment of the invention.
As shown in figure 4, clock signal clk 1_L-CLK2_R is square-wave signal, duty ratio 1/2, enabling signal STV1_
L-STV2_R is single pulse signal, and voltage signal V1 and V2 are the alternating signal of duty ratio 1/2.
It all include being used for transmission starting in the first part of gate driving circuit and the main path of second part referring to Fig. 3
The signal wire of signal STV1_L-STV2_R, clock signal clk 1_L-CLK2_R and voltage signal V1 and V2.Enabling signal
Failing edge of the STV1_R in enabling signal STV1_L starts, and failing edge of the enabling signal STV2_R in enabling signal STV2_L opens
It is dynamic.Phase successively delays 1/4 clock cycle between clock signal clk 1_L-CLK2_R.Voltage signal V2 is in voltage signal V1
Failing edge starting, phase delays 1/2 clock cycle.In addition, when the high level of voltage signal V1 and voltage signal V2 continue
Between for display time for being respectively field picture, the sum of high level lasting time of voltage signal V1 and voltage signal V2 is a frame
The display time.
In the present embodiment, gate driving circuit uses interleaved mode, in the first half frame scan odd number of each frame
Capable grid line, in the grid line of later half frame scan even number line, as shown in Figure 4.Certainly, in other embodiments of the present invention, exist
The grid line of the first half frame scan even number line of each frame, in the grid line of later half frame scan odd-numbered line, invention is not limited thereto
System.
Fig. 5 shows the circuit of n-th grade of drive element of the grid in gate driving circuit according to a second embodiment of the present invention
Schematic diagram.
As shown in figure 5, drive element of the grid 200 includes input module 210, the first pull-down module 220, the first output module
230, the second pull-down module 240, the second output module 250 and stable module 260.
Input module 210 includes first switch tube T1, and the control terminal of first switch tube T1 receives prime and transmits signal Zn-2,
First path terminal receives enabling signal V3, and alternate path end is connect with first node Q.
First output module 230 includes second switch T2 and first capacitor C1, the control terminal of second switch T2 and the
One node Q connection, the first path terminal are connect with output end for receiving clock signal clk 1, alternate path end to export the same level biography
Delivery signal Zn, first capacitor C1 are connected between the control terminal of second switch T2 and alternate path end.
Wherein, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2.Certainly,
It will be appreciated by those skilled in the art that can also be arranged between the control terminal and alternate path end of second switch T2
Separate storage capacitor, at this point, first capacitor C1 is the parasitic capacitance between the control terminal and alternate path end of second switch T2
The sum of with separate storage capacitor.
Second output module 250 includes the 11st switch transistor T 11 and the 12nd switch transistor T 12, the 11st switch transistor T 11
Control terminal is connect with first node Q, and for receiving voltage signal V1, alternate path end is connect with output end with defeated the first path terminal
Gate drive signal Gn out.The control terminal of 12nd switch transistor T 12 is connect with first node Q, and the first path terminal is for receiving electricity
Signal V2 is pressed, alternate path end is connect to export gate drive signal Gn+1 with output end.
First pull-down module 220 includes third switch transistor T 3, and the control terminal of third switch transistor T 3 is for receiving rear class transmitting
Signal Zn+2, the first path terminal are connect with first node Q, and alternate path end is for receiving enabling signal V4.It transmits and believes when rear class
When number Zn+2 is high level, third switch transistor T 3 is connected, and enabling signal V4 is provided to first node Q to drag down first node Q
Current potential.It should be noted that the structure of the first pull-down module 220 is not limited only to above-mentioned structure, it is also possible to other multiple open
The structure of pipe combination is closed, those skilled in the art can select as the case may be.
Second pull-down module 240 includes the 9th switch transistor T 9 and the tenth switch transistor T 10, and the control terminal of the 9th switch transistor T 9 is used
In receiving clock signal clk 2, the first path terminal is for receiving low level signal VGL, alternate path end and the 11st switching tube
The alternate path end of T11 connects.For receiving clock signal clk 2, the first path terminal is used for the control terminal of tenth switch transistor T 10
Low level signal VGL is received, alternate path end is connect with the alternate path end of 12 switch transistor Ts 12 of ground.As clock signal CLK2
When for high level, low level signal VGL is provided to the 11st switching tube by the 9th switch transistor T 9 and the conducting of the tenth switch transistor T 10
The alternate path end of T11 and the 12nd switch transistor T 12.
Stable module 260 includes the 4th to the 8th switch transistor T 4-T8, and the control terminal of the 4th switch transistor T 4 receives clock signal
CLK2, the first path terminal are connected to the same level transmitting signal output end, and alternate path end is for receiving low level signal VGL.At that time
When clock signal CLK2 is high level, low level signal VGL is provided to the same level transmitting signal output by the conducting of the 4th switch transistor T 4
End.The control terminal of 6th switch transistor T 6 is connected to first node Q, and the first path terminal is connected to second node QB, alternate path end
For receiving low level signal VGL.For receiving clock signal clk 1, the first path terminal is used for the control terminal of 8th switch transistor T 8
Direct current signal VDC is received, alternate path end is connect with second node QB.The control terminal of 5th switch transistor T 5 is connected to second node
QB, the first path terminal are connected to first node Q, and alternate path end receives low level signal VGL.The control terminal of 7th switch transistor T 7
It is connected to second node QB, the first path terminal is connected to the same level transmitting signal output end, and alternate path end is for receiving low level
Signal VGL.
Fig. 6 shows the working timing figure of the drive element of the grid of second embodiment of the invention.Referring to Fig. 5 and Fig. 6 couples
The working principle of the drive element of the grid of second embodiment of the invention is described in detail.
In the first stage, when prime transmitting signal Zn-2 becomes high level from low level, first switch tube T1 conducting, the
Enabling signal V3 is supplied to first node Q by one switch transistor T 1, and enabling signal V3 is direct current high level, is carried out to first node Q
Precharge, the current potential of first node Q become high level from low level, are connected the 6th switch transistor T 6, and the 6th switch transistor T 6 is by low electricity
Ordinary mail VGL is respectively supplied to second node QB, by the current potential of second node QB down for low level, the 4th switch transistor T 4,
Five switch transistor Ts 5 and the shutdown of the 7th switch transistor T 7.
In second stage, when clock signal CLK1 is high level by low level raising, by the bootstrapping of first capacitor C1
Effect, the current potential of first node Q continues to increase, because of second switch T2, the 11st switch transistor T 11 and the 12nd switching tube
T12 has been opened in the first stage, so in second stage second switch T2, the 11st switch transistor T 11 and the 12nd
Switch transistor T 12 is sufficiently conductive, exports the same level transmitting signal Zn via second switch T2.In upper field, because of voltage signal V1
For high level, voltage signal V2 is low level, therefore drive element of the grid is believed via the 11st switch transistor T 11 output gate driving
Number Gn；In lower field, voltage signal V1 becomes low level, and voltage signal V2 becomes high level, then drive element of the grid passes through at this time
Gate drive signal Gn+1 is exported by the 12nd switch transistor T 12.
It should be noted that in the present invention, control terminal and the alternate path end of second switch T2 can be directly used
Between parasitic capacitance as first capacitor C1, can also be in the control of second switch T2 or in order to promote pull-up effect
Separate storage capacitor is set between end and alternate path end.Wherein, the parasitism electricity of the separate storage capacitor and second switch T2
Hold cylinder barrel in parallel to be equal between the control terminal and alternate path end of second switch T2 as first capacitor C1, i.e. first capacitor C1
Parasitic capacitance and the sum of separate storage capacitor.
In the phase III, when clock signal CLK1 becomes low level, output waveform is dragged down by second switch T2
For low level, while the current potential of first node Q being dragged down by the coupling of first capacitor C1.When rear class transmits signal Zn+2
When becoming high level from low level, third switch transistor T 3 is connected, and enabling signal V4 is supplied to first node by third switch transistor T 3
Q, enabling signal V4 are direct current low level, therefore by the current potential of first node Q down for low level.
In fourth stage, when clock signal CLK1 and clock signal clk 2 alternately become high level from low level, stablize
Module 260 and the second pull-down module 240 are alternately opened, so that first node Q, gate drive signal output end and the same level transmitting letter
The current potential of number output end stabilizes to low level.Specifically, when clock signal CLK1 is high level, the conducting of the 8th switch transistor T 8,
D. c. voltage signal VDC is provided to second node QB by the 8th switch transistor T 8, and second node QB is high level, and the 5th and the 7th opens
Pipe T5 and T7 conducting are closed, low level signal VGL is provided to first node Q respectively and the same level transmits signal output end.Work as clock
When signal CLK2 is high level, the 9th switch transistor T 9 and the conducting of the tenth switch transistor T 10, the 9th switch transistor T 9 and the tenth switching tube
Low level signal VGL is provided to the alternate path end of the 11st switch transistor T 11 and the 12nd switch transistor T 12 by T10 respectively, by grid
Driving signal Gn and gate drive signal Gn+1 maintain low level state for pole.
It should be noted that the first to the 12nd switch transistor T 1-T12 can use such as non-crystalline silicon tft, oxide TFT
Or the switch elements such as low temperature polycrystalline silicon N-TFT and realize.Such as in embodiments of the present invention, the first to the 12nd switching tube
T1-T12 is N-type TFT, and the first path terminal of each transistor and alternate path end can be interchanged (i.e. drain electrode and
Source electrode can be interchanged), but of the invention it is practiced without limitation to this.
In conclusion the gate driving circuit of the embodiment of the present invention includes successively cascade multiple drive element of the grid, when
When one of drive element of the grid carries out pixel charging, only the pixel for being separated by level-one with it is pre-charged, is reduced simultaneously
The quantity of the grid line of opening reduces the overlapping period of adjacent drive element of the grid output waveform, can avoid in display
There is the phenomenon that band, promotes the display quality of display device.
In preferred embodiment, the transmitting signal and gate drive signal of drive element of the grid are defeated by different modules
Out, so that the load reduction of transfer unit, to enhance the stability of circuit signal transmitting.
In preferred embodiment, every level-one drive element of the grid of gate driving circuit drives a plurality of grid line, full
It is conducive to reduce the quantity of drive element of the grid under the premise of sufficient gate driving circuit driving capability, reduces corresponding laying out pattern face
Product, so as to realize narrow frame, low-power consumption display device.
Similarly, it can be also effectively reduced using the power consumption of the display device of above-mentioned drive element of the grid.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.
Claims (10)
1. a kind of gate driving circuit, including cascade multiple drive element of the grid, which is characterized in that each gate driving
Unit includes:
Input module is connected with first node, according to the first enabling signal and the second enabling signal, fills to first node
Electricity；
First output module is connected in the first node with the input module, generates the same level according to the first clock signal and passes
Delivery signal；
Second output module is connected in the first node with the input module, more according to the corresponding generation of multiple voltage signals
A gate drive signal, and the gate drive signal is provided in output end；
First pull-down module is connected with the first node, will under the control of third enabling signal and the 4th enabling signal
The first node is pulled down to low level signal；
Second pull-down module is connected with second output module, under the control of second clock signal by the grid
Driving signal is pulled down to low level signal；And
Stable module is connected with the first node and output end, believes in first clock signal and the second clock
Number control under, by the gate drive signal and described the same level transmitting signal be maintained at the low level signal.
2. gate driving circuit according to claim 1, which is characterized in that the voltage signal includes at least first voltage
Signal and second voltage signal,
Second output module generates first gate driving signal, second output module according to the first voltage signal
Second grid driving signal is generated according to the second voltage signal.
3. gate driving circuit according to claim 1, which is characterized in that the input module includes:
First switch tube, control terminal reception first enabling signal, the first path terminal reception second enabling signal, second
Path terminal is connect with the first node.
4. gate driving circuit according to claim 1, which is characterized in that first output module includes:
Second switch, control terminal are connect with the first node, and the first path terminal is used to receive first clock signal, the
Two path terminals are for generating the same level transmitting signal；
First capacitor is connected between the control terminal of the second switch and alternate path end.
5. gate driving circuit according to claim 1, which is characterized in that first pull-down module includes:
Third switching tube, for receiving the third enabling signal, the first path terminal is connect control terminal with the first node, the
Two path terminals are for receiving the 4th enabling signal.
6. gate driving circuit according to claim 1, which is characterized in that the stable module includes:
6th switching tube, control terminal are connect with the first node, and the first path terminal is connected to second node, alternate path termination
Receive the low level signal；
8th switching tube, control terminal are used to receive d. c. voltage signal for receiving first clock signal, the first path terminal,
Alternate path end is connected to the second node；
5th switching tube, control terminal are connected to the second node, and the first path terminal is connected to the first node, alternate path
End is for receiving the low level signal；
7th switching tube, control terminal are connected to the second node, and the first path terminal is connected to the same level transmitting signal output
End, alternate path end is for receiving the low level signal.
7. gate driving circuit according to claim 6, which is characterized in that the stable module further include:
4th switching tube, control terminal are connected to the same level transmitting letter for receiving the second clock signal, the first path terminal
Number output end, alternate path end is for receiving the low level signal.
8. gate driving circuit according to claim 2, which is characterized in that second output module includes:
11st switching tube, control terminal are connected to the first node, and the first path terminal is used to receive the first voltage signal,
Alternate path end is for exporting the first gate driving signal；
12nd switching tube, control terminal are connected to the first node, and the first path terminal is used to receive the second voltage signal,
Alternate path end is used to export the second grid driving signal,
Wherein, when the first voltage signal is high level, the 11st switching tube conducting, output effective described first
Gate drive signal；
When the second voltage signal is high level, the 12nd switching tube conducting exports the effective second grid
Driving signal.
9. gate driving circuit according to claim 8, which is characterized in that second pull-down module includes:
9th switching tube, control terminal receive the second clock signal, and the first path terminal is used to receive the low level signal, the
Two path terminals are connected to the alternate path end of the 11st switching tube；
Tenth switching tube, control terminal receive the second clock signal, and the first path terminal is connected to the 12nd switching tube
Alternate path end, alternate path end are used to receive the low level signal,
Wherein, when the second clock signal is effective, the 9th switching tube and the conducting of the tenth switching tube, respectively by the low electricity
Ordinary mail number is provided to the alternate path end of the 11st switching tube and the 12nd switching tube.
10. a kind of display device characterized by comprising
Gate driving circuit according to any one of claim 1 to 9, for providing multiple gate drive signals；
Data drive circuit, for providing multiple luma datas；And
Display panel, the display panel include the multiple pixel units and a plurality of grid line and a plurality of data for being arranged in array
Line,
Wherein, the display panel receives the multiple gate drive signal via a plurality of grid line, thus by row selection
The multiple pixel unit, and the multiple luma data is received by column via the multiple data lines, to be supplied to choosing
Fixed pixel unit is to realize that image is shown.
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| CN201811056150.9A CN109192154B (en) | 2018-09-11 | 2018-09-11 | Gate drive circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109979407A (en) * | 2019-04-22 | 2019-07-05 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuit, TFT substrate and display device |
| CN110264939A (en) * | 2019-06-27 | 2019-09-20 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display control method |
| CN110390903A (en) * | 2019-06-20 | 2019-10-29 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN111415623A (en) * | 2020-03-31 | 2020-07-14 | 合肥京东方显示技术有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN112908235A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN112908276A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN112927644A (en) * | 2021-02-02 | 2021-06-08 | 合肥维信诺科技有限公司 | Gate drive circuit and display panel |
| WO2023108471A1 (en) * | 2021-12-15 | 2023-06-22 | 京东方科技集团股份有限公司 | Driver circuit and display apparatus |
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| CN107622758A (en) * | 2016-07-14 | 2018-01-23 | 三星显示有限公司 | Gate driving circuit and the display device with gate driving circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109979407A (en) * | 2019-04-22 | 2019-07-05 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuit, TFT substrate and display device |
| CN110390903A (en) * | 2019-06-20 | 2019-10-29 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN110264939A (en) * | 2019-06-27 | 2019-09-20 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display control method |
| CN111415623A (en) * | 2020-03-31 | 2020-07-14 | 合肥京东方显示技术有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN111415623B (en) * | 2020-03-31 | 2021-05-14 | 合肥京东方显示技术有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN112908235A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
| CN112908276A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| CN112927644A (en) * | 2021-02-02 | 2021-06-08 | 合肥维信诺科技有限公司 | Gate drive circuit and display panel |
| CN112927644B (en) * | 2021-02-02 | 2022-08-23 | 合肥维信诺科技有限公司 | Gate drive circuit and display panel |
| WO2023108471A1 (en) * | 2021-12-15 | 2023-06-22 | 京东方科技集团股份有限公司 | Driver circuit and display apparatus |
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