KR101936678B1 - Organic Light Emitting Display Device - Google Patents

Abstract

An embodiment of the present invention is a display panel comprising: a display panel; A data driver for supplying a data signal to the display panel; And shift register blocks which are supplied with a scan signal to a display panel and are connected to receive at least three gate shift clocks among a first start voltage and a plurality of gate shift clocks and sequentially output a first pulse signal, 1: 1 to the output terminals of the shift register blocks, receives at least one of the gate control clocks of the second start voltage and the plurality of gate control clocks, delays the first pulse signal and outputs it as a second pulse signal, And a scan driver including control blocks connected to the organic light emitting display device.

Description

[0001] The present invention relates to an organic light emitting display device,

An embodiment of the present invention relates to an organic light emitting display.

An organic electroluminescent device used in an organic electroluminescent display device is a self-luminous device in which a light emitting layer is formed between two electrodes. The organic electroluminescent device injects electrons and holes from the electron injecting electrode and the hole injecting electrode into the light emitting layer, and excites the excited electrons and holes, And emits light when it is dropped to the ground state.

In the organic light emitting display, when a scan signal, a data signal, a power supply, and the like are supplied to the subpixels arranged in a matrix form, the selected subpixel emits light, thereby displaying an image.

The scan driver for supplying the scan signals to the subpixels may include a step of forming a thin film transistor mounted on the substrate in the form of an integrated circuit (IC) or forming a thin film transistor included in the subpixels, and forming a gate in panel (GIP) do.

The conventional GIP type scan driver can reduce the horizontal time (hereinafter referred to as " HT ") of outputting a scan signal if it is formed on a substrate, but can not increase it. That is, in the conventional GIP type scan driver, it is possible to change the HT only within 1 Hertz if the 1 Hertz drive is determined, and the HT can not be increased beyond that.

Therefore, in the conventional GIP type scan driver, it is required to perform a panel revision when the adjustment of the HT is required.

SUMMARY OF THE INVENTION An embodiment of the present invention for solving the problems of the background art described above forms a GIP type scan driver which can be varied to increase or decrease the horizontal time even if the layout of the panel is fixed. In addition, since the embodiment of the present invention generates a scan signal in a voltage mode rather than a clock boosting scheme, a GIP type scan driver capable of minimizing the influence of the CLK line delay (CLK load) and varying the horizontal time Panel revolution is not required even if the horizontal time is required, and the scan signal period can be changed corresponding to the sub pixels of various structures, thereby forming a GIP type scan driver which can reduce the cost in the panel design .

According to an embodiment of the present invention, there is provided a display panel comprising: a display panel; A data driver for supplying a data signal to the display panel; And shift register blocks which are supplied with a scan signal to a display panel and are connected to receive at least three gate shift clocks among a first start voltage and a plurality of gate shift clocks and sequentially output a first pulse signal, 1: 1 to the output terminals of the shift register blocks, receives at least one of the gate control clocks of the second start voltage and the plurality of gate control clocks, delays the first pulse signal and outputs it as a second pulse signal, And a scan driver including control blocks connected to the organic light emitting display device.

The scan driver delays the first pulse signal by a second start voltage spaced apart from the first start voltage by a predetermined interval to output the second pulse signal as a second pulse signal, and the second pulse signal is a pulse that the second start voltage falls from a logic high to a logic low It can be delayed until the interval.

The scan driver includes a plurality of gate shift clocks including four gate shift clocks sequentially changing from logic high to logic high from the outside and two gate control clocks having mutually opposite logic high and logic low polarities Multiple gate control clocks can be supplied as clock signals.

The shift register blocks include a first pull-down transistor that is turned on according to the voltage of the Q node to supply a first gate shift clock to the first output node to discharge the first output node, A first pull-up transistor that is turned on in response to the voltage of the QB node to supply a high potential voltage to the first output node to charge the first output node, and a second pull-up transistor that charges and discharges the Q node, And switch circuits, respectively.

The first switch circuit includes a Q node discharging circuit for discharging the Q node in response to the first start voltage or the first pulse signal of the previous shift register block and a Q node charging circuit for charging the Q node in response to the discharging voltage of the QB node. A QB node discharge circuit for discharging a QB node in response to a third gate shift clock and a QB node charge circuit for charging a QB node in response to a first pulse signal of a first start voltage or a previous shift register block can do.

The gate electrode of the Q node discharging circuit is commonly connected to the terminal to which the first start voltage is inputted and the second electrode is connected to the Q node and the gate electrode of the Q node charging circuit is connected to the QB node The first electrode is connected to the Q node, the second electrode is connected to the terminal to which the high potential voltage is input, the gate electrode of the QB node discharge circuit is connected to the terminal to which the third gate shift clock is input, The second electrode is connected to the QB node, the gate electrode of the QB node charging circuit is connected to the terminal to which the first start voltage is inputted, the first electrode is connected to the QB node and the second electrode is connected to the QB node, The gate electrode of the first pull-down transistor is connected to the Q node, the first electrode is connected to the terminal to which the first gate shift clock is input, and the second electrode is connected to the terminal to which the high voltage is input, And a first gate electrode of the pull-up transistor is coupled to the QB node, a first electrode is connected to the first output node may be connected to a terminal to which a second electrode of the input is the high potential voltage.

A second pull-down transistor that is turned on according to the voltage of the RQQ node to supply a low potential voltage to the second output node to discharge the second output node; A second pull-up transistor that is turned on in response to the voltage of the node to supply a high potential voltage to the second output node to charge the second output node; and a second switch circuit that charges and discharges the RQQ node and charges and discharges the RBB node, . ≪ / RTI >

The second switch circuit includes an RSQ node discharging circuit for discharging the RSQ node in response to the second start voltage or the third pulse signal of the previous shift register block and an RSQ node charging circuit for charging the RSQ node in response to the first pulse signal. An RQQ node discharging circuit for discharging the RQQ node in response to the first pulse signal; an RQQ node charging circuit for charging the RQQ node in response to the discharge voltage of the RSQ node; An RBB node charging circuit for charging the RBB node in response to the first pulse signal and a third pulse signal opposite to the second pulse signal output through the second output node to the third output node, And outputting the RQB node output circuit.

The gate electrode of the RSQ node discharge circuit is connected to the terminal to which the second start voltage is inputted, the first electrode is connected to the terminal to which the first gate control clock is inputted, the second electrode is connected to the RSQ node, The gate electrode of the RQQ node discharge circuit is connected to the first output terminal, the first electrode of the RQQ node discharge circuit is connected to the terminal to which the high potential voltage is inputted, the second electrode thereof is connected to the RSQ node, The first electrode is connected to the terminal to which the low potential voltage is inputted, the second electrode is connected to the RQQ node, the gate electrode of the RQQ node charging circuit is connected to the RSQ node and the first electrode is connected to the terminal to which the high potential voltage is inputted The second electrode is connected to the RQQ node, the gate electrode of the RBB node discharge circuit is connected to the RSQ node, the first electrode is connected to the terminal to which the low potential voltage is input, the second electrode is connected to the RBB node, time The gate electrode of the RQB node output circuit is connected to the RBB node, and the gate electrode of the RBB node output circuit is connected to the first output terminal, The second electrode is connected to the third output node, the gate electrode of the second pull-down transistor is connected to the RQQ node, and the first electrode is connected to the terminal to which the low potential voltage is inputted The second electrode is connected to the second output node, the gate electrode of the second pull-up transistor is connected to the RBB node, the first electrode is connected to the terminal to which the high potential voltage is inputted and the second electrode is connected to the second output node .

The RQB node output circuit may output a third pulse signal opposite to the second pulse signal output through the second output node in response to the voltage of the RBB node to transfer the voltage corresponding to the second start voltage to the next stage .

The embodiment of the present invention has an effect of forming a GIP type scan driver which can be varied so as to increase or decrease the horizontal time even if the layout of the panel is fixed. In addition, since the scan signal is generated by a voltage method other than the clock boosting method, the effect (CLK load) of the clock line delay (CLK load) can be minimized. In addition, since a GIP-type scan driver capable of varying the horizontal time is provided, it is possible to change the cycle of a scan signal in response to a sub-pixel having various structures, The cost can be reduced.

1 is a schematic block diagram of an organic light emitting display device.
2 is a block diagram of a block included in a scan driver according to an embodiment of the present invention.
3 is a circuit configuration diagram of a first shift register block and a first control block included in a scan driver according to an embodiment of the present invention.
FIG. 4 is a schematic block diagram of a scan driver according to an embodiment of the present invention; FIG.
5 is a diagram for describing operational characteristics in which a first stage outputs a second pulse signal of a gate low voltage according to an embodiment of the present invention;
FIG. 6 is a timing chart according to the operation characteristics of FIG. 5; FIG.
7 is a diagram for describing operational characteristics in which a first stage outputs a second pulse signal of a gate high voltage according to an embodiment of the present invention;
8 is a timing chart according to the operation characteristics of Fig.
9 is a timing chart for explaining that the scan driver is driven by 1HT according to an embodiment of the present invention;
10 is a timing chart for explaining that the scan driver is driven by 2HT according to another embodiment of the present invention.
11 is a waveform diagram of a scan signal output through each output node when the scan driver is driven by 2HT.
12 is a timing chart for explaining that the scan driver is driven by 5HT according to another embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting display device.

As shown in FIG. 1, the organic light emitting display includes a timing driver TCN, a display panel PNL, a scan driver SDRV, and a data driver DDRV.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a data signal RGB from the outside. The timing driver TCN is connected to the data driver DDRV and the data driver DDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit SDRV. The timing driver TCN can count the data enable signal DE in one horizontal period to determine the frame period so that the externally supplied vertical sync signal Vsync and horizontal sync signal Hsync can be omitted. The control signals generated in the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the scan driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDRV. ).

The display panel PNL includes a display unit having sub-pixels SP arranged in a matrix form. The subpixels SP may be formed as a passive matrix or an active matrix. When the subpixels SP are formed in an active matrix type, the subpixels SP may be formed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor, a driving transistor, a capacitor, and an organic light emitting diode, Or a structure in which a capacitor is further added. The subpixels SP having the above structure may be formed by a top emission method, a bottom emission method, or a dual emission method depending on the structure.

The scan driver SDRV is responsive to the gate timing control signal GDC supplied from the timing driver TCN to turn on the swing width of the gate drive voltage at which the transistors of the subpixels SP included in the display panel PNL are operable And sequentially generates a scan signal while shifting the level of the signal. The scan driver SDRV supplies the scan signals generated through the scan lines SL1 to SLm to the subpixels SP included in the display panel PNL.

The data driver DDRV samples and latches the digital data signal RGB supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN, . The data driver DDRV converts a digital data signal RGB into a gamma reference voltage and converts the digital data signal into an analog data signal. The data driver DDRV supplies the data signals converted through the data lines DL1 to DLn to the sub-pixels SP included in the display panel PNL.

Hereinafter, the configuration of the scan driver SDRV according to one embodiment of the present invention will be described in more detail.

FIG. 2 is a block diagram illustrating a configuration of blocks included in a scan driver according to an embodiment of the present invention. FIG. 3 is a block diagram of a first shift register block and a first control block included in a scan driver according to an exemplary embodiment of the present invention. FIG. 4 is a schematic block diagram of a scan driver according to an embodiment of the present invention. Referring to FIG.

As shown in FIG. 2, the scan driver receives at least three gate shift clocks among a first start voltage VST and a plurality of gate shift clocks CLK1 to CLK4, and sequentially outputs a first pulse signal And shift register blocks (SR Block) connected thereto. The scan driver is connected to the output terminals SR01 to SR04 of the shift register blocks SR01 to SR04 in a one-to-one correspondence with at least one of the second start voltage RVST and the plurality of gate control clocks RCLK1 to RCLK2. Control blocks (CN Block) that are connected to receive the gate control clocks of the plurality of gate control clocks and delay the first pulse signals and output the delayed second pulse signals.

For example, the first shift register block SR [1] receives the first start voltage VST and the first, third and fourth gate shift clocks CLK1, CLK3 and CLK4, SRO1) to output the first pulse signal. The first control block CN [1] receives the first pulse signal output through the first output node SRO1 and the second start voltage RVST and the first gate control clock RCLK1, And outputs the second pulse signal through the node OUT1.

The first shift register block SR [1] and the first control block CN [1] have such a connection relationship, and the second shift register block SR [2] and the second shift register block SR [ 2 control block (CN [2]) is connected as follows.

The second shift register block SR [2] outputs the first pulse signal output from the first output node SRO1 of the first shift register block SR [1] to the voltage corresponding to the first start voltage VST As shown in FIG. The second control block CN [2] outputs the third pulse signal output from the third output node RQB1 of the first control block CN [1] to the voltage corresponding to the second start voltage RVST To be supplied.

In this manner, the fourth shift register block SR [4] and the fourth control block CN [4] as well as the third shift register block SR [3] and the third control block CN [ A dependent connection relationship is formed up to the N-th shift register block and the N-th control block, which are not shown.

3, a first start voltage VST, a first gate shift clock CLK1, a third gate shift clock CLK3, a low potential voltage ( GVSS) and a high-potential voltage (GVDD).

The first pull-down transistor T5, the first pull-up transistor T6 and the first to third capacitors C1 to C3 are connected to the first shift register block SR [1] .

The first switch circuits T1 to T4 include a Q node discharging circuit T1, a Q node charging circuit T2, a QB node discharging circuit T3 and a QB node charging circuit T4. The Q node discharging circuit T1 turns on the QB node charging circuit T4 and discharges the Q node Q in response to the first start voltage VST. The Q node charging circuit T2 serves to charge the Q node Q in response to the discharge voltage of the QB node. The QB node discharge circuit T3 serves to discharge the QB node QB in response to the third gate shift clock signal CLK3. The QB node charging circuit T4 functions to charge the QB node QB in response to the first start voltage VST.

The first pull-down transistor T5 has a role of outputting a first pulse signal of a logic low (voltage corresponding to the first gate shift clock) through the first output node SRO1 in response to the voltage of the Q node Q do. The first pull-up transistor T6 serves to output a first pulse signal of a logic high (voltage corresponding to the high-potential voltage) through the first output node SRO1 in response to the voltage of the QB node QB.

The first and second capacitors C1 and C2 serve to hold the node's voltage at a logic low or a logic high voltage when the Q node Q and the QB node QB are electrically floating . The third capacitor C3 serves to bootstrap discharge the Q node Q. [

The connection relationship of the circuits included in the first shift register block SR [1] will now be described.

The gate electrode of the Q node discharging circuit T1 and the first electrode are connected in common to the terminal to which the first start voltage VST is input and the second electrode is connected to the Q node Q. The gate electrode of the Q node charging circuit T2 is connected to the QB node QB, the first electrode thereof is connected to the Q node Q and the second electrode is connected to the terminal to which the high potential voltage GVDD is inputted.

The gate electrode of the QB node discharge circuit T3 is connected to the terminal to which the third gate shift clock signal CLK3 is inputted and the first electrode is connected to the terminal to which the low potential voltage GVSS is inputted and the second electrode is connected to the QB node QB. The gate electrode of the QB node charging circuit T4 is connected to the terminal to which the first start voltage VST is inputted and the first electrode is connected to the QB node QB and the second electrode is connected to the high potential voltage GVDD Terminal.

The gate of the first pull-down transistor T5 is connected to the Q node Q, the first electrode of the first pull-down transistor T5 is connected to the input terminal of the first gate shift clock CLK1, . The gate electrode of the first pull-up transistor T6 is connected to the QB node QB, the first electrode thereof is connected to the first output node SRO1 and the second electrode thereof is connected to the terminal to which the high potential voltage GVDD is inputted .

One end of the first capacitor C1 is connected to the Q node Q and the other end is connected to the terminal to which the high potential voltage GVDD is inputted. One end of the second capacitor C2 is connected to the QB node QB and the other end is connected to the terminal to which the high potential voltage GVDD is inputted. One end of the third capacitor C3 is connected to the gate electrode of the first pull-down transistor T5 and the other end is connected to the first output node SRO1.

3, a second start voltage RVST, a first gate control clock RCLK1, a low voltage GVSS and a high voltage GVDD are applied to the first control block CN [1] .

The first control block CN [1] includes the second switch circuits T7 to T13, the second pull-down transistor T14, the second pull-up transistor T15 and the fourth to sixth capacitors C4 to C6 do.

The RSQ node discharge circuit T7, the RSQ node charge circuit T8, the RQQ node discharge circuit T9, the RQQ node charge circuit T10, the RBB node discharge circuit T11, and the second switch circuit T7 are connected to the second switch circuits T7 to T13, An RBB node charging circuit T12 and an RQB node output circuit T13.

The RSQ node discharge circuit T7 serves to discharge the RSQ node RSQ to reset the first pulse signal in response to the second start voltage RVST. The RSQ node charging circuit T8 functions to charge the RSQ node RSQ in response to the first pulse signal of the first output node SRO1. The RQQ node discharge circuit T9 serves to discharge the RQQ node RQQ in response to the first pulse signal of the first output node SRO1. The RQQ node charging circuit T10 functions to charge the RQQ node RQQ in response to the voltage of the RSQ node. The RBB node discharge circuit T11 serves to discharge the RBB node RBB in response to the voltage of the RSQ node so as to turn on the second pull-up transistor T15. The RBB node charging circuit T12 serves to charge the RBB node RBB in response to the first pulse signal of the first output node SRO1 to turn off the second pull-up transistor T15. The RQB node output circuit T13 outputs the second start signal RVST in response to the voltage of the RBB node RBB to transfer the second start voltage RVST to the next stage, 3 pulse signal.

The second pull-down transistor T14 serves to output a second pulse signal corresponding to the gate-low voltage through the second output node OUT1 in response to the voltage of the RQQ node RQQ. The second pull-up transistor T15 serves to output a second pulse signal corresponding to the gate high voltage through the second output node OUT1 in response to the voltage of the RBB node RBB.

The fourth and fifth capacitors C4 and C5 serve to hold the voltage of the node at a voltage of logic low or logic high when the RSQ node RSQ and the RQQ node RQQ are electrically floated. The sixth capacitor C6 serves to bootstrap the RQQ node RQQ.

The connection relationship of the circuits included in the first control block CN [1] will now be described.

The gate electrode of the RSQ node discharging circuit T7 is connected to the terminal to which the second start voltage RVST is inputted and the first electrode is connected to the terminal to which the first gate control clock RCLK1 is inputted, (RSQ). The gate electrode of the RSQ node charging circuit T8 is connected to the first output terminal SRO1, the first electrode is connected to the terminal to which the high potential voltage GVDD is input, and the second electrode is connected to the RSQ node RSQ . The gate electrode of the RQQ node discharging circuit T9 is connected to the first output terminal SRO1, the first electrode is connected to the terminal to which the low potential voltage GVSS is input, and the second electrode is connected to the RQQ node RQQ . The gate electrode of the RQQ node charging circuit T10 is connected to the RSQ node RSQ, the first electrode of the RQQ node charging circuit T10 is connected to the terminal to which the high potential voltage GVDD is input, and the second electrode thereof is connected to the RQQ node RQQ. The gate electrode of the RBB node discharge circuit T11 is connected to the RSQ node RSQ, the first electrode is connected to the terminal to which the low potential voltage GVSS is input, and the second electrode is connected to the RBB node RBB. The gate electrode of the RBB node charging circuit T12 is connected to the first output terminal SRO1, the first electrode is connected to the terminal to which the high potential voltage GVDD is input, and the second electrode is connected to the RBB node RBB . The gate electrode of the RQB node output circuit T13 is connected to the RBB node RBB and the first electrode thereof is connected to the terminal to which the high potential voltage GVDD is inputted and the second electrode thereof is connected to the third output node RQB1 .

The gate electrode of the second pull-down transistor T14 is connected to the RQQ node RQQ, the first electrode thereof is connected to the terminal to which the low potential voltage GVSS is inputted and the second electrode thereof is connected to the second output node OUT1 . The gate electrode of the second pull-up transistor T15 is connected to the RBB node RBB, the first electrode thereof is connected to the terminal to which the high potential voltage GVDD is inputted and the second electrode thereof is connected to the second output node OUT1 .

One end of the fourth capacitor C4 is connected to the RSQ node RSQ and the other end is connected to the terminal to which the high potential voltage GVDD is inputted. One end of the fifth capacitor C5 is connected to the RQQ node RQQ and the other end is connected to the terminal to which the high potential voltage GVDD is inputted. One end of the sixth capacitor C6 is connected to the RQQ node RQQ and the other end is connected to the second output node OUT1.

In the above description, the configuration and connection relationship of the first shift register block SR [1] and the first control block CN [1] have been mainly described. However, the configuration and connection relationship of the first shift register block SR [1] and the first control block CN [1] as well as other blocks are also formed as shown in FIG. 4, which are connected in series to each other through respective second output nodes OUT1 to OUT4. The first to fourth stages STG [1] to STG [4] To output the second pulse signal. Here, although only the first to fourth stages STG [1] to STG [4] are shown in the drawing, the Nth stage (N is an integer of 4 or more) is configured.

In addition, the first pulse signals output through the first output nodes SRO1 to SRO4 located at the front end receive the first start voltage. In addition, they receive the third pulse signal output through the third output nodes RQB1 to RQB4 located at the front end as the second start voltage.

In the above description, the transistor included in the first shift register block SR [1] and the first control block CN [1] is an N-type transistor. However, ≪ / RTI > The first electrode and the second electrode may be defined as a source electrode and a drain electrode, or a drain electrode and a source electrode.

Hereinafter, operation characteristics of the scan driver according to an embodiment of the present invention will be described.

5 is a view for explaining an operational characteristic in which a first stage outputs a second pulse signal of a gate low voltage according to an embodiment of the present invention, FIG. 6 is a timing chart according to the operation characteristic of FIG. 5, 7 is a view for explaining an operation characteristic in which the first stage outputs a second pulse signal of a gate high voltage according to an embodiment of the present invention, and Fig. 8 is a timing diagram according to the operation characteristics of Fig.

5 to 8, when the first start voltage VST is input to the first shift register block SR [1] and then the first gate shift clock CLK1 is input, And a first pulse signal of a logic low is outputted to the first output node SRO1.

The RQQ node discharge circuit T9 and the RBB node charge circuit T12 are turned on in accordance with the first pulse signal of the logic low inputted to the first control block CN [1]. Accordingly, the RQQ node RQQ is discharged to a logic low through the RQQ node discharge circuit T9 to turn on the second pull-down transistor T14 and the second output node OUT1 to the low potential voltage GVSS. A gate-low voltage corresponding to the gate-source voltage is output. On the other hand, the RBB node RBB is charged to a logic high via the RBB node charging circuit T12, and the second pull-up transistor T15 is turned off.

Thereafter, when the second start voltage RVST and the first gate control clock are input in synchronism with the first control block CN [1], the RQQ node charging circuit T10 and the RBB node discharging circuit T11 are turned on . Accordingly, the RBB node RBB is discharged to a logic low, the second pull-up transistor T15 is turned on, and the gate high voltage corresponding to the high-potential voltage GVDD is output to the second output node OUT1 . Alternatively, the RQQ node RQQ is charged to a logic high through the RQQ node charging circuit T10, and the second pull-down transistor T14 is turned off.

As can be seen from the above description, the scan driver according to the embodiment of the present invention is configured such that the timing of the voltage applied to the gate nodes of the second pull-down transistor T14 and the second pull-up transistor T15 is the second start voltage RVST, Lt; / RTI >

Accordingly, when the input period of the second start voltage RVST is constantly input with respect to the first start voltage VST, the second pulse signal outputted to the second output node OUT1, i.e., the horizontal time of the scan signal Time (hereinafter abbreviated as HT) can be changed at any time. In other words, since HT of the scan signal is delayed by the second start voltage (RVST) spaced apart from the first start voltage (VST) by a predetermined interval, the second pulse signal whose HT is changed by the delayed interval . At this time, the second pulse signal is delayed until the second start voltage RVST falls from logic high to logic low.

In the above description, the fourth gate shift clock CLK4 is synchronized with the first start voltage VST and has the highest input priority, and thereafter the first gate shift clock CLK1, the second gate shift clock CLK2, And the third gate shift clock CLK3 in the order of 1 Hertz. However, the input priorities of each gate shift clock may be different for each stage. In the case of the first gate control clock RCLK1, it can be synchronized with the fourth gate shift clock CLK4 in a certain period. In the case of the second gate control clock RCLK2, a first gate shift clock CLK1). However, the first gate control clock RCLK1 and the second gate control clock RCLK2 are always input with opposite polarities. In the above description, the scan driver is driven using the 4-phase gate shift clock and the 2-phase gate control clock, but the present invention is not limited thereto.

Hereinafter, the scan driver is driven by various HTs according to one embodiment of the present invention.

FIG. 9 is a timing chart for explaining that the scan driver is driven by 1 HT according to an embodiment of the present invention, FIG. 10 is a timing chart for explaining that the scan driver is driven by 2HT according to another embodiment of the present invention, FIG. 11 is a waveform diagram of a scan signal output through each output node when the scan driver is driven by 2HT, FIG. 12 is a waveform diagram of a scan driver driven by 5HT according to another embodiment of the present invention, Timing diagram.

9, when the first gate voltage VST is input to the scan driver according to the exemplary embodiment of the present invention, the first pulse signal SRO1 is generated in synchronization with the first gate shift clock, Is output. At this time, the RQQ node RQQ is discharged to the same voltage as the first pulse signal SRO1, and the RQB node RQB is charged to a voltage opposite to the first pulse signal SRO1. Since the second pulse signal OUT1 is reset when the input second start voltage RVST and the first gate control clock RCLK1 are synchronized after the first pulse signal SRO1 is output and delayed by 1HT, The pulse signal OUT1 is outputted so as to have a period of 1 Hertz.

The above description explains the driving state of the second pulse signal OUT1 outputted from the first stage by the Nth output timing (N out Timing). Thereafter, the driving state of the second pulse signal OUT1 output from the second stage by the (N + 1) th output timing (N + 1 out Timing) will also be the same as above, The pulse signal OUT1 is outputted.

According to the above description, since the second start voltage RVST is input with a separation time of 1 Hertz immediately after the first start voltage VST is inputted, the output timing of the second pulse signal OUT1 is determined to have 1 Hertz And all the stages also output the second pulse signal OUT1 so as to have a period of 1 Hertz.

As shown in FIG. 10, the scan driver according to another embodiment of the present invention receives the first start voltage VST and then receives the first pulse signal SRO1 in synchronization with the first gate shift clock, Is output. At this time, the RQQ node RQQ is discharged to the same voltage as the first pulse signal SRO1, and the RQB node RQB is charged to a voltage opposite to the first pulse signal SRO1. Since the second pulse signal OUT1 is reset when the inputted second start voltage RVST is synchronized with the first gate control clock RCLK1 after the first pulse signal SRO1 is outputted and delayed by 2HT, The pulse signal OUT1 is outputted so as to have a period of 2 Hertz.

The above description explains the driving state of the second pulse signal OUT1 outputted from the first stage by the Nth output timing (N out Timing). Thereafter, the driving state of the second pulse signal OUT2 output from the second stage by the (N + 1) th output timing (N out Timing) will also be as described above, and the second pulse signal (OUT2) is outputted.

Therefore, when the second start voltage RVST is input with the 2-second separation time with respect to the first start voltage VST, the waveform of the scan signal output through each of the output nodes OUT1 to OUT4 is sequentially Lt; / RTI >

According to the above description, since the second start voltage RVST is input with a 2-HT separation time immediately after the first start voltage VST is input, the output timing of the second pulse signal OUT1 is determined to have 2HT And all the stages also output the second pulse signal OUT1 having a period of 2HT.

12, in the scan driver according to another embodiment of the present invention, after the first start voltage VST is input, when the first gate shift clock is input, the first pulse signal SRO1 Is output. Since the second pulse signal OUT1 is reset when the input second start voltage RVST and the first gate control clock RCLK1 are synchronized after the first pulse signal SRO1 is outputted and delayed by 5HT, The pulse signal OUT1 is outputted so as to have a period of 5HT.

The above description explains the driving state of the second pulse signal OUT1 outputted from the first stage by the Nth output timing (N out Timing). Thereafter, the driving state of the second pulse signal output from the second stage by the (N + 1) th output timing will also be as described above, and a second pulse signal having a period of 5HT is also output.

According to the above description, immediately after the first start voltage VST is inputted, since the second start voltage RVST is inputted at a time interval of 5HT, the output timing of the second pulse signal OUT1 is determined to have 5HT And all the stages also output the second pulse signal OUT1 having a period of 5HT.

The organic light emitting display according to the present invention has the effect of forming a GIP type scan driver which can be varied to increase or decrease the horizontal time even if the layout of the panel is fixed. In addition, the organic light emitting display according to the present invention generates a scan signal in a voltage mode rather than a clock boosting mode, thereby minimizing the influence of a CLK line delay (CLK load). Further, since the organic light emitting display according to the present invention provides a GIP type scan driver which can vary the horizontal time, panel revision is not required even though horizontal time adjustment is required, The period of the scan signal can be changed, thereby reducing the cost of the panel design.

Meanwhile, in the exemplary embodiment of the present invention, a scan driver for driving the organic light emitting display device is described as an example, but the present invention can also be applied to other display devices such as a liquid crystal display device.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: timing driver PNL: display panel
SDRV: scan driver DDRV: data driver
SR [1]: first shift register block CN [1]: first control block
T1 to T4: first switch circuit T5: first pull-down transistor
T6: First pull-up transistor C1 to C6: First to sixth capacitors
GVSS: low potential voltage GVDD: high potential voltage
T14: second pull-down transistor T15: second pull-up transistor
STG [1] to STG [4]: First to fourth stages

Claims (10)

Display panel;
A data driver for supplying a data signal to the display panel; And
And a scan driver for supplying a scan signal to the display panel,
The scan driver may include:
A shift register block which is connected to receive at least three gate shift clocks among a first start voltage and a plurality of gate shift clocks and sequentially output a first pulse signal,
And a gate control unit for receiving the first pulse signal and receiving at least one gate control clock among a second start voltage and a plurality of gate control clocks, And control blocks which are activated to generate a second pulse signal and to which the second pulse signal is output as the scan signal,
Wherein the second pulse signal is output at a logic low level by a spacing interval between the first start voltage and the second start voltage that are spaced apart from each other by a predetermined interval and the first start voltage is changed from a logic low to a logic high, Wherein the output voltage is logically lowered from a logic high to a time when the start voltage is polled to logic low. delete The method according to claim 1,
The scan driver
The plurality of gate shift clocks including four gate shift clocks sequentially changing from logic high to logic low from the outside, and the two gate control clocks having mutually opposite logic high and logic low polarities. Wherein the gate control clocks of the plurality of pixels are supplied as clock signals. The method according to claim 1,
The shift register blocks
A first output node for outputting the first pulse signal,
A first pull-down transistor that is turned on according to the voltage of the Q node to supply a first gate shift clock to the first output node to discharge the first output node,
A first pull-up transistor that is turned on in response to a voltage of the QB node to supply a high potential voltage to the first output node to charge the first output node;
And a first switch circuit for charging and discharging the Q node and charging and discharging the QB node, respectively. 5. The method of claim 4,
Wherein the first switch circuit comprises:
A Q node discharge circuit for discharging the Q node in response to the first start voltage or the first pulse signal of the previous shift register block,
A Q node charging circuit for charging the Q node in response to a discharge voltage of the QB node;
A QB node discharge circuit for discharging the QB node in response to a third gate shift clock,
And a QB node charging circuit for charging the QB node in response to the first start voltage or the first pulse signal of the previous shift register block. 6. The method of claim 5,
The gate electrode of the Q node discharge circuit and the first electrode are commonly connected to a terminal to which the first start voltage is input and the second electrode is connected to the Q node,
A gate electrode of the Q node charging circuit is connected to the QB node, a first electrode is connected to the Q node, a second electrode is connected to a terminal to which a high potential voltage is input,
A gate electrode of the QB node discharge circuit is connected to a terminal to which the third gate shift clock is input, a first electrode is connected to a terminal to which a low potential voltage is input, a second electrode is connected to the QB node,
A gate electrode of the QB node charging circuit is connected to a terminal to which the first start voltage is inputted, a first electrode is connected to the QB node, a second electrode is connected to a terminal to which the high potential voltage is input,
A gate electrode of the first pull-down transistor is connected to the Q node, a first electrode is connected to a terminal to which the first gate shift clock is input, a second electrode is connected to the first output node,
Wherein a gate electrode of the first pull-up transistor is connected to the QB node, a first electrode is connected to the first output node, and a second electrode is connected to a terminal to which the high potential voltage is input. Device. The method according to claim 1,
The gate control clocks
A second output node for outputting the second pulse signal,
A second pull-down transistor that is turned on in response to a voltage of the RQQ node to supply a low potential voltage to the second output node to discharge the second output node;
A second pull-up transistor that is turned on in response to the voltage of the RBB node to supply a high potential voltage to the second output node to charge the second output node;
And a second switch circuit for charging and discharging the RQQ node and charging and discharging the RBB node. 8. The method of claim 7,
Wherein the second switch circuit comprises:
An RSQ node discharge circuit for discharging an RSQ node in response to the second start voltage or the third pulse signal of the previous shift register block,
An RSQ node charging circuit for charging the RSQ node in response to the first pulse signal;
An RQQ node discharge circuit for discharging the RQQ node in response to the first pulse signal;
An RQQ node charging circuit for charging the RQQ node in response to a discharge voltage of the RSQ node;
An RBB node discharge circuit for discharging the RBB node in response to a discharge voltage of the RSQ node;
An RBB node charging circuit for charging the RBB node in response to the first pulse signal;
And an RQB node output circuit for outputting the third pulse signal opposite to the second pulse signal output through the second output node to a third output node. 9. The method of claim 8,
A gate electrode of the RSQ node discharge circuit is connected to a terminal to which the second start voltage is input, a first electrode is connected to a terminal to which a first gate control clock is input, a second electrode is connected to the RSQ node,
A gate electrode of the RSQ node charging circuit is connected to a first output terminal, a first electrode is connected to a terminal to which the high potential voltage is input, a second electrode is connected to the RSQ node,
A gate electrode of the RQQ node discharge circuit is connected to the first output terminal, a first electrode is connected to a terminal to which the low potential voltage is input, a second electrode is connected to the RQQ node,
A gate electrode of the RQQ node charging circuit is connected to the RSQ node, a first electrode is connected to a terminal to which the high potential voltage is input, a second electrode is connected to the RQQ node,
A gate electrode of the RBB node discharge circuit is connected to the RSQ node, a first electrode is connected to a terminal to which the low potential voltage is input, a second electrode is connected to the RBB node,
A gate electrode of the RBB node charging circuit is connected to the first output terminal, a first electrode is connected to a terminal to which the high potential voltage is input, and a second electrode is connected to the RBB node,
A gate electrode of the RQB node output circuit is connected to the RBB node, a first electrode is connected to a terminal to which the high potential voltage is input, a second electrode is connected to the third output node,
A gate electrode of the second pull-down transistor is connected to the RQQ node, a first electrode is connected to a terminal to which the low potential voltage is input, and a second electrode is connected to the second output node,
Wherein a gate electrode of the second pull-up transistor is connected to the RBB node, a first electrode is connected to a terminal to which the high potential voltage is input, and a second electrode is connected to the second output node. Device. 10. The method of claim 9,
Wherein the RQB node output circuit is responsive to the voltage of the RBB node to transfer a voltage corresponding to the second start voltage to the next stage, and the third pulse, which is opposite to the second pulse signal output through the second output node, And outputs a signal to the organic light emitting display device.

Images