KR102307678B1 - Emitting control signal driver of display device and method of driving the same, And Organic Light Emitting Display Device - Google Patents

Abstract

The present invention provides a light emitting control signal driver and a driving method of a display device that prevents leakage current of the Q node of a buffer block and increases an initialization period to prevent screen abnormalities due to overshoot, and an organic light emitting display device it's about

Description

Emitting control signal driver of display device and method of driving the same, And Organic Light Emitting Display Device

The present invention provides a light emitting control signal driver and a driving method of a display device that prevents leakage current of the Q node of a buffer block and increases an initialization period to prevent screen abnormalities due to overshoot, and an organic light emitting display device is about

With the development of various portable electronic devices such as mobile communication terminals and notebook computers, the demand for a flat panel display device applicable thereto is gradually increasing. In response to this, flat panel display devices such as a liquid crystal display (LCD), a plasma display (PDP), and an organic light emitting diode display (OLED) are being commercialized.

Among these flat panel displays, an active matrix type organic light emitting diode display has advantages of low voltage driving, thinness, excellent viewing angle, and fast response speed.

A display panel of an organic light emitting diode display includes a plurality of pixels defined by scan lines and data lines. Each pixel is formed with an organic light emitting diode and a pixel circuit for driving the organic light emitting diode.

The pixel circuit includes a scan transistor for supplying a data voltage in response to a gate pulse of a scan line, a driving transistor for controlling the amount of current supplied to the organic light emitting diode (OLED) according to the data voltage supplied to the gate electrode, and a driving transistor for and a sampling transistor and an emission control transistor for compensating for a threshold voltage.

Since the threshold voltage of the driving transistor cannot be accurately sensed without controlling the emission of the organic light emitting diode, the emission control transistor controls the emission of the organic light emitting diode (OLED) while the sampling transistor samples the threshold voltage of the driving transistor.

1 is a diagram illustrating an emission control signal driver of an organic light emitting diode display according to the related art, and FIG. 2 is a diagram illustrating timings of a clock signal and an output signal of the emission control signal driver illustrated in FIG. 1 . 1 shows one channel 1 among a plurality of channels 1 constituting the emission control signal driver.

1 and 2 , each channel 1 of the emission control signal driver of the organic light emitting diode display according to the related art includes a shift register block 10 and a buffer block 20 . The shift register block 10 and the buffer block 20 include stages corresponding to the number of channels.

Three gate shift clocks are input to the shift register block 10 from among the four-phase gate shift clocks CLK1 to CLK4 that are shifted by a predetermined phase difference and swing between the gate high voltage VGH and the gate low voltage VGL. do. The shift register block 10 sequentially outputs the inverter clock EMG out according to the input gate shift clocks and supplies it to the buffer block 20 .

A gate high voltage VGH and a gate low voltage VGL are supplied to the buffer block 20 . The buffer block 20 receives the EMG out clock and the gate shift clock from the shift resist block 10 , generates an EM out clock, and supplies the generated EM out clock to the emission control signal line of the pixel.

The emission control signal driving unit of the organic light emitting diode display according to the related art, when the EMG out clock is high, the emission control signal EM out is in a low state, and the second of the buffer block 20 is When the gate shift clock EM CLK2 is input as high, the output of the buffer block 20 becomes high. The emission control signal driver of the organic light emitting diode display according to the prior art transmits the emission control signal EM out so that the 0 initialization period (①), the sampling period (②), and the program period (③) are all operated during one horizontal period (1H). to output Then, the light emission control signal EM out is output so that the light emitting diode emits light in the light emission period ④ after the program period ③.

Looking at the T9 transistor (Q node charging/discharging transistor) of the buffer block 20, during the light emission period (④), a voltage of -4.5V is formed at the source of the T9 transistor and a voltage of 17.9V is formed at the drain of the T9 transistor, and 22.4V is applied to the T9 transistor. High junction stress (HJS) of

Accordingly, a voltage drop occurs at the Q node due to the leakage current of the T9 transistor, and a malfunction of the output of the emission control signal EM out occurs due to the voltage drop of the Q node. In addition, since the initialization period is very short, less than one horizontal period (1H), overshoot occurs in the organic light emitting diode.

3 is a diagram for explaining a problem in which a screen defect occurs due to a light emission control signal according to the related art.

Referring to FIG. 3 , during the sampling operation of the pixels of the nth stage, since the pixels of the n-1 and n+1 stages are in the bladder, a lateral current flows to the organic light emitting diodes of the pixels of the nth stage during the program period. will flow For this reason, there is a problem in that a screen defect occurs due to overshoot.

The present invention is to solve the above problems, and it is a technical task to provide a GIP (gate in panel) type light emission control signal driver and a driving method thereof, which can prevent the voltage drop of the Q node of a buffer block. .

The present invention is to solve the above problems, and to provide a light emission control signal driver and a driving method thereof, which prevent screen abnormalities by setting an initialization period, a sampling period, and a program period during three horizontal periods (3H). do it with

The present invention has a technical problem to reduce the size of the buffer block of the light emission control signal driver.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

The light emission control signal driver of the display device according to an embodiment of the present invention receives three gate shift clocks from among the five-phase gate shift clocks swinging between a gate high voltage and a gate low voltage and outputs an inverter clock. ; and a buffer block receiving one of the four-phase gate shift clocks swinging between a gate high voltage and a gate low voltage and an inverter clock of the plurality of shift register blocks and outputting a light emission control signal; and , the buffer block includes a plurality of stages, and the output terminal of the stage of the previous stage is connected to the source of the Q node charge/discharge transistor of the stage of the next stage.

A method of driving a light emission control signal driver according to an embodiment of the present invention includes: receiving three gate shift clocks from among five-phase gate shift clocks swinging between a gate high voltage and a gate low voltage and outputting an inverter clock; and receiving one of the four-phase gate shift clocks swinging between a gate high voltage and a gate low voltage and an inverter clock of the plurality of shift register blocks and outputting a light emission control signal, wherein the The summing of the initialization period and the sampling period of the emission control signal is maintained for 2 horizontal cycle times, and the program period is maintained for 1 horizontal cycle time.

In an organic light emitting display device according to an embodiment of the present invention, an organic light emitting diode is disposed in a plurality of pixels, and a scan transistor, a sampling transistor, an emission control transistor, a driving transistor, and a storage capacitor for emitting light of the organic light emitting diode are provided. a display panel disposed on a plurality of pixels; and a light emission control signal driver supplying a light emission control signal to the light emission control transistor, wherein the light emission control signal driver includes a gate shift of three of the five-phase gate shift clocks swinging between a gate high voltage and a gate low voltage. A shift register block receiving a clock input and outputting an inverter clock, one gate shift clock among the four-phase gate shift clocks swinging between a gate high voltage and a gate low voltage, and inverter clocks of the plurality of shift register blocks are input and a buffer block for receiving and outputting a light emission control signal, wherein the buffer block includes a plurality of stages, and an output terminal of a stage of a previous stage is connected to a source of a Q node charge/discharge transistor of a stage of a next stage.

The emission control signal driver according to an embodiment of the present invention may prevent a voltage drop of the Q node of the buffer block.

The light emission control signal driver according to an embodiment of the present invention can prevent screen abnormalities by allowing the initialization period, the sampling period, and the program period to be formed during three horizontal periods 3H.

The light emission control signal driver according to an embodiment of the present invention can reduce the number of transistors constituting the buffer block, thereby reducing the size of the buffer block. When the emission control signal driver is disposed on the substrate of the organic light emitting display device in the GIP method, the size of the buffer block may be reduced to realize a narrow bezel.

In addition, other features and advantages of the present invention may be newly recognized through embodiments of the present invention.

1 is a diagram illustrating a light emission control signal driver of an organic light emitting display device according to the related art.
FIG. 2 is a diagram illustrating timings of a clock signal and an output signal of the emission control signal driver shown in FIG. 1 .
3 is a diagram for explaining a problem in which a screen defect occurs due to a light emission control signal according to the related art.
4 is a diagram illustrating a pixel of an organic light emitting display device to which a light emission control signal of the present invention is applied.
5 is a diagram schematically illustrating a light emission control signal driver of a display device according to an exemplary embodiment of the present invention.
FIG. 6 is a diagram illustrating timings of a shifter register block and a gate shift clock of the emission control signal driver shown in FIG. 5 and an output signal.
FIG. 7 is a diagram illustrating timings of a buffer block and a gate shift clock of the emission control signal driver shown in FIG. 5 and an output signal.
8 is a diagram illustrating a light emission control signal output from a light emission control signal driver of the present invention.
9 is a diagram illustrating a buffer block of a light emission control signal driver of a display device according to another embodiment of the present invention.
10 is a diagram illustrating a buffer block of a light emission control signal driver of a display device according to another embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

It should be noted that in the present specification, in adding reference numbers to the components of each drawing, the same numbers are used for the same components, even if they are indicated on different drawings, as much as possible.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

The term 'at least one' should be understood to include all possible combinations from one or more related items. For example, the meaning of 'at least one of the first item, the second item and the third item' means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item and the third item. It means a combination of all items that can be presented from more than one.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

4 is a diagram illustrating a pixel of an organic light emitting display device to which a light emission control signal of the present invention is applied. 4 illustrates one pixel among a plurality of pixels formed in an organic light emitting diode display.

Referring to FIG. 4 , each of the plurality of pixels formed in the display panel includes an organic light emitting diode (OLED) and a pixel circuit (PC) for emitting light from the organic light emitting diode (OLED).

A data line for supplying a data voltage Data or a reference voltage Vref to the pixel circuit PC, a scan line for supplying a scan signal scan1, and a sampling signal scan2 Each pixel area is formed by a sampling signal line for supplying the emission control signal, an emission control signal line (EM line) for supplying the emission control signal, a driving power line for supplying driving power, and an initialization signal line (INI line) to which an initialization signal is applied. This is defined

Each of the pixel circuits PC formed in the plurality of pixels includes a scan transistor T1 , a sampling transistor T2 , an emission control transistor T3 , a driving transistor DT, and a storage capacitor Cstg.

The pixel circuit PC is divided into an initialization period (①), a sampling period (②), a program period (③), and a light emission period (④) to control light emission of the organic light emitting diode.

The initialization period (①) initializes the gate node and the source node of the driving transistor DT, and the emission control signal EM of the emission control signal driver is turned off.

The sampling period (②) senses the threshold voltage Vth of the driving transistor DT, and the voltage at the source node of the driving transistor reaches the difference value Vref-Vth between the reference voltage Vref and the threshold voltage Vth. and the light emission control signal EM of the light emission control signal driver is turned on.

In the program period (③), a data voltage is input to the pixel circuit PC, and the Vgs voltage of the driving transistor DT is set by the storage capacitor Cstg and the Coled capacitor. At this time, the emission control signal EM of the emission control signal driver is turned off.

In the light emission period (4), the organic light emitting diode (OLED) emits light by the Vgs voltage of the driving transistor DT, and the light emission control signal EM of the light emission control signal driver is turned on.

When the scan signal scan1 is supplied to the scan transistor T1, the driving TFT D-TFT is turned on, and when the emission control signal EM is supplied to the emission control transistor T3, the VDD voltage changes to the driving TFT (D- TFT) to emit light from the organic light emitting diode (OLED). As such, the pixel circuit PC of the organic light emitting display controls the light emission of the organic light emitting diode OLED using the light emission control signal EM.

5 is a diagram schematically illustrating a light emission control signal driver of a display device according to an exemplary embodiment of the present invention. 5 illustrates one channel among a plurality of channels constituting the emission control signal driver 100 .

Referring to FIG. 5 , each stage of the emission control signal driver 100 includes a shift register block 110 and a buffer block 120 . The shift register block 110 and the buffer block 120 include stages corresponding to the number of channels.

In each stage of the shift register block 110, three gate shifts are made among the five-phase gate shift clocks CLK1 to CLK5 that are shifted by a predetermined phase difference and swing between the gate high voltage VGH and the gate low voltage VGL. clock is input. The five-phase gate shift clocks CLK1 to CLK5 are sequentially shifted from the first gate shift clock CLK1 to the fifth gate shift clock CLK5 at regular intervals.

For example, first, third, and fifth gate shift clocks CLK1 , CLK3 , and CLK5 may be input to the first stage of the shift register block 110 . The first, second, and fourth gate shift clocks CLK1 , CLK2 , and CLK4 may be input to the second stage of the shift register block 110 . The second, third, and fifth gate shift clocks CLK2 , CLK3 , and CLK5 may be input to the third stage of the shift register block 110 . In addition, the first, third, and fourth gate shift clocks CLK1 , CLK3 , and CLK4 may be input to the fourth stage of the shift register block 110 .

The shift register block 110 generates an inverter clock EMG out according to the input gate shift clocks, and supplies the inverter clock EMG out to the buffer block 120 .

In each stage of the buffer block 120 , one gate shift clock is shifted by a predetermined phase difference and among the four-phase gate shift clocks CLK1 to CLK4 swinging between the gate high voltage VGH and the gate low voltage VGL. and an inverter clock EMG out from the shift resist block 110 is input. In this case, the inverter clock EMG out of the nth stage of the shift register block 110 is supplied to the nth stage of the buffer block 120 .

In addition, the EM start signal VST signal is input to the first stage of the buffer block 120 , and the output signal (emission control signal) of the previous stage is input to the remaining stages except for the first stage. For example, the output signal of the first stage is input to the source of the T9 transistor T9 which is the Q node charge/discharge transistor of the second stage.

When designing the layout of the circuit constituting the buffer block 120, by connecting the emission control signal output terminal of the first stage and the source terminal of the T9 transistor of the second stage, the output of the remaining stages except for the first stage The terminal is connected to the source of the T9 transistor of the next stage.

The output terminal of the n-1th stage is connected to the source of the T9 transistor (Q node charging and discharging transistor) of the nth stage, and the output terminal of the nth stage is connected to the T9 transistor (Q node charging and discharging) of the n+1th stage. transistor) is connected to the source.

In this way, until the last stage, the output terminal of the previous stage is connected with the source of the T9 transistor (Q-node charging and discharging transistor) of the next stage.

FIG. 6 is a diagram illustrating timings of a shifter register block and a gate shift clock of the emission control signal driver shown in FIG. 5 and an output signal. 6 illustrates an nth stage among a plurality of stages constituting the shifter register block 110 .

Referring to FIG. 6 , each stage of the shifter register block 110 generates and outputs an inverter clock EMG out according to input gate shift clocks, a plurality of transistors T1 to T8 and TA and a plurality of capacitors. (CB, CQ, CQB). The plurality of transistors T1 to T8 and TA may be implemented as an N-type MOS-FET or a P-type MOS-FET.

In the n-th stage of the shifter resistor block 110 , three gates are shifted by a predetermined phase difference and among the five-phase gate shift clocks CLK1 to CLK5 swinging between the gate high voltage VGH and the gate low voltage VGL. Shift clocks are input.

For example, the first gate shift clock CLK1 , the third gate shift clock CLK3 , and the fifth gate shift clock CLK5 are input to the nth stage of the shifter register block 110 shown in FIG. 6 .

A gate high voltage VGH and a gate low voltage VGL are supplied to each stage of the shifter resistor block 110 . The gate high voltage VGH is set to a voltage higher than the threshold voltage of the plurality of transistors T1 to T8 and TA, and the gate low voltage VGL is set to a voltage lower than the absolute value of the threshold voltages of the transistors. The gate high voltage VGH may be set to about 20V, and the gate low voltage VGL may be set to about -5V.

However, the present invention is not limited thereto, and the gate high voltage VGH is set to a voltage lower than the threshold voltage of the plurality of transistors T1 to T8 and TA, and the gate low voltage VGL is higher than the absolute value of the threshold voltages of the transistors. It can also be set to voltage.

A start voltage VST is input to a start terminal start. This start voltage VST is input to the gate of the first transistor T1 . The gate high voltage VGH is input to the source of the first transistor T1 , and the drain of the first transistor T1 is connected to the source of the second transistor T2 .

The fifth gate shift clock CLK5 is input to the gate of the second transistor T2 , and the drain of the second transistor is connected to the Q node.

The gate of the third transistor T3 is connected to the QB node, and the source of the third transistor T3 is connected to the gate low voltage VGL terminal. The drain of the third transistor T3 is connected to the gate of the eighth transistor T8.

The third gate shift clock CLK3 is input to the gate of the fourth transistor T4 , and the gate high voltage VGH is input to the source of the fourth transistor T4 . The drain of the fourth transistor T4 is connected to the drain of the fifth transistor T5 .

A start voltage VST is input to the gate of the fifth transistor T5 , and the source of the fifth transistor T5 is connected to a gate low voltage VGL terminal. The fifth transistor T5 is turned on by the start voltage VST to maintain the QB node at the gate low voltage VGL.

The gate of the sixth transistor T6 is connected to the QB node, and the first gate shift clock CLK1 is input to the source of the sixth transistor T6 . The drain of the sixth transistor T6 is connected to the output terminal. When the first gate shift clock CLK1 is input to the sixth transistor T6 , the voltage of the Q node is boosted to output the high voltage inverter clock EMG out to the buffer block.

The eighth transistor T8 is turned on by the output of the stabilization transistor TA to maintain the gate low voltage VGL of the voltage of the QB node.

The gate of the seventh transistor T7 is connected to the QB node, and the drain of the seventh transistor T7 is connected to the output terminal. The source of the seventh transistor T7 is connected to the gate low voltage VGL terminal. The voltage of the output terminal is decreased to the gate low voltage VGL by the sixth transistor T6. The seventh transistor is turned on when the voltage of the QB node is high to maintain the voltage of the output terminal as the gate low voltage VGL.

FIG. 7 is a diagram illustrating timings of a buffer block and a gate shift clock of the emission control signal driver shown in FIG. 5 and an output signal. 7 illustrates an nth stage among a plurality of stages constituting the buffer block 120 .

Each stage constituting the buffer block 120 includes a plurality of transistors T9 to T13 and a capacitor CB, and the plurality of transistors T9 to T13 is implemented as an N-type MOS-FET or a P-type MOS-FET. can be

A gate high voltage VGH and a gate low voltage VGL are supplied to the nth stage of the buffer block 120 . In addition, the inverter clock EMG out, which is an output signal of the stage of the shifter register block 110 , is supplied to the stage of the buffer block 120 . For example, the EMG out(n) clock, which is an output signal of the n-th stage of the shifter register block 110 , is supplied to the n-th stage of the buffer block 120 .

In addition, in each stage of the buffer block 120 , one gate is shifted by a predetermined phase difference and among the four-phase gate shift clocks CLK1 to CLK4 swinging between the gate high voltage VGH and the gate low voltage VGL. A shift clock is input. 7 illustrates that the second gate shift clock EM CLK2 is input to the nth stage.

An EM start signal (VST) signal is input to a first stage of the buffer block 120 , and an output signal (emission control signal) of a previous stage is input to the remaining stages except for the first stage. For example, the output signal of the n-1 th stage is input to the source of the ninth transistor T9 of the n th stage. The gate of the ninth transistor T9 is connected to the QB node, and the drain of the ninth transistor T9 is connected to the Q node. Here, the ninth transistor T9 is a switching transistor for charging or discharging the Q node. That is, the ninth transistor T9 is turned on by the voltage of the QB node to charge or discharge the voltage of the QB node.

The EMG out(n) clock of the nth stage of the shift register block 110 is applied to the gate of the ninth transistor T9 of the nth stage of the buffer block 120 to discharge the Q node. When the EMG out(n) clock of the nth stage of the shift register block 110 is not input, the ninth transistor T9 of the nth stage of the buffer block 120 does not operate, so that the Q node is charged. That is, when the EMG out of the shift register block 110 is high, the Q node of the buffer block 120 is discharged, and on the contrary, when the EMG out is low, the Q node of the buffer block 120 is charged. do.

The gate of the tenth transistor T10 is connected to the Q node, and the source of the tenth transistor is connected to the gate high voltage (VGH) terminal. The drain of the tenth transistor is connected to the output terminal. The tenth transistor T10 is a pull-up transistor and is turned on by the voltage of the Q node to output the gate high voltage VGH as the emission control signal EM out. The emission control signal EM out is applied to the emission control signal line of each pixel.

The eleventh transistors T11a and T11b are pull-down transistors, and two transistors are connected in series. The eleventh transistors T11a and T11b are turned on by the voltage of the QB node to drop the voltage of the output terminal to the gate low voltage VGH. The pull-down transistor is vulnerable to deterioration by maintaining the on state for a long time, and thus, two transistors are arranged in series to reduce deterioration.

The twelfth transistor T12 is a Q node charging transistor. The second gate shift clock EM CLK2 is input to the gate of the twelfth transistor T12 , and the gate high voltage VGH is input to the source of the twelfth transistor T12 . The drain of the twelfth transistor T12 is connected to the Q node. The twelfth transistor T12 is turned on by one of the four-phase gate shift clocks CLK1 to CLK4 to charge the Q node to the gate high voltage VGH. 7 illustrates an example of charging the Q node by inputting the second gate shift clock EM CLK2 to the twelfth transistor T12 of the nth stage.

The thirteenth transistor T13 is a stabilization transistor. The gate of the thirteenth transistor T13 is connected to the output terminal, the source of the thirteenth transistor T13 is connected to the gate high voltage (VGH) terminal, and the drain of the thirteenth transistor T13 is the first pull-down transistor. It is connected to a node between the source electrode of T11a and the drain of the second pull-down transistor T11b. The thirteenth transistor T13 is turned on by the gate high voltage VGH of the output terminal to maintain the node between the source electrode of the T11 transistor and the drain of the T11b transistor at the gate high voltage VGH.

Here, the outputs of the stages of the buffer block are determined by the on-off of the pull-up transistor T10 and the pull-down transistors T11a and T11b to determine the output of the gate high voltage VGH and the gate low voltage VGL. . Accordingly, when the EMG out clock of the stages of the shift register block is high, the emission control signal EM out of the stages of the buffer block is maintained low.

Each stage of the buffer block 120 including this configuration allows the initialization period (①), the sampling period (②), and the program period (③) to be driven for a time of three horizontal periods (3H), The light emission control signal EM is output to become the light emission period (4) after the program period (3).

8 is a diagram illustrating a light emission control signal output from a light emission control signal driver of the present invention.

Referring to FIG. 8 , the light emission control signal EM is output so that the initialization period ① is the longest among the three horizontal periods 3H. At this time, the light emission control signal EM out is output so that the time of the initialization period (①) is longer than the sum of the sampling period (②) and the program period (③).

Looking at the emission control signal EM out, the first high signal of the emission control signal EM out during one frame period is the driving transistor ( DT) is used as a signal for sensing the threshold voltage (Vth). Subsequently, the second high signal of the emission control signal EM out is used as a signal for actually emitting the organic light emitting diode OLED by applying the voltage VDD to the driving transistor DT during the emission period ④.

Here, the light emission control signal EM is output so that the initialization period (①) has the longest time of two horizontal periods, the program period (③) is the second longest, and the sampling period (②) has the shortest time. The program period (3) is a time of one horizontal period.

That is, the initialization period (①) and the sampling period (②) of the emission control signal are combined and maintained for 2 horizontal cycle times, and the program period (③) is maintained for 1 horizontal cycle time.

Again, looking at the ninth transistor T9 shown in FIG. 7 , since the output voltage of the previous stage is supplied to the source of the ninth transistor T9, a voltage of 12.5V is applied to the source of the T9 transistor during the light emission period ④; A voltage of 17.9V is formed at the drain and -4.5V at the gate.

In the prior art, a negative voltage of -4.5V was applied to the source of the T9 transistor, but in the present invention, a positive voltage of 12.5V is applied to the source of the T9 transistor.

In the previous description, it has been described that a voltage of 12.5V is applied to the source of the T9 transistor, but the present invention is not limited thereto, and the voltage applied to the source of the T9 transistor is determined according to the voltage output from the stage of the buffer block.

Accordingly, a voltage difference of 5.4V is formed between the source and drain of the T9 transistor, so that there is no high junction stress (HJS) and no leakage current as in the prior art.

Since there is no leakage current of the T9 transistor, the voltage drop of the Q node does not occur and the emission control signal EM out is normally output. That is, a malfunction of the output of the emission control signal EM out due to the voltage drop of the Q node does not occur.

In addition, the initialization period (①) and the sampling period (②) are combined and maintained for a time of two horizontal periods (2H). At this time, the sampling period (②) is very short, several us. Accordingly, it is possible to initialize each pixel by maintaining the initialization period (①) for most of the time of the two horizontal periods (2H) minus the sampling period (②). Through this, it is possible to reduce the effect of light emission of other pixels vertically adjacent to each other before the light emission period (④).

Here, in order to prevent the threshold voltage (Vth) of the T9 transistor from being shifted positively, the stress condition of the T9 transistor may be changed to Negative Bias Temperature Stress (NBTS).

9 is a diagram illustrating a buffer block of a light emission control signal driver of a display device according to another exemplary embodiment of the present invention. 9 illustrates an nth stage among a plurality of stages constituting the buffer block 130 .

Referring to FIG. 9 , each stage of the buffer block 130 of the light emission control signal driver of the display device according to another embodiment of the present invention is connected to the second pull-down transistor T11b among the two pull-down transistors T11 and T11b. Except that the structure is changed, other configurations are the same as those of the embodiment described with reference to FIG. 7 . Accordingly, detailed descriptions of the above-described components will be omitted.

The gate of the first pull-down transistor T11a is connected to the QB node, and the source is connected to the drain of the second pull-down transistor T11b. A drain of the first pull-down transistor T11a is connected to an output terminal.

The gate of the second pull-down transistor T11b is connected to the QB node, and the drain thereof is connected to the source of the first pull-down transistor T11a. The source of the second pull-down transistor T11b is connected to the output terminal of the previous stage. That is, the output signal EM out (n-1) of the n-1 th stage is applied to the source of the second pull-down transistor T11b of the n th stage of the buffer block 130 .

Similarly to the ninth transistor T9, when the output signal EM out of the previous stage is applied to the source of the second pull-down transistor T11b, the output of the stage is reduced in the sampling period (②) and the light emission period (④). When it is high, it is possible to prevent leakage currents of the first pull-down transistor T11a and the second pull-down transistor T11b from occurring.

10 is a diagram illustrating a buffer block of a light emission control signal driver of a display device according to another embodiment of the present invention. 10 illustrates an nth stage among a plurality of stages constituting the buffer block 140 .

Referring to FIG. 10 , in each stage of the buffer block 130 of the light emission control signal driver of the display device according to another embodiment of the present invention, the configuration of the pull-down transistor T11 is changed, and the thirteenth transistor T13 is formed. Except for not disposing, other configurations are the same as those of the embodiment described with reference to FIG. 7 . Accordingly, detailed descriptions of the above-described components will be omitted.

A pull-down transistor T11a is constituted by one transistor. The gate of the pull-down transistor T11a is connected to the QB node, and the drain is connected to the output terminal. The source of the pull-down transistor T11a is connected to the output terminal of the stage of the previous stage. That is, the n-th stage output signal EM out (n-1) is applied to the source of the n-th stage pull-down transistor T11a of the buffer block 140 .

When the output signal EM out of the previous stage is applied to the source of the pull-down transistor T11a in the same manner as the ninth transistor T9, the output of the stage is high ( high), it is possible to prevent a leakage current of the pull-down transistor T11a from occurring.

In the embodiment with reference to FIG. 7 , a transistor T13 for maintaining a node between the source electrode of the first pull-down transistor T11a and the drain of the second pull-down transistor T11b at the gate high voltage VGH is disposed.

On the other hand, in another embodiment with reference to FIG. 10 , the output signal EM out of the previous stage is applied to the source of the first pull-down transistor T11a. Through this, the leakage current of the pull-down transistor T11a is prevented from occurring without disposing the T13 transistor.

Through this, the size of the buffer block 140 may be reduced by reducing the number of transistors constituting the buffer block 140 . When the light emission control signal driver is disposed on the substrate of the organic light emitting diode display in the GIP method, reducing the size of the buffer block 140 has an advantageous effect in realizing the narrow bezel.

Those skilled in the art to which the present invention pertains will be able to understand that the above-described present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: light emission control signal driver
110: shift register block
120, 130, 140: buffer block

Claims (16)

a shift register block receiving three gate shift clocks from among five gate shift clocks swinging between a gate high voltage and a gate low voltage and outputting an inverter clock; and
a buffer block receiving one gate shift clock among the four-phase gate shift clocks swinging between the gate high voltage and the gate low voltage and the inverter clock of the shift register block and outputting a light emission control signal;
The buffer block includes a plurality of stages, and the output terminal of the previous stage is connected to the source of the Q node charge/discharge transistor of the next stage. According to claim 1,
A light emission control signal driver of a display device that supplies a positive voltage to a source of a Q node charge/discharge transistor during an emission period of pixels to which the emission control signal is applied. According to claim 1,
a pull-down transistor connected to an output terminal of each of the plurality of stages of the buffer block;
A gate of the pull-down transistor is connected to a QB node, a drain is connected to an output terminal of a current stage, and a source is connected to an output terminal of the previous stage. 4. The method of claim 3,
A light emission control signal driver of a display device in which a source of a Q-node charge/discharge transistor and a source of the pull-down transistor are connected. According to claim 1,
A light emission control signal driver configured to maintain the sum of the initialization period and the sampling period of the light emission control signal for two horizontal cycle times, and maintain the program period for one horizontal cycle time. receiving three gate shift clocks from among five gate shift clocks swinging between a gate high voltage and a gate low voltage and outputting an inverter clock;
Comprising: receiving one of the gate shift clocks of the four phase gate shift clocks swinging between the gate high voltage and the gate low voltage and the inverter clock and outputting a light emission control signal;
A method of driving a light emission control signal driving unit for maintaining a total of the initialization period and the sampling period of the light emission control signal for 2 horizontal cycle times and maintaining the program period for 1 horizontal cycle time. 7. The method of claim 6,
The buffer block for outputting the light emission control signal includes a plurality of stages,
The step of outputting the light emission control signal comprises:
A method of driving a light emission control signal driver comprising the step of applying an output signal of a stage of a previous stage to a source of a Q node charge/discharge transistor of a stage of a next stage. 8. The method of claim 7,
and supplying a positive voltage to the source of the Q node charge/discharge transistor of the next stage during the emission period of the pixels to which the emission control signal output from the stage of the previous stage is applied. driving method. 8. The method of claim 7,
In the step of outputting the light emission control signal,
and applying the output signal of the previous stage to the source of the pull-down transistor of the next stage. a display panel in which an organic light emitting diode is disposed in a plurality of pixels, and a light emission control transistor and a driving transistor for emitting light of the organic light emitting diode are disposed in the plurality of pixels; and
a light emission control signal driver supplying a light emission control signal to the light emission control transistor;
The light emission control signal driving unit,
a shift register block that receives three gate shift clocks from among the five phase gate shift clocks swinging between a gate high voltage and a gate low voltage and outputs an inverter clock;
a buffer block receiving one of the gate shift clocks of four phases swinging between a gate high voltage and a gate low voltage and an inverter clock of the shift register block and outputting a light emission control signal;
The buffer block includes a plurality of stages, and an output terminal of a previous stage is connected to a source of a Q node charge/discharge transistor of a next stage. 11. The method of claim 10,
A plurality of stages,
a Q node charging transistor that is turned on by one of the four-phase gate shift clocks to charge the Q node to a gate high voltage;
a pull-up transistor turned on by the voltage of the Q node and outputting a light emission control signal of the gate high voltage to an output terminal;
a first pull-down transistor that is turned on by the voltage of the QB node to drop the voltage of the output terminal to a gate low voltage; and
and the Q-node charge/discharge transistor. 12. The method of claim 11,
The Q node charge/discharge transistor is turned on by the voltage of the QB node to charge or discharge the voltage of the Q node. 12. The method of claim 11,
A gate of the first pull-down transistor is connected to the QB node, a drain is connected to the output terminal, and a source is connected to an output terminal of a stage of the previous stage. 12. The method of claim 11,
a second pull-down transistor connected in series with the first pull-down transistor;
A gate of the second pull-down transistor is connected to the QB node, a drain is connected to a source of the first pull-down transistor T11a, and a source is connected to an output terminal of the previous stage. . 15. The method of claim 14,
a stabilization transistor for maintaining a first node between the source of the first pull-down transistor and the drain of the second pull-down transistor at the gate high voltage;
A gate of the stabilization transistor is connected to the output terminal, a source is connected to a gate high voltage terminal, and a drain is connected to the first node. 12. The method of claim 11,
An organic light emitting diode display for maintaining a total of an initialization period and a sampling period of the emission control signals output from the plurality of stages for 2 horizontal cycle times, and maintaining a program period for 1 horizontal cycle time.

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