KR20180095773A - Gate driving circuit and display dedvice using the same - Google Patents

Abstract

A gate driving circuit implementing a narrow bezel comprises: a scan control signal output circuit outputting a scan control signal; a light emission control signal output circuit outputting a light emission control signal different from the scan control signal; and a logic circuit between the scan control signal output circuit and the light emission control signal output circuit. The scan control signal output circuit and the light emission control signal output circuit provides a gate driving circuit sharing one Q node and one QB node through the logic circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driving circuit,

 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit and a display device using the same, and more particularly, to a gate driving circuit which outputs a scan control signal and a light emission control signal in a single circuit, will be.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of a display device such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a micro light emitting diode (micro LED) .

In addition, there is an increasing demand for a display device having enhanced design aspects such as a smart watch, a tile-type display device, and a seamless display device.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, can supply a scan signal, a data signal, or the like to subpixels included in a display panel, have.

Such a display apparatus includes a display panel including a plurality of sub-pixels and a driver for driving the display panel. The driver includes a gate driver circuit for supplying a scan control signal to the display panel, and a data driver for supplying a data signal to the display panel.

The gate driver circuit for outputting the scan control signal may include not only an integrated circuit type but also a thin film transistor process and a built-in display panel formed on a display panel in a gate in panel (GIP) form.

The gate drive circuit in the form of a gate-in panel is supplied with a clock signal from an external device, receives a shift register circuit for generating a sequential scan control signal based on the clock signal, and an output signal and a clock signal from the shift register circuit. And an inverter circuit for generating a control signal.

However, the gate drive circuit of the gate-in-panel type proposed in the related art is difficult to implement Narrow Bezel due to the complexity and layout limitations of the shift register circuit and the inverter circuit, and its improvement is required.

The present invention for solving the above-described problems of the background art can reduce the non-display area (NA) to enable narrow bezel implementation and to secure a design margin.

Accordingly, a problem to be solved by the present invention is to provide a gate driving circuit which can realize a narrow bezel by integrating a scan control signal output circuit (or a shift register circuit) and a light emission control signal output circuit (or inverter circuit) And a display device.

The present invention provides a gate drive circuit including a plurality of stages. (N is a positive integer) stage of the plurality of stages is connected to the first start signal stage and the first clock signal stage and includes a first circuit for controlling the first node and the second node, A third circuit connected to the second node and the third node for controlling the fourth node and the fifth node, and a third circuit connected to the third node and the fourth node for outputting the light emission control signal to the first output terminal, And a fourth circuit for outputting a scan control signal to the second output terminal. The gate driving circuit of the present invention is characterized in that it can simultaneously output the emission control signal and the scan control signal.

In another aspect, the present invention provides a gate driving circuit incorporating a scan control signal control circuit for outputting a scan control signal through a first output terminal and a light emission control signal control circuit for outputting a light emission control signal through a second output terminal. During a period in which the emission control signal output circuit outputs the emission control signal to the first voltage, the scan control signal output circuit controls the scan control signal to be output to the second voltage higher than the first voltage for a specific period.

In another aspect, the present invention provides a display device including a display portion having pixels, a non-display portion adjacent to the display portion, and a circuit portion in a non-display portion and outputting control signals related to the operation of the pixels. The circuit unit has a structure in which a scan control signal output circuit and a light emission control signal output circuit are integrated, and has a feature in which the area of the non-display area is reduced compared with a display device having no integrated circuit part.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The present invention can integrate the scan control signal output circuit and the emission control signal output circuit so that the scan control signal and the emission control signal are output from a single circuit, thereby reducing the area occupied by the gate drive circuit.

The present invention has the effect of varying the pulse width of the emission control signal by adding a logic circuit to the gate drive circuit.

The present invention has an effect of not only realizing a narrow bezel by reducing a non-display area (NA) but also securing a design margin.

1 is a schematic block diagram of a display device.
FIG. 2 is a diagram illustrating a configuration of a subpixel shown in FIG. 1. FIG.
3 is a block diagram showing a part of a conventional gate driving circuit.
4 is a block diagram showing a part of a gate driving circuit according to an embodiment of the present invention.
5A and 5B are diagrams for explaining pulse width variable driving.
6 is a circuit configuration diagram of an integrated output circuit according to an embodiment of the present invention.
7 is an input / output waveform diagram of an integrated output circuit according to an embodiment of the present invention.
8 is a circuit configuration diagram of an integrated output circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Brief Description of the Drawings The advantages and features of the present disclosure, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shape, size, number and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise. In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display device according to the present invention is implemented as a television, a set-top box, a navigation device, a video player, a Blu-ray player, a personal computer (PC), a home theater, a mobile phone, The display device may be selected from a liquid crystal display device, an organic light emitting display device, a quantum dot display device, an electrophoretic display device, a plasma display device, a flat panel display device, a flexible display device, Do not.

Hereinafter, an organic electroluminescent display device will be described as an example for convenience of explanation. In addition, the transistor described below may be referred to as a source electrode, a drain electrode, a drain electrode, and a source electrode, depending on the type except for the gate electrode, but the first electrode and the second electrode are not limited thereto.

Fig. 1 is a schematic block diagram of a display device, and Fig. 2 is an exemplary configuration diagram of subpixels shown in Fig.

As shown in FIG. 1, a display device includes a display panel 100, a timing controller 110, a data driver 120, and gate drive circuits 130, 140A, and 140B. The gate driver circuit may be referred to as a gate driver or a scan driver.

The display panel 100 includes sub-pixels connected to the data lines DL and the scan lines GL which cross each other.

The display panel 100 includes a display area AA in which subpixels are formed and a non-display area LNA in which a driving circuit for driving various signal lines or subpixels is disposed outside the display area AA .

2, a pixel circuit PC connected to the scan control signal lines SRO1 and SRO2, the emission control signal lines EMO1 and EMO2 and the data line DL1 is connected to one subpixel SP . The pixel circuit PC shown in FIG. 2 receives a plurality of scan control signals and a plurality of emission control signals. However, depending on the type of the pixel circuit PC, one scan control signal or one emission control signal As shown in FIG.

The pixel circuit PC of the subpixel SP may include a plurality of transistors and one or more capacitors, and various types of compensation circuits may be further added.

1, the timing controller 110 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to an image board. The timing controller 110 outputs timing control signals for controlling the operation timings of the data driver 120 and the gate driver circuits 130, 140A, and 140B based on the input timing signals.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with the data signal DATA and the source timing control signal DDC from the timing controller 110. The source driver ICs convert the data signal DATA from a digital signal into an analog signal in response to the source timing control signal DDC and supply it through the data lines DL of the display panel 100. [ The source drive ICs are connected to the data lines DL of the display panel 100 by a process such as a COG (Chip on Glass) process or a TAB (Tape Automated Bonding) process.

The gate drive circuits 130, 140A and 140B include a level shifter circuit 130 and signal output circuits 140A and 140B. The level shifter circuit 130 may be formed on an external substrate connected to the display panel 100 in the form of an IC. The level shifter circuit 130 shifts the level of the signal and the voltage supplied through the clock signal line, the start signal line, the gate high voltage line and the gate low voltage line, etc., under the control of the timing control section 110, (140A, 140B).

The signal output circuits 140A and 140B may be formed in the form of a thin film transistor on the display panel 100 by a gate-in-panel (GIP) method. The signal output circuits 140A and 140B may be formed separately in the left and right non-display areas LNA and RNA of the display panel 100. [ The signal output circuits 140A and 140B include a plurality of stages for shifting and outputting a scan signal based on the signals output from the level shifter circuit 130 and various voltages CLK, EVST, VGH, and VGL.

The signal output circuits 140A and 140B include a scan control signal output circuit for outputting a scan control signal used for turning on or off switching transistors among a plurality of transistors included in subpixels, And a light emission control signal output circuit for outputting a light emission control signal used for turning on or off the light emission control signal.

Hereinafter, embodiments of the present invention for solving the problems of the conventional gate driving circuit will be described.

3 is a block diagram showing a part of a conventional gate driving circuit.

3, the scan signal output circuits SR [1] and SR [2] and the emission signal output circuits EM [1] and EM [2] are formed in the signal output circuits 140A and 140B of the gate drive circuit, , EM [2]) were separately constructed and arranged. For example, scan control signal output circuits SR [1] and SR [2] are arranged on one side of the display area AA and emission control signal output circuits EM [1] and EM [ [2]). However, when the scan control signal output circuits SR [1] and SR [2] and the emission control signal output circuits EM [1] and EM [2] are separately configured as in the conventionally proposed gate drive circuit , The area occupied by the circuit is widened, and therefore the non-display area (LNA, RNA) is inevitably increased.

4 is a block diagram showing a part of a gate driving circuit according to an embodiment of the present invention.

4, the gate driving circuit includes one scan control signal output circuit SR [1], SR [2] and the emission control signal output circuits EM [1] and EM [2] And a heterogeneous control signal integrated output circuit (NSDa, NSDb). For example, a first integrated output circuit NSDa for outputting the first emission control signal and the first scan control signal at the same time is disposed on one side of the display area AA, and a second emission control signal And a second integrated output circuit (NSDb) for simultaneously outputting the second scan control signal.

The scan control signal output circuits SR [1] and SR [2] and the emission control signal output circuits EM [1] and EM [2] are controlled so that the scan control signal and the emission control signal are outputted from a single circuit, EM [2]), the area of the gate driving circuit and the non-display area (LNA, RNA) can be drastically reduced.

Referring to FIG. 4, the first integrated output circuit NSDa and the second integrated output circuit NSDb are disposed on one side and the other side of the display panel 100, respectively, but are not limited thereto. For example, the same integrated output circuit may be disposed on one side and the other side of the display area AA, or an integrated output circuit may be disposed on only one side of the display area AA.

The gate drive circuit includes a plurality of stages STG1 and STG2. The plurality of stages STG1 and STG2 may share the input signals with each other, and some output signals of one stage may be connected to the inputs of the other stages.

5A and 5B are diagrams for explaining pulse width variable driving.

As shown in FIGS. 5A and 5B, when the pulse width variable driving for controlling the width of the emission signal is performed, the emission time EMT of the organic light emitting diode can be variously controlled in the form of tn or ti.

More than one scan control signal output circuit and at least one light emission control signal output circuit are required to generate an output for variable pulse width drive. Therefore, when the conventional gate driving circuit is used, the number of blocks required for the circuit configuration increases, which makes it difficult to implement the narrow bezel.

6 is a circuit configuration diagram of the integrated output circuit shown in FIG.

The integrated output circuit NSD shown in FIG. 6 corresponds to the N-th (N is a natural number) stage of the plurality of stages. The integrated output circuit (NSD) may be disposed on one side of the display panel (100).

The integrated output circuit NSD includes a first circuit portion (or a setting circuit) SC, a second circuit portion (or EM), a third circuit portion (or a logic circuit) LC, (Or a scan control signal output circuit; hereinafter referred to as SR).

The first circuit unit SC includes first through fourth transistors T1 through T4 and a first capacitor C1. The second circuit portion EM includes the fifth to sixth transistors T5 and T6 and the second to third capacitors C2 and C3. The third circuit LC includes seventh to tenth transistors T7 to T10 and a fifth capacitor C5. The fourth circuit SR includes the 11th to 12th transistors T11 to T12 and the fourth capacitor C4.

The first transistor T1 operates in response to the signal of the first clock signal line ECLK1 and transmits the signal of the first start signal stage EVST to the first node N2 or Q2 node. At this time, the first start signal stage (EVST) of the other stage except for the first stage may be connected to the output stage of the previous stage. The gate electrode of the first transistor T1 is connected to the first clock signal line ECLK1, the first electrode to the first start signal stage EVST and the second electrode to the first node N1. The first node N1 and the fourth node (or Q node N4) shown in FIG. 6 are connected to each other.

The second transistor T2 operates in response to the signal of the first start signal stage EVST and discharges the second node N2 to the low potential voltage terminal VGL. The gate electrode of the second transistor T2 is connected to the first start signal terminal EVST, the first electrode to the second node N2 and the second electrode to the low potential voltage terminal VGL.

The first capacitor C1 is disposed between the first transistor T1 and the second transistor T2. One electrode of the first capacitor C1 is connected to the gate electrode of the first transistor T1 and the first clock signal line ECLK1 and the other electrode of the first capacitor C1 is connected to the first electrode of the second transistor T2. The first capacitor C1 acts as a switching transistor for controlling the third transistor T3. Since the area occupied by the capacitor is smaller than the area occupied by the transistor, the area of the integrated output circuit (NSD) can be further reduced.

The third transistor T3 operates in response to the signal of the second node N2 and transmits the signal of the first clock signal ECLK1 to the third node (or the QB node N3). The gate electrode of the third transistor T3 is connected to the second node N2, the first electrode to the first clock signal terminal ECLK1 and the second electrode to the third node N3.

The fourth transistor T4 operates in response to the signal of the first node N1 and discharges the third node N3 to the low potential voltage terminal VGL. The gate electrode of the fourth transistor T4 is connected to the first node N1, the first electrode to the third node N3, and the second electrode to the low potential voltage terminal VGL.

The second capacitor C2 helps to prevent the charged voltage at the third node N3 from discharging quickly. The second capacitor C2 is disposed between the third node N3 and the low potential voltage terminal VGL and one electrode of the second capacitor C2 is connected to the third node N3, And is connected to the voltage terminal VGL.

The fifth transistor T5 operates in response to the signal of the fourth node (or the Q node N4) and transmits the signal of the high potential terminal VGH to the first output terminal EMO. The gate electrode of the fifth transistor T5 is connected to the fourth node N4, the first electrode to the high potential terminal VGH and the second electrode to the first output terminal EMO.

The third capacitor C3 is disposed between the fourth node N4 and the first output terminal EMO. One electrode of the third capacitor C3 is connected to the fourth node N4 and the other electrode is connected to the first output terminal EMO. The third capacitor C3 further increases the voltage of the fourth node N4 for a predetermined time. This makes it possible to output a more stable emission control signal with a minimum delay.

The sixth transistor T6 discharges the first output terminal EMO to the low potential voltage terminal VGL corresponding to the signal of the third node N3. The gate electrode of the sixth transistor T6 is connected to the third node N3, the first electrode is connected to the first output terminal EMO, and the second electrode is connected to the low potential voltage terminal VGL.

The seventh transistor T7 transmits the signal of the third node N3 to the fifth node (or the SQ node N5) corresponding to the signal of the second start signal SVST. The gate electrode of the seventh transistor T7 is connected to the second start signal terminal SVST, the first electrode is connected to the third node N3, and the second electrode is connected to the fifth node N5.

The eighth transistor T8 transfers the signal of the fourth node N4 to the sixth node (or the SQB node N6) in response to the signal of the second start signal SVST. The gate electrode of the eighth transistor T8 is connected to the second start signal terminal SVST, the first electrode is connected to the fourth node N4, and the second electrode is connected to the sixth node N6.

The ninth transistor T9 discharges the fifth node N5 corresponding to the signal of the sixth node N6. The gate electrode of the ninth transistor T9 is connected to the sixth node N6, the first electrode is connected to the fifth node N5, and the second electrode is connected to the low potential voltage terminal VGL.

The tenth transistor T10 transfers the signal of the high potential terminal VGH to the sixth node N6 in response to the signal of the second clock signal terminal SCLK3 of the subsequent stage. The gate electrode of the tenth transistor T10 is connected to the second clock signal terminal SCLK3 of the subsequent stage, the first electrode to the high potential terminal VGH and the second electrode to the sixth node N6 . Although the gate electrode of the tenth transistor T10 shown in FIG. 6 is connected to the second clock signal stage SCLK3 of the second stage after the second stage, it is not limited thereto. For example, the gate electrode of the tenth transistor T10 may be connected to the second clock signal terminal SCLK4 of the third stage, or may be connected to a separate signal terminal.

The fifth capacitor C5 helps to prevent the charged voltage at the sixth node N6 from discharging quickly. The fifth capacitor C5 is disposed between the sixth node N6 and the low potential voltage terminal VGL and one electrode of the fifth capacitor C5 is connected to the sixth node N6, (VGL).

The eleventh transistor T11 transfers the signal of the third clock signal terminal SCLK1 to the second output terminal SRO corresponding to the signal of the fifth node N5. The gate electrode of the eleventh transistor T11 is connected to the fifth node N5, the first electrode is connected to the third clock signal terminal SCLK1, and the second electrode is connected to the second output terminal SRO.

The fourth capacitor C4 is disposed between the fifth node N5 and the second output terminal SRO. One electrode of the fourth capacitor C4 is connected to the fifth node N5, and the other electrode thereof is connected to the second output terminal SRO. The fourth capacitor C4 further increases the voltage of the fifth node N5 for a predetermined time. As a result, a more stable and delay-minimized scan control signal can be output.

The twelfth transistor T12 discharges the second output terminal SRO corresponding to the signal of the sixth node N6. The gate electrode of the twelfth transistor T12 is connected to the sixth node N6, the first electrode thereof is connected to the second output terminal SRO, and the second electrode thereof is connected to the low potential voltage terminal VGL.

On the other hand, the signal of the low potential voltage terminal VGL is the first voltage (or the low voltage) and the signal of the high potential voltage terminal VGH is the second voltage (or the high voltage) higher than the first voltage. The first clock signal line SCLK1, the first output signal EMO, and the second output signal SRO are input to the first input terminal OUT, the first start signal stage EVST, the second start signal stage SVST, the first clock signal stage ECLK1, ) Swings at different timings between the first voltage and the second voltage.

The integrated output circuit NSD according to an embodiment of the present invention can simultaneously output the emission control signal and the scan control signal. 6, the integrated output circuit NSD includes a third circuit LC between the light emission control signal output circuit EM and the scan control signal output circuit SR. The scan control signal output circuit SR shares the third node N3 and the fourth node N4 of the emission control signal output circuit EM via the third circuit LC. Therefore, the configuration of the integrated output circuit NSD can be simplified and the area occupied by the gate drive circuit can be minimized.

The third node N3 of the emission control signal output circuit EM is selectively connected to the fifth node N5 of the scan control signal output circuit SR through the third circuit LC. The fourth node N4 of the emission control signal output circuit EM is selectively connected to the fifth node N5 of the scan control signal output circuit SR through the third circuit LC. Therefore, during a period in which the first output terminal EMO outputs a low voltage, the multi-output of the scan control signal through the second output terminal SRO can be interrupted. The input / output waveform diagram of FIG. 7 will be described in detail.

7 is an input / output waveform diagram of an integrated output circuit according to an embodiment of the present invention.

During a period in which the first start signal stage (EVST) at the beginning of the first section is maintained at a high voltage, the second transistor T2 is turned on. Accordingly, the second node N2 is discharged to the low potential voltage terminal VGL and becomes the low voltage, and the third transistor T3 is turned off. During the same period, the first clock signal line ECLK1 is held at a low voltage, so that the first transistor T1 is turned off. Accordingly, the fourth node N4 connected to the first node N1 and the first node N1 maintains the fourth interval state of the previous frame by the third capacitor C3. In addition, the third node N3 maintains the fourth section state of the previous frame by the second capacitor C2. In the fourth period of the previous frame, the first node N1 is the third voltage (or the bootstrapping voltage), and the third node N3 is the low voltage state. The third voltage will be described again in the fourth section.

While the first node N1 and the fourth node N4 are held at the third voltage, the fifth transistor T5 is turned on. Therefore, the first output terminal EMO of the light emission control signal output circuit EM outputs a high voltage of the high potential terminal VGH.

During the same period, the second start signal stage SVST is held at the low voltage, so that the eighth transistor T8 is turned off. Thus, the sixth node N6 is held in the fourth section of the previous frame by the fifth capacitor C5. In the fourth period of the previous frame, the sixth node N6 is in a high voltage state.

While the sixth node N6 is held at the high voltage, the twelfth transistor T12 is turned on. Accordingly, the second output terminal SRO of the scan control signal output circuit SR is discharged to the low potential voltage terminal VGL and outputs the low voltage.

Even if the signal of the first start signal stage (EVST) falls to the low voltage in the first section, there is no change in the drive phase.

In the second section, the first start signal stage (EVST) is maintained at a low voltage. At this time, when the signal of the first clock signal terminal ECLK1 rises to a high voltage, the first transistor T1 is turned on. Accordingly, the first node N1 and the fourth node N4 are discharged to the first start signal stage EVST and become the low voltage state.

During the same time, the second transistor T2 is in a turned off state, so that the second node N2 is in a floating state. At this time, when the first clock signal terminal ECLK1 is toggled to a high voltage, the potential of the second node N2 also rises by the first capacitor C1. Thus, the third transistor T3 is turned on. Thus, the third node N3 is in a high voltage state. The first capacitor C1 functions as a switching transistor and occupies a small space compared to the transistor, which is effective in implementing a narrow bezel.

The sixth transistor T6 is turned on so that the first output terminal EMO of the emission control signal output circuit EM is discharged to the low potential voltage terminal VGL and the low voltage .

During the same time, since the signal of the second start signal SVST is at a high voltage, the fifth node N5 is brought into the high voltage state by the seventh transistor T7. Accordingly, the eleventh transistor T11 is turned on and the second clock signal line SCLK1 is connected to the second output terminal SRO. As shown in Fig. 7, the timing at which the signal of the second start signal stage SVST rises to the high voltage may be faster than the timing at which the signal of the first clock signal line ECLK1 rises to the high voltage.

The second output terminal SRO of the scan control signal output circuit SR outputs a low voltage because the state of the second clock signal terminal SCLK1 is the low voltage in the early part of the second section. Then, when the signal of the second clock signal terminal SCLK1 becomes a high voltage, the second output terminal SRO also outputs a high voltage. At this time, the fifth node N5 rises to a bootstrapping voltage higher than the high voltage by the fourth capacitor C4. Accordingly, the second output terminal SRO can output a scan control signal having a more stable and minimized delay.

When the signal of the second clock signal terminal SCLK1 falls from the high voltage to the low voltage, the second output terminal SRO outputs the low voltage, and the signal of the fifth node N5 falls again to the high voltage. Further, even if the signal of the first clock signal line ECLK1 is toggled, since the first start signal stage EVST does not change, the first node N1 and the third node N3 are also unchanged.

Since the first start signal stage EVST is maintained in the same state in the third section, the first node N1, the third node N3, and the fourth node N4 are also unchanged. Therefore, the first output terminal EMO of the emission control signal output circuit EM outputs a low voltage.

Then, when the signal of the second clock signal terminal SCLK3 of the subsequent stage rises from the low voltage to the high voltage, the sixth node N6 is brought into a high voltage state by the tenth transistor T10. Therefore, the fifth node N5 is discharged by the ninth transistor T9 to be in the low voltage state, and the eleventh transistor T11 is turned off. The second output terminal SRO of the scan control signal output circuit SR is discharged by the twelfth transistor T12 and outputs a low voltage. Every time the second clock signal stage SCLK3 of the rear stage is toggled during the third period, the sixth node N6 is refreshed to a high voltage. Further, during a period in which the second clock signal terminal SCLK3 of the subsequent stage is kept at the low voltage after being toggled, the signal of the sixth node N6 maintains the high voltage by the fifth capacitor C5.

The signals of the first clock signal terminal ECLK1 and the second start signal terminal SVST are not toggled even when the signal of the first start signal terminal EVST rises to the high voltage at the end of the third section, And the scan control signal.

In the fourth section, the signal of the first start signal stage (EVST) is maintained at a high voltage. At this time, when the signal of the first clock signal terminal ECLK1 is toggled, the first transistor T1 and the second transistor T2 are turned on. Therefore, the first node N1 and the fourth node N4 are brought into the high voltage state by the first transistor T1, and the third node N3 is brought into the low voltage state by the fourth transistor T4 .

The fifth transistor T5 is turned on by the fourth node N4 and the sixth transistor T6 is turned off by the third node N3 so that the first output terminal EMO outputs a high voltage. On the other hand, the first electrode of the fifth transistor T5 is always connected to the high voltage terminal VGH to which a high voltage is applied, and the first electrode of the first transistor T1 is connected between the first voltage and the second voltage And is connected to a first start signal stage (EVST) to which a swing signal is applied. Therefore, the rate at which the first output terminal EMO rises from the low voltage to the specific voltage is faster than the rate at which the first node N1 and the fourth node N4 rise from the low voltage to the specific voltage. Thus, the fourth node N4 rises to a bootstrapping voltage higher than the high voltage by the third capacitor C3. Accordingly, the first output stage EMO can output a more stable and emission-minimized emission control signal.

On the other hand, since the second start signal stage SVST is in the low voltage state, the seventh transistor T7 and the eighth transistor T8 are turned off. Thus, the fifth node N5 and the sixth node N6 are in the floating state, but are held in the state immediately before by the fifth capacitor C5. Thereafter, when the signal of the second clock signal terminal SCLK3 of the rear stage is toggled in the first section of the next frame, the sixth node N6 is recharged to the high voltage again. Therefore, the second output terminal SRO can stably output the low voltage until the second clock signal terminal SCLK2 is toggled in the second section.

As described above, the logic circuit LC controls the fifth node N5 and the sixth node N6 so that a specific scan control signal is output during a specific period. That is, the logic circuit LC controls the fifth node N5 and the sixth node N6 so that the scan control signal is toggled once when the emission control signal is held at the low voltage. Further, the logic circuit LC controls the fifth node N5 and the sixth node N6 so that the scan control signal is not toggled when the emission control signal is held at the low voltage. In addition, the logic circuit LC controls the scan control signal from being toggled regardless of the toggle of the second clock signal stage (SCLK1) during the third period. Therefore, there is an effect that the pulse width of the emission control signal can be changed freely.

The first clock signal ECLK2 and the second clock signal SCLK2, SCLK4 shown in Fig. 7 can be used at different stages. In an embodiment of the present invention, the first clock signal is implemented in two phases and the second clock signal is implemented in four phases, but the present invention is not limited thereto.

8 is a circuit configuration diagram of an integrated output circuit according to an embodiment of the present invention.

The circuit shown in Fig. 8 is designed to improve the reliability and stability of the circuit shown in Fig. The integrated output circuit NSD shown in FIG. 8 is the same as the integrated output circuit NSD shown in FIG. 5 except for the sixth transistor T6b, the thirteenth transistor T13 and the fourteenth transistor T14. Therefore, the repetitive description is omitted.

Referring to FIG. 7, the fourth node N4 is maintained at the bootstrapping voltage in the first section, a part of the second section, and a part of the fourth section. As described above, the bootstrapping voltage of the fourth node N4 causes the fifth transistor T5 to be stably turned on. Accordingly, the response speed of the first output stage EMO can be improved.

On the other hand, when the first output terminal EMO outputs a high voltage, the first node N1 and the fourth node N4 may be discharged through the first transistor T1. In order to prevent this, the integrated output circuit NSD may further include a thirteenth transistor T13. The thirteenth transistor T13 is disposed between the first node N1 and the fourth node N4 and thus can separate the first node N1 and the fourth node N4. The gate electrode of the thirteenth transistor T13 is connected to the high potential terminal VGH, the first electrode to the fourth node N4, and the second electrode to the first node N1.

The fourth node N4 is disconnected from the first node N1 by the thirteenth transistor T13 in a period in which the fourth node N4 is maintained at the bootstrapping voltage, But is maintained at a high voltage, not a voltage. Thus, the thirteenth transistor T13 is turned off, and even if the signal of the first node N1 is discharged to the first start signal stage EVST, the fourth node N4 is maintained at the bootstrapping voltage . Therefore, the emission control signal can be output more stably.

On the other hand, the emission control signal for controlling the emission time of the organic light emitting diode generally has a very long time to be maintained at a high voltage. Likewise, the emission control signal output through the first output stage EMO is relatively longer than a period in which a period in which a high voltage is maintained is maintained in a low voltage. Further, the third node N3 of the integrated output circuit NSD is relatively longer than a period in which the section maintained at the low voltage is maintained at the high voltage. Therefore, the sixth transistor T6 shown in FIG. 6 is relatively longer than the section in which the section in which the sixth transistor T6 is maintained in the turned-off state is maintained in the turned-on state.

When the transistor is in a generally turned off state, the greater the voltage difference between the first electrode and the second electrode, the stronger the junction stress. The gate electrode of the sixth transistor T6 shown in FIG. 6 is connected to the third node N3, the first electrode is connected to the first output terminal EMO, and the second electrode is connected to the low potential voltage terminal VGL. Thus, the sixth transistor T6 is relatively longer in the turn-off interval than the other transistors included in the integrated output circuit NSD, thereby being exposed to a larger junction stress than the other transistors. Therefore, degradation of the sixth transistor T6 may progress rapidly, resulting in a change in characteristics of the device. As a result, the reliability of the integrated output circuit (NSD) can be weakened.

The sixth transistor T6b may be further disposed between the sixth transistor T6 and the low potential voltage terminal VGL to minimize deterioration of the sixth transistor T6. Thus, the junction stress applied to the sixth transistor T6 can be dispersed. The gate electrode of the sixth transistor T6b is commonly connected to the gate electrode of the third node N3 and the sixth transistor T6. The first electrode of the sixth transistor T6b is connected to the second electrode of the sixth transistor T6 and the second electrode of the sixth transistor T6b is connected to the low potential terminal VGL.

Meanwhile, the integrated output circuit NSD may further include a fourteenth transistor T14. The fourteenth transistor T14 can artificially reduce the junction stress of the sixth transistor T6 by applying a specific voltage between the sixth transistor T6 and the sixth transistor T6b. The gate electrode of the fourteenth transistor T14 is connected to the first output terminal EMO, the first electrode to the high potential terminal VGH and the second electrode to the second electrode of the sixth transistor T6.

During the period in which the sixth transistor T6 is kept in the turned off state, the fourteenth transistor T14 connected to the first output terminal EMO applies a high voltage to the second electrode of the sixth transistor T6. Therefore, the fourteenth transistor T14 can control the sixth transistor T6 to be minimally exposed to the junction stress. As a result, the element deterioration of the sixth transistor T6 can be minimized, and the reliability of the integrated output circuit NSD can be further improved.

Although the integrated output circuit NSD of FIG. 8 is illustrated as being added with the sixth transistor T6b, the thirteenth transistor T13, and the fourteenth transistor T14 as compared with the integrated output circuit NSD of FIG. 6, But the present invention is not limited thereto. For example, one or two or more of the sixth transistor T6b, the thirteenth transistor T13, and the fourteenth transistor T14 may be added to the integrated output circuit NSD of FIG. 6.

The integrated output circuit NSD according to the embodiment of the present invention can simultaneously output the scan control signal and the emission control signal for driving the display panel. This minimizes the size of the bezel to enable the implementation of the narrow bezel, and is effective in securing the design margin.

The gate drive circuit and the display device according to the embodiment of the present invention can be described as follows.

There is provided a gate drive circuit including a plurality of stages connected to each other in a dependent manner according to an embodiment of the present invention. An Nth stage of the plurality of stages is connected to the first start signal stage and the first clock signal stage and includes a first circuit for controlling the first node and the second node, a first circuit connected to the first node and the second node, A third circuit connected to the second node and the third node for controlling the fourth node and the fifth node, and a third circuit connected to the fourth node and the fifth node, And a fourth circuit for outputting a control signal, and is capable of simultaneously outputting the emission control signal and the scan control signal.

In a gate driving circuit according to an embodiment of the present invention, the first circuit includes a first transistor for charging a first node, a second transistor for charging a second node, a third transistor for discharging a second node, A first capacitor disposed between the clock signal terminal and a sixth node, and a fourth transistor discharging a sixth node, wherein the fifth node is commonly connected to the first capacitor, the second transistor and the fourth transistor do.

In the gate driving circuit according to an embodiment of the present invention, the gate of the first transistor is connected to the first clock signal terminal, the gate of the second transistor is connected to the sixth node, And the gate of the fourth transistor may be coupled to a previous stage output stage.

In the gate driving circuit according to an embodiment of the present invention, the second circuit may include a fifth transistor for charging the first output terminal, a sixth transistor for discharging the first output terminal, and a sixth transistor for discharging the first output terminal, And a second capacitor.

In the gate driving circuit according to an embodiment of the present invention, the gate of the fifth transistor may be connected to the third node, and the gate of the sixth transistor may be connected to the second node.

In the gate driving circuit according to an embodiment of the present invention, the third circuit may include a seventh transistor for charging the fourth node, an eighth transistor for discharging the fourth node, a ninth transistor for charging the fifth node, And a tenth transistor for discharging five nodes.

In the gate driving circuit according to an embodiment of the present invention, the gate of the seventh transistor and the gate of the tenth transistor are connected to the second start signal terminal, the gate of the eighth transistor is connected to the fifth node, The gate of the transistor may be connected to the second clock signal terminal.

In the gate driving circuit according to an embodiment of the present invention, the fourth circuit includes an eleventh transistor for charging the signal of the third clock signal terminal to the second output terminal, a twelfth transistor for discharging the second output terminal, And a third capacitor disposed between the first output terminal and the second output terminal.

In the gate driving circuit according to an embodiment of the present invention, the gate of the eleventh transistor may be connected to the fourth node, and the gate of the twelfth transistor may be connected to the sixth node.

In the gate driving circuit according to an embodiment of the present invention, the third circuit may control the scan control signal to toggle once during a period in which the emission control signal is held low.

The gate drive circuit according to an embodiment of the present invention may further include a thirteenth transistor disposed between the first node and the third node, the thirteenth transistor may further include a first node and a third node, And the delay of the emission control signal is minimized.

A gate driver circuit according to an embodiment of the present invention is provided. The gate driving circuit includes a scan control signal output circuit for outputting a scan control signal through a first output terminal and a light emission control signal output circuit for outputting a light emission control signal through a second output terminal. During a period in which the emission control signal output circuit outputs the emission control signal to the first voltage, the scan control signal output circuit controls the scan control signal to be output to the second voltage higher than the first voltage for a specific period.

In the gate driving circuit according to an embodiment of the present invention, the scan control signal output circuit includes a first transistor connected to a first node, a first transistor corresponding to a signal of the first node, It is possible to control to output a clock signal at the clock signal end.

In the gate driving circuit according to an embodiment of the present invention, the scan control signal output circuit includes a second transistor connected to the second node, and the second transistor is connected to the first node so that the first output terminal is discharged corresponding to the signal of the second node. Can be controlled.

The gate driving circuit according to an embodiment of the present invention further includes a first capacitor disposed between the first node and the first output terminal, and the voltage of the first node while the first output terminal outputs the first voltage is And may be raised to a second voltage higher than the first voltage by the first capacitor.

In the gate driving circuit according to an embodiment of the present invention, the light emission control signal output circuit includes a third transistor connected to the third node, and the third transistor has a second output terminal corresponding to the signal of the third node, It is possible to control so that the control signal is outputted.

In the gate driving circuit according to an embodiment of the present invention, the emission control signal output circuit includes a fourth transistor connected to the fourth node, and the fourth transistor is connected to the fourth node so that the second output terminal is discharged Can be controlled.

The gate driving circuit according to an embodiment of the present invention further includes a second capacitor disposed between the third node and the second output terminal, and the voltage of the third node while the second output terminal outputs the first voltage is And may be raised to a second voltage higher than the first voltage by a second capacitor.

In the gate driving circuit according to an embodiment of the present invention, the second output terminal may be configured to output the signal of the high potential terminal during a period in which the third transistor is turned on.

A display device according to an embodiment of the present invention is provided. The display device includes a display portion having a plurality of pixels, a non-display portion adjacent to the display portion, and a circuit portion disposed in the non-display portion and outputting control signals related to the operation of the pixels. The circuit portion has a structure in which the scan control signal output circuit and the light emission control signal output circuit are integrated, and the area of the non-display portion is reduced as compared with a display device having no integrated circuit portion.

In the display apparatus according to an embodiment of the present invention, the scan control signal output circuit outputs a scan control signal through a first output terminal, and the emission control signal output circuit outputs a light emission control signal through a second output terminal.

The scan control signal output circuit may include a first transistor and a second transistor connected to the first output terminal, the emission control signal output circuit may include a third transistor connected to the second output terminal, And a fourth transistor.

The gate of the first transistor is selectively connected to the gate of the fourth transistor by the fifth transistor, and the gate of the second transistor is connected to the gate of the third transistor by the sixth transistor. In the display device according to an embodiment of the present invention, Gate. ≪ / RTI >

The display device according to an embodiment of the present invention includes a first capacitor disposed between the first output terminal and the gate of the first transistor and the voltage applied to the gate of the first transistor is boosted by the first capacitor .

The display device according to an embodiment of the present invention includes a second capacitor disposed between the gates of the second output terminal and the third transistor and the voltage applied to the gate of the third transistor is boosted by the second capacitor .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: Data driver 130, 140A, 140B: Gate driver circuit
SR: Scan control signal output circuit
EM: emission control signal output circuit
LC: Logic circuit NSD: Integrated output circuit

Claims (25)

In a gate drive circuit including a plurality of stages,
And an Nth (N is a positive integer) stage of the plurality of stages,
A first circuit coupled to the first start signal stage and the first clock signal stage and controlling the first node and the second node;
A second circuit coupled to the first node and the second node for outputting a light emission control signal to a first output terminal;
A third circuit coupled to the second node and the third node for controlling the fourth node and the fifth node; And
And a fourth circuit coupled to the fourth node and the fifth node for outputting a scan control signal to a second output terminal,
And to simultaneously output the emission control signal and the scan control signal. The method according to claim 1,
The first circuit comprising:
A first transistor for charging a first node;
A second transistor for charging the second node;
A third transistor for discharging the second node;
A first capacitor disposed between the first clock signal terminal and a sixth node; And
And a fourth transistor for discharging the sixth node,
And the fifth node is commonly connected to the first capacitor, the second transistor, and the fourth transistor. 3. The method of claim 2,
A gate of the first transistor is connected to the first clock signal terminal,
A gate of the second transistor is connected to the sixth node,
A gate of the third transistor is connected to the first node,
And a gate of the fourth transistor is connected to the output of the previous stage. 3. The method of claim 2,
The second circuit comprising:
A fifth transistor for charging the first output terminal;
A sixth transistor for discharging the first output terminal; And
And a second capacitor disposed between the third node and the first output terminal. 5. The method of claim 4,
A gate of the fifth transistor is connected to the third node,
And a gate of the sixth transistor is coupled to the second node. 5. The method of claim 4,
The third circuit comprising:
A seventh transistor for charging the fourth node;
An eighth transistor for discharging the fourth node;
A ninth transistor for charging the fifth node; And
And a tenth transistor for discharging the fifth node. The method according to claim 6,
A gate of the seventh transistor and a gate of the tenth transistor are connected to a second start signal terminal,
A gate of the eighth transistor is connected to the fifth node,
And a gate of the ninth transistor is connected to a second clock signal terminal. The method according to claim 6,
Wherein the fourth circuit comprises:
An eleventh transistor for charging a signal of a third clock signal terminal to the second output terminal;
A twelfth transistor for discharging the second output terminal; And
And a third capacitor disposed between the fourth node and the second output terminal. 9. The method of claim 8,
A gate of the eleventh transistor is connected to the fourth node,
And a gate of the twelfth transistor is connected to the sixth node. The method according to claim 1,
Wherein the third circuit controls the scan control signal to be toggled once during a period in which the emission control signal is held low. 5. The method of claim 4,
Further comprising a thirteenth transistor disposed between the first node and the third node, wherein the thirteenth transistor separates the first node and the third node to generate a discharge of the third node, A gate drive circuit that controls delay to be minimized. A scan control signal output circuit for outputting a scan control signal through a first output terminal; And
And a light emission control signal output circuit for outputting a light emission control signal through a second output terminal,
During a period in which the emission control signal output circuit outputs the emission control signal as a first voltage, the scan control signal output circuit controls the scan control signal to be output as a second voltage higher than the first voltage for a specific period , Gate drive circuit. 13. The method of claim 12,
Wherein the scan control signal output circuit includes a first transistor connected to a first node and the first transistor is controlled to output a clock signal of a first clock signal terminal to the first output terminal in correspondence with a signal of the first node, Gate drive circuit. 14. The method of claim 13,
Wherein the scan control signal output circuit includes a second transistor connected to a second node and the second transistor controls the first output terminal to discharge corresponding to a signal of the second node. 14. The method of claim 13,
Further comprising a first capacitor disposed between the first node and the first output, the voltage of the first node being greater than the first voltage by the first capacitor while the first output is outputting a first voltage, Rising to a second higher voltage. 13. The method of claim 12,
Wherein the emission control signal output circuit includes a third transistor connected to a third node and the third transistor controls the emission control signal to be output to the second output terminal in response to the signal of the third node, in. 17. The method of claim 16,
Wherein the emission control signal output circuit includes a fourth transistor connected to a fourth node and the fourth transistor controls the second output terminal to discharge corresponding to a signal of the fourth node. 17. The method of claim 16,
Further comprising a second capacitor disposed between the third node and the second output terminal, wherein the voltage of the third node while the second output terminal outputs the first voltage is higher than the first voltage Rising to a second higher voltage. 17. The method of claim 16,
And the second output terminal is configured to output a signal of a high potential terminal during a period in which the third transistor is turned on. A display unit having a plurality of pixels;
A non-display portion adjacent to the display portion; And
And a circuit section in the non-display section and outputting control signals associated with the operation of the pixels,
Wherein the non-display area of the non-display area is reduced as compared with a display device having no integrated circuit structure. 21. The method of claim 20,
Wherein the scan control signal output circuit outputs a scan control signal through a first output terminal and the emission control signal output circuit outputs a light emission control signal through a second output terminal. 22. The method of claim 21,
Wherein the scan control signal output circuit includes a first transistor and a second transistor connected to the first output terminal and the emission control signal output circuit includes a third transistor and a fourth transistor connected to the second output terminal, . 23. The method of claim 22,
Wherein a gate of the first transistor is selectively connected to a gate of the fourth transistor by a fifth transistor and a gate of the second transistor is selectively connected to a gate of the third transistor by a sixth transistor, . 24. The method of claim 23,
And a first capacitor disposed between the first output terminal and the gate of the first transistor, wherein a voltage applied to a gate of the first transistor is reinforced by the first capacitor. 24. The method of claim 23,
And a second capacitor disposed between the second output terminal and the gate of the third transistor, wherein a voltage applied to the gate of the third transistor is reinforced by the second capacitor.

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