KR102656478B1 - Gate driver, display device and driving method using the same - Google Patents

Abstract

According to this embodiment, a start pulse and a trigger pulse applied later than the start pulse are input, and the timing at which the trigger pulse is output is determined in response to a first trigger clock having a second pulse width narrower than the first pulse width. It includes a timing unit and a signal output unit that receives a trigger pulse and outputs a gate signal corresponding to the first clock with a first pulse width and stops output of the gate signal by receiving a second trigger clock with a second pulse width. To provide a gate driver and a display device using the same.

Description

Gate driver, display device using the same and driving method thereof {GATE DRIVER, DISPLAY DEVICE AND DRIVING METHOD USING THE SAME}

These embodiments relate to a gate driver, a display device using the same, and a method of driving the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), organic Various matrix-type display devices, such as organic light emitting display devices (OLED), are being used.

A matrix-type display device arranges a plurality of pixels in the horizontal and vertical directions, and writes the data signal transmitted through the data line to the pixels that receive the gate signal through the gate line, so that the display device displays an image. You can do it.

The gate driver used in this matrix-type display device outputs a gate signal by switching high and low signals using a plurality of transistors. When the transistor deteriorates and the threshold voltage of the transistor increases, the gate signal is output normally. Problems that do not work may occur.

Therefore, an increase in threshold voltage due to deterioration of the transistor must be prevented.

The purpose of the present embodiments is to provide a gate driver that can prevent the threshold voltage of a transistor from changing and a display device using the same.

The purpose of the present embodiments is to provide a method of driving a display device that prevents the threshold voltage of a transistor from changing.

In one aspect, the present embodiments receive a start pulse and a trigger pulse applied later than the start pulse, and the point at which the trigger pulse is output in response to the first trigger clock having a second pulse width narrower than the first pulse width. A timing unit that determines, and a signal that receives a trigger pulse and outputs a gate signal corresponding to the first clock with a first pulse width, and stops the output of the gate signal by receiving a second trigger clock with a second pulse width. A gate driver including an output unit is provided.

In another aspect, a display panel where a plurality of gate lines and a plurality of data lines intersect, a gate driver that transmits a gate signal to the plurality of gate lines, and a drive IC that transmits a data signal to the data line, the gate driver Includes a plurality of stages that sequentially output gate signals, where the kth stage among the plurality of stages is the k-3th gate signal output from the k-3th stage, and the k-2th stage output from the k-2th stage. A timing unit that receives the th gate signal and determines when the trigger pulse is output in response to the first trigger clock having a second pulse width narrower than the first pulse width, and a timing unit that receives the k-3 th gate signal and determines the first trigger clock A display device is provided that includes a signal output unit that outputs a k-th gate signal corresponding to a first clock with a pulse width, receives a second trigger clock with a second pulse width, and stops the output of the k-th gate signal. .

In another aspect, a step of sequentially receiving a start pulse and a trigger pulse, receiving a first clock having a first pulse width and a second clock having a second pulse width narrower than the first pulse width, and responding to the second clock A method of driving a display device comprising determining an output point of a gate signal and terminating the gate signal in response to a third clock having a second pulse width so that the gate signal has a first pulse width. It is provided.

According to the present embodiments, a gate driver that can prevent the threshold voltage of a transistor from changing, a display device using the same, and a method of driving the same can be provided.

1 is a structural diagram showing an example of a display device according to this embodiment.
FIG. 2 is a structural diagram showing an embodiment of the gate drive shown in FIG. 1.
FIG. 3 is a structural diagram showing one embodiment of the stage shown in FIG. 2.
FIG. 4A is a timing diagram showing a first embodiment of a first trigger signal and a second trigger signal input to the stage shown in FIG. 3.
FIG. 4B is a timing diagram showing a second embodiment of the first trigger signal and the second trigger signal input to the stage shown in FIG. 3.
Figure 5 is a graph showing the change time of the threshold voltage of a transistor.
FIG. 6 is a circuit diagram showing one embodiment of the stage shown in FIG. 3.
FIG. 7 is a timing diagram showing one embodiment of the operation of the stage shown in FIG. 6.
Figure 8 is a flowchart showing a method of driving a display device according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

1 is a structural diagram showing an example of a display device according to this embodiment.

Referring to FIG. 1 , the display device 100 may include a display panel 110, gate drivers 120a and 120b, a drive IC 130, and a control unit 140.

In the display panel 110, a plurality of gate lines GL and a plurality of data lines DL intersect, and an area where the gate lines GL and data lines DL intersect may be defined as a pixel. Additionally, a data signal may be input to the pixel in response to the gate signal transmitted through the gate line GL. The wiring included in the display panel 110 is not limited to this. The display panel 110 includes an active area 111 in which a plurality of pixels are arranged to display an image, and an inactive area arranged outside the active area 111 and in which wiring and circuits for driving the display panel 110 are arranged. It can be divided into areas 110a and 110b.

The gate drivers 120a and 120b may sequentially transmit gate signals to the plurality of gate lines GL. Gate drivers 120a and 120b may be connected to the gate line GL on one side of the display panel. Additionally, the gate drivers 120a and 120b may be disposed in the non-active areas 110a and 110b of the display panel 110 and connected to the gate line GL. The gate drivers 120a and 120b, when disposed in the non-active areas 110a and 110b of the display panel 110, include a plurality of GIP (Gate In Panel) circuits 121a, 12na, 121b, and 12nb that output gate signals. It can be displayed. The gate drivers 120a and 120b are shown as being disposed on both sides of the display panel 110, but the gate drivers 120a and 120b are not limited thereto and may be disposed on one side of the display panel 110.

The drive IC 130 may be connected to a plurality of data lines DL to transmit data signals. The drive IC 130 can receive a digital image signal, generate an analog data signal, and transmit it to a plurality of data lines (DL). Here, the drive IC 130 is displayed as one, but is not limited to this and may be plural depending on the resolution of the display panel 110.

The control unit 140 can control the gate drivers 120a and 120b and the drive IC 130 to supply gate signals and data signals to the display panel 110. Additionally, the control unit 140 can receive digital image signals from an external device and supply them to the drive IC 130.

FIG. 2 is a structural diagram showing an embodiment of the gate drive shown in FIG. 1.

Referring to FIG. 2, the gate driver may include a plurality of stages 221, 222, 223, 224, and 225. One gate signal is output from one stage, and each stage can output gate signals sequentially. Outputting gate signals sequentially means outputting one gate signal from one stage and then outputting another gate signal from another stage. Here, the gate driver is shown as having five stages (221, 222, 223, 224, and 225), but this is for convenience of explanation, and the number of each stage may be determined according to the resolution of the display panel 110 as shown in FIG. 1.

In order for the stages 221, 222, 223, 224, and 225 to output gate signals sequentially, one stage can output a gate signal when it receives a gate signal from the previous stage. The gate signal received from the previous stage may be a start pulse (SP) and a trigger pulse (TP). When the gate driver is disposed in the non-active area 110b of the display panel 110 shown in FIG. 1, one stage may be one GIP circuit.

FIG. 3 is a structural diagram showing one embodiment of the stage shown in FIG. 2.

Referring to FIG. 3, the stage 300 receives a start pulse (SP) and a trigger pulse (TP) applied later than the start pulse (SP), and has a first pulse width narrower than the first pulse width. A timing unit 310 that determines when the trigger pulse (TP) is output in response to the trigger clock (T-CLK1), and a first clock (CLK) that receives the trigger pulse (TP) and has a first pulse width. It may include a signal output unit 320 that outputs a gate signal corresponding to and receives a second trigger clock (T-CLK2) having a second pulse width to stop the output of the gate signal.

If the stage 300 is the kth stage outputting the kth gate signal among a plurality of stages, the stage receives the k-3th gate signal output from the k-3th stage 300 as a start pulse (SP). The k-2th gate signal output from the k-2th stage 300 can be input as a trigger pulse (TP). However, it is not limited to this.

FIG. 4A is a timing diagram showing a first embodiment of the first trigger signal and the second trigger signal input to the stage shown in FIG. 3, and FIG. 4B is a timing diagram showing the first embodiment of the first trigger signal and the second trigger signal input to the stage shown in FIG. 3. This is a timing diagram showing the second embodiment of the two-trigger signal.

Referring to FIGS. 4A and 4B, the first trigger signal (T-CLK1) and the second trigger signal (T-CLK2) may be generated in synchronization with the generation of the first clock (CLK). Additionally, the first trigger signal (T-CLK1) may be generated when the first clock (CLK1) is generated, and the second trigger signal (T-CLK2) may be generated when the first clock (CLK1) ends. In addition, the first trigger signal (T-CLK1) and the second trigger signal (T-CLK2) may repeat high and low states, and the high and low states of the first clock (CLK1) are 1:1. Although expressed as a ratio, the high state period of the first trigger signal (T-CLK1) and the second trigger signal (T-CLK2) may be implemented to be shorter than the low state period. In addition, the high voltage level of the first trigger signal (T-CLK1) and the second trigger signal (T-CLK2) may be lower than the voltage level of the high voltage (VGH) of the first clock (CLK1), and the low voltage The voltage level of may also be lower than the voltage level of the low voltage (VGL) of the first clock (CLK1).

Therefore, the high state section of the first trigger signal (T-CLK1) and the second trigger signal (T-CLK2) is short or the high and low voltages are set low, so that the first trigger signal (T-CLK1) and the second trigger signal (T-CLK1) are Deterioration of the transistor to which the trigger signal (T-CLK2) is applied can be prevented.

Figure 5 is a graph showing the change time of the threshold voltage of a transistor.

Referring to FIG. 5, the threshold voltage (Vth) of the transistor may change due to deterioration. When the switching signal is applied to the gate electrode of the transistor in a 1:1 ratio between the high section and the low section like the first clock, the threshold voltage (Vth) of the transistor can be changed as shown in curve a. And, as shown in FIG. 4A, when a switching signal whose high period is shorter than the low period is applied to the gate electrode of the transistor, the threshold voltage (Vth) of the transistor may change as shown in curve b. In addition, as shown in Figure 4b, when the switching signal is applied to the gate electrode of the transistor with the high section being shorter than the low section but the high and low state voltage levels being low, the threshold voltage (Vth) of the transistor is curved. It can be changed as c.

Therefore, it can be seen that if the high section of the switching signal is shortened, the increase in the voltage level of the threshold voltage (Vth) over time becomes smaller. In particular, it can be seen that if the voltage level of the high section and low section of the switching signal is lowered, the increase in the voltage level of the threshold voltage (Vth) over time becomes smaller.

FIG. 6 is a circuit diagram showing one embodiment of the stage shown in FIG. 3.

Referring to FIG. 6, the stage 600 may include a signal output unit 620 and a timing unit 610.

The signal output unit 620 includes a first transistor (M1) that outputs a gate signal corresponding to the first clock (CLK1) to the second node (N2) in response to the voltage of the first node (N1), and a second A second transistor (M2), which transmits a low voltage to the second node (N2) in response to the trigger clock (T-CLK2), is connected between the first node (N1) and the second node (N2), and the first node It may include a capacitor (C) that maintains the voltage of (N1). In addition, the timing unit 620 generates a third transistor (M3) that outputs a start pulse to the first node (N1) and a trigger pulse (k-2 ^th ) in response to the first trigger clock (T-CLK1). It may include a fourth transistor (M4) that transmits data to one node (N1).

The first transistor (M1) has a first electrode connected to the first clock input terminal that transmits the first clock (CLK1), a gate electrode connected to the first node (N1), and a second electrode connected to the second node (N2). can be connected Accordingly, the first transistor M1 can transmit the first clock CLK1 to the second node N2 by the voltage of the first node N1. The second node (N2) may be the output terminal of the stage. The stage can output the kth gate signal (K ^th ).

The second transistor (M2) has a first electrode connected to the low voltage input terminal through which the low voltage (VGL) is transmitted, and a gate electrode connected to the second trigger clock clock input terminal through which the second trigger signal (T-CLK2) is input. Two electrodes may be connected to the second node (N2). Accordingly, the second transistor M2 can transmit a low voltage to the second node N2 in response to the third clock.

The capacitor C may be connected between the first node N1 and the second node N2 to maintain the voltage of the first node N1. Additionally, the voltage of the first node (N1) can be lowered in response to the voltage of the second node (N2).

The third transistor M3 may have a first electrode connected to a gate electrode and a second electrode connected to the first node N1. Also, the first electrode and the gate electrode of the third transistor M3 may be connected to the output terminal of the k-3th stage where the k-3th gate signal (k-3 ^th ) is output. Additionally, the k-3th gate signal (k- ^3th ) may be a start pulse, and the output terminal of the k-3th stage may be a start pulse input terminal.

The fourth transistor (M4) has a first electrode connected to the output terminal of the k-2th stage where the k-2th gate signal (k-2 ^th ) is output, a gate electrode connected to the first trigger clock input terminal, and a second The electrode may be connected to the first node (N1).

Additionally, the stage 600 may further include a fifth transistor (M5). The fifth transistor M5 may have a first electrode connected to the first node N1 and a gate electrode connected to the output terminal of the k+4th stage that outputs the k+4th gate signal (K+ ^4th ). Two electrodes can be connected to the low voltage input terminal where the low voltage (VGL) is transmitted. And, a low voltage can be applied to the first node (N1) in response to the k+4th gate signal (K+ ^4th ).

Additionally, the stage 600 may further include a sixth transistor (M6) and a seventh transistor (M7). The sixth transistor (M6) has a first electrode connected to the first node (N1), a gate electrode connected to a reset signal input terminal through which a reset signal (Reset) is transmitted, and a second electrode connected to the low voltage input terminal (VGL). there is. In addition, the seventh transistor M7 has a first electrode connected to the first node N1, a gate electrode connected to a stable signal input terminal where a stable signal (stable) is input, and a second electrode connected to the low voltage (VGL). This can be connected to the low voltage input terminal. Accordingly, the sixth transistor M6 and the seventh transistor M7 can apply the low voltage VGL to the first node N1.

Additionally, the stage 300 may further include an eighth transistor (M8). The first electrode of the eighth transistor M8 may be connected to a first clock input terminal that transmits the first clock CLK1, and the gate electrode and second electrode may be connected to the second node N2. The eighth transistor M8 functions as a diode and can remove ripples from the voltage of the gate signal output from the second node N2.

The signal output unit 620 may alternately turn on/off the first transistor (M1) and the second transistor (M2) to output a gate signal from the second node (N2). When the second transistor (M2) deteriorates, the threshold voltage of the transistor increases, which causes a problem in that the voltage of the second node (N2) does not decrease. However, the turn-on time of the second transistor (M2) is shortened through the second trigger clock (T-CLK2) with a short pulse width to prevent deterioration of the second transistor (M2), as shown in FIG. 5. Likewise, if the threshold voltage is prevented from rising, the problem of the voltage of the second node (N2) not lowering even when the second transistor (M2) is turned on can be solved.

The third transistor M3 of the timing unit 610 repeats turn-on/turn-off and can transmit a trigger pulse to the first node N1. When the third transistor (M3) deteriorates and the threshold voltage rises, the point at which the k-2th gate signal (k-2 ^th ) is transmitted to the first node (N1) is delayed, and this causes the second node (N2) The gate signal may not be output normally. However, the turn-on time of the fourth transistor (M4) is shortened through the first trigger clock (T-CLK1) with a short pulse width to prevent deterioration of the fourth transistor (M4), as shown in FIG. 5. Likewise, if the threshold voltage is prevented from rising, the timing at which the k-2th gate signal (k-2 ^th ) is applied to the first node (N1) can be prevented from being delayed.

In addition, by lowering the high and low state voltage levels of the first trigger clock (T-CLK1) and the second trigger clock (T-CLK2), the third transistor (M3) and fourth transistor (M4) The voltage difference between the gate electrode and the source electrode of one transistor may be set lower than the voltage difference between the gate electrode and the source electrode of the first transistor (M1). As a result, deterioration of the third transistor M3 and fourth transistor M4 can be further suppressed.

FIG. 7 is a timing diagram showing one embodiment of the operation of the stage shown in FIG. 6.

Referring to FIG. 7 , the k-3th gate signal (k-3 ^th ) may be transmitted to the first electrode and gate electrode of the third transistor (M3). When the k-3th gate signal (k-3 ^th ) is transmitted, the voltage of the first node (N1) may increase. And, the k-2th gate signal (K-2 ^th ) may be transmitted to the first electrode of the fourth transistor (M4). And, while the k-2th gate signal (K-2 ^th ) is transmitted, the first trigger clock (T-CLK1) can be applied to the gate electrode of the fourth transistor (M4). The time when the first trigger clock (T-CLK1) is applied may be when the first clock (CLK1) is in a high state. When the first trigger clock (T-CLK1) is applied to the gate of the fourth transistor (M4), the k-2th gate signal (K-2 ^th ) may be transmitted to the first node (N1). Accordingly, the voltage of the first node (N1) may rise again when the first trigger clock (T-CLK1) is transmitted.

And, at the point when the first trigger clock (T-CLK1) is in the low state, the k-3th gate signal (K-3 ^th ) is in the low state, so the third transistor (M3) and the fourth transistor (M4) are in the low state. It can be in a floating state at one node (N1). The first node (N1) is connected to the first electrode of the capacitor (C), so the voltage of the first node (N1) can be maintained. Accordingly, the voltage of the first node (N1) is low because the first trigger clock (T-CLK1) is low, so the trigger pulse is not transmitted to the first node (N1) and the k-3th gate signal (k-3 ^th ) It can be maintained even if it is not delivered to the first node (N1).

Additionally, when the second trigger clock (T-CLK2) is transmitted, a low voltage may be applied to the second node (N2) through the second transistor (M2). Therefore, the output terminal of the stage is connected to the second node (N2), so the stage can prevent the kth gate signal (K ^th ) from being output. The time when the second trigger clock (T-CLK2) is applied may be when the first clock (CLK1) is in a low state. Accordingly, the k-th gate signal (K ^th ) may be synchronized with the first clock (CLK1). In addition, when the voltage of the second node (N2) is lowered by the capacitor (C), the voltage of the first node (N1) is also lowered, so that the voltage of the first node (N1) is lowered and the first transistor (M1) is in the off state. You can make it happen.

Figure 8 is a flowchart showing a method of driving a display device according to the present invention.

Referring to FIG. 8, a method of driving a display device may apply a start pulse and a trigger pulse (S800). The start pulse and trigger pulse may be pulse signals that occur sequentially. Additionally, the control unit can transmit the start pulse and trigger pulse to the gate driver of the display device. The gate driver includes a plurality of stages, and each stage can output a gate signal. Gate signals output from each stage may be output sequentially. If the stage outputs the first gate signal, the start pulse and trigger pulse can be received from the control unit. However, in the case of a stage placed in the middle, the start pulse and trigger pulse can be received from the stage that previously output the gate signal. If the stage is the k-th stage, the start pulse may be a gate signal output from the k-3th stage, and the trigger pulse may be a gate signal output from the k-2th stage. However, it is not limited to this.

By receiving the first trigger signal, the timing at which the gate signal is applied can be determined (S810). When the first trigger signal is applied while receiving the start pulse and trigger pulse, the point in time at which the trigger pulse is output can be determined, and the gate signal can be output in response to the point in time at which the trigger pulse is output. When the first trigger signal is delivered, the voltage level of the trigger pulse can be added to the start pulse voltage level. The first trigger signal may be applied at the rising point of the first clock, and the gate signal may be a signal corresponding to the high signal of the first clock. The first trigger signal may be a signal whose pulse width is narrower than that of the first clock. Since the pulse width of the first trigger signal is set to be narrow, the deterioration of the transistor that receives the first trigger signal and performs the switching operation may be delayed compared to when the pulse width is wide.

By receiving the second trigger signal, it is possible to determine when the gate signal ends (S820). When the second trigger signal is received, a low voltage is applied to the output terminal and the gate signal can be terminated. The second trigger signal can be applied at the falling point of the first clock, so the gate signal can have the same pulse width as the first clock. The second trigger signal may be a signal whose pulse width is narrower than that of the first clock. Since the pulse width of the second trigger signal is set to be narrow, the deterioration of the transistor that receives the second trigger signal and performs the switching operation may be delayed compared to when the pulse width is wide.

The above description and attached drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art will be able to combine the components without departing from the essential characteristics of the present invention. , various modifications and transformations such as separation, substitution, and change will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display device
110: display panel
120 gate driver
130 Drive IC
140 control unit

Claims (10)

A start pulse and a trigger pulse applied later than the start pulse are input, and the trigger pulse is generated in response to a first trigger clock having a second pulse width narrower than the first pulse width of the first clock having a first pulse width. a timing unit that determines when to output and outputs the input trigger pulse; and
It includes a signal output unit that receives the trigger pulse output from the timing unit, outputs a gate signal corresponding to the first clock, and receives a second trigger clock having the second pulse width to stop output of the gate signal. do,
A gate driver wherein at least one of the first trigger clock and the second trigger clock has a lower high voltage voltage level and a lower low voltage voltage level than the first clock. According to paragraph 1,
The signal output unit includes a first transistor that outputs a gate signal corresponding to the first clock to a second node in response to the voltage of the first node, and a low voltage to the second node in response to the second trigger clock. It includes a second transistor that transmits power, and a capacitor connected between the first node and the second node and maintaining the voltage of the first node,
The timing unit is a gate driver including a third transistor that outputs the start pulse to the first node, and a fourth transistor that transmits the trigger pulse to the first node in response to the first trigger clock. delete According to paragraph 2,
A gate driver wherein the voltage difference between the gate electrode and the source electrode of any one of the third transistor and the fourth transistor is lower than the voltage difference between the gate electrode and source electrode of the first transistor. A display panel where a plurality of gate lines and a plurality of data lines intersect;
a gate driver that transmits gate signals to the plurality of gate lines; and
Includes a drive IC that transmits a data signal to the data line,
The gate driver includes a plurality of stages that sequentially output gate signals, and the kth stage of the plurality of stages is,
The k-3th gate signal output from the k-3th stage and the k-2th gate signal output from the k-2th stage are input, and the first pulse width of the first clock having the first pulse width is greater than the first pulse width. a timing unit that determines a point in time at which the k-2th gate signal is output in response to a first trigger clock having a narrow second pulse width and outputs the k-2th gate signal; and
Receives the k-2th gate signal output from the timing unit, outputs the kth gate signal corresponding to the first clock, and receives the second trigger clock with the second pulse width to generate the kth gate signal. It includes a signal output unit that stops the output,
A display device wherein at least one of the first trigger clock and the second trigger clock has a lower high voltage voltage level and a lower low voltage voltage level than the first clock. According to clause 5,
The signal output unit includes a first transistor that outputs a gate signal corresponding to the first clock to a second node in response to the voltage of the first node, and a low voltage to the second node in response to the second trigger clock. It includes a second transistor that transmits power, and a capacitor connected between the first node and the second node and maintaining the voltage of the first node,
The timing unit includes a third transistor that outputs the k-3th gate signal to the first node, and a fourth transistor that transmits the k-2th gate signal to the first node in response to the first trigger clock. Display device including. delete According to clause 6,
A display device in which a voltage difference between a gate electrode and a source electrode of any one of the third transistor and the fourth transistor is lower than a voltage difference between the gate electrode and the source electrode of the first transistor. sequentially receiving a start pulse and a trigger pulse applied later than the start pulse;
A first clock having a first pulse width and a first trigger clock having a second pulse width narrower than the first pulse width are input, an output time of the trigger pulse is determined in response to the first trigger clock, and the trigger pulse is generated. outputting as a gate signal; and
A step of terminating the gate signal in response to a second trigger clock having the second pulse width so that the gate signal has the first pulse width,
A method of driving a display device, wherein at least one of the first trigger clock and the second trigger clock has a lower high voltage voltage level and a lower low voltage voltage level than the first clock. delete

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