CN110136663A - Gate driving circuit and display device - Google Patents
Gate driving circuit and display device Download PDFInfo
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- CN110136663A CN110136663A CN201910276131.5A CN201910276131A CN110136663A CN 110136663 A CN110136663 A CN 110136663A CN 201910276131 A CN201910276131 A CN 201910276131A CN 110136663 A CN110136663 A CN 110136663A
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- node
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- clock signal
- grid
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
This application discloses a kind of gate driving circuit and display devices.The gate driving circuit includes cascade multiple drive element of the grid.Drive element of the grid includes: input module, is connected with first node, and under the control of the first clock signal, enabling signal charges to first node；Output module is connected with first node, generates the same level gate drive signal according to second clock signal, and provide the same level gate drive signal in output end；Pull-down module is connected with the first node, and the first node is pulled down to low level signal under the control of third clock signal；And maintenance module, it is connected with third clock signal output terminal, according to the third clock signal, stablizes the signal and the same level gate drive signal of the first node.The gate driving circuit enhances the stability of circuit, and area needed for capable of reducing the design parameter of component and being laid out increases design space, is conducive to the realization of narrow frame and low-power consumption.
Description
Technical field
The present invention relates to field of display technology, relate more specifically to gate driving circuit and display device.
Background technique
Liquid crystal display device is change the phenomenon that being changed under the action of electric field using the orientation of liquid crystal molecule
The display device of light source light transmittance.Due to having the advantages that display is high-quality, small in size and low in energy consumption, liquid crystal display device is
It is widely used in the mobile terminal of such as mobile phone and the large scale display panel of such as flat panel TV.Liquid crystal in recent years
Show that the development of device presents the development trend of high integration, low cost, integrative display driving is increasingly becoming flat panel display
Research hotspot.So-called integrative display driving circuit, which refers to, uses the peripheral circuits such as gate driving circuit and source electrode drive circuit
Switching tube (TFT) is realized and is made in TFT substrate together with pixel switch pipe.With traditional circuit (IC) driving method phase
Than, the quantity of peripheral driver chip can not only be reduced using the method for integrated gate driving and its press seal program, reduce cost,
And make display periphery more slim, so that display mould group is more compact, mechanically and electrically reliability is enhanced.
In existing gate driving circuit, drive element of the grid includes input module, output module and pull-down module.
In existing framework, the design of 8T duty ratio 25% is used, QB point need to be maintained always to high potential in the maintenance stage will
Switching tube opening in pull-down module works, and will cause the risk of voltage drift, the stability of circuit is poor.In addition, existing
The framework of the gate driving circuit of technology is complex, and more harsh to the limitation of the parameter of component, is unfavorable for being formed relatively narrow
Frame.
Therefore, it is necessary to provide improved technical solution to overcome the above technical problem existing in the prior art.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of gate driving circuit and display devices, to increase
The stability of circuit realizes narrow frame and reduces power consumption.
According to an aspect of the present invention, a kind of gate driving circuit, including cascade multiple drive element of the grid, institute are provided
State multiple drive element of the grid respectively include: input module is connected with first node, under the control of the first clock signal,
Enabling signal charges to the first node；Output module is connected with the first node, according to second clock signal
The same level gate drive signal is generated, and provides the same level gate drive signal in output end；Pull-down module, with described first
Node is connected, and the first node is pulled down to low level signal under the control of third clock signal；And maintenance module,
It is connected with third clock signal output terminal, according to the third clock signal, stablizes the signal of the first node and described
The same level gate drive signal.
Preferably, the gate driving circuit further include: pull-up module, respectively with second clock signal input part and described
Maintenance module is connected, for improving the voltage of second node in the maintenance module.
Preferably, the pull-up module includes: the second capacitor, is connected to the second clock signal input part and described
Between two nodes.
Preferably, the enabling signal of the first order drive element of the grid in the multiple drive element of the grid is described
The external signal provided of gate driving circuit；Intergrade drive element of the grid in the multiple drive element of the grid and last
The enabling signal of grade drive element of the grid is the gate drive signal that prime drive element of the grid provides.
Preferably, the input module includes: first switch tube, and the control terminal of the first switch tube and the first clock are believed
Number input terminal is connected, and receives first clock signal；First path terminal of the first switch tube receives the starting
Signal；The alternate path end of the first switch tube is connected with the first node.
Preferably, the output module includes: second switch, the control terminal of the second switch and the first segment
Point is connected, and the first path terminal is driven for receiving the second clock signal, alternate path end for generating the same level grid
Dynamic signal；First capacitor is connected between the control terminal of the second switch and the alternate path end.
Preferably, the pull-down module includes: third switching tube, and the control terminal of the third switching tube is described for receiving
Third clock signal, the first path terminal are connected with the first node, and alternate path end is for receiving the low level signal.
Preferably, the maintenance module includes: the 4th switching tube, when the control terminal of the 4th switching tube is connected to third
Clock signal input part, the first path terminal are connect with first voltage signal input part, and alternate path end is connected with second node；The
Five switching tubes, the control terminal of the 5th switching tube are connected to the second node, the first path terminal and the first node phase
Connection, alternate path end receive the low level signal；6th switching tube, the control terminal of the 6th switching tube are connected to described
First node, the first path terminal are connected with the second node, and alternate path end receives the low level signal；7th switch
Pipe, the control terminal of the 7th switching tube are connected to the second node, and the first path terminal is connected with the output end, and second
Path terminal receives the low level signal.
Preferably, the gate driving circuit is the sided configuration for including first part and second part, described first
Multiple drive element of the grid in point are respectively that the respective gates line of odd-numbered line provides gate drive signal, in the second part
Multiple drive element of the grid be respectively even number line respective gates line provide gate drive signal.
According to another aspect of the present invention, a kind of display device is provided, comprising: above-mentioned gate driving circuit, for mentioning
For multiple gate drive signals；Data drive circuit, for providing multiple luma datas；And display panel, the display surface
Plate includes the multiple pixel units and a plurality of grid line and multiple data lines for being arranged in array, wherein the display panel warp
The multiple gate drive signal is received by a plurality of grid line, to select the multiple pixel unit, Yi Jijing by row
The multiple luma data is received by column by the multiple data lines, to be supplied to selected pixel unit to realize that image is aobvious
Show.
The gate driving circuit provided according to embodiments of the present invention, the input module of drive element of the grid are eliminated for anti-
It to the switching tube of scanning, and uses clock signal to open switching tube as signal source and carries out preliminary filling, such design may make electricity
Road in low temperature driving have preferable performance and can coupled noise in bucking circuit, and the parameter of related component can be reduced
Design, is advantageously implemented narrow frame and low-power consumption.
The gate driving circuit provided according to embodiments of the present invention, drive element of the grid devise maintenance module to strengthen electricity
The stability on road, the architecture design of maintenance module make the switching tube in node QB exchange driving maintenance module, reduce voltage
The risk of drift improves the stability of circuit；The parameter that such architecture design can reduce switching tube in maintenance module simultaneously is set
Meter, is easy to implement narrow frame and low-power consumption.
The gate driving circuit provided according to embodiments of the present invention has stronger stability and preferably drives energy
Power, therefore the parameter designing of multiple components can be optimized, area needed for capable of reducing layout increases design space.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic block diagram of drive element of the grid according to an embodiment of the present invention；
Fig. 2 shows the circuit diagrams of drive element of the grid according to an embodiment of the present invention；
Fig. 3 shows the schematic block diagram of gate driving circuit according to an embodiment of the present invention；
Fig. 4 shows the enabling signal, clock signal and gate driving of drive element of the grid according to an embodiment of the present invention
The waveform diagram of signal；
Fig. 5 shows the voltage oscillogram of first node Q and second node QB according to an embodiment of the present invention；
Fig. 6 to Fig. 8 shows the grid of multiple drive element of the grid according to an embodiment of the present invention at different temperatures and drives
The waveform diagram of dynamic signal.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.This
Outside, certain well known parts may be not shown in figure.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.Hereinafter
Many specific details of the invention, such as structure, material, size, treatment process and the technology of component are described, so as to more clear
Understand the present invention to Chu.But it just as the skilled person will understand, can not be according to these specific details
To realize the present invention.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region when describing the structure of component
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if by part turnover, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
Fig. 1 shows the schematic block diagram of drive element of the grid according to an embodiment of the present invention, as shown in Figure 1, grid drives
Moving cell 100 includes input module 110, output module 120, pull-down module 130, maintenance module 140 and pull-up module 150.
Wherein, for receiving enabling signal (Gn-2), output end is connect the input terminal of input module 110 with first node Q,
For being pre-charged according to the first clock signal (CLK1) to first node Q.
Output module 120 is connect with first node Q and second clock signal (CLK2) input terminal according to first node Q's
Control voltage exports the clock signal clk 2 received for the same level gate drive signal Gn.
Pull-down module 130 is connect to divide with third clock signal (CLK4) input terminal and low level signal (VGL) input terminal
Not Jie Shou third clock signal clk 4 and low level signal VGL, for low level to be believed according to the clock signal clk 4 that receives
Number VGL is provided to first node Q to drag down the current potential of first node Q.
Maintenance module 140 is connect with first voltage signal (V1) input terminal, is received first voltage signal (V1).Maintenance module
140 also connect with third clock signal (CLK4) input terminal and low level signal (VGL) input terminal, for according to receive when
Low level signal VGL is provided to first node Q and the same level gate drive signal (Gn) output end to stablize by clock signal CLK4
The signal of one node Q and this gate drive signal output end.
Pull-up module 150 is connect with second clock signal (CLK2) and maintenance module 140 respectively, for believing second clock
Number it is provided to maintenance module 140.
Fig. 2 shows the circuit diagrams of drive element of the grid according to an embodiment of the present invention, as shown in Fig. 2, input mould
Block 110 includes first switch tube T1.The control terminal of first switch tube T1 connect with the first clock signal input terminal and receives first
Clock signal clk 1；The first path terminal of first switch tube T1 connect with enabling signal input terminal and receives enabling signal Gn-2；
The alternate path end of first switch tube T1 is connect with first node Q.
Output module 120 includes second switch T2 and first capacitor C1.The control terminal and first segment of second switch T2
Point Q connection；The first path terminal of second switch T2 is connect to receive clock signal clk 2 with second clock signal input part；The
The alternate path end of two switch transistor Ts 2 is connect to export the same level gate drive signal Gn with output end.First capacitor C1 is connected to
Between the control terminal and alternate path end of two switch transistor Ts 2.
Pull-down module 130 includes third switch transistor T 3.The control terminal and third clock signal input terminal of third switch transistor T 3
Connection is to receive clock signal clk 4；First path terminal of third switch transistor T 3 is connect with first node Q；Third switch transistor T 3
Alternate path end is connect to receive low level signal VGL with low level signal input terminal.It should be noted that the first pull-down module 130
Structure be not limited only to above-mentioned structure, be also possible to the structure of other multiple switch pipes combination, those skilled in the art
It can be selected as the case may be.
Maintenance module 140 includes the 4th to the 7th switch transistor T 4-T7.The control terminal and third clock of 4th switch transistor T 4 are believed
The connection of number input terminal is to receive clock signal clk 4；The first path terminal and first voltage signal input part of 4th switch transistor T 4 connect
It connects to receive first voltage signal (V1)；The alternate path end of 4th switch transistor T 4 is connect with second node QB.5th switching tube
The control terminal of T5 is connect with second node QB；First path terminal of the 5th switch transistor T 5 is connect with first node Q；5th switching tube
The alternate path end of T5 is connect to receive low level signal VGL with low level signal input terminal.The control terminal of 6th switch transistor T 6
It is connect with first node Q；First path terminal of the 6th switch transistor T 6 is connect with second node QB；The second of 6th switch transistor T 6 is logical
Terminal is connect to receive low level signal VGL with low level signal input terminal.The control terminal and second node of 7th switch transistor T 7
QB connection；First path terminal of the 7th switch transistor T 7 is connect with the same level gate drive signal output end；The of 7th switch transistor T 7
Two path terminals are connect to receive low level signal VGL with low level signal input terminal.
In one embodiment of the invention, maintenance module 140 includes the first maintenance unit and the second maintenance unit.First
Maintenance unit is connect with first node Q and low level signal input terminal, for being incited somebody to action according to the signal of the second node QB received
Low level signal VGL is provided to first node Q to stablize the signal of first node Q.Second maintenance unit and the same level gate driving
Signal output end is connected with low level signal input terminal, for according to the signal of second node QB received by low level signal
VGL is provided to the same level gate drive signal output end to stablize the signal of the same level gate drive signal output end.For example, such as Fig. 2
Shown, the first maintenance unit 141 includes the 5th switch transistor T 5, and the second maintenance unit 142 includes the 7th switch transistor T 7.5th switch
The control terminal of pipe T5 is connect with second node QB；First path terminal of the 5th switch transistor T 5 is connect with first node Q；5th switch
The alternate path end of pipe T5 is connect to receive low level signal VGL with low level signal input terminal.5th switch transistor T 5 is according to connecing
Low level signal VGL is provided to first node Q to stablize the signal of first node Q by the signal of the second node QB received.The
The control terminal of seven switch transistor Ts 7 is connect with second node QB；The first path terminal and the same level gate drive signal of 7th switch transistor T 7
Output end connection；The alternate path end of 7th switch transistor T 7 is connect to receive low level signal VGL with low level signal input terminal.
Low level signal VGL is provided to the same level gate drive signal according to the signal of the second node QB received by the 7th switch transistor T 7
Output end is to stablize the signal of the same level gate drive signal output end.
Pull-up module 150 includes the second capacitor C2.Second capacitor C2 respectively with second clock signal input part and the second section
Point QB connection, for second clock signal to be provided to second node QB.
Fig. 3 shows the schematic block diagram of gate driving circuit according to an embodiment of the present invention, as shown in figure 3, display dress
Setting 300 includes gate driving circuit display panel 310, thereon includes the multiple pixel units for being arranged in array, each pixel list
Member is, for example, thin film transistor (TFT) comprising pixel electrode and the transistor for the on or off pixel electrode, the transistor
(thin-film transistor,TFT).In display panel 310, it is located at same a line (institute in " row " such as corresponding diagram
The transverse direction shown) pixel unit in each transistor grid be connected and to the fringe region of display panel 310 draw one
Grid line, to form gate lines G [1] to G [n].
Gate driving circuit according to an embodiment of the present invention is, for example, integrated gate drive circuitry (Gate Driver in
Array is abbreviated as GIA) 320, including successively cascade n gate driving circuit.The n drive element of the grid respectively with display
Gate lines G [1] on panel 310 is connected to G [n] is corresponding.Via grid line by the pixel list on row selection display panel 310
Member.Corresponding grayscale signal is provided to realize that image is shown by column via data line.
In a preferred embodiment, the gate driving circuit 320 of the embodiment of the present invention is sided configuration, the n grid
Driving unit cascades the left and right sides for being set to display panel 310, including first part 320a and second part 320b respectively.Under
Face is illustrated by even number of n.In first part 320a, with odd-numbered line grid line (gate lines G [1], G [3] ..., G [n-
1]) connected drive element of the grid (GIA [1], GIA [3] ..., GIA [n-1]) cascade is set to the left side of display panel 310
Side.In second part 320b, with even number line grid line (gate lines G [2], G [4] ..., G [n]) the gate driving list that is connected
Member (GIA [2], GIA [4] ..., GIA [n]) cascade is set to the right side of display panel 310.Certainly the present invention not as
Limitation, in the preferred embodiment of the invention, with even number line grid line (gate lines G [2], G [4] ..., G [n]) grid that connect
Pole driving unit (GIA [2], GIA [4] ..., GIA [n]) be located at display panel 310 right side；With odd-numbered line grid line (grid
Polar curve G [1], G [3] ..., G [n-1]) connection drive element of the grid (GIA [1], GIA [3] ..., GIA [n-1]) be located at
The left side of display panel 310, those skilled in the art can select as the case may be.
Every level-one drive element of the grid all includes enabling signal input terminal, the first clock signal input terminal, second clock letter
Number input terminal, third clock signal input terminal, first voltage signal input part, low level signal input terminal and the same level grid drive
Dynamic signal output end.The same level gate drive signal output end is used to drive the pixel unit of display panel 310.
For be located at the left side of display panel 310 drive element of the grid (GIA [1], GIA [3] ..., GIA [n-1]),
First clock signal input terminal, second clock signal input part and third clock signal input terminal are connected with multiple clock lines respectively
To receive three clock signals in clock signal clk 1-CLK4, such as first order drive element of the grid GIA [1] receives clock
Signal CLK1, clock signal clk 2 and clock signal clk 4；Third level drive element of the grid GIA [3] reception clock signal clk 1,
Clock signal clk 2 and clock signal clk 3.For being located at drive element of the grid (GIA [2], GIA on 310 right side of display panel
[4] ..., GIA [n]), the first clock signal input terminal, second clock signal input part and third clock signal input terminal
It is connected respectively with a plurality of clock letter line to receive three clock signals in clock signal clk 5-CLK8, such as second level grid
Driving unit GIA [2] receives clock signal clk 5, clock signal clk 6 and clock signal clk 8；Fourth stage drive element of the grid
GIA [4] receives clock signal clk 5, clock signal clk 6 and clock signal clk 7.
When drive element of the grid is first order drive element of the grid, the enabling signal input terminal of the drive element of the grid
For inputting enabling signal STV1.
When drive element of the grid is second level drive element of the grid, the enabling signal input terminal of the drive element of the grid
For inputting enabling signal STV2.
When drive element of the grid is the third level any drive element of the grid (i-stage grid into n-th grade of drive element of the grid
Driving circuit) when, the enabling signal input terminal of the i-stage drive element of the grid is electrically connected to the i-th -2 grades gate driving lists
The gate drive signal output end of member.
Gate driving circuit according to this embodiment generates multiple gate drivings using cascade multiple drive element of the grid
Signal selects the pixel unit of corresponding line for being provided to grid line.In sided configuration, which includes using
First part in driving odd-numbered line grid line and second part for driving even number line grid line.With the gate driving circuit
First part for, relatively narrow layout area is only needed on the interconnection path between adjacent drive element of the grid, for passing
Defeated prime gate drive signal Gi-2.
The gate driving circuit of the embodiment of the present invention eliminates reverse scan compared with the gate driving circuit of the prior art
Switching tube, so as to reduce corresponding layout area and load of signal line, so as to realize that narrow frame, low-power consumption are shown
Device.
It should be noted that although describing the gate driving circuit using sided configuration in this embodiment, it is of the invention
It is without being limited thereto.When being applied to the gate driving circuit of one-sided configuration, gate driving circuit of the invention is also beneficial to reduce side
Frame and power consumption.
In the above embodiment of the invention, eliminate the switching tube of reverse scan, and use the first clock signal as
First switch tube T1 is connected signal source, carries out preliminary filling to first node using enabling signal, can reduce first switch tube T1
With the parameter of first capacitor C1, advantageously reduce frame and power consumption, such design also may make circuit have when low temperature driving compared with
It good performance and can offset since second clock signal is via coupled noise caused by second switch.
Fig. 4 shows the enabling signal, clock signal and gate driving of drive element of the grid according to an embodiment of the present invention
The waveform diagram of signal.Referring to Fig. 2 and Fig. 4, to the embodiment of the present invention by taking first order drive element of the grid GIA [1] as an example
The working principle of drive element of the grid is described in detail.Wherein, abscissa indicates time (s), and ordinate indicates signal level
(V)。
As described above, the enabling signal input terminal of first order drive element of the grid GIA [1] receives enabling signal STV1,
First clock signal input terminal, second clock signal input part, third clock signal input terminal, low level signal input terminal,
One voltage signal inputs receive clock signal clk 1, CLK2, CLK4, low level signal VGL and first voltage signal V1 respectively.
In the first stage, when the first clock signal (CLK1) becomes high level from low level, first switch tube T1 conducting,
Enabling signal STV1 is supplied to first node Q by first switch tube T1, is pre-charged to first node Q, the electricity of first node Q
Position becomes high level from low level, is connected second switch T2 and the 6th switch transistor T 6, and the 6th switch transistor T 6 is by low level signal
VGL is supplied to second node QB, by the current potential of second node QB down for low level, the 5th switch transistor T 5 and the 7th switch transistor T 7
Shutdown.
In second stage, second switch T2 has been switched on via the preliminary filling of first stage, when second clock signal
(CLK2) by low level increase be high level when, by the boot strap of first capacitor C1, the current potential of first node Q is drawn high, the
Two switch transistor Ts 2 are sufficiently conductive, export the same level gate drive signal Gn via second switch T2.
In the phase III, second clock signal (CLK2) at this time is low level, by second switch T2 by output wave
Shape is pulled low to low level, while being dragged down the current potential of first node Q by the coupling of first capacitor C1.When third clock is believed
When number (CLK4) becomes high level from low level, third switch transistor T 3 and the conducting of the 4th switch transistor T 4, third switch transistor T 3 will be low
Level signal VGL is supplied to first node Q, by the current potential of first node Q down for low level；4th switch transistor T 4 is electric by first
Pressure signal V1 is supplied to second node QB, and the 5th switch transistor T 5 and the 7th switch transistor T 7 are connected.5th switch transistor T 5 is by low electricity
Ordinary mail VGL is supplied to first node Q, so that the current potential of first node Q stabilizes to low level；7th switch transistor T 7 is by low level
Signal VGL is supplied to the same level gate drive signal output end so that the current potential of the same level gate drive signal output end stabilize to it is low
Level.
In fourth stage, when second clock signal (CLK2) becomes high level from low level, the height of second clock signal
Level is capacitively coupled to second node QB via second, further increases the voltage of second node QB, makes an uproar to effectively inhibit
Sound.
Fig. 5 shows the voltage oscillogram of first node Q and second node QB according to an embodiment of the present invention.In conjunction with Fig. 4,
The related description and Fig. 5 of Fig. 4, it can be seen that second node QB maintains 3V, only four in 3/4ths frame time voltages
/ mono- frame time is in 17V.Second node QB is promoted to 17V rapidly when first node Q has noise and carries out noise suppression.
Drive element of the grid according to the above embodiment of the present invention, it is possible to reduce the 5th switch transistor T 5 and the 7th switch transistor T 7
Parameter designing, and make second node QB for exchange driving the 5th switch transistor T 5 and the 7th switch transistor T 7, keep circuit whole
Risk that is more stable and reducing voltage drift.It is quick condition in charging stage second node QB point, so the 6th switching tube
(T6) parameter designing can also reduce.The diminution of 5th switch transistor T 5, the 6th switch transistor T 6 and 7 parameter of the 7th switch transistor T, has
Conducive to reduction frame and power consumption.
Fig. 6 to Fig. 8 shows the grid of multiple drive element of the grid according to an embodiment of the present invention at different temperatures and drives
The waveform diagram of dynamic signal, abscissa indicate time (s), and ordinate indicates signal level (V).Fig. 6 shows real according to the present invention
Apply the waveform diagram of gate drive signal of the multiple drive element of the grid of example when room temperature drives (27 DEG C)；Fig. 7 shows basis
The waveform diagram of gate drive signal of the multiple drive element of the grid of the embodiment of the present invention when low temperature drives (- 20 DEG C)；Fig. 8 shows
Gate drive signal of the multiple drive element of the grid according to an embodiment of the present invention at high temperature driven (70 DEG C, -3V) is gone out
Waveform diagram.In conjunction with Fig. 2, Fig. 5 to Fig. 8 it can be seen that, gate driving circuit according to an embodiment of the present invention low temperature drive when have compared with
It good performance and can offset since second clock signal (CLK2) is via coupled noise caused by second switch (T2), and
And the parameter designing of first switch tube (T1) and first capacitor (C1) can be reduced, be conducive to reduce frame and power consumption.
It should be noted that the first to the 7th switch transistor T 1-T7 referred in the present invention is N-type TFT,
And (i.e. drain electrode and source electrode can be interchanged) can be interchanged in the first path terminal of each transistor and alternate path end, but it is of the invention
Be practiced without limitation to this.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of gate driving circuit, including cascade multiple drive element of the grid, which is characterized in that the multiple gate driving
Unit respectively include:
Input module is connected with first node, under the control of the first clock signal, enabling signal to the first node into
Row charging；
Output module is connected with the first node, generates the same level gate drive signal, Yi Ji according to second clock signal
Output end provides the same level gate drive signal；
Pull-down module is connected with the first node, is pulled down to the first node under the control of third clock signal
Low level signal；And
Maintenance module is connected with third clock signal output terminal, according to the third clock signal, stablizes the first node
Signal and the same level gate drive signal.
2. gate driving circuit according to claim 1, which is characterized in that the gate driving circuit further include:
Pull-up module is connected with second clock signal input part and the maintenance module respectively, for improving the maintenance mould
The voltage of second node in block.
3. gate driving circuit according to claim 2, which is characterized in that the pull-up module includes:
Second capacitor is connected between the second clock signal input part and the second node.
4. gate driving circuit according to claim 1, which is characterized in that first in the multiple drive element of the grid
The enabling signal of grade drive element of the grid is the signal that the outside of the gate driving circuit provides；
The starting of intergrade drive element of the grid and most rear class drive element of the grid in the multiple drive element of the grid
Signal is the gate drive signal that prime drive element of the grid provides.
5. gate driving circuit according to claim 1, which is characterized in that the input module includes:
First switch tube, the control terminal of the first switch tube are connected with the first clock signal input terminal, and receive described
One clock signal；First path terminal of the first switch tube receives the enabling signal；The second of the first switch tube is logical
Terminal is connected with the first node.
6. gate driving circuit according to claim 1, which is characterized in that the output module includes:
Second switch, the control terminal of the second switch are connected with the first node, and the first path terminal is for receiving
The second clock signal, alternate path end is for generating the same level gate drive signal；
First capacitor is connected between the control terminal of the second switch and the alternate path end.
7. gate driving circuit according to claim 1, which is characterized in that the pull-down module includes:
Third switching tube, the control terminal of the third switching tube is for receiving the third clock signal, the first path terminal and institute
It states first node to be connected, alternate path end is for receiving the low level signal.
8. gate driving circuit according to claim 1, which is characterized in that the maintenance module includes:
4th switching tube, the control terminal of the 4th switching tube are connected to third clock signal input terminal, the first path terminal and the
The connection of one voltage signal inputs, alternate path end is connected with second node；
5th switching tube, the control terminal of the 5th switching tube are connected to the second node, the first path terminal and described first
Node is connected, and alternate path end receives the low level signal；
6th switching tube, the control terminal of the 6th switching tube are connected to the first node, the first path terminal and described second
Node is connected, and alternate path end receives the low level signal；
7th switching tube, the control terminal of the 7th switching tube are connected to the second node, the first path terminal and the output
End is connected, and alternate path end receives the low level signal.
9. gate driving circuit according to claim 1, which is characterized in that the gate driving circuit be include first
Divide the sided configuration with second part, multiple drive element of the grid in the first part are respectively the respective gates of odd-numbered line
Line provides gate drive signal, and multiple drive element of the grid in the second part are respectively that the respective gates line of even number line mentions
For gate drive signal.
10. a kind of display device characterized by comprising
Gate driving circuit according to any one of claim 1 to 9, for providing multiple gate drive signals；
Data drive circuit, for providing multiple luma datas；And
Display panel, the display panel include the multiple pixel units and a plurality of grid line and a plurality of data for being arranged in array
Line,
Wherein, the display panel receives the multiple gate drive signal via a plurality of grid line, thus by row selection
The multiple pixel unit, and the multiple luma data is received by column via the multiple data lines, to be supplied to choosing
Fixed pixel unit is to realize that image is shown.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910276131.5A CN110136663A (en) | 2019-04-08 | 2019-04-08 | Gate driving circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910276131.5A CN110136663A (en) | 2019-04-08 | 2019-04-08 | Gate driving circuit and display device |
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| CN110136663A true CN110136663A (en) | 2019-08-16 |
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| CN201910276131.5A Pending CN110136663A (en) | 2019-04-08 | 2019-04-08 | Gate driving circuit and display device |
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| CN110599898A (en) * | 2019-08-20 | 2019-12-20 | 深圳市华星光电技术有限公司 | Grid driving array type display panel |
| CN112908276A (en) * | 2021-01-26 | 2021-06-04 | 昆山龙腾光电股份有限公司 | Grid driving circuit and display device |
| WO2022199182A1 (en) * | 2021-03-25 | 2022-09-29 | 惠科股份有限公司 | Gate driving circuit and display device |
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| US20180068630A1 (en) * | 2015-09-28 | 2018-03-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Goa circuits and liquid crystal devices |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
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Application publication date: 20190816 |